BR0013846A - Processo para formação de um padrão condutor em substratos dielétricos - Google Patents

Processo para formação de um padrão condutor em substratos dielétricos

Info

Publication number
BR0013846A
BR0013846A BR0013846-0A BR0013846A BR0013846A BR 0013846 A BR0013846 A BR 0013846A BR 0013846 A BR0013846 A BR 0013846A BR 0013846 A BR0013846 A BR 0013846A
Authority
BR
Brazil
Prior art keywords
conductive pattern
metal film
dielectric substrates
forming
protective layer
Prior art date
Application number
BR0013846-0A
Other languages
English (en)
Other versions
BR0013846B1 (pt
Inventor
Michael Guggemos
Franz Kohnle
Original Assignee
Atotech Deutschland Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atotech Deutschland Gmbh filed Critical Atotech Deutschland Gmbh
Publication of BR0013846A publication Critical patent/BR0013846A/pt
Publication of BR0013846B1 publication Critical patent/BR0013846B1/pt

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/02—Local etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/12—Using specific substances
    • H05K2203/122—Organic non-polymeric compounds, e.g. oil, wax or thiol
    • H05K2203/124—Heterocyclic organic compounds, e.g. azole, furan
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1333—Deposition techniques, e.g. coating
    • H05K2203/135—Electrophoretic deposition of insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • ing And Chemical Polishing (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Inorganic Insulating Materials (AREA)
  • Liquid Crystal (AREA)
  • Manufacturing Of Electric Cables (AREA)
  • Chemically Coating (AREA)

Abstract

Patente de Invenção: "PROCESSO PARA FORMAçãO DE UM PADRãO CONDUTOR EM SUBSTRATOS DIELéTRICOS". Para formar um padrão condutor em substratos dielétricos, é proposto um processo, no qual a) um substrato coberto com um filme metálico é revestido com uma camada protetora, que é formada tratando-se o filme metálico com uma solução, que contém pelo menos um composto contendo nitrogênio, b) a camada protetora é removida por radiação de UV, pelo menos parcialmente, nas regiões que não correspondem ao padrão condutor a ser formado, de tal modo que o filme metálico está exposto e c) o filme metálico exposto é depois removido por corrosão. Por meio desse processo, podem ser produzidos padrões condutores extremamente finos, de modo reprodutível, em substratos dielétricos.
BRPI0013846-0A 1999-09-10 2000-07-18 processo para formação de um padrão condutor em substratos dielétricos. BR0013846B1 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19944908A DE19944908A1 (de) 1999-09-10 1999-09-10 Verfahren zum Bilden eines Leitermusters auf dielektrischen Substraten
PCT/DE2000/002423 WO2001020059A2 (de) 1999-09-10 2000-07-18 Verfahren zum bilden eines leitermusters auf dielektrischen substraten

Publications (2)

Publication Number Publication Date
BR0013846A true BR0013846A (pt) 2002-05-14
BR0013846B1 BR0013846B1 (pt) 2010-06-15

Family

ID=7922575

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0013846-0A BR0013846B1 (pt) 1999-09-10 2000-07-18 processo para formação de um padrão condutor em substratos dielétricos.

Country Status (15)

Country Link
US (1) US6806034B1 (pt)
EP (1) EP1218566B1 (pt)
JP (1) JP2003509590A (pt)
KR (1) KR20020031178A (pt)
CN (1) CN1240874C (pt)
AT (1) ATE233833T1 (pt)
AU (1) AU7267800A (pt)
BR (1) BR0013846B1 (pt)
CA (1) CA2382916A1 (pt)
DE (2) DE19944908A1 (pt)
HK (1) HK1044804B (pt)
MX (1) MXPA02002194A (pt)
MY (1) MY127027A (pt)
TW (1) TW529324B (pt)
WO (1) WO2001020059A2 (pt)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT412094B (de) * 2003-05-13 2004-09-27 Austria Tech & System Tech Verfahren zur beschichtung von rohlingen zur herstellung von gedruckten leiterplatten (pcb)
JP2007173676A (ja) * 2005-12-26 2007-07-05 Sumitomo Metal Mining Co Ltd 回路形成法
US8475924B2 (en) * 2007-07-09 2013-07-02 E.I. Du Pont De Nemours And Company Compositions and methods for creating electronic circuitry
US20090017309A1 (en) * 2007-07-09 2009-01-15 E. I. Du Pont De Nemours And Company Compositions and methods for creating electronic circuitry
US20100193950A1 (en) * 2009-01-30 2010-08-05 E.I.Du Pont De Nemours And Company Wafer level, chip scale semiconductor device packaging compositions, and methods relating thereto
DE102009032217A1 (de) * 2009-07-06 2011-01-13 Gebr. Schmid Gmbh & Co. Verfahren und Vorrichtung zur Behandlung von Substraten
CN103517566A (zh) * 2012-06-28 2014-01-15 昆山联滔电子有限公司 非导电载体上的导体轨道的制造方法
CN103533764A (zh) * 2012-07-05 2014-01-22 昆山联滔电子有限公司 非导电基板上形成导体线路的制造方法
JP6198384B2 (ja) * 2012-11-28 2017-09-20 富士フイルム株式会社 半導体基板のエッチング方法及び半導体素子の製造方法
CN103731994B (zh) * 2013-12-30 2017-04-19 天津市德中技术发展有限公司 用覆厚导电层基板材料制作厚导电层电路结构电路板的方法
TWI639370B (zh) * 2014-04-16 2018-10-21 南韓商Ｌｇ化學股份有限公司 形成導電圖案用之組成物，使用該組成物形成導電圖案之方法，及於其上具有導電圖案之樹脂組件
CN112552079B (zh) * 2019-09-26 2023-09-12 航天特种材料及工艺技术研究所 一种金属化陶瓷基复合材料及曲面金属化的方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE732249C (de) 1935-11-27 1943-02-25 Lorenz C Ag Verfahren zur Verstaerkung von in der Spannung stark unterschiedlichen Impulsen grosser Flankensteilheit
US3547629A (en) * 1962-09-27 1970-12-15 American Screen Process Equip Photoflash method of transferring information and fabricating printed circuits
JPS6190492A (ja) * 1984-10-11 1986-05-08 四国化成工業株式会社 銅スル−ホ−ルプリント配線板の製造方法
DE3732249A1 (de) * 1987-09-24 1989-04-13 Siemens Ag Verfahren zur herstellung von dreidimensionalen leiterplatten
EP0364132A1 (en) * 1988-09-29 1990-04-18 Shikoku Chemicals Corporation Method for forming conversion coating on surface of copper or copper alloy
DE3926708A1 (de) * 1989-08-12 1991-02-14 Basf Ag Photopolymerisierbares schichtuebertragungsmaterial
JPH0465184A (ja) 1990-07-05 1992-03-02 Kansai Paint Co Ltd 電着前処理方法
DE4131065A1 (de) * 1991-08-27 1993-03-04 Siemens Ag Verfahren zur herstellung von leiterplatten
DE4222968A1 (de) * 1992-07-13 1994-01-20 Hoechst Ag Positiv-arbeitendes strahlungsempfindliches Gemisch und damit hergestelltes Aufzeichnungsmaterial
DE4311807C2 (de) * 1993-04-03 1998-03-19 Atotech Deutschland Gmbh Verfahren zur Beschichtung von Metallen und Anwendung des Verfahrens in der Leiterplattentechnik
DE4339019A1 (de) * 1993-11-10 1995-05-11 Atotech Deutschland Gmbh Verfahren zur Herstellung von Leiterplatten
DE59503175D1 (de) * 1994-04-25 1998-09-17 Siemens Nv Verfahren zur bildung metallischer leitermuster auf elektrisch isolierenden unterlagen
WO1997015173A1 (en) 1995-10-17 1997-04-24 Minnesota Mining And Manufacturing Company Method for radiation-induced thermal transfer of resist for flexible printed circuitry
JP4189609B2 (ja) * 1997-01-31 2008-12-03 テイラー，ジェームズ、エム． サブストレート材料をプライミングする組成物及び方法
DE10112023A1 (de) * 2001-03-07 2002-10-02 Atotech Deutschland Gmbh Verfahren zum Bilden eines Metallmusters auf einen dielektrischen Substrat

Also Published As

Publication number Publication date
MXPA02002194A (es) 2002-12-16
DE19944908A1 (de) 2001-04-12
US6806034B1 (en) 2004-10-19
CA2382916A1 (en) 2001-03-22
TW529324B (en) 2003-04-21
MY127027A (en) 2006-11-30
WO2001020059A3 (de) 2001-09-27
CN1240874C (zh) 2006-02-08
EP1218566A2 (de) 2002-07-03
DE50001425D1 (de) 2003-04-10
HK1044804B (zh) 2003-08-01
AU7267800A (en) 2001-04-17
KR20020031178A (ko) 2002-04-26
EP1218566B1 (de) 2003-03-05
HK1044804A1 (en) 2002-11-01
CN1373817A (zh) 2002-10-09
JP2003509590A (ja) 2003-03-11
ATE233833T1 (de) 2003-03-15
BR0013846B1 (pt) 2010-06-15
WO2001020059A2 (de) 2001-03-22

Similar Documents

Publication Publication Date Title
ATE488621T1 (de) Galvanisches verfahren zur herstellung einer mehrlagenstruktur
DE59503657D1 (de) Verfahren zur strukturierten Metallisierung der Oberfläche von Substraten
BR0013846B1 (pt) processo para formação de um padrão condutor em substratos dielétricos.
BR0109647B1 (pt) elemento de metal eletricamente condutivo de superfìcie tratada e processo de formação do mesmo.
DK1319254T3 (da) Fremgangsmåde til fremstilling af en halvleder-metalkontakt gennem et dielektrisk lag
MY141591A (en) Metal pattern formation
EP1054296A3 (en) Fine pattern forming method
KR840004826A (ko) 반도체 장치 제조를 위한 석판 처리공정
KR940010240A (ko) 표면적이 극대화된 도전층 제조 방법
TW374203B (en) A method for forming a fine contact hole in a semiconductor device
TW399298B (en) Manufacturing method of via hole
TW201836451A (zh) 圖案化基板的方法
JPS566434A (en) Manufacture of semiconductor device
KR970076073A (ko) 반도체장치의 포토레지스트 패턴 형성방법
TH46463A (th) วิธีในการสร้างแบบลายตัวนำไฟฟ้าบนวัสดุฐานรองไดอิเล็กตริก
TH46463B (th) วิธีในการสร้างแบบลายตัวนำไฟฟ้าบนวัสดุฐานรองไดอิเล็กตริก
TW340252B (en) Process of forming a via hole
JPS55107781A (en) Etching method for metal film
KR960005865A (ko) 반도체 소자의 금속배선 형성방법
JPS6473087A (en) Formation of metallic pattern
JPS56101756A (en) Manufacture of semiconductor device
TH59178B (th) การขึ้นรูปแบบรูปโลหะ
JPS647528A (en) Manufacture of semiconductor device
JPS57102025A (en) Manufacture of semiconductor device
EP0634698A4 (en) PROCESS FOR FORMING A POSITIVE POLYIMIDE PATTERN.

Legal Events

Date Code Title Description
B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements
B11N Dismissal: publication cancelled [chapter 11.14 patent gazette]

Free format text: REFERENTE A RPI 2014 DE 11/08/2009.

B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 18/07/2000, OBSERVADAS AS CONDICOES LEGAIS.

B21F Lapse acc. art. 78, item iv - on non-payment of the annual fees in time

Free format text: REFERENTE A 16A ANUIDADE.

B24J Lapse because of non-payment of annual fees (definitively: art 78 iv lpi, resolution 113/2013 art. 12)

Free format text: EM VIRTUDE DA EXTINCAO PUBLICADA NA RPI 2385 DE 20-09-2016 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDA A EXTINCAO DA PATENTE E SEUS CERTIFICADOS, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.