ATE546882T1 - Dreiwertige logikfunktionsschaltung - Google Patents

Dreiwertige logikfunktionsschaltung

Info

Publication number
ATE546882T1
ATE546882T1 AT07707806T AT07707806T ATE546882T1 AT E546882 T1 ATE546882 T1 AT E546882T1 AT 07707806 T AT07707806 T AT 07707806T AT 07707806 T AT07707806 T AT 07707806T AT E546882 T1 ATE546882 T1 AT E546882T1
Authority
AT
Austria
Prior art keywords
logic function
function circuit
valued logic
variable
circuits
Prior art date
Application number
AT07707806T
Other languages
English (en)
Inventor
Yasushi Hibino
Masaaki Shirase
Original Assignee
Japan Adv Inst Science & Tech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Adv Inst Science & Tech filed Critical Japan Adv Inst Science & Tech
Application granted granted Critical
Publication of ATE546882T1 publication Critical patent/ATE546882T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0002—Multistate logic

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
AT07707806T 2006-01-31 2007-01-31 Dreiwertige logikfunktionsschaltung ATE546882T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006023474A JP4288355B2 (ja) 2006-01-31 2006-01-31 三値論理関数回路
PCT/JP2007/051620 WO2007088901A1 (ja) 2006-01-31 2007-01-31 三値論理関数回路

Publications (1)

Publication Number Publication Date
ATE546882T1 true ATE546882T1 (de) 2012-03-15

Family

ID=38327472

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07707806T ATE546882T1 (de) 2006-01-31 2007-01-31 Dreiwertige logikfunktionsschaltung

Country Status (7)

Country Link
US (1) US7755391B2 (de)
EP (1) EP2007013B1 (de)
JP (1) JP4288355B2 (de)
KR (1) KR100971644B1 (de)
CN (1) CN101395801B (de)
AT (1) ATE546882T1 (de)
WO (1) WO2007088901A1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102415143B1 (ko) * 2010-01-20 2022-07-01 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치 및 휴대 전화기
US8847625B2 (en) * 2012-02-16 2014-09-30 Southern Methodist University Single clock distribution network for multi-phase clock integrated circuits
CN102916687B (zh) * 2012-09-27 2015-07-08 浙江工商大学 基于cmos工艺的三值时钟发生器
CN103248355B (zh) * 2013-05-20 2016-02-10 浙江工商大学 一种基于cmos工艺的tandor门电路
CN103326709B (zh) * 2013-05-20 2016-02-17 浙江工商大学 基于cmos工艺的torand电路单元
CN104052434B (zh) * 2013-07-03 2016-09-28 浙江工商大学 一种时钟变换电路
CN104320126A (zh) * 2014-11-14 2015-01-28 浙江工商大学 Qc变换bc21的电路单元
CN104579310A (zh) * 2014-11-14 2015-04-29 浙江工商大学 基于cmos的qb32模块电路单元
CN104467758B (zh) * 2014-11-14 2017-09-26 浙江水利水电学院 一种qb31的电路单元
CN104320127A (zh) * 2014-11-14 2015-01-28 浙江工商大学 一种qc转换为bc13的cmos电路单元
CN104320128A (zh) * 2014-11-14 2015-01-28 浙江工商大学 一种基于cmos的qbc23电路
CN104333370A (zh) * 2014-11-14 2015-02-04 浙江工商大学 基于四二值时钟的qbc20电路
KR101689159B1 (ko) * 2015-07-10 2016-12-23 울산과학기술원 3진수 논리회로
JP6545213B2 (ja) * 2017-03-17 2019-07-17 アンリツ株式会社 ３値信号発生装置及び３値信号発生方法
KR101928223B1 (ko) 2017-12-29 2018-12-11 울산과학기술원 삼진 논리 회로 장치
US10855881B1 (en) * 2019-12-18 2020-12-01 Ricoh Company, Ltd. Vectorized multi-level halftoning using ternary logic
CN113810043A (zh) * 2021-09-03 2021-12-17 杭州电子科技大学 基于忆阻器的平衡三值译码器电路

Family Cites Families (12)

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Publication number Priority date Publication date Assignee Title
JPS615623A (ja) 1984-06-20 1986-01-11 Res Dev Corp Of Japan 多値論理回路
JP3248784B2 (ja) 1993-07-20 2002-01-21 シャープ株式会社 多値論理回路
JP3381205B2 (ja) 1994-01-14 2003-02-24 日本電信電話株式会社 Ｃｍｏｓ多値論理回路
KR100233558B1 (ko) * 1996-06-29 1999-12-01 김영환 반도체 소자의 제조방법
US6133754A (en) 1998-05-29 2000-10-17 Edo, Llc Multiple-valued logic circuit architecture; supplementary symmetrical logic circuit structure (SUS-LOC)
JP3387859B2 (ja) * 1998-12-15 2003-03-17 日本電気株式会社 ３値スイッチ回路
US6573758B2 (en) * 2001-09-27 2003-06-03 International Business Machines Corporation Fast, symmetrical XOR/XNOR gate
US6828838B1 (en) * 2003-05-30 2004-12-07 Intel Corporation Vectored flip-flops and latches with embedded output-merge logic and shared clock drivers
JP2005001866A (ja) 2003-06-13 2005-01-06 Canon Electronics Inc シート排出装置及びプリンタ装置
JP3870272B2 (ja) 2005-01-06 2007-01-17 国立大学法人北陸先端科学技術大学院大学 三値論理関数回路及び多値論理関数回路
US7373569B2 (en) * 2005-12-15 2008-05-13 P.A. Semi, Inc. Pulsed flop with scan circuitry
US7693701B2 (en) * 2007-06-07 2010-04-06 International Business Machines Corporation Structure for a configurable low power high fan-in multiplexer

Also Published As

Publication number Publication date
EP2007013A9 (de) 2009-07-08
CN101395801B (zh) 2011-05-18
JP2007208512A (ja) 2007-08-16
EP2007013B1 (de) 2012-02-22
EP2007013A2 (de) 2008-12-24
EP2007013A4 (de) 2010-11-17
US20090295428A1 (en) 2009-12-03
KR20080098509A (ko) 2008-11-10
US7755391B2 (en) 2010-07-13
CN101395801A (zh) 2009-03-25
KR100971644B1 (ko) 2010-07-26
WO2007088901A1 (ja) 2007-08-09
JP4288355B2 (ja) 2009-07-01

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