ATE200365T1 - Verfahren zur herstellung einer integrierten halbleiterschaltungsanordnung mit komplementären feldeffekttransistoren - Google Patents
Verfahren zur herstellung einer integrierten halbleiterschaltungsanordnung mit komplementären feldeffekttransistorenInfo
- Publication number
- ATE200365T1 ATE200365T1 AT91304831T AT91304831T ATE200365T1 AT E200365 T1 ATE200365 T1 AT E200365T1 AT 91304831 T AT91304831 T AT 91304831T AT 91304831 T AT91304831 T AT 91304831T AT E200365 T1 ATE200365 T1 AT E200365T1
- Authority
- AT
- Austria
- Prior art keywords
- producing
- field effect
- circuit arrangement
- effect transistors
- semiconductor circuit
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 4
- 230000000295 complement effect Effects 0.000 title 1
- 230000005669 field effect Effects 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000002184 metal Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/56—Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
- C23C14/568—Transferring the substrates through a series of coating stations
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/04—Coating on selected surface areas, e.g. using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/02—Contacts, special
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2139612A JP2895166B2 (ja) | 1990-05-31 | 1990-05-31 | 半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE200365T1 true ATE200365T1 (de) | 2001-04-15 |
Family
ID=15249347
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT91304831T ATE200365T1 (de) | 1990-05-31 | 1991-05-29 | Verfahren zur herstellung einer integrierten halbleiterschaltungsanordnung mit komplementären feldeffekttransistoren |
Country Status (5)
Country | Link |
---|---|
US (2) | US5218232A (de) |
EP (1) | EP0459773B1 (de) |
JP (1) | JP2895166B2 (de) |
AT (1) | ATE200365T1 (de) |
DE (1) | DE69132569T2 (de) |
Families Citing this family (38)
Publication number | Priority date | Publication date | Assignee | Title |
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SG59964A1 (en) * | 1989-09-26 | 1999-02-22 | Canon Kk | Process for forming deposited film and process for preparing semiconductor device |
DE69109366T2 (de) * | 1990-05-31 | 1995-10-19 | Canon Kk | Verfahren zur Herstellung einer Halbleiteranordnung mit Gatestruktur. |
JP2892170B2 (ja) * | 1990-07-20 | 1999-05-17 | 株式会社東芝 | 熱処理成膜方法 |
JPH05251649A (ja) * | 1991-12-20 | 1993-09-28 | Nippon Steel Corp | Mos型半導体装置及びその製造方法 |
JP3395263B2 (ja) * | 1992-07-31 | 2003-04-07 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
JPH06196419A (ja) * | 1992-12-24 | 1994-07-15 | Canon Inc | 化学気相堆積装置及びそれによる半導体装置の製造方法 |
US5468669A (en) * | 1993-10-29 | 1995-11-21 | At&T Corp. | Integrated circuit fabrication |
JP3045946B2 (ja) * | 1994-05-09 | 2000-05-29 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 半導体デバイスの製造方法 |
JPH07335834A (ja) * | 1994-06-07 | 1995-12-22 | Nippon Motorola Ltd | 半導体集積回路装置の出力ドライバ |
EP0689085B1 (de) * | 1994-06-20 | 2003-01-29 | Canon Kabushiki Kaisha | Anzeigevorrichtung und Verfahren zu ihrer Herstellung |
JP3109979B2 (ja) * | 1994-06-20 | 2000-11-20 | キヤノン株式会社 | 液晶表示装置 |
JP3126630B2 (ja) * | 1994-06-20 | 2001-01-22 | キヤノン株式会社 | ディスプレイ |
US5726720A (en) * | 1995-03-06 | 1998-03-10 | Canon Kabushiki Kaisha | Liquid crystal display apparatus in which an insulating layer between the source and substrate is thicker than the insulating layer between the drain and substrate |
JP3219674B2 (ja) | 1995-03-09 | 2001-10-15 | キヤノン株式会社 | 液晶表示装置 |
JP3292657B2 (ja) * | 1995-04-10 | 2002-06-17 | キヤノン株式会社 | 薄膜トランジスタ及びそれを用いた液晶表示装置の製造法 |
US5942786A (en) * | 1996-02-01 | 1999-08-24 | United Microelectronics Corp. | Variable work function transistor high density mask ROM |
JP3188411B2 (ja) * | 1996-10-18 | 2001-07-16 | キヤノン株式会社 | 反射型液晶装置用画素電極基板、該画素電極基板を用いた液晶装置及び該液晶装置を用いた表示装置 |
JP3513371B2 (ja) * | 1996-10-18 | 2004-03-31 | キヤノン株式会社 | マトリクス基板と液晶装置とこれらを用いた表示装置 |
JP3571887B2 (ja) * | 1996-10-18 | 2004-09-29 | キヤノン株式会社 | アクティブマトリクス基板及び液晶装置 |
JPH113861A (ja) * | 1997-06-12 | 1999-01-06 | Sony Corp | 半導体装置の製造方法及びその装置 |
DE19734728C1 (de) * | 1997-08-11 | 1999-04-01 | Siemens Ag | Integrierte Schaltungsanordnung mit mindestens zwei unterschiedlich dotierten Gebieten, die elektrisch miteinander verbunden sind, und Verfahren zu deren Herstellung |
US6162714A (en) * | 1997-12-16 | 2000-12-19 | Lsi Logic Corporation | Method of forming thin polygates for sub quarter micron CMOS process |
KR100255134B1 (ko) * | 1997-12-31 | 2000-05-01 | 윤종용 | 반도체 장치 및 그 제조 방법 |
EP0936667A1 (de) * | 1998-01-20 | 1999-08-18 | Lucent Technologies Inc. | Gitterangepasste Barriere für zweifach dotierte Polysilizium-Gates |
US6352913B1 (en) | 1998-04-28 | 2002-03-05 | Compaq Computer Corporation | Damascene process for MOSFET fabrication |
KR100306372B1 (ko) * | 1998-06-29 | 2001-10-19 | 박종섭 | 반도체소자의 게이트전극 형성방법 |
DE19840824C1 (de) | 1998-09-07 | 1999-10-21 | Siemens Ag | Ferroelektrischer Transistor, dessen Verwendung in einer Speicherzellenanordnung und Verfahren zu dessen Herstellung |
EP1370716A4 (de) * | 2001-02-12 | 2007-08-08 | Starck H C Inc | Tantal-silicium- und niob-silicium-substrate für kondensatoranoden |
JP4000256B2 (ja) * | 2001-12-11 | 2007-10-31 | 富士通株式会社 | 半導体装置及びその製造方法 |
US7166896B2 (en) * | 2002-08-26 | 2007-01-23 | Micron Technology, Inc. | Cross diffusion barrier layer in polysilicon |
US6943405B2 (en) * | 2003-07-01 | 2005-09-13 | International Business Machines Corporation | Integrated circuit having pairs of parallel complementary FinFETs |
US7323731B2 (en) | 2003-12-12 | 2008-01-29 | Canon Kabushiki Kaisha | Photoelectric conversion device, method of manufacturing photoelectric conversion device, and image pickup system |
US20050140634A1 (en) * | 2003-12-26 | 2005-06-30 | Nec Corporation | Liquid crystal display device, and method and circuit for driving liquid crystal display device |
US7737519B2 (en) * | 2004-05-06 | 2010-06-15 | Canon Kabushiki Kaisha | Photoelectric conversion device and manufacturing method thereof |
CN100446079C (zh) | 2004-12-15 | 2008-12-24 | 日本电气株式会社 | 液晶显示装置、其驱动方法及其驱动电路 |
JP4969779B2 (ja) * | 2004-12-28 | 2012-07-04 | 株式会社東芝 | 半導体装置の製造方法 |
KR100802270B1 (ko) * | 2005-08-31 | 2008-02-11 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
DE102015009861A1 (de) * | 2015-08-04 | 2017-02-09 | Manz Ag | Substratbearbeitungsvorrichtung und Beschichtungsverfahren |
Family Cites Families (21)
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CH581904A5 (de) * | 1974-08-29 | 1976-11-15 | Centre Electron Horloger | |
GB2038883B (en) * | 1978-11-09 | 1982-12-08 | Standard Telephones Cables Ltd | Metallizing semiconductor devices |
US4446476A (en) * | 1981-06-30 | 1984-05-01 | International Business Machines Corporation | Integrated circuit having a sublayer electrical contact and fabrication thereof |
JPS594067A (ja) * | 1982-06-30 | 1984-01-10 | Fujitsu Ltd | 半導体装置 |
JPS5957469A (ja) * | 1982-09-28 | 1984-04-03 | Fujitsu Ltd | 半導体装置 |
DE3314879A1 (de) * | 1983-04-25 | 1984-10-25 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von stabilen, niederohmigen kontakten in integrierten halbleiterschaltungen |
JPS59231871A (ja) * | 1983-06-14 | 1984-12-26 | Nec Corp | 半導体装置 |
DE3326142A1 (de) * | 1983-07-20 | 1985-01-31 | Siemens AG, 1000 Berlin und 8000 München | Integrierte halbleiterschaltung mit einer aus aluminium oder aus einer aluminiumlegierung bestehenden aeusseren kontaktleiterbahnebene |
US4710897A (en) * | 1984-04-27 | 1987-12-01 | Kabushiki Kaisha Toshiba | Semiconductor memory device comprising six-transistor memory cells |
JPS6146063A (ja) * | 1984-08-10 | 1986-03-06 | Hitachi Ltd | 半導体装置の製造方法 |
US4648175A (en) * | 1985-06-12 | 1987-03-10 | Ncr Corporation | Use of selectively deposited tungsten for contact formation and shunting metallization |
JP2741854B2 (ja) * | 1986-06-18 | 1998-04-22 | 株式会社日立製作所 | 半導体集積回路装置 |
US4833094A (en) * | 1986-10-17 | 1989-05-23 | International Business Machines Corporation | Method of making a dynamic ram cell having shared trench storage capacitor with sidewall-defined bridge contacts and gate electrodes |
US4851257A (en) * | 1987-03-13 | 1989-07-25 | Harris Corporation | Process for the fabrication of a vertical contact |
JPS63299251A (ja) * | 1987-05-29 | 1988-12-06 | Toshiba Corp | 半導体装置の製造方法 |
US4905073A (en) * | 1987-06-22 | 1990-02-27 | At&T Bell Laboratories | Integrated circuit with improved tub tie |
JPH0623429B2 (ja) * | 1988-07-28 | 1994-03-30 | 日電アネルバ株式会社 | シリコン基板上にアルミニウムの平滑な薄膜を作製する方法とそれを用いた光学的反射鏡 |
US5084417A (en) * | 1989-01-06 | 1992-01-28 | International Business Machines Corporation | Method for selective deposition of refractory metals on silicon substrates and device formed thereby |
PT95232B (pt) * | 1989-09-09 | 1998-06-30 | Canon Kk | Processo de producao de uma pelicula de aluminio depositada |
SG43924A1 (en) * | 1989-09-26 | 1997-11-14 | Canon Kk | Process for forming metal deposited film containing aluminium as main component by use of alkyl aluminium hydride |
US5057895A (en) * | 1990-08-06 | 1991-10-15 | Harris Corporation | Trench conductor and crossunder architecture |
-
1990
- 1990-05-31 JP JP2139612A patent/JP2895166B2/ja not_active Expired - Fee Related
-
1991
- 1991-05-24 US US07/705,596 patent/US5218232A/en not_active Expired - Lifetime
- 1991-05-29 DE DE69132569T patent/DE69132569T2/de not_active Expired - Fee Related
- 1991-05-29 AT AT91304831T patent/ATE200365T1/de not_active IP Right Cessation
- 1991-05-29 EP EP91304831A patent/EP0459773B1/de not_active Expired - Lifetime
-
1995
- 1995-03-30 US US08/414,049 patent/US5700719A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2895166B2 (ja) | 1999-05-24 |
EP0459773B1 (de) | 2001-04-04 |
US5700719A (en) | 1997-12-23 |
DE69132569D1 (de) | 2001-05-10 |
JPH0434922A (ja) | 1992-02-05 |
EP0459773A3 (en) | 1992-06-03 |
EP0459773A2 (de) | 1991-12-04 |
US5218232A (en) | 1993-06-08 |
DE69132569T2 (de) | 2001-08-30 |
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