ATE174124T1 - Verfahren zur herstellung und zum testen von integrierten schaltungen und testanordnung für integrierte schaltungen - Google Patents
Verfahren zur herstellung und zum testen von integrierten schaltungen und testanordnung für integrierte schaltungenInfo
- Publication number
- ATE174124T1 ATE174124T1 AT89906938T AT89906938T ATE174124T1 AT E174124 T1 ATE174124 T1 AT E174124T1 AT 89906938 T AT89906938 T AT 89906938T AT 89906938 T AT89906938 T AT 89906938T AT E174124 T1 ATE174124 T1 AT E174124T1
- Authority
- AT
- Austria
- Prior art keywords
- integrated circuits
- integrated circuit
- vias
- forming
- producing
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31912—Tester/user interface
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/0735—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card arranged on a flexible frame or film
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70653—Metrology techniques
- G03F7/70658—Electrical testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49764—Method of mechanical manufacture with testing or indicating
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Human Computer Interaction (AREA)
- Manufacturing & Machinery (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Measuring Leads Or Probes (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/194,596 US4924589A (en) | 1988-05-16 | 1988-05-16 | Method of making and testing an integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE174124T1 true ATE174124T1 (de) | 1998-12-15 |
Family
ID=22718181
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT89906938T ATE174124T1 (de) | 1988-05-16 | 1989-05-15 | Verfahren zur herstellung und zum testen von integrierten schaltungen und testanordnung für integrierte schaltungen |
Country Status (7)
Country | Link |
---|---|
US (1) | US4924589A (de) |
EP (2) | EP0864870A3 (de) |
JP (2) | JPH03504657A (de) |
AT (1) | ATE174124T1 (de) |
BR (1) | BR8907190A (de) |
DE (1) | DE68928870D1 (de) |
WO (1) | WO1989011659A1 (de) |
Families Citing this family (98)
Publication number | Priority date | Publication date | Assignee | Title |
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EP0508707A1 (de) * | 1991-04-12 | 1992-10-14 | Texas Instruments Incorporated | Anordnung zum Testen von Schaltungen auf dem Wafer |
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US9768083B1 (en) | 2017-06-27 | 2017-09-19 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells |
US10096530B1 (en) | 2017-06-28 | 2018-10-09 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells |
US9865583B1 (en) | 2017-06-28 | 2018-01-09 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells |
US10496777B1 (en) * | 2017-11-17 | 2019-12-03 | Xilinx, Inc. | Physical synthesis for multi-die integrated circuit technology |
US10839125B1 (en) | 2018-09-24 | 2020-11-17 | Xilinx, Inc. | Post-placement and post-routing physical synthesis for multi-die integrated circuits |
US11238206B1 (en) | 2021-03-26 | 2022-02-01 | Xilinx, Inc. | Partition wire assignment for routing multi-partition circuit designs |
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US3795975A (en) * | 1971-12-17 | 1974-03-12 | Hughes Aircraft Co | Multi-level large scale complex integrated circuit having functional interconnected circuit routed to master patterns |
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-
1988
- 1988-05-16 US US07/194,596 patent/US4924589A/en not_active Expired - Lifetime
-
1989
- 1989-05-15 BR BR898907190A patent/BR8907190A/pt not_active IP Right Cessation
- 1989-05-15 EP EP98201447A patent/EP0864870A3/de not_active Withdrawn
- 1989-05-15 AT AT89906938T patent/ATE174124T1/de not_active IP Right Cessation
- 1989-05-15 WO PCT/US1989/002088 patent/WO1989011659A1/en active IP Right Grant
- 1989-05-15 EP EP89906938A patent/EP0561765B1/de not_active Expired - Lifetime
- 1989-05-15 DE DE68928870T patent/DE68928870D1/de not_active Expired - Lifetime
- 1989-05-15 JP JP1506466A patent/JPH03504657A/ja active Pending
-
1997
- 1997-10-22 JP JP9289893A patent/JPH10150083A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
EP0561765A4 (de) | 1992-05-07 |
EP0864870A3 (de) | 2000-07-19 |
DE68928870D1 (de) | 1999-01-14 |
JPH03504657A (ja) | 1991-10-09 |
EP0561765A1 (de) | 1993-09-29 |
BR8907190A (pt) | 1991-03-05 |
EP0864870A2 (de) | 1998-09-16 |
JPH10150083A (ja) | 1998-06-02 |
EP0561765B1 (de) | 1998-12-02 |
US4924589A (en) | 1990-05-15 |
WO1989011659A1 (en) | 1989-11-30 |
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