ATE150585T1 - Verfahren zur herstellung einer halbleitervorrichtung mit einer verdrahtungsstruktur hoher dichte - Google Patents

Verfahren zur herstellung einer halbleitervorrichtung mit einer verdrahtungsstruktur hoher dichte

Info

Publication number
ATE150585T1
ATE150585T1 AT91304829T AT91304829T ATE150585T1 AT E150585 T1 ATE150585 T1 AT E150585T1 AT 91304829 T AT91304829 T AT 91304829T AT 91304829 T AT91304829 T AT 91304829T AT E150585 T1 ATE150585 T1 AT E150585T1
Authority
AT
Austria
Prior art keywords
semiconductor device
groove
hole
wiring structure
producing
Prior art date
Application number
AT91304829T
Other languages
English (en)
Inventor
Fumio Murooka
Tetsuo Asaba
Shigeyuki Matsumoto
Osamu Ikeda
Toshihiko Ichise
Yukihiko Sakashita
Shunsuke Inoue
Original Assignee
Canon Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Kk filed Critical Canon Kk
Application granted granted Critical
Publication of ATE150585T1 publication Critical patent/ATE150585T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67167—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers surrounding a central transfer chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67173—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers in-line arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67745—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber characterized by movements or sequence of movements of transfer devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
AT91304829T 1990-05-31 1991-05-29 Verfahren zur herstellung einer halbleitervorrichtung mit einer verdrahtungsstruktur hoher dichte ATE150585T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP13961690 1990-05-31
JP13962190 1990-05-31
JP13962090 1990-05-31

Publications (1)

Publication Number Publication Date
ATE150585T1 true ATE150585T1 (de) 1997-04-15

Family

ID=27317903

Family Applications (1)

Application Number Title Priority Date Filing Date
AT91304829T ATE150585T1 (de) 1990-05-31 1991-05-29 Verfahren zur herstellung einer halbleitervorrichtung mit einer verdrahtungsstruktur hoher dichte

Country Status (4)

Country Link
US (1) US5614439A (de)
EP (1) EP0460857B1 (de)
AT (1) ATE150585T1 (de)
DE (1) DE69125210T2 (de)

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Publication number Priority date Publication date Assignee Title
JP2934353B2 (ja) * 1992-06-24 1999-08-16 三菱電機株式会社 半導体装置およびその製造方法
JPH07221174A (ja) * 1993-12-10 1995-08-18 Canon Inc 半導体装置及びその製造方法
US5665644A (en) 1995-11-03 1997-09-09 Micron Technology, Inc. Semiconductor processing method of forming electrically conductive interconnect lines and integrated circuitry
US6004839A (en) * 1996-01-17 1999-12-21 Nec Corporation Semiconductor device with conductive plugs
US6091150A (en) * 1996-09-03 2000-07-18 Micron Technology, Inc. Integrated circuitry comprising electrically insulative material over interconnect line tops, sidewalls and bottoms
JPH10125777A (ja) * 1996-10-17 1998-05-15 Nec Corp 半導体装置の製造方法
TW571373B (en) 1996-12-04 2004-01-11 Seiko Epson Corp Semiconductor device, circuit substrate, and electronic machine
KR19980044215A (ko) * 1996-12-06 1998-09-05 문정환 반도체소자의 배선구조 및 그 형성방법
US5920081A (en) * 1997-04-25 1999-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Structure of a bond pad to prevent testing probe pin contamination
US6332835B1 (en) 1997-11-20 2001-12-25 Canon Kabushiki Kaisha Polishing apparatus with transfer arm for moving polished object without drying it
US6388198B1 (en) * 1999-03-09 2002-05-14 International Business Machines Corporation Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality
JP4752108B2 (ja) * 2000-12-08 2011-08-17 ソニー株式会社 半導体装置およびその製造方法
DE102005045057A1 (de) * 2005-09-21 2007-03-22 Infineon Technologies Ag Integrierte Schaltungsanordnung mit mehreren Leitstrukturlagen und Koaxialleitung sowie Verfahren
DE102005045056B4 (de) * 2005-09-21 2007-06-21 Infineon Technologies Ag Integrierte Schaltungsanordnung mit mehreren Leitstrukturlagen und Kondensator
DE102005045059B4 (de) * 2005-09-21 2011-05-19 Infineon Technologies Ag Integrierte Schaltungsanordnung mit mehreren Leitstrukturlagen und Spule sowie Verfahren zur Herstellung

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FR2461360A1 (fr) * 1979-07-10 1981-01-30 Thomson Csf Procede de fabrication d'un transistor a effet de champ du type dmos a fonctionnement vertical et transistor obtenu par ce procede
JPS59154040A (ja) * 1983-02-22 1984-09-03 Toshiba Corp 半導体装置の製造方法
IL86162A (en) * 1988-04-25 1991-11-21 Zvi Orbach Customizable semiconductor devices
US5084413A (en) * 1986-04-15 1992-01-28 Matsushita Electric Industrial Co., Ltd. Method for filling contact hole
JP2579937B2 (ja) * 1987-04-15 1997-02-12 株式会社東芝 電子回路装置およびその製造方法
US4776087A (en) * 1987-04-27 1988-10-11 International Business Machines Corporation VLSI coaxial wiring structure
JPH0611044B2 (ja) * 1987-05-07 1994-02-09 日本電気株式会社 半導体装置の製造方法
JP2621287B2 (ja) * 1988-01-29 1997-06-18 三菱電機株式会社 多層配線層の形成方法
JPH01235254A (ja) * 1988-03-15 1989-09-20 Nec Corp 半導体装置及びその製造方法
US4977105A (en) * 1988-03-15 1990-12-11 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing interconnection structure in semiconductor device
JPH01248643A (ja) * 1988-03-30 1989-10-04 Seiko Epson Corp 半導体集積回路装置の製造方法
JPH021928A (ja) * 1988-06-10 1990-01-08 Toshiba Corp 半導体集積回路
NL8900010A (nl) * 1989-01-04 1990-08-01 Philips Nv Halfgeleiderinrichting en werkwijze voor het vervaardigen van een halfgeleiderinrichting.
US5060029A (en) * 1989-02-28 1991-10-22 Small Power Communication Systems Research Laboratories Co., Ltd. Step cut type insulated gate SIT having low-resistance electrode and method of manufacturing the same
JPH0750708B2 (ja) * 1989-04-26 1995-05-31 株式会社東芝 半導体装置
JP2765967B2 (ja) * 1989-07-26 1998-06-18 沖電気工業株式会社 半導体素子
PT95232B (pt) * 1989-09-09 1998-06-30 Canon Kk Processo de producao de uma pelicula de aluminio depositada
JP2721023B2 (ja) * 1989-09-26 1998-03-04 キヤノン株式会社 堆積膜形成法
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US5173442A (en) * 1990-07-23 1992-12-22 Microelectronics And Computer Technology Corporation Methods of forming channels and vias in insulating layers
JP3123092B2 (ja) * 1991-03-06 2001-01-09 日本電気株式会社 半導体装置の製造方法
US5286674A (en) * 1992-03-02 1994-02-15 Motorola, Inc. Method for forming a via structure and semiconductor device having the same
US5279988A (en) * 1992-03-31 1994-01-18 Irfan Saadat Process for making microcomponents integrated circuits

Also Published As

Publication number Publication date
EP0460857A3 (en) 1992-07-29
US5614439A (en) 1997-03-25
DE69125210D1 (de) 1997-04-24
EP0460857A2 (de) 1991-12-11
DE69125210T2 (de) 1997-08-07
EP0460857B1 (de) 1997-03-19

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