KR950007021A - 평탄화된 절연막을 갖는 반도체장치 - Google Patents

평탄화된 절연막을 갖는 반도체장치 Download PDF

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KR950007021A
KR950007021A KR1019940015706A KR19940015706A KR950007021A KR 950007021 A KR950007021 A KR 950007021A KR 1019940015706 A KR1019940015706 A KR 1019940015706A KR 19940015706 A KR19940015706 A KR 19940015706A KR 950007021 A KR950007021 A KR 950007021A
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insulating film
sir
semiconductor device
manufacturing
wiring pattern
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KR0135576B1 (en
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히데토시 니시오
타카코 후루세
유미코 하마다
히로유끼 우에수기
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세끼자와 다다시
후지쓰 가부시끼가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
    • H01L21/02222—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen the compound being a silazane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • H01L21/3121—Layers comprising organo-silicon compounds
    • H01L21/3125—Layers comprising organo-silicon compounds layers comprising silazane compounds

Abstract

표면에 요철을 갖는 반도체기판을 준비하는 공정과; 실라잔결합을 하는 유기실리콘과 산화제를 사용하여 프라즈마를 발생시켜 프라즈마화학기상퇴적에 의해 반도체기판상에 평탄화절연막을 퇴적하는 공정을 포함하는 반도체 장치의제조방법. 유기실리콘은 HMCTSZ일 수 있으며 퇴적중의 기판온도는 100℃이하, 예를 들어 50℃가 바람직하다.

Description

평탄화된 절연막을 갖는 반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A도 및 제1B도는 본 발명의 기본 실시예에 의한 반도체장치의 제조방법을 설명하기 위한 단면도 및 블록도,
제2A도∼제2D도는 본 발명의 실시예에 사용하는 유기실리콘의 구조를 나타낸 개략도.

Claims (16)

  1. 표면에 요철을 갖는 반도체기판을 준비하는 공정과; 실라잔결합을 갖는 유기실리콘과 산화제를 사용하여 플라즈마를 발생시켜 플라즈마 화학기상퇴적(CVD)에 의해 상기 반도체기판상에 요철을 평탄화하는 평탄화절연막을 퇴적하는 공정을 포함하는 절연막을 갖는 반도체장치의 제조방법.
  2. 제1항에 있어서, 상기 유기실리콘이 시클로실라잔 결합을 갖는 반도체장치의 제조방법.
  3. 제1항에 있어서, 상기 유기실리콘이 (SiR3)2NR, (SiR2NR)3, (SiR2NR)4가, (여기에는 R은 페닐기, 비닐기, CnH2n+1(n=0, 또는 정수임)중의 적어도 1종인 반도체장치의 제조방법.
  4. 제1항에 있어서, 상기 산화제가 O2,N2O, NO 중의 적어도 1종인 반도체장치의 제조방법.
  5. 제1항에 있어서, 상기 퇴적공정에서 NH3또는NF3의 첨가시켜 플라즈마를 발생시키는 반도체장치의 제조방법.
  6. 제1항에 있어서, 상기 반도체기판을 준비하는 공정이 기판상에 배선패턴을 형성하는 공정을 더 포함하는 반도체장치의 제조방법.
  7. 제6항에 있어서, 상기 반도체기판을 준비하는 상기 공정이 CVD에 의해 배선패턴상에 형상이 동일한 절연막을 형성하는 공정을 더 포함하는 반도체장치의 제조방법.
  8. 제1항에 있어서, 상기 평탄화절연막을 형성하는 상기 공정을 약 100℃이하의 기판온도에서 실시하는 반도체장치의 제조방법.
  9. 제1항에 있어서, 적어도 상기 블록부상의 상기 평탄화절연막을 에치 백하는 공정을 더 포함하는 반도체장치의 제조방법.
  10. 제6항에 있어서, 상기 평탄화 절연막에 접촉구멍을 형성시켜 상기 배선패턴을 노출하는 공정과; 상기 접촉구멍에 노출된 상기 배선패턴상에 금속을 선택성장시키는 공정을 더 포함하는 반도체장치의 제조방법.
  11. 제3항에 있어서, 상기 반도체기판을 준비하는 상기 공정이 CVD에 의해 배선패턴상에 형상이 동일한 절연막을 형성하는 공정을 더 포함하는 반도체장치의 제조방법.
  12. 제8항에 있어서, 상기 반도체기판을 준비하는 상기 공정이 CVD에 의해 배선패턴상에 형상이 동일한 절연막을 형성하는 공정을 더 포함하는 반도체장치의 제조방법.
  13. 제10항에 있어서, 상기 반도체 기판을 준비하는 상기 공정이 CVD에 의해 배선패턴상에 형상이 동일한 절연막을 형성하는 공정을 더 포함하는 반도체장치의 제조방법.
  14. 산소원자와 (SiR3)2NR, (SiR2NR)3, (SiR2NR)4가, (여기에는 R은 CnH2n+1(n=0, 1, 2, 3, …n임)로 표시되는 원자단을 함유하는 혼합가스를 반응시켜 플라즈마를 발생시키고, 플라즈마화학기상 퇴적법을 사용하는 공정으로 된 절연막의 퇴적방법.
  15. 제14항에 있어서, 상기 혼합가스는 암모늄이 첨가된 절연막의 퇴적방법.
  16. 산소원자와 (SiR3)2NR, (SiR2NR)3, (SiR2NR)4가, (여기에는 R은 메틸기, 페닐기, H기임)로 표시되는 원자단을 함유하는 혼합가스를 반응시켜 플라즈마를 발생시키고, 플라즈마화학기상퇴적법을 사용하는 공정으로 된 절연막의 퇴적방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR94015706A 1993-08-26 1994-06-30 Semiconductor device having planerizing insulating film KR0135576B1 (en)

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JP93-211200 1993-08-26
JP21120093 1993-08-26

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