EP0460857A3 - Semiconductor device with a high density wiring structure and method for producing the same - Google Patents
Semiconductor device with a high density wiring structure and method for producing the same Download PDFInfo
- Publication number
- EP0460857A3 EP0460857A3 EP19910304829 EP91304829A EP0460857A3 EP 0460857 A3 EP0460857 A3 EP 0460857A3 EP 19910304829 EP19910304829 EP 19910304829 EP 91304829 A EP91304829 A EP 91304829A EP 0460857 A3 EP0460857 A3 EP 0460857A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- semiconductor device
- groove
- hole
- wiring structure
- producing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000009413 insulation Methods 0.000 abstract 3
- 239000004020 conductor Substances 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 229910000838 Al alloy Inorganic materials 0.000 abstract 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract 1
- -1 alkylaluminum hydride Chemical class 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 238000000151 deposition Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 abstract 1
- 239000001257 hydrogen Substances 0.000 abstract 1
- 229910052739 hydrogen Inorganic materials 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
- H01L21/67167—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers surrounding a central transfer chamber
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
- H01L21/67173—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers in-line arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
- H01L21/67745—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber characterized by movements or sequence of movements of transfer devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/05—Etch and refill
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13962190 | 1990-05-31 | ||
JP13962090 | 1990-05-31 | ||
JP139616/90 | 1990-05-31 | ||
JP139620/90 | 1990-05-31 | ||
JP139621/90 | 1990-05-31 | ||
JP13961690 | 1990-05-31 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0460857A2 EP0460857A2 (en) | 1991-12-11 |
EP0460857A3 true EP0460857A3 (en) | 1992-07-29 |
EP0460857B1 EP0460857B1 (en) | 1997-03-19 |
Family
ID=27317903
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP91304829A Expired - Lifetime EP0460857B1 (en) | 1990-05-31 | 1991-05-29 | Method for producing a semiconductor device with a high density wiring structure |
Country Status (4)
Country | Link |
---|---|
US (1) | US5614439A (en) |
EP (1) | EP0460857B1 (en) |
AT (1) | ATE150585T1 (en) |
DE (1) | DE69125210T2 (en) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2934353B2 (en) * | 1992-06-24 | 1999-08-16 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
JPH07221174A (en) * | 1993-12-10 | 1995-08-18 | Canon Inc | Semiconductor device and manufacturing method thereof |
US5665644A (en) * | 1995-11-03 | 1997-09-09 | Micron Technology, Inc. | Semiconductor processing method of forming electrically conductive interconnect lines and integrated circuitry |
US6004839A (en) * | 1996-01-17 | 1999-12-21 | Nec Corporation | Semiconductor device with conductive plugs |
US6091150A (en) * | 1996-09-03 | 2000-07-18 | Micron Technology, Inc. | Integrated circuitry comprising electrically insulative material over interconnect line tops, sidewalls and bottoms |
JPH10125777A (en) * | 1996-10-17 | 1998-05-15 | Nec Corp | Manufacture of semiconductor device |
TW571373B (en) * | 1996-12-04 | 2004-01-11 | Seiko Epson Corp | Semiconductor device, circuit substrate, and electronic machine |
KR19980044215A (en) * | 1996-12-06 | 1998-09-05 | 문정환 | Wiring Structure of Semiconductor Device and Formation Method |
US5920081A (en) * | 1997-04-25 | 1999-07-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure of a bond pad to prevent testing probe pin contamination |
US6332835B1 (en) | 1997-11-20 | 2001-12-25 | Canon Kabushiki Kaisha | Polishing apparatus with transfer arm for moving polished object without drying it |
US6388198B1 (en) * | 1999-03-09 | 2002-05-14 | International Business Machines Corporation | Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality |
JP4752108B2 (en) * | 2000-12-08 | 2011-08-17 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
DE102005045056B4 (en) * | 2005-09-21 | 2007-06-21 | Infineon Technologies Ag | Integrated circuit arrangement with multiple conductive structure layers and capacitor |
DE102005045059B4 (en) * | 2005-09-21 | 2011-05-19 | Infineon Technologies Ag | Integrated circuit arrangement with several Leitstrukturlagen and coil and method for manufacturing |
DE102005045057A1 (en) * | 2005-09-21 | 2007-03-22 | Infineon Technologies Ag | Integrated circuit especially for coaxial leads has three conductive traces spaced above substrate that are up to ten times longer than their width |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0333132A2 (en) * | 1988-03-15 | 1989-09-20 | Nec Corporation | Semiconductor device having multilayered wiring structure with a small parasitic capacitance |
EP0353426A2 (en) * | 1988-06-10 | 1990-02-07 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device comprising conductive layers |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2461360A1 (en) * | 1979-07-10 | 1981-01-30 | Thomson Csf | METHOD FOR MANUFACTURING A VERTICALLY OPERATING DMOS-TYPE FIELD EFFECT TRANSISTOR AND TRANSISTOR OBTAINED THEREBY |
JPS59154040A (en) * | 1983-02-22 | 1984-09-03 | Toshiba Corp | Manufacture of semiconductor device |
IL86162A (en) * | 1988-04-25 | 1991-11-21 | Zvi Orbach | Customizable semiconductor devices |
US5084413A (en) * | 1986-04-15 | 1992-01-28 | Matsushita Electric Industrial Co., Ltd. | Method for filling contact hole |
JP2579937B2 (en) * | 1987-04-15 | 1997-02-12 | 株式会社東芝 | Electronic circuit device and method of manufacturing the same |
US4776087A (en) * | 1987-04-27 | 1988-10-11 | International Business Machines Corporation | VLSI coaxial wiring structure |
JPH0611044B2 (en) * | 1987-05-07 | 1994-02-09 | 日本電気株式会社 | Method for manufacturing semiconductor device |
JP2621287B2 (en) * | 1988-01-29 | 1997-06-18 | 三菱電機株式会社 | Method of forming multilayer wiring layer |
US4977105A (en) * | 1988-03-15 | 1990-12-11 | Mitsubishi Denki Kabushiki Kaisha | Method for manufacturing interconnection structure in semiconductor device |
JPH01248643A (en) * | 1988-03-30 | 1989-10-04 | Seiko Epson Corp | Manufacture of semiconductor integrated circuit device |
NL8900010A (en) * | 1989-01-04 | 1990-08-01 | Philips Nv | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE. |
US5060029A (en) * | 1989-02-28 | 1991-10-22 | Small Power Communication Systems Research Laboratories Co., Ltd. | Step cut type insulated gate SIT having low-resistance electrode and method of manufacturing the same |
JPH0750708B2 (en) * | 1989-04-26 | 1995-05-31 | 株式会社東芝 | Semiconductor device |
JP2765967B2 (en) * | 1989-07-26 | 1998-06-18 | 沖電気工業株式会社 | Semiconductor element |
PT95232B (en) * | 1989-09-09 | 1998-06-30 | Canon Kk | PRODUCTION PROCESS OF A DEPOSITED ALUMINUM FILM |
EP0420594B1 (en) * | 1989-09-26 | 1996-04-17 | Canon Kabushiki Kaisha | Process for forming metal deposited film containing aluminium as main component by use of alkyl aluminium hydride |
JP2721023B2 (en) * | 1989-09-26 | 1998-03-04 | キヤノン株式会社 | Deposition film formation method |
DE69026669T2 (en) * | 1989-09-26 | 1996-10-17 | Canon Kk | Process for producing a deposited layer using alkyl aluminum hydride and process for producing a semiconductor device |
US5132774A (en) * | 1990-02-05 | 1992-07-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including interlayer insulating film |
US5173442A (en) * | 1990-07-23 | 1992-12-22 | Microelectronics And Computer Technology Corporation | Methods of forming channels and vias in insulating layers |
JP3123092B2 (en) * | 1991-03-06 | 2001-01-09 | 日本電気株式会社 | Method for manufacturing semiconductor device |
US5286674A (en) * | 1992-03-02 | 1994-02-15 | Motorola, Inc. | Method for forming a via structure and semiconductor device having the same |
US5279988A (en) * | 1992-03-31 | 1994-01-18 | Irfan Saadat | Process for making microcomponents integrated circuits |
-
1991
- 1991-05-29 DE DE69125210T patent/DE69125210T2/en not_active Expired - Fee Related
- 1991-05-29 AT AT91304829T patent/ATE150585T1/en active
- 1991-05-29 EP EP91304829A patent/EP0460857B1/en not_active Expired - Lifetime
-
1995
- 1995-02-21 US US08/393,928 patent/US5614439A/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0333132A2 (en) * | 1988-03-15 | 1989-09-20 | Nec Corporation | Semiconductor device having multilayered wiring structure with a small parasitic capacitance |
EP0353426A2 (en) * | 1988-06-10 | 1990-02-07 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device comprising conductive layers |
Non-Patent Citations (6)
Title |
---|
APPLIED PHYSICS LETTERS, vol. 57, no. 12, 17 September 1990, NEW YORK (US) pages 1221-1223; & TSUBOUCHI ET AL: "Complete Planarization of via holes wish aluminium by selective and non-selective chemical vapour deposition" * |
IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, vol. 10, no. 3, September 1987, NEW YORK (US) pages 314-320; KWON AND PEASE: "Closely packed Microstrip Lines as Very High Speed Chip-to-Chip Interconnects" * |
JAPANESE JOURNAL OF APPLIED PHYSICS, SUPPLEMENTS: EXTENDED ABSTRACTS OF THE 21ST CONFERENCE ON SOLID STATE DEVICES AND MATERIALS 1989, TOKYO (JA) pages 29-32; SEKIGUCHI ET AL: "Epitaxial Growth of Al (100) on S1 (100) by Gas-Temperature-Controlled Chemical Vapor Deposition" * |
PATENT ABSTRACT OF JAPAN, vol. 13, no. 103 (E-725)10 March 1989; & JP-A-63 275 142 (NEC) 11 November 1988 * |
PATENT ABSTRACTS OF JAPAN, vol. 13, no. 486 (E-840)6 November 1989; & JP-A-1 194 440 (MITSUBISHI ELECTRIC) 4 August 1989 * |
PATENT ABSTRACTS OF JAPAN, vol. 13, no. 594 (E-867)27 December 1989; & JP-A-1 248 643 (SEIKO EPSON) 4 October 1989 * |
Also Published As
Publication number | Publication date |
---|---|
DE69125210T2 (en) | 1997-08-07 |
US5614439A (en) | 1997-03-25 |
EP0460857A2 (en) | 1991-12-11 |
DE69125210D1 (en) | 1997-04-24 |
ATE150585T1 (en) | 1997-04-15 |
EP0460857B1 (en) | 1997-03-19 |
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