AT516988A3 - Verfahren zum Beschichten eines Substrats - Google Patents
Verfahren zum Beschichten eines SubstratsInfo
- Publication number
- AT516988A3 AT516988A3 ATA50292/2016A AT502922016A AT516988A3 AT 516988 A3 AT516988 A3 AT 516988A3 AT 502922016 A AT502922016 A AT 502922016A AT 516988 A3 AT516988 A3 AT 516988A3
- Authority
- AT
- Austria
- Prior art keywords
- substrate
- vias
- coating
- insulating material
- electrically insulating
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title abstract 6
- 239000011248 coating agent Substances 0.000 title abstract 4
- 238000000576 coating method Methods 0.000 title abstract 3
- 238000000034 method Methods 0.000 title abstract 2
- 239000012777 electrically insulating material Substances 0.000 abstract 2
- 230000001143 conditioned effect Effects 0.000 abstract 1
- 239000011810 insulating material Substances 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02307—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a liquid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
- H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/6715—Apparatus for applying a liquid, a resin, an ink or the like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Application Of Or Painting With Fluid Materials (AREA)
- Formation Of Insulating Films (AREA)
- Other Surface Treatments For Metallic Materials (AREA)
Abstract
Die Erfindung betrifft das Beschichten von Substraten, die mit Vias versehen sind. Hierbei tritt das Problem auf, dass durch das Beschichtungsmittel Luft in den Vias eingeschlossen wird. Dies ist nachteilig hinsichtlich der Planheit der Oberfläche. Um dieses Problem zu lösen, ist erfindungsgemäß ein Verfahren zum Beschichten eines Substrats vorgesehen, das mit Vias versehen ist, wobei die folgenden Schritte ausgeführt werden: das Substrat wird konditioniert; und das Substrat (10) wird so mit einem elektrisch isolierenden Material beschichtet, dass im Substrat vorhandene Vias vollständig mit dem elektrisch isolierenden Material ausgefüllt werden, so dass das isolierende Material eine möglichst ebene Oberfläche hat.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL2014598A NL2014598B1 (en) | 2015-04-08 | 2015-04-08 | Method for coating a substrate. |
Publications (3)
Publication Number | Publication Date |
---|---|
AT516988A2 AT516988A2 (de) | 2016-10-15 |
AT516988A3 true AT516988A3 (de) | 2018-04-15 |
AT516988B1 AT516988B1 (de) | 2022-10-15 |
Family
ID=53718091
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ATA50292/2016A AT516988B1 (de) | 2015-04-08 | 2016-04-08 | Verfahren zum Beschichten eines Substrats |
Country Status (9)
Country | Link |
---|---|
US (1) | US9799554B2 (de) |
JP (1) | JP6700925B2 (de) |
KR (1) | KR102530371B1 (de) |
CN (1) | CN106057639B (de) |
AT (1) | AT516988B1 (de) |
CH (1) | CH710963A8 (de) |
DE (1) | DE102016106400A1 (de) |
NL (1) | NL2014598B1 (de) |
TW (1) | TWI701085B (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL2019096B1 (en) * | 2017-06-20 | 2018-12-27 | Suss Microtec Lithography Gmbh | Nozzle tip adapter, nozzle assembly as well as nozzle |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070032061A1 (en) * | 2005-08-05 | 2007-02-08 | Farnworth Warren M | Methods of forming through-wafer interconnects and structures resulting therefrom |
EP1840940A1 (de) * | 2006-03-28 | 2007-10-03 | Erich Dipl.-Ing. Thallner | Vorrichtung und Verfahren zum Beschichten eines mikro- und/oder nanostrukturierten Struktursubstrats |
WO2008123049A1 (ja) * | 2007-03-30 | 2008-10-16 | Jsr Corporation | 被膜形成方法及びそれに用いる樹脂組成物、絶縁膜を有する構造体及びその製造方法並びに電子部品 |
DE102011054825A1 (de) * | 2010-11-03 | 2012-05-03 | Infineon Technologies Ag | Ein Halbleiterbauelement und ein Verfahren zum Herstellen eines Halbleiterbauelements |
WO2014170928A1 (ja) * | 2013-04-18 | 2014-10-23 | 国立大学法人東北大学 | マイクロ空室の内壁面処理方法 |
Family Cites Families (29)
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JPH04245629A (ja) * | 1991-01-31 | 1992-09-02 | Texas Instr Japan Ltd | 半導体装置の絶縁膜形成方法および半導体装置 |
JP3069762B2 (ja) * | 1993-03-25 | 2000-07-24 | 東京エレクトロン株式会社 | 塗布膜形成方法及びその装置 |
TW276353B (de) * | 1993-07-15 | 1996-05-21 | Hitachi Seisakusyo Kk | |
JPH07100429A (ja) * | 1993-10-01 | 1995-04-18 | Toray Ind Inc | ポリマ溶液の塗布方法 |
JP2967734B2 (ja) * | 1996-10-18 | 1999-10-25 | 日本電気株式会社 | 薄膜の形成方法 |
JPH10214892A (ja) * | 1997-01-30 | 1998-08-11 | Sony Corp | 半導体装置の製造方法 |
JPH11251312A (ja) * | 1998-03-06 | 1999-09-17 | Matsushita Electron Corp | 半導体装置の製造方法 |
JPH11330674A (ja) * | 1998-05-07 | 1999-11-30 | Ngk Spark Plug Co Ltd | 配線基板の製造方法 |
JP3598462B2 (ja) * | 2000-05-09 | 2004-12-08 | 東京エレクトロン株式会社 | 乾燥方法及び乾燥装置 |
JP2002043420A (ja) * | 2000-07-24 | 2002-02-08 | Mitsubishi Electric Corp | 半導体装置の製造方法及び製造装置 |
JP4408006B2 (ja) * | 2001-06-28 | 2010-02-03 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
FR2830683A1 (fr) * | 2001-10-10 | 2003-04-11 | St Microelectronics Sa | Realisation d'inductance et de via dans un circuit monolithique |
JP2003133723A (ja) * | 2001-10-25 | 2003-05-09 | Matsushita Electric Ind Co Ltd | 導電性ペースト充填方法および導電性ペースト充填装置 |
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KR100756809B1 (ko) * | 2006-04-28 | 2007-09-07 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
JP5168933B2 (ja) * | 2007-02-16 | 2013-03-27 | 富士通株式会社 | 化合物半導体装置の製造方法 |
US8034702B2 (en) * | 2007-08-16 | 2011-10-11 | Micron Technology, Inc. | Methods of forming through substrate interconnects |
EP2201600B1 (de) * | 2007-10-15 | 2019-01-02 | IMEC vzw | Verfahren zur herstellung von substratdurchkontaktierungen |
KR20090045669A (ko) * | 2007-11-02 | 2009-05-08 | 주식회사 하이닉스반도체 | 소자분리막 제조 방법 |
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DE102008045068A1 (de) | 2008-08-29 | 2010-03-04 | Suss Microtec Lithography Gmbh | Verfahren zur Resist-Beschichtung einer Vertiefung in der Oberfläche eines Substrats, insbesondere eines Wafers |
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-
2015
- 2015-04-08 NL NL2014598A patent/NL2014598B1/en active
-
2016
- 2016-04-07 KR KR1020160042827A patent/KR102530371B1/ko active IP Right Grant
- 2016-04-07 TW TW105110914A patent/TWI701085B/zh active
- 2016-04-07 DE DE102016106400.9A patent/DE102016106400A1/de active Pending
- 2016-04-07 CH CH00450/16A patent/CH710963A8/de not_active Application Discontinuation
- 2016-04-08 US US15/093,834 patent/US9799554B2/en active Active
- 2016-04-08 JP JP2016077941A patent/JP6700925B2/ja active Active
- 2016-04-08 CN CN201610217798.4A patent/CN106057639B/zh active Active
- 2016-04-08 AT ATA50292/2016A patent/AT516988B1/de active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070032061A1 (en) * | 2005-08-05 | 2007-02-08 | Farnworth Warren M | Methods of forming through-wafer interconnects and structures resulting therefrom |
EP1840940A1 (de) * | 2006-03-28 | 2007-10-03 | Erich Dipl.-Ing. Thallner | Vorrichtung und Verfahren zum Beschichten eines mikro- und/oder nanostrukturierten Struktursubstrats |
WO2008123049A1 (ja) * | 2007-03-30 | 2008-10-16 | Jsr Corporation | 被膜形成方法及びそれに用いる樹脂組成物、絶縁膜を有する構造体及びその製造方法並びに電子部品 |
DE102011054825A1 (de) * | 2010-11-03 | 2012-05-03 | Infineon Technologies Ag | Ein Halbleiterbauelement und ein Verfahren zum Herstellen eines Halbleiterbauelements |
WO2014170928A1 (ja) * | 2013-04-18 | 2014-10-23 | 国立大学法人東北大学 | マイクロ空室の内壁面処理方法 |
Also Published As
Publication number | Publication date |
---|---|
NL2014598A (en) | 2016-10-12 |
TWI701085B (zh) | 2020-08-11 |
US9799554B2 (en) | 2017-10-24 |
KR102530371B1 (ko) | 2023-05-09 |
JP6700925B2 (ja) | 2020-05-27 |
DE102016106400A1 (de) | 2016-10-13 |
KR20160120678A (ko) | 2016-10-18 |
CH710963A8 (de) | 2016-12-30 |
CN106057639A (zh) | 2016-10-26 |
AT516988A2 (de) | 2016-10-15 |
AT516988B1 (de) | 2022-10-15 |
JP2017018941A (ja) | 2017-01-26 |
US20160300759A1 (en) | 2016-10-13 |
TW201707802A (zh) | 2017-03-01 |
CH710963A2 (de) | 2016-10-14 |
NL2014598B1 (en) | 2017-01-20 |
CN106057639B (zh) | 2021-09-21 |
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