CH710963A8 - Verfahren zum Beschichten eines Substrats. - Google Patents

Verfahren zum Beschichten eines Substrats. Download PDF

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Publication number
CH710963A8
CH710963A8 CH00450/16A CH4502016A CH710963A8 CH 710963 A8 CH710963 A8 CH 710963A8 CH 00450/16 A CH00450/16 A CH 00450/16A CH 4502016 A CH4502016 A CH 4502016A CH 710963 A8 CH710963 A8 CH 710963A8
Authority
CH
Switzerland
Prior art keywords
substrate
coating
vias
flatness
conditioned
Prior art date
Application number
CH00450/16A
Other languages
English (en)
Other versions
CH710963A2 (de
Inventor
Fischer Katrin
Palitschka Florian
Robert Southworth Darren
Whitney William
Original Assignee
Suss Microtec Lithography Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suss Microtec Lithography Gmbh filed Critical Suss Microtec Lithography Gmbh
Publication of CH710963A2 publication Critical patent/CH710963A2/de
Publication of CH710963A8 publication Critical patent/CH710963A8/de

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02307—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a liquid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/6715—Apparatus for applying a liquid, a resin, an ink or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Application Of Or Painting With Fluid Materials (AREA)
  • Formation Of Insulating Films (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)

Abstract

Die Erfindung betrifft das Beschichten von Substraten (10), die mit Vias (16) versehen sind. Hierbei tritt das Problem auf, dass durch das Beschichtungsmittel Luft in den Vias eingeschlossen wird. Dies ist nachteilig hinsichtlich der Planheit der Oberfläche. Um dieses Problem zu lösen, ist erfindungsgemäss ein Verfahren zum Beschichten eines Substrats vorgesehen, das mit Vias versehen ist, wobei die folgenden Schritte ausgeführt werden: das Substrat wird konditioniert; und das Substrat wird mit einem isolierenden Material (20) beschichtet.
CH00450/16A 2015-04-08 2016-04-07 Verfahren zum Beschichten eines Substrats. CH710963A8 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL2014598A NL2014598B1 (en) 2015-04-08 2015-04-08 Method for coating a substrate.

Publications (2)

Publication Number Publication Date
CH710963A2 CH710963A2 (de) 2016-10-14
CH710963A8 true CH710963A8 (de) 2016-12-30

Family

ID=53718091

Family Applications (1)

Application Number Title Priority Date Filing Date
CH00450/16A CH710963A8 (de) 2015-04-08 2016-04-07 Verfahren zum Beschichten eines Substrats.

Country Status (9)

Country Link
US (1) US9799554B2 (de)
JP (1) JP6700925B2 (de)
KR (1) KR102530371B1 (de)
CN (1) CN106057639B (de)
AT (1) AT516988B1 (de)
CH (1) CH710963A8 (de)
DE (1) DE102016106400A1 (de)
NL (1) NL2014598B1 (de)
TW (1) TWI701085B (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL2019096B1 (en) * 2017-06-20 2018-12-27 Suss Microtec Lithography Gmbh Nozzle tip adapter, nozzle assembly as well as nozzle

Family Cites Families (34)

* Cited by examiner, † Cited by third party
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JP3069762B2 (ja) * 1993-03-25 2000-07-24 東京エレクトロン株式会社 塗布膜形成方法及びその装置
TW276353B (de) * 1993-07-15 1996-05-21 Hitachi Seisakusyo Kk
JPH07100429A (ja) * 1993-10-01 1995-04-18 Toray Ind Inc ポリマ溶液の塗布方法
JP2967734B2 (ja) 1996-10-18 1999-10-25 日本電気株式会社 薄膜の形成方法
JPH10214892A (ja) * 1997-01-30 1998-08-11 Sony Corp 半導体装置の製造方法
JPH11251312A (ja) * 1998-03-06 1999-09-17 Matsushita Electron Corp 半導体装置の製造方法
JPH11330674A (ja) * 1998-05-07 1999-11-30 Ngk Spark Plug Co Ltd 配線基板の製造方法
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JP2002043420A (ja) * 2000-07-24 2002-02-08 Mitsubishi Electric Corp 半導体装置の製造方法及び製造装置
JP4408006B2 (ja) * 2001-06-28 2010-02-03 富士通マイクロエレクトロニクス株式会社 半導体装置およびその製造方法
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JP2003133723A (ja) * 2001-10-25 2003-05-09 Matsushita Electric Ind Co Ltd 導電性ペースト充填方法および導電性ペースト充填装置
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Also Published As

Publication number Publication date
AT516988B1 (de) 2022-10-15
US9799554B2 (en) 2017-10-24
CN106057639B (zh) 2021-09-21
TWI701085B (zh) 2020-08-11
DE102016106400A1 (de) 2016-10-13
CH710963A2 (de) 2016-10-14
JP2017018941A (ja) 2017-01-26
NL2014598B1 (en) 2017-01-20
JP6700925B2 (ja) 2020-05-27
NL2014598A (en) 2016-10-12
US20160300759A1 (en) 2016-10-13
KR102530371B1 (ko) 2023-05-09
CN106057639A (zh) 2016-10-26
AT516988A3 (de) 2018-04-15
AT516988A2 (de) 2016-10-15
KR20160120678A (ko) 2016-10-18
TW201707802A (zh) 2017-03-01

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