WO2024119742A1 - 一种半导体器件及其制造方法 - Google Patents
一种半导体器件及其制造方法 Download PDFInfo
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- WO2024119742A1 WO2024119742A1 PCT/CN2023/098227 CN2023098227W WO2024119742A1 WO 2024119742 A1 WO2024119742 A1 WO 2024119742A1 CN 2023098227 W CN2023098227 W CN 2023098227W WO 2024119742 A1 WO2024119742 A1 WO 2024119742A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 85
- 239000010410 layer Substances 0.000 claims description 136
- 238000000034 method Methods 0.000 claims description 32
- 229910052751 metal Inorganic materials 0.000 claims description 24
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- 230000009467 reduction Effects 0.000 abstract description 2
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- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
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- 102100026388 L-amino-acid oxidase Human genes 0.000 description 5
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- 239000000463 material Substances 0.000 description 5
- 230000001105 regulatory effect Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 101000827703 Homo sapiens Polyphosphoinositide phosphatase Proteins 0.000 description 2
- 102100023591 Polyphosphoinositide phosphatase Human genes 0.000 description 2
- 101100012902 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) FIG2 gene Proteins 0.000 description 2
- 101100233916 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) KAR5 gene Proteins 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
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- 229910000314 transition metal oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
Definitions
- the present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same.
- resistive random access memory is one of the most promising next-generation non-volatile memories. Compared with traditional floating gate flash memory, it has obvious advantages in device structure, speed, scalability, and three-dimensional integration potential.
- the basic structure of RRAM is a metal-insulator-metal (MIM) structure, which mainly includes a bottom electrode, a resistive switching layer and a top electrode.
- MIM metal-insulator-metal
- the resistive switching layer is made of various oxide film materials, and can reversibly switch between different resistance states under the action of external voltage, current and other electrical signals. This reversible transition is mostly achieved through the formation and breaking of conductive filaments.
- the manufacturing method of the MIM structure is to deposit all the thin films in sequence and then use a mask to etch to obtain a resistive switching structure (R).
- the size of the resistive switching structure is defined by the mask, which has great limitations.
- the present application provides a semiconductor device and a method for manufacturing the same to at least solve the above technical problems.
- the first aspect of the present application provides a semiconductor device, comprising: a substrate, a fin and a resistive switching structure;
- the substrate has a plurality of first through holes, wherein the first surfaces of the first through holes are located on the lower surface of the substrate and are used to connect the first metal layer, and the second surfaces of the first through holes are located on the upper surface of the substrate;
- the fin is perpendicular to the upper surface of the substrate, and the lower surface of the fin overlaps with a partial area of the second surface of the first through hole;
- the resistive switching structure comprises: a bottom electrode, a resistive switching layer and a top electrode, wherein:
- the vertical portion of the bottom electrode is coated on the side wall of the fin, the first plane portion of the bottom electrode covers the second surface of the first through hole, the second plane portion of the bottom electrode covers the top of the fin, the lower end of the vertical portion of the bottom electrode is connected to the first plane portion thereof, and the upper end is connected to the second plane portion thereof;
- the vertical portion of the resistive layer is coated on the side wall of the vertical portion of the bottom electrode, the first plane portion of the resistive layer conformally covers the first plane portion of the bottom electrode and the upper surface of the substrate, the second plane portion of the resistive layer covers the second plane portion of the bottom electrode, the lower end of the vertical portion of the resistive layer is connected to the first plane portion thereof, and the upper end is connected to the second plane portion thereof;
- the vertical portion of the top electrode covers the side wall of the vertical portion of the resistive layer.
- the vertical portion of the top electrode is connected to the second metal layer through a second through hole or a wire groove.
- the planar portion of the top electrode covers the first planar portion of the resistive layer, and the lower end of the vertical portion of the top electrode is connected to the planar portion thereof.
- the communicating part of the top electrode is connected to the second metal layer through a second through hole or a wire groove.
- the upper surface of the vertical portion of the top electrode is flush with the upper surface of the second planar portion of the resistive layer.
- a second aspect of the present application provides a semiconductor device, comprising: a substrate, a fin, and a resistive switching structure, wherein:
- the substrate has a plurality of first through holes, wherein the first surfaces of the first through holes are located on the lower surface of the substrate and are used to connect the first metal layer, and the second surfaces of the first through holes are located on the upper surface of the substrate;
- the resistive switching structure comprises: a bottom electrode, a resistive switching layer and a top electrode, wherein:
- the vertical portion of the bottom electrode covers the sidewall of the fin, the planar portion of the bottom electrode covers the second surface of the first through hole, and the vertical portion and the planar portion of the bottom electrode are connected;
- the vertical portion of the resistive switching layer covers the side wall of the vertical portion of the bottom electrode.
- the planar portion of the bottom electrode conformally covers the planar portion of the bottom electrode and the upper surface of the substrate;
- the vertical portion of the top electrode covers the side wall of the vertical portion of the resistive switching layer, and the planar portion of the top electrode conformally covers the planar portion of the resistive switching layer, so that the top electrodes of two adjacent resistive switching structures are connected.
- the communicating part of the top electrode is connected to the second metal layer through a second through hole or a wire groove.
- top of the vertical portion of the top electrode, the top of the vertical portion of the resistive layer, the top of the vertical portion of the bottom electrode and the top of the fin are flush.
- a third aspect of the present application provides a method for manufacturing a semiconductor device, wherein a substrate has a plurality of first through holes, wherein a first surface of the first through holes is located on a lower surface of the substrate and is used to connect a first metal layer, and a second surface of the first through holes is located on an upper surface of the substrate, the method comprising:
- the resistive switching layer and the top electrode layer are deposited in sequence, and after a planarization treatment, the top electrode layer is etched to obtain the semiconductor device described in the first aspect.
- a fourth aspect of the present application provides a method for manufacturing a semiconductor device, wherein a substrate has a plurality of first through holes, wherein a first surface of the first through holes is located on a lower surface of the substrate and is used to connect a first metal layer, and a second surface of the first through holes is located on an upper surface of the substrate, the method comprising:
- the resistive switching layer and the top electrode layer are deposited in sequence and planarized to obtain the semiconductor device described in the second aspect.
- the above-mentioned fin-based resistive switching structure is a three-dimensional structure, and the size of its resistive switching region is calculated according to the area of the resistive switching region in the vertical direction. If the size of the resistive switching structure is to be adjusted, it is only necessary to adjust the height of the fin. The substrate area is irrelevant, and the resistive switching structure can be miniaturized while the size of the resistive switching area can be controlled.
- FIG1 is a schematic cross-sectional view of a first semiconductor device provided in Embodiment 1;
- FIG2 shows a schematic diagram of a second through hole or wire groove in the first semiconductor device provided in the first embodiment
- FIG3 shows a schematic cross-sectional view of a second semiconductor device provided in Embodiment 1;
- FIG4 shows a schematic diagram of a second through hole or wire groove in a second semiconductor device provided in Embodiment 1;
- FIG5 is a schematic diagram showing a semiconductor device implementing 1T2R according to the first embodiment
- FIG6 shows a schematic cross-sectional view of a semiconductor device provided in Embodiment 2.
- FIG7 is a schematic top view of a semiconductor device provided in Embodiment 2.
- FIG8 is a schematic diagram showing a second through hole or wire groove in a semiconductor device provided in the second embodiment
- FIG9 is a schematic diagram showing a semiconductor device implementing 1T1R according to the second embodiment.
- FIG10 is a schematic diagram showing a manufacturing process of a semiconductor device provided in Embodiment 1;
- FIG. 11 is a schematic diagram showing a manufacturing process of a semiconductor device provided in the second embodiment.
- first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as “first” or “second” may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of “plurality” is two or more, unless otherwise clearly and specifically defined.
- FIG1 is a cross-sectional view of the semiconductor device, including: a substrate 10, a fin 20 and a resistive switching structure, the resistive switching structure at least consisting of a bottom electrode 30, a resistive switching layer 40 and a top electrode 50. It should be noted that more functional layers can be added to the resistive switching structure in all examples of the present application according to requirements, and the present application does not limit this.
- the substrate 10 has a plurality of first through holes 11. As an example, only two first through holes are shown in FIG1 , and the number of through holes is not limited in this application.
- the first through hole 11 is filled with metal (e.g., copper), and its first surface (also called the first end surface or the first end) is located on the lower surface of the substrate 10 and connected to the first metal layer (M1), and the second surface (also called the second end surface or the second end) of the first through hole 11 is located on the upper surface of the substrate 10.
- metal e.g., copper
- M1 first metal layer
- the fin 20 is perpendicular to the upper surface of the substrate 10, and the lower surface of the fin overlaps with a portion of the second surface of the first through hole 11.
- the fin 20 is provided to support the resistive switching structure formed subsequently. In order to energize the resistive switching structure, the fin 20 cannot completely cover the second surface of the first through hole 11, and a portion of the second surface of the first through hole 11 needs to be reserved to communicate with the bottom electrode 30 of the resistive switching structure.
- the material of the fin 20 can be silicon nitride (SiN).
- the resistive switching structure includes: a bottom electrode 30, a resistive switching layer 40 and a top electrode 50, wherein:
- the bottom electrode 30 covers the fin 20 and the second surface of the first through hole 11 in a conformal manner.
- the vertical portion 31 of the bottom electrode 30 covers the side wall of the fin 20
- the first planar portion 32 of the bottom electrode 30 covers the second surface of the first through hole 11
- the second planar portion 33 of the bottom electrode 30 covers the top of the fin 20.
- the lower end of the vertical portion 31 is connected to the first planar portion 32, and the upper end is connected to the second planar portion 33. Part 33 is connected.
- the resistive layer 40 conformally covers the bottom electrode 30 and the upper surface of the substrate 10. As shown in FIG1 , a vertical portion 41 of the resistive layer 40 is coated on the side wall of the vertical portion 31 of the bottom electrode 30. A first planar portion 42 of the resistive layer 40 conformally covers the first planar portion 32 of the bottom electrode 30 and the upper surface of the substrate 10. A second planar portion 43 of the resistive layer 40 covers the second planar portion 33 of the bottom electrode 30. The lower end of the vertical portion 41 is connected to the first planar portion 42 thereof, and the upper end is connected to the second planar portion 43 thereof.
- the vertical portion 51 of the top electrode 50 covers the sidewall of the vertical portion 41 of the resistive layer 40 .
- the upper surface of the vertical portion 51 of the top electrode 50 is flush with the upper surface of the second planar portion 43 of the resistive layer 40 .
- each of the bottom electrode 30, the resistive switching layer 40 and the top electrode 50 has a portion that is perpendicular to the substrate 10, and the vertical portions of the three films (i.e., the vertical portion 31, the vertical portion 41 and the vertical portion 51) form a resistive switching structure.
- the resistive switching region is the region where the vertical portion 31 of the bottom electrode 30 and the vertical portion 51 of the top electrode 50 overlap in the vertical direction of the substrate 10 (the resistive switching region is located in the resistive switching layer 40).
- the vertical portion 51 of the top electrode 50 is connected to the second metal layer ( M2 ) through the second through hole 12 or the wire groove 13 .
- the top electrode 50 further includes a planar portion 52 , which covers the first planar portion 42 of the resistive layer 40 .
- the lower end of the vertical portion 51 of the top electrode 50 is connected to the planar portion 52 , so that the top electrodes 50 of two adjacent resistive structures are connected.
- two resistive switching structures can be formed on one first through hole 11 based on one fin 20 .
- the two adjacent resistive switching structures mentioned above do not refer to the two resistive switching structures on the left and right here, but refer to the two resistive switching structures between two adjacent fins 20 .
- the portion in communication with the top electrode 50 is connected to the second metal layer ( M2 ) through the second through hole 12 or the wire groove 13 .
- a dielectric layer may be deposited to cover the resistive switching structure after forming the top electrode 50.
- the dielectric layer is not shown in Figures 1 and 3.
- a second through hole 12 or a line groove 13 may be etched in the dielectric layer.
- a first through hole 11 is connected to a corresponding transistor through a corresponding first metal layer (M1), so that one transistor (T) can control two resistive switching structures. (R), i.e., 1T2R.
- T the transistor
- R two resistive switching structures.
- the bottom electrodes 30 of the left and right resistive switching structures formed based on the fin 20 are connected, and the bottom electrodes of the two resistive switching structures are connected to the same transistor through a first through hole 11. Therefore, no matter the top electrode 50 shown in FIG. 1 is cut off or the top electrode 50 shown in FIG. 3 is connected, one transistor can control the left and right resistive switching structures in one fin structure.
- the case where the top electrode 50 is connected is taken as an example for explanation, wherein the resistive structure includes R1 to R4, the transistor 14 includes transistors 141 and 142, R1 and R2 are connected to the transistor 141 through the first through hole 111, and R3 and R4 are connected to the transistor 142 through the first through hole 112. Then, by controlling the switch of the transistor 141, R1 and R2 can be simultaneously switched between high and low resistance states, and by controlling the switch of the transistor 142, R3 and R4 can be simultaneously switched between high and low resistance states.
- the fin-based resistive switching structure is a three-dimensional structure, while the existing stacked resistive switching structure is a planar structure.
- the size of the stacked resistive switching structure is calculated according to its planar size. The larger the resistive switching structure is, the larger the substrate area it occupies is.
- the size of the three-dimensional resistive switching structure of the present application is calculated according to the area of the resistive switching region in the vertical direction. If the size of the resistive switching structure is to be adjusted, it is only necessary to adjust the height of the fin. The higher the fin height is, the larger the resistive switching region is. Therefore, the existing stacked resistive switching structure is not conducive to its miniaturization, and regulating the size of the resistive switching region directly affects the integration.
- the size of the resistive switching region of the three-dimensional resistive switching structure is not related to the substrate area it occupies, and the size of the resistive switching region can be regulated while miniaturizing the resistive switching structure.
- one transistor can control two resistive switching structures, with a high degree of integration.
- FIG6 is a cross-sectional view of the semiconductor device
- FIG7 is a top view of the semiconductor device. It includes: a substrate 10, a fin 20, and a resistive switching structure, which is composed of at least a bottom electrode 30, a resistive switching layer 40, and a top electrode 50. It should be noted that more functional layers can be added to the resistive switching structure in all examples of the present application as required, and the present application does not limit this.
- the semiconductor device provided by this example is described in detail below with reference to FIG. 6 and FIG. 7 .
- the substrate 10 includes a plurality of first through holes 11. As an example, FIG. 6 shows only four first through holes. The number of through holes is not limited in this application.
- the first through holes 11 are filled with metal (such as copper).
- the first surface (also called the first end surface or the first end) of the first through hole 11 is located on the lower surface of the substrate 10 and is in contact with the first metal layer (M1).
- the second surface (also called the second end surface or the second end) of the first through hole 11 is located on the upper surface of the substrate 10 .
- Every two first through holes 11 in the substrate 10 are grouped together, and a fin 20 is disposed on the upper surface of the substrate 10 between the two first through holes 11 in the group, and the fin 20 is perpendicular to the upper surface of the substrate 10.
- the fin 20 is disposed to support the resistive switching structure formed subsequently, and the material of the fin 20 can be silicon nitride (SiN).
- the bottom electrode 30 includes a vertical portion 31 covering the side wall of the fin 20 and a planar portion 32 covering the second surface of the first through hole 11, and the vertical portion 31 is connected to the planar portion 32.
- the planar portion 32 is in contact with the second surface of the first through hole 11, so that the resistive switching structure can be powered through the first through hole 11.
- the size of the planar portion 32 in the direction parallel to the upper surface of the substrate 10 can be as large as possible (as long as the planar portions 32 of two adjacent resistive switching structures are not connected), which can reduce the impedance of the resistive switching structure.
- the vertical portion 41 of the resistive layer 40 is coated on the sidewall of the vertical portion 31 of the bottom electrode 30 , and the planar portion 42 conformally covers the planar portion 32 of the bottom electrode 30 and the upper surface of the substrate 10 .
- the planar portion 42 can isolate the planar portions 32 of the bottom electrodes 30 of two adjacent resistive structures.
- the vertical portion 51 of the top electrode 50 covers the sidewall of the vertical portion 41 of the resistive layer 40 , and the planar portion 52 conformally covers the planar portion 42 of the resistive layer 40 , so that the top electrodes 50 of two adjacent resistive structures can be connected.
- top of the fin 20 , the top of the vertical portion 31 of the bottom electrode 30 , the top of the vertical portion 41 of the resistive layer 40 , and the top of the vertical portion 51 of the top electrode 50 are flush, as shown in FIG. 6 .
- the vertical portion 31 of the bottom electrode 30, the vertical portion 41 of the resistive layer 40 and the vertical portion 51 of the top electrode 50 constitute a resistive structure
- the resistive region is the region where the vertical portion 31 of the bottom electrode 30 and the vertical portion 51 of the top electrode 50 overlap in the vertical direction of the substrate 10 (the resistive region is located in the resistive layer 40).
- two resistive switching structures on the left and right can be formed between two first through holes 11 of a group based on one fin 20, and the fin 20 is used to isolate the two resistive switching structures on the left and right.
- the two adjacent resistive switching structures mentioned above do not refer to the two resistive switching structures on the left and right here, but refer to the two resistive switching structures between two adjacent fins 20.
- the portion connected to the top electrode 50 is connected to the second through-hole.
- the via 12 or the wire slot 13 is connected to the second metal layer (M2).
- a dielectric layer may be deposited to cover the resistive switching structure after forming the top electrode 50.
- the dielectric layer is not shown in Figures 6 and 7.
- a second through hole 12 or a line groove 13 may be etched in the dielectric layer.
- two first through holes 11 of a group are connected to the corresponding transistors 14 through their respective corresponding first metal layers (M1), so that one transistor (T) can control one resistive switching structure (R), i.e., 1T1R.
- the first through hole 111 is connected to the transistor 141
- the first through hole 112 is connected to the transistor 142
- the first through hole 113 is connected to the transistor 143.
- the fin-based resistive switching structure is a three-dimensional structure
- the existing stacked resistive switching structure is a planar structure.
- the size of the stacked resistive switching structure is calculated according to its planar size. The larger the resistive switching structure is, the larger the substrate area it occupies is.
- the size of the three-dimensional resistive switching structure of the present application is calculated according to the area of the resistive switching region in the vertical direction. If the size of the resistive switching structure is to be adjusted, it is only necessary to adjust the height of the fin. The higher the fin height is, the larger the resistive switching region is. Therefore, the existing stacked resistive switching structure is not conducive to its miniaturization, and regulating the size of the resistive switching region directly affects the integration.
- the size of the resistive switching region of the three-dimensional resistive switching structure is not related to the substrate area it occupies, and the size of the resistive switching region can be regulated while miniaturizing the resistive switching structure.
- the bottom electrode is partially etched away at the top of the fin, so the fin becomes an insulating layer between the resistive switching structures, that is, a space, such as the space between R1 and R2. Therefore, the thinner the fin, the smaller the space between R1 and R2.
- the traditional stacked resistive switching structure first forms R, reserves enough space between R, and then fills the dielectric layer to form the space between R.
- the space created in this way is larger in volume.
- the solution of the present application is to make the space (i.e., fin) and then make R. Therefore, the space can be minimized, which can greatly improve the integration.
- the present application also provides a method for manufacturing a semiconductor device, as shown in FIG10 , comprising:
- the process of this example starts with planarizing the first through hole on the substrate, and then performing the following steps:
- the fin can be etched out by exposure and development using a yellow light process.
- the top electrode layer can also be etched to etch away the portion of the top electrode connecting two adjacent resistive structures.
- the resulting resistive structure is shown in FIG1 .
- the dielectric layer is deposited, the dielectric layer is etched to obtain a second through hole or wire groove, as shown in FIG2 .
- the present application also provides a method for manufacturing a semiconductor device, as shown in FIG11 , comprising:
- the process of this example starts with planarizing the first through hole on the substrate, and then performing the following steps:
- Every two first through holes in the substrate are grouped together, and fins are etched in the upper surface area of the substrate between the two first through holes in the group, wherein the fins are perpendicular to the upper surface of the substrate.
- the fins can be etched by exposure and development using a yellow light process.
- ALD atomic layer deposition
- the bottom electrode layer is conformally covered on the structure in step 2, so that the bottom electrode can serve as a strong support for the fins to prevent the fins from collapsing; an organic transition layer is deposited on the bottom electrode layer.
- voids are easily generated after the resistive switching structures are separated and then filled with a dielectric layer, which is not conducive to the isolation between the resistive switching structures.
- the above-mentioned manufacturing method of the present application uses fins to isolate the resistive switching structures, which can completely avoid the generation of voids.
- the flatness of the resistive switching structure depends on the flattening process of the first through hole (i.e., the chemical mechanical polishing process (CMP)), and the control of the CMP process is not fine enough, and the flatness is increasingly difficult to meet the challenges brought by the reduction of device size.
- CMP chemical mechanical polishing process
- the formation of the bottom electrode is deposited on the side wall of the fin by the ALD growth method, and the verticality and flatness of the side wall of the fin can be finely controlled by etching in the second step, so that the flatness of the resistive switching structure that depends on the side wall of the fin is guaranteed.
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Abstract
一种半导体器件及其制造方法，半导体器件具有如下设置：鳍片（20）垂直于衬底（10）的上表面，阻变结构位于鳍片（20）的侧壁，由底电极（30）的垂直部分（31）、阻变层（40）的垂直部分（41）和顶电极（50）的垂直部分（51）组成，阻变区域即为底电极（30）的垂直部分（31）和顶电极（50）的垂直部分（51）重合的区域。该阻变区域的大小是按照垂直方向阻变区域的面积来计算，若要调整阻变结构的大小，则只需调整鳍片（20）的高度即可。因此，基于鳍片（20）的阻变结构其阻变区域的大小和其占用的衬底面积不相关，可以实现阻变结构微缩的同时又能调控阻变区域的大小。
Description
相关申请的交叉引用
本申请要求于2022年12月7日提交中国专利局，申请号为2022115788411，发明名称为“一种半导体器件及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
本申请涉及半导体技术领域，尤其涉及一种半导体器件及其制造方法。
现有技术中，阻变式存储器(Resistive Random Access Memory，RRAM)是当前最具应用前景的下一代非易失性存储器之一，与传统浮栅闪存相比，在器件结构、速度、可缩性、三维集成潜力等方面都具有明显的优势。
RRAM的基本结构为金属-绝缘体-金属(MIM)结构，主要包括底电极、阻变层和顶电极。其中，阻变层为各种氧化薄膜材料制造而成，在外加电压、电流等电信号的作用下，可在不同电阻状态之间进行可逆的转变。而这种可逆的转变大多是通过导电细丝的形成和断裂来实现的。
目前，MIM结构的制造方式为依次沉积完所有的薄膜后使用光罩进行刻蚀得到阻变结构(R)，阻变结构的大小是由光罩定义，局限性较大。
发明内容
本申请提供了一种半导体器件及其制造方法，以至少解决以上技术问题。
本申请第一方面提供了一种半导体器件，包括：衬底、鳍片和阻变结构；
所述衬底中具有多个第一通孔，所述第一通孔的第一面位于所述衬底的下表面，用于连接第一金属层，所述第一通孔的第二面位于所述衬底的上表面；
所述鳍片垂直于所述衬底的上表面，所述鳍片的下表面与所述第一通孔的第二面的部分区域重合；
所述阻变结构包括：底电极、阻变层和顶电极，其中：
所述底电极的垂直部分包覆于所述鳍片的侧壁，所述底电极的第一平面部分覆盖于所述第一通孔的第二面，所述底电极的第二平面部分覆盖于所述鳍片的顶部，所述底电极的垂直部分的下端与其第一平面部分连通，上端与其第二平面部分连通；
所述阻变层的垂直部分包覆于所述底电极垂直部分的侧壁，所述阻变层的第一平面部分随型覆盖所述底电极的第一平面部分和所述衬底的上表面，所述阻变层的第二平面部分覆盖所述底电极的第二平面部分，所述阻变层垂直部分的下端与其第一平面部分连通，上端与其第二平面部分连通；
所述顶电极的垂直部分包覆于所述阻变层垂直部分的侧壁。
其中，所述顶电极的垂直部分通过第二通孔或线槽连接第二金属层。
其中，所述顶电极的平面部分覆盖所述阻变层的第一平面部分，所述顶电极的垂直部分的下端与其平面部分连通。
其中，所述顶电极连通的部分通过第二通孔或线槽连接第二金属层。
其中，所述顶电极垂直部分的上表面和所述阻变层的第二平面部分的上表面平齐。
本申请第二方面提供了一种半导体器件，包括：衬底、鳍片和阻变结构，其中：
所述衬底中具有多个第一通孔，所述第一通孔的第一面位于所述衬底的下表面，用于连接第一金属层，所述第一通孔的第二面位于所述衬底的上表面；
将所述衬底中的每两个第一通孔分为一组，在该组两个第一通孔之间的衬底上表面区域设置所述鳍片，所述鳍片垂直于所述衬底的上表面；
所述阻变结构包括：底电极、阻变层和顶电极，其中：
所述底电极的垂直部分包覆于所述鳍片的侧壁，所述底电极的平面部分覆盖于所述第一通孔的第二面，所述底电极的垂直部分和平面部分连通；
所述阻变层的垂直部分包覆于所述底电极垂直部分的侧壁，所述阻变层
的平面部分随型覆盖所述底电极的平面部分和所述衬底的上表面；
所述顶电极的垂直部分包覆于所述阻变层垂直部分的侧壁，所述顶电极的平面部分随型覆盖所述阻变层的平面部分，以使相邻两个阻变结构的顶电极连通。
其中，所述顶电极连通的部分通过第二通孔或线槽连接第二金属层。
其中，所述顶电极垂直部分的顶部、所述阻变层垂直部分的顶部、所述底电极垂直部分的顶部和鳍片的顶部平齐。
本申请第三方面提供一种半导体器件的制造方法，衬底中具有多个第一通孔，所述第一通孔的第一面位于所述衬底的下表面，用于连接第一金属层，所述第一通孔的第二面位于所述衬底的上表面，该方法包括：
在所述衬底的上表面沉积功能层，并进行刻蚀，得到垂直于所述衬底的上表面的鳍片，所述鳍片的下表面与所述第一通孔的第二面的部分区域重合；
依次沉积底电极层和有机过渡层，通过曝光显影对底电极层进行刻蚀，并去除所述有机过渡层，得到覆盖于鳍片的底电极；
依次沉积阻变层和顶电极层，进行平坦化处理后，对顶电极层进行刻蚀，得到第一方面所述的半导体器件。
本申请第四方面提供一种半导体器件的制造方法，衬底中具有多个第一通孔，所述第一通孔的第一面位于所述衬底的下表面，用于连接第一金属层，所述第一通孔的第二面位于所述衬底的上表面，该方法包括：
在所述衬底的上表面沉积功能层，将所述衬底中的每两个第一通孔分为一组，在该组两个第一通孔之间的衬底上表面区域刻蚀出所述鳍片，所述鳍片垂直于所述衬底的上表面；
依次沉积底电极层和有机过渡层，通过曝光显影对底电极层进行刻蚀，并去除所述有机过渡层，得到覆盖于鳍片的底电极；
依次沉积阻变层和顶电极层，进行平坦化处理，得到第二方面所述的半导体器件。
上述基于鳍片的阻变结构是一种立体的结构，其阻变区域的大小是按照垂直方向阻变区域的面积来计算，若要调整阻变结构的大小，则只需调整鳍片的高度即可。因此，本申请立体的阻变结构其阻变区域的大小和其占用的
衬底面积不相关，可以实现阻变结构微缩的同时又能调控阻变区域的大小。
通过参考附图阅读下文的详细描述，本申请示例性实施方式的上述以及其他目的、特征和优点将变得易于理解。在附图中，以示例性而非限制性的方式示出了本申请的若干实施方式，其中：
在附图中，相同或对应的标号表示相同或对应的部分。
图1示出了实施例一提供的第一种半导体器件的正切面示意图；
图2示出了实施例一提供的第一种半导体器件中第二通孔或线槽的示意图；
图3示出了实施例一提供的第二种半导体器件的正切面示意图；
图4示出了实施例一提供的第二种半导体器件中第二通孔或线槽的示意图；
图5示出了实施例一提供的半导体器件实现1T2R的示意图；
图6示出了实施例二提供的半导体器件的正切面示意图；
图7示出了实施例二提供的半导体器件的俯视示意图；
图8示出了实施例二提供的半导体器件中第二通孔或线槽的示意图；
图9示出了实施例二提供的半导体器件实现1T1R的示意图；
图10示出了实施例一提供的半导体器件的制造流程示意图；
图11示出了实施例二提供的半导体器件的制造流程示意图。
为使本申请的目的、特征、优点能够更加的明显和易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而非全部实施例。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特
征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或隐含地包括至少一个该特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
实施例一
本申请一示例提供了一种半导体器件，如图1所示，图1为半导体器件的正切面图，包括：衬底10、鳍片20和阻变结构，该阻变结构至少由底电极30、阻变层40和顶电极50组成。需要指出的是，本申请所有示例中的阻变结构中还可以根据需求增加更多的功能层，本申请对此不做限制。
衬底10中具有多个第一通孔11，作为示例，图1中仅示出了两个第一通孔，对于通孔的数量本申请不做限制。第一通孔11中填充有金属(例如铜)，其第一面(又称第一端面或第一端)位于衬底10的下表面，与第一金属层(M1)连接，第一通孔11的第二面(又称第二端面或第二端)位于衬底10的上表面。
鳍片20垂直于衬底10的上表面，且鳍片的下表面与第一通孔11的第二面的部分区域重合。鳍片20的设置用于支撑后续形成的阻变结构，为了向阻变结构通电，鳍片20不能完全覆盖第一通孔11的第二面，需要预留出第一通孔11第二面的部分区域与阻变结构的底电极30连通。鳍片20的材料可采用氮化硅(SiN)。
阻变结构包括：底电极30、阻变层40和顶电极50，其中：
底电极30随型覆盖鳍片20和第一通孔11的第二面，如图1所示，底电极30的垂直部分31包覆于鳍片20的侧壁，底电极30的第一平面部分32覆盖于所述第一通孔11的第二面，底电极30的第二平面部分33覆盖于鳍片20的顶部，垂直部分31的下端与其第一平面部分32连通，上端与其第二平面
部分33连通。
阻变层40随型覆盖底电极30和衬底10的上表面，如图1所示，阻变层40的垂直部分41包覆于底电极30垂直部分31的侧壁，阻变层40的第一平面部分42随型覆盖底电极30的第一平面部分32和衬底10的上表面，阻变层40的第二平面部分43覆盖底电极30的第二平面部分33，垂直部分41的下端与其第一平面部分42连通，上端与其第二平面部分43连通。
顶电极50的垂直部分51包覆于阻变层40垂直部分41的侧壁。其中，顶电极50的垂直部分51的上表面和阻变层40的第二平面部分43的上表面平齐。
基于上述的结构可知，底电极30、阻变层40和顶电极50均有一个部分是垂直于衬底10的，而这三个薄膜的垂直部分(即垂直部分31、垂直部分41和垂直部分51)形成了阻变结构。阻变区域即为底电极30的垂直部分31和顶电极50的垂直部分51在衬底10的垂直方向上重合的区域(阻变区域位于阻变层40)。
如图2所示，示例中的半导体器件，顶电极50的垂直部分51通过第二通孔12或者线槽13连接到第二金属层(M2)。
如图3所示，顶电极50还包括平面部分52，平面部分52覆盖阻变层40的第一平面部分42，顶电极50的垂直部分51的下端与其平面部分52连通，如此相邻两个阻变结构的顶电极50连通。
通过图1和图3所示的结构可知，一个第一通孔11上基于一个鳍片20可形成左右两个阻变结构。而前述提及的相邻的两个阻变结构并非指此处的左右两个阻变结构，而是指相邻两个鳍片20之间的两个阻变结构。
如图4所示，该示例中的半导体器件，顶电极50连通的部分通过第二通孔12或者线槽13连接到第二金属层(M2)。
需要指出的是，在形成顶电极50之后可沉积介质层对阻变结构进行包覆，为了方便说明，图1和图3中并未示出介质层。在形成介质层后，可在介质层中刻蚀出第二通孔12或者线槽13。
基于图1和图3所示的半导体器件，一个第一通孔11通过对应的第一金属层(M1)连接对应的晶体管，可实现1个晶体管(T)控制两个阻变结构
(R)、即1T2R。图1和图3所示的半导体器件中，基于鳍片20形成的左右两个阻变结构的底电极30是连通的，且这两个阻变结构的底电极均通过一个第一通孔11连接至同一个晶体管，因此，不论是图1所示的顶电极50被切断的情形还是图3所示的顶电极50连通的情形，均是一个晶体管可以控制一个鳍片结构中的左右两个阻变结构。
如图5所示，以顶电极50连通的情形为例进行说明，其中，阻变结构包括R1至R4，晶体管14包括晶体管141和142，R1和R2通过第一通孔111连接至晶体管141，R3和R4通过第一通孔112连接至晶体管142，则通过控制晶体管141的开关可以同时使R1和R2实现高低阻态之间的转换，通过控制晶体管142的开关可以同时使R3和R4实现高低阻态之间的转换。
基于鳍片的阻变结构是一种立体的结构，现有的堆叠式阻变结构是一种平面结构，该堆叠式阻变结构的大小是按其平面大小计算，阻变结构越大，其占用的衬底面积越大，而本申请立体的阻变结构的大小则是按照垂直方向阻变区域的面积来计算，若要调整阻变结构的大小，则只需调整鳍片的高度即可，鳍片高度越高，阻变区域越大。因此，现有的堆叠式阻变结构不利于其微缩,调控阻变区域大小则直接影响集成度，而立体的阻变结构其阻变区域的大小和其占用的衬底面积不相关，可以实现阻变结构微缩的同时又能调控阻变区域的大小。
基于该示例的结构，可以做到1个晶体管控制2个阻变结构,集成度较高。
实施例二
本申请提供了一种半导体器件，如图6和图7所示。图6为半导体器件的正切面图，图7为半导体器件的俯视图。包括：衬底10、鳍片20和阻变结构，该阻变结构至少由底电极30、阻变层40和顶电极50组成。需要指出的是，本申请所有示例中的阻变结构中还可以根据需求增加更多的功能层，本申请对此不做限制。
下面结合图6和图7对该示例提供的半导体器件进行详细的说明。
衬底10包括多个第一通孔11，作为示例，图6中仅示出了四个第一通孔，对于通孔的数量本申请不做限制。第一通孔11中填充有金属(例如铜)，其第一面(又称第一端面或第一端)位于衬底10的下表面，与第一金属层(M1)
连接，第一通孔11的第二面(又称第二端面或第二端)位于衬底10的上表面。
将衬底10中的每两个第一通孔11分为一组，在该组两个第一通孔11之间的衬底10的上表面区域设置鳍片20，鳍片20垂直于衬底10的上表面。鳍片20的设置用于支撑后续形成的阻变结构，鳍片20的材料可采用氮化硅(SiN)。
底电极30包括包覆于鳍片20侧壁的垂直部分31和覆盖于第一通孔11第二面的平面部分32，垂直部分31和平面部分32连通。其中，平面部分32与第一通孔11的第二面接触，从而可以通过第一通孔11为阻变结构供电。另外，平面部分32沿平行于衬底10上表面方向的尺寸可以尽量的大(只要保证相邻两个阻变结构的平面部分32不连通即可)，这样可以减小阻变结构的阻抗。
阻变层40的垂直部分41包覆于底电极30垂直部分31的侧壁，平面部分42随型覆盖底电极30的平面部分32和衬底10的上表面，平面部分42可隔绝相邻两个阻变结构的底电极30的平面部分32。
顶电极50的垂直部分51包覆于阻变层40垂直部分41的侧壁，平面部分52随型覆盖阻变层40的平面部分42，如此可使相邻两个阻变结构的顶电极50连通。
其中，鳍片20的顶部、底电极30垂直部分31的顶部、阻变层40垂直部分41的顶部和顶电极50垂直部分51的顶部平齐，如图6所示。
在上述的结构中，底电极30的垂直部分31、阻变层40的垂直部分41和顶电极50的垂直部分51组成了阻变结构，阻变区域即为底电极30的垂直部分31和顶电极50的垂直部分51在衬底10的垂直方向上重合的区域(阻变区域位于阻变层40)。
通过图6和图7所示的结构可知，一组的两个第一通孔11之间基于一个鳍片20可形成左右两个阻变结构，鳍片20用于隔绝左右两个阻变结构。而前述提及的相邻的两个阻变结构并非指此处的左右两个阻变结构，而是指相邻两个鳍片20之间的两个阻变结构。
如图8所示，该示例中的半导体器件，顶电极50连通的部分通过第二通
孔12或者线槽13连接到第二金属层(M2)。
需要指出的是，在形成顶电极50之后可沉积介质层对阻变结构进行包覆，为了方便说明，图6和图7中并未示出介质层。在形成介质层后，可在介质层中刻蚀出第二通孔12或者线槽13。
基于图6和图7所示的半导体器件，本申请中一组的两个第一通孔11分别通过各自对应的第一金属层(M1)连接对应的晶体管14，可实现1个晶体管(T)控制一个阻变结构(R)、即1T1R。参见图9所示，第一通孔111连接至晶体管141、第一通孔112连接至晶体管142、第一通孔113连接至晶体管143，通过控制晶体管141的开关可以使R1实现高低阻态之间的转换，通过控制晶体管142的开关可以使R2实现高低阻态之间的转换，通过控制晶体管143的开关可以使R3实现高低阻态之间的转换。
实施例二提供的方案中，基于鳍片的阻变结构是一种立体的结构，现有的堆叠式阻变结构是一种平面结构，该堆叠式阻变结构的大小是按其平面大小计算，阻变结构越大，其占用的衬底面积越大，而本申请立体的阻变结构的大小则是按照垂直方向阻变区域的面积来计算，若要调整阻变结构的大小，则只需调整鳍片的高度即可，鳍片高度越高，阻变区域越大。因此，现有的堆叠式阻变结构不利于其微缩,调控阻变区域大小则直接影响集成度，而立体的阻变结构其阻变区域的大小和其占用的衬底面积不相关，可以实现阻变结构微缩的同时又能调控阻变区域的大小。
结合图9，底电极在鳍片顶部的部分被刻蚀掉，那么鳍片也就变成了阻变结构之间的绝缘层、即space，例如R1和R2之间的space。所以鳍片越薄，R1和R2之间的space就越小。而传统的堆叠式阻变结构则是先形成R，在R之间预留足够的空间再填充介电层形成R之间的space，如此制造出的space体积较大。而本申请的方案则是做出space(即鳍片)再做出R，因此，可以使space做到最小，如此可以极大地提高集成度。
为了实现实施例一所示的半导体器件，本申请还提供了一种半导体器件的制造方法，如图10所示，包括：
该示例的工艺起点为：对衬底上的第一通孔进行平坦化处理，之后执行如下的步骤：
1、在衬底的上表面沉积功能层，可采用氮化硅(SiN)。
2、对功能层进行刻蚀，得到垂直于衬底的上表面的鳍片，鳍片的下表面与第一通孔的第二面的部分区域重合，即一个第一通孔上设置有一个鳍片。可采用黄光工艺曝光显影刻蚀出鳍片。
3、依次沉积底电极层和有机过渡层。采用ALD生长底电极层，使底电极层随型覆盖在第2步的结构上，如此底电极可以作为鳍片的强支撑，防止鳍片倒塌；在底电极层上沉积有机过渡层。
4、通过曝光显影对底电极层进行刻蚀，然后去除剩余的有机过渡层，得到覆盖于鳍片的底电极。底电极的垂直部分包覆于所述鳍片的侧壁，所述底电极的第一平面部分覆盖于所述第一通孔的第二面，所述底电极的第二平面部分覆盖于所述鳍片的顶部，所述底电极的垂直部分的下端与其第一平面部分连通，上端与其第二平面部分连通。
5、依次沉积阻变层和顶电极层，进行平坦化处理，将鳍片顶部对应的顶电极部分去除，得到的阻变结构如图3所示，此处不再赘述。需要指出的是，在沉积完顶电极层后，还需要沉积介质层，再进行平坦化处理，最后对介质层进行刻蚀，得到第二通孔或者线槽，如图4所示。
进行平坦化处理，将鳍片顶部对应的顶电极部分去除后，还可对顶电极层进行刻蚀，将相邻两个阻变结构之间顶电极连通的部分刻蚀掉，得到的阻变结构如图1所示，然后再沉积介质层后，对介质层进行刻蚀，得到第二通孔或者线槽，如图2所示。
为了实现实施例二所示的半导体器件，本申请还提供了一种半导体器件的制造方法，如图11所示，包括：
该示例的工艺起点为：对衬底上的第一通孔进行平坦化处理，之后执行如下的步骤：
1、在衬底的上表面沉积功能层，可采用氮化硅(SiN)。
2、将衬底中的每两个第一通孔分为一组，在该组两个第一通孔之间的衬底上表面区域刻蚀出鳍片，鳍片垂直于衬底的上表面。可采用黄光工艺曝光显影刻蚀出鳍片。
3、依次沉积底电极层和有机过渡层。其中，可采用ALD生长底电极层，
使底电极层随型覆盖在第2步的结构上，如此底电极可以作为鳍片的强支撑，防止鳍片倒塌；在底电极层上沉积有机过渡层。
4、通过曝光显影对底电极层进行刻蚀，然后去除剩余的有机过渡层，得到覆盖于鳍片的底电极。
5、依次沉积阻变层和顶电极层，其中，阻变层的沉积可采用ALD生长法。
6、进行平坦化处理，得到阻变结构。其该结构如图6所示，此处不再赘述。需要指出的是，在沉积完顶电极层后，还需要沉积介质层，再进行该步骤的平坦化处理，得到图6所示的阻变结构之后可再沉积一层介质层，最后对介质层进行刻蚀，得到第二通孔或者线槽，如图8所示。
在本申请提供的上述两种制造方法相比现有的堆叠阻变结构的制造方法有如下的优点：
1、在堆叠式阻变结构的制造工艺中，将阻变结构隔开后填充介质层，容易产生空隙(void),不利于阻变结构之间的隔绝，而本申请的上述制造方法用鳍片隔绝阻变结构，可以完全避免void的产生。
2、堆叠式阻变结构的制造工艺中，阻变结构的平坦度依赖于第一通孔的平坦化处理(即化学机械抛光工艺(Chemical Mechanical Polishing，CMP))，而CMP工艺的控制不够精细，平坦度越来越难以符合器件尺寸缩小带来的挑战。本申请上述的方法中，底电极的形成采用ALD生长法沉积到鳍片的侧壁，而鳍片侧壁的垂直度和平坦度可以在第2步中通过蚀刻的方法来精细控制，使得依赖于鳍片侧壁的阻变结构的平整性得到保障。
3、堆叠式阻变结构之间的切断需要通过蚀刻实现，会对阻变层(过渡金属氧化物(Transition Metal Oxides，TMO))带来损伤(plasma damage)。通过上述制造方法可知，鳍片式的阻变结构之间无需切断，即不需要对TMO进行刻蚀，避免了由此造成的损伤。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情
况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
前述描述旨在使得任何本领域的技术人员能够实现和使用本申请内容，并且在特定应用及其要求的上下文中提供。此外，仅出于例证和描述的目的，给出本申请的实施例的前述描述。它们并非旨在为详尽的或将本申请限制于所公开的形式。因此，许多修改和变型对于本领域熟练的从业者将显而易见，并且本文所定义的一般性原理可在不脱离本申请的实质和范围的前提下应用于其他实施例和应用。此外，前述实施例的论述并非旨在限制本申请。因此，本申请并非旨在限于所示出的实施例，而是将被赋予与本文所公开的原理和特征一致的最宽范围。
Claims (10)
- 一种半导体器件，其特征在于，包括：衬底、鳍片和阻变结构；所述衬底中具有多个第一通孔，所述第一通孔的第一面位于所述衬底的下表面，用于连接第一金属层，所述第一通孔的第二面位于所述衬底的上表面；所述鳍片垂直于所述衬底的上表面，所述鳍片的下表面与所述第一通孔的第二面的部分区域重合；所述阻变结构包括：底电极、阻变层和顶电极，其中：所述底电极的垂直部分包覆于所述鳍片的侧壁，所述底电极的第一平面部分覆盖于所述第一通孔的第二面，所述底电极的第二平面部分覆盖于所述鳍片的顶部，所述底电极的垂直部分的下端与其第一平面部分连通，上端与其第二平面部分连通；所述阻变层的垂直部分包覆于所述底电极垂直部分的侧壁，所述阻变层的第一平面部分随型覆盖所述底电极的第一平面部分和所述衬底的上表面，所述阻变层的第二平面部分覆盖所述底电极的第二平面部分，所述阻变层垂直部分的下端与其第一平面部分连通，上端与其第二平面部分连通；所述顶电极的垂直部分包覆于所述阻变层垂直部分的侧壁。
- 根据权利要求1所述的半导体器件，其特征在于，所述顶电极的垂直部分通过第二通孔或线槽连接第二金属层。
- 根据权利要求1所述的半导体器件，其特征在于，所述顶电极的平面部分覆盖所述阻变层的第一平面部分，所述顶电极的垂直部分的下端与其平面部分连通。
- 根据权利要求3所述的半导体器件，其特征在于，所述顶电极连通的部分通过第二通孔或线槽连接第二金属层。
- 根据权利要求1所述的半导体器件，其特征在于，所述顶电极垂直部分的上表面和所述阻变层的第二平面部分的上表面平齐。
- 一种半导体器件，其特征在于，包括：衬底、鳍片和阻变结构，其中：所述衬底中具有多个第一通孔，所述第一通孔的第一面位于所述衬底的 下表面，用于连接第一金属层，所述第一通孔的第二面位于所述衬底的上表面；将所述衬底中的每两个第一通孔分为一组，在该组两个第一通孔之间的衬底上表面区域设置所述鳍片，所述鳍片垂直于所述衬底的上表面；所述阻变结构包括：底电极、阻变层和顶电极，其中：所述底电极的垂直部分包覆于所述鳍片的侧壁，所述底电极的平面部分覆盖于所述第一通孔的第二面，所述底电极的垂直部分和平面部分连通；所述阻变层的垂直部分包覆于所述底电极垂直部分的侧壁，所述阻变层的平面部分随型覆盖所述底电极的平面部分和所述衬底的上表面；所述顶电极的垂直部分包覆于所述阻变层垂直部分的侧壁，所述顶电极的平面部分随型覆盖所述阻变层的平面部分，以使相邻两个阻变结构的顶电极连通。
- 根据权利要求6所述的半导体器件，其特征在于，所述顶电极连通的部分通过第二通孔或线槽连接第二金属层。
- 根据权利要求6所述的半导体器件，其特征在于，所述顶电极垂直部分的顶部、所述阻变层垂直部分的顶部、所述底电极垂直部分的顶部和鳍片的顶部平齐。
- 一种半导体器件的制造方法，其特征在于，衬底中具有多个第一通孔，所述第一通孔的第一面位于所述衬底的下表面，用于连接第一金属层，所述第一通孔的第二面位于所述衬底的上表面，该方法包括：在所述衬底的上表面沉积功能层，并进行刻蚀，得到垂直于所述衬底的上表面的鳍片，所述鳍片的下表面与所述第一通孔的第二面的部分区域重合；依次沉积底电极层和有机过渡层，通过曝光显影对底电极层进行刻蚀，并去除所述有机过渡层，得到覆盖于鳍片的底电极；依次沉积阻变层和顶电极层，进行平坦化处理后，对顶电极层进行刻蚀，得到权利要求1至5任一所述的半导体器件。
- 一种半导体器件的制造方法，其特征在于，衬底中具有多个第一通孔，所述第一通孔的第一面位于所述衬底的下表面，用于连接第一金属层，所述第一通孔的第二面位于所述衬底的上表面，该方法包括：在所述衬底的上表面沉积功能层，将所述衬底中的每两个第一通孔分为一组，在该组两个第一通孔之间的衬底上表面区域刻蚀出所述鳍片，所述鳍片垂直于所述衬底的上表面；依次沉积底电极层和有机过渡层，通过曝光显影对底电极层进行刻蚀，并去除所述有机过渡层，得到覆盖于鳍片的底电极；依次沉积阻变层和顶电极层，进行平坦化处理，得到权利要求6至8任一所述的半导体器件。
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| CN106611816A (zh) * | 2015-10-22 | 2017-05-03 | 华邦电子股份有限公司 | Rram装置与其形成方法 |
| US9806255B1 (en) * | 2017-01-23 | 2017-10-31 | United Microelectronics Corp. | Resistive random access memory and method of forming the same |
| US10651380B1 (en) * | 2019-01-29 | 2020-05-12 | Globalfoundries Singapore Pte. Ltd. | Memory devices and methods of forming the same |
| US20200395541A1 (en) * | 2019-06-12 | 2020-12-17 | Globalfoundries Inc. | Vertical memory devices |
| CN111640864A (zh) * | 2020-05-28 | 2020-09-08 | 厦门半导体工业技术研发有限公司 | 一种半导体集成电路器件及其制造方法 |
| CN115867123A (zh) * | 2022-12-07 | 2023-03-28 | 厦门半导体工业技术研发有限公司 | 一种半导体器件及其制造方法 |
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| TW202425788A (zh) | 2024-06-16 |
| CN115867123A (zh) | 2023-03-28 |
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