WO2024012342A1 - 芯片和制备方法 - Google Patents

芯片和制备方法 Download PDF

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Publication number
WO2024012342A1
WO2024012342A1 PCT/CN2023/106063 CN2023106063W WO2024012342A1 WO 2024012342 A1 WO2024012342 A1 WO 2024012342A1 CN 2023106063 W CN2023106063 W CN 2023106063W WO 2024012342 A1 WO2024012342 A1 WO 2024012342A1
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WO
WIPO (PCT)
Prior art keywords
substrate
chip
hole
doping
type
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PCT/CN2023/106063
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English (en)
French (fr)
Inventor
何林峰
苏帅
武龙
侯明辰
魏巍
张亚文
Original Assignee
华为技术有限公司
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Publication of WO2024012342A1 publication Critical patent/WO2024012342A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions

Definitions

  • Embodiments of the present application relate to the field of semiconductor technology, and in particular, to a chip and a preparation method.
  • modules with high production costs that are used to implement the core functions of the chip such as modules that implement digital processing functions in the chip, or modules that implement storage functions
  • Modules with low production costs and used to implement chip auxiliary functions or peripheral functions such as electrostatic protection modules used to resist electrostatic discharge events that may occur at any time from the production process to use
  • Modules are packaged together to form a packaged system.
  • diodes are usually used as electrostatic protection devices, and the diodes are usually arranged between the signal terminals of core functional modules and public signal lines (such as public ground lines or power lines).
  • the electrostatic protection capability of a diode is determined by the size of the PN junction area during the production process.
  • the area occupied by the PN junction per unit area of the chip is too small. If you want to increase the PN junction area, you need to occupy more area of the chip. , reducing chip utilization. Therefore, how to increase the proportion of the area occupied by the PN junction in the electrostatic protection device within the unit area of the chip to improve the efficiency of the electrostatic protection device has become a problem that needs to be solved.
  • the proportion of the area occupied by the PN junction in the electrostatic protection device within the unit area of the chip can be increased to improve the efficiency of the electrostatic protection device.
  • inventions of the present application provide a chip.
  • the chip includes a substrate.
  • a first through hole is opened in the substrate and penetrates the upper and lower surfaces of the substrate.
  • the inner wall and bottom of the first through hole are sequentially At least two layers of doping materials are attached, and the at least two layers of doping materials include P-type doping materials and N-type doping materials.
  • the first through hole is also filled with a first conductive material, and the first through hole is filled with a first conductive material.
  • a conductive material is in contact with the first doping material in the at least two layers of doping materials; a first conductive line and a functional circuit are provided on the upper surface of the substrate, the first conductive line and the first The conductive material is connected to the functional circuit; a second conductive line is provided on the lower surface of the substrate, and the second conductive line is in contact with the second doping material in the at least two layers of doping materials.
  • a through hole is opened in the chip substrate, and at least two layers of polysilicon are attached to the bottom end and side walls of the through hole.
  • the at least two layers of polysilicon include P-type doped polysilicon and N-type doped polysilicon.
  • Hybrid polysilicon, P-type doped polysilicon and N-type doped polysilicon form a PN junction.
  • the area of the PN junction of the electrostatic protection transistor in the chip is the area of the bottom end and side wall of the through hole.
  • the area of the PN junction in the chip per unit area can be increased.
  • both P-type doped polysilicon and N-type doped polysilicon are attached to the bottom end and sidewall of the through hole on the substrate, that is, the N-type will not be caused by the excessive thickness of the substrate of the chip. If the doped silicon substrate is too thick, the on-resistance of the electrostatic protection transistor can be reduced, which in turn can reduce the voltage clamping capability of the electrostatic protection transistor.
  • the electrostatic protection transistor in the chip provided by the embodiment of the present application can improve the electrostatic protection performance.
  • the substrate is further provided with a second through hole penetrating the upper and lower surfaces of the substrate, and the second through hole is filled with a second conductive material;
  • the functional circuit is connected to the second conductive line through the second conductive material.
  • the chip includes a diode, an inner wall and a bottom of the first through hole Two layers of doping material are attached in sequence, the first doping material is a P-type doping material, and the second doping material is an N-type doping material.
  • the chip includes an NPN transistor, and three layers of doping material are sequentially attached to the inner wall and bottom of the first through hole, and the three layers of doping material include N Type doping material, P-type doping material and N-type doping material; wherein, the first doping material is an N-type doping material, and the second doping material is an N-type doping material.
  • the chip includes a PNP transistor, and three layers of doping material are sequentially attached to the inner wall and bottom of the first through hole, and the three layers of doping material include P Type doping material, N-type doping material and P-type doping material; wherein, the first doping material is a P-type doping material, and the second doping material is a P-type doping material.
  • the chip includes a thyristor, and four layers of doping material are sequentially attached to the inner wall and bottom of the first through hole, and the four layers of doping material include N-type doping material, P-type doping material, N-type doping material and P-type doping material; wherein, the first doping material is P-type doping material, and the second doping material is N-type Doping materials.
  • the chip further includes a substrate, and the substrate is disposed on the substrate.
  • the N-type doped material is formed by doping silicon material with phosphorus element; the P-type doped material is formed by doping silicon material with boron. formed from elements.
  • embodiments of the present application provide a method for preparing a chip.
  • the method includes: providing a substrate; forming a first through hole on the substrate, wherein the first through hole penetrates the At least two layers of doping materials are attached to the upper and lower surfaces of the substrate, the inner wall and the bottom of the first through hole in sequence, and the at least two layers of doping materials include P-type doping materials and N-type doping materials, so
  • the first through hole is also filled with a first conductive material, and the first conductive material is in contact with the first doping material in the at least two layers of doping materials; a first conductive material is formed on the upper surface of the substrate.
  • a conductive line the first conductive line is connected to the first conductive material; a second conductive line is formed on the lower surface of the substrate, the second conductive line is connected to the at least two layers of doped materials.
  • the second doped material is in contact; a functional circuit is provided on the upper surface of the substrate, and the functional circuit is connected to the first conductive line.
  • forming a first through hole on the substrate includes: forming a first through hole and a second through hole on the substrate; wherein, The second through hole penetrates the upper and lower surfaces of the substrate, the second through hole is filled with a second conductive material, and the functional circuit is connected to the second conductive line through the second conductive material.
  • Figure 1A is a circuit diagram of a chip with electrostatic protection in the prior art provided by an embodiment of the present application;
  • Figure 1B is a schematic structural diagram of the diode shown in Figure 1A;
  • FIG. 2 is a schematic structural diagram of the chip 100 provided by the embodiment of the present application.
  • Figure 3 is a circuit diagram of the chip 100 shown in Figure 2 provided by an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of the chip 200 provided by the embodiment of the present application.
  • Figure 5 is a schematic structural diagram of a specific embodiment corresponding to the chip 100 shown in Figure 2 provided by the embodiment of the present application;
  • Figure 6 is a circuit diagram of the chip 100 shown in Figure 5 provided by an embodiment of the present application.
  • Figure 7 is a schematic structural diagram of another specific embodiment corresponding to the chip 100 shown in Figure 2 provided by the embodiment of the present application;
  • Figure 8 is a circuit diagram of the chip 100 shown in Figure 7 provided by an embodiment of the present application.
  • Figure 9 is a schematic structural diagram of another specific embodiment corresponding to the chip 100 shown in Figure 2 provided by the embodiment of the present application;
  • Figure 10 is a circuit diagram of the chip 100 shown in Figure 9 provided by an embodiment of the present application.
  • Figure 11 is a schematic structural diagram of another specific embodiment corresponding to the chip 100 shown in Figure 2 provided by the embodiment of the present application;
  • Figure 12 is a circuit diagram of the chip 100 shown in Figure 11 provided by an embodiment of the present application.
  • Figure 13 is a flow chart of the preparation method of the chip 100 shown in Figure 6 provided by the embodiment of the present application;
  • FIGS. 14A to 14H are schematic structural diagrams of the chip 100 shown in FIG. 6 during the preparation process.
  • FIG. 1A is a circuit diagram of a chip with electrostatic protection in the prior art provided by an embodiment of the present application.
  • a chip with electrostatic protection includes power lines, ground wires, signal lines, diodes P1 and P2 for electrostatic protection, and protected functional circuits.
  • the diode P1 and the diode P2 are respectively arranged between the ground line and the signal line, and the signal line and the power line.
  • the chip includes a substrate S, a P-type doped silicon substrate embedded in the substrate S, and an N-type doped silicon substrate.
  • a PN junction is formed between the P-type doped silicon substrate and the N-type doped silicon substrate.
  • the metal M1 in contact with the P-type doped silicon substrate leads to the anode of the diode; the metal M2 in contact with the N-type doped silicon substrate leads to the cathode of the diode.
  • a barrier layer is also provided between the N-type doped silicon substrate and the substrate S, and between the P-type doped silicon substrate and the N-type doped silicon substrate.
  • the P-type doped silicon substrate is placed at the bottom, the N-type doped silicon substrate is placed on the P-type doped silicon substrate, and the P-type doped silicon substrate.
  • the part in contact with the N-type doped silicon substrate is the cross-sectional area of the through hole. This results in the PN junction area being too small per unit area of the chip, thereby reducing the electrostatic protection efficiency of the diode. .
  • the P-type doped silicon substrate and the N-type doped silicon substrate are arranged up and down along the thickness direction of the substrate S.
  • the substrate S is too thick, the N-type doped silicon substrate is also too thick, which means This results in a large on-resistance of the diode, thereby reducing the voltage clamping capability of the diode.
  • a through hole is opened in the chip substrate, and at least two layers of polysilicon are attached to the bottom end and side walls of the through hole.
  • the at least two layers of polysilicon include P-type doped polysilicon and N-type doped polysilicon. , P-type doped polysilicon and N-type doped polysilicon form a PN junction.
  • the chip provided by the embodiment of the present application is the area of the bottom end and side wall of the through hole, so compared with the existing technology, the area of the PN junction in the chip per unit area can be increased.
  • both P-type doped polysilicon and N-type doped polysilicon are attached to the bottom end and sidewall of the through hole on the substrate, that is, the N-type will not be caused by the excessive thickness of the substrate of the chip.
  • the electrostatic protection transistor in the chip provided by the embodiment of the present application can improve the electrostatic protection performance.
  • the chip provided by the embodiment of the present application will be described in detail below through the embodiments shown in FIGS. 2 to 11 .
  • FIG. 2 is a schematic structural diagram of the chip 100 provided by an embodiment of the present application.
  • the chip 100 may be a system in package chip.
  • the chip 100 includes a substrate 10 and a functional circuit 11 disposed on the substrate 10 .
  • the substrate 10 may also be called a silicon wafer, and the material of the substrate 10 is silicon.
  • the substrate 10 is also provided with a through hole 12 , and the through hole 12 is used to embed an electrostatic protection transistor to protect the functional circuit 11 .
  • a conductive trace 13 is also provided on the upper surface of the substrate 10 for connecting the functional circuit 11 and the electrostatic protection transistor in the through hole 12 .
  • the substrate 10 is also provided with a through hole for connecting the functional circuit 11 to the common ground.
  • the through hole can be disposed under the functional circuit 11 and covered by the functional circuit 11 .
  • the lower surface of the substrate 10 is also provided with conductive lines for connecting the electrostatic protection transistor and the functional circuit 11 to a common ground.
  • the planar circuit of chip 100 shown in Figure 2 The structure is shown in Figure 3. Among them, the through holes on the substrate 10 for connecting the functional circuit 11 to the common ground are reference numerals 14 shown in FIG. 3 , and the conductive circuits on the lower surface of the substrate 10 are reference numerals 15 shown in FIG. 3 .
  • the chip 100 shown in Figure 2 is a bare chip formed directly on the substrate 10.
  • the chip provided in the embodiment of the present application can also be a chip packaging structure formed after being packaged with a substrate, as shown in Figure 4.
  • Figure 4 is a schematic diagram of this application.
  • the application embodiment provides a schematic structural diagram of the chip 200.
  • the chip 200 shown in FIG. 4 also includes a substrate 20 , and the chip 100 shown in FIG. 2 is disposed on the substrate 20 .
  • a plurality of pins 21 are provided on the substrate 20.
  • Each lead-out terminal of the functional circuit 11, each lead-out terminal of the electrostatic protection transistor embedded in the through hole 12, the upper surface conductive circuit 13 and the lower surface conductive circuit 15 on the substrate 10 are respectively Lead to each pin 21 of the substrate 20 to realize board-level connection between the chip 200 and other chips or components.
  • the functional circuit 11 can be a memory (Memory), a discrete device, an Application Processor (AP), a Micro-Electro-Mechanical System (MEMS), a microwave radio frequency chip, or an application-specific integrated circuit. (ApplicationSpecific Integrated Circuit, ASIC for short), etc.
  • the functional circuit 11 can be pre-integrated on one or more bare chips and then installed on the chip 100 .
  • the above-mentioned application processing chips or application-specific integrated circuits can be central processing units (CPU), image processors (Graphics Processing Unit, GPU), artificial intelligence processors (such as neural network processors), integrated computing Amplifiers, filters, etc.
  • the memory can be cache, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM) or other memory.
  • the electrostatic protection transistor provided by the embodiment of the present application may be a diode, a triode or a thyristor.
  • the structure of the electrostatic protection transistor provided by the embodiment of the present application and its connection relationship with the functional circuit 11 in the chip 100 will be described in more detail below through the examples shown in FIGS. 5 to 11 .
  • FIG. 5 is a schematic diagram of a planar circuit structure in which the electrostatic protection transistor is a diode in the chip 100 provided by the embodiment of the present application.
  • the chip 100 includes a diode P1 and a diode P2.
  • the diode P1 is disposed between the conductive line 13 and the conductive line 15 (ie, the common ground Gnd), and the diode P2 is disposed between the conductive line 13 and the power line Pdd.
  • the functional circuit 11 is connected to the conductive line 15 and the power supply line Pdd, respectively.
  • the structure of the chip 100 shown in FIG. 5 is shown in FIG. 6 . It should be noted that FIG.
  • FIG. 6 only schematically shows the structure of the diode P1 and the situation in which the functional circuit 11 is connected to the conductive line 15 through a through hole.
  • the structure of the diode P2 and the structure in which the functional circuit 11 is connected to the power line Vdd through the through hole are respectively the same as the structure of the diode P1 and the structure in which the functional circuit 11 is connected to the conductive line 15 through the through hole.
  • the chip 100 includes a substrate 10 .
  • the substrate 10 is provided with a through hole 12 penetrating the upper and lower surfaces of the substrate 10 .
  • the through hole 12 is formed by etching the substrate 10 .
  • the via 12 is isolated from the substrate 10 by a barrier layer 21 .
  • the material of the barrier layer 21 may include, but is not limited to: silicon nitride (SiNx), titanium nitride (TiN) or titanium tungsten alloy (TiW).
  • N-type semiconductor material 22 and P-type semiconductor material 23 are sequentially deposited on the inner wall and bottom of the through-hole 12 .
  • the N-type semiconductor material 22 is close to the inner wall of the through-hole 12 , that is, close to the barrier layer 21 , and the P-type semiconductor material 23 is close to the inner wall of the through-hole 12 . attached to the N-type semiconductor material 22.
  • the N-type semiconductor material 22 is made by doping polysilicon with phosphorus element
  • the P-type semiconductor material 23 is made by doping polysilicon with boron element.
  • a PN junction is formed between the N-type semiconductor material 22 and the P-type semiconductor material 23 .
  • the through hole 12 is also filled with conductive material 24 , and the conductive material 24 is in contact with the P-type semiconductor material 23 .
  • the conductive material 24 may include, for example, but is not limited to: metal materials, heavily doped polysilicon materials, and the like.
  • the upper surface of the substrate 10 is also provided with conductive lines 13 , which cover the through holes 12 and are connected to the conductive material 24 .
  • the conductive lines 13 are isolated from the N-type semiconductor material 22 and the P-type semiconductor material 23 by insulating materials.
  • the insulating material is silicon oxide, for example.
  • the conductive line 13 is used not only to lead out the anode of the diode P1 but also to connect with the functional circuit 11 .
  • a conductive trace 15 is provided on the lower surface of the substrate 10 , and the conductive trace 15 covers the through hole 12 and is in contact with the N-type semiconductor material 22 .
  • the conductive trace 15 is used not only to draw out the cathode of the diode P1 but also as the common ground Gnd of the chip 100 .
  • the upper surface of the substrate 10 is also provided with a functional circuit 11
  • the substrate 10 is also provided with a through hole 14 penetrating the upper and lower surfaces of the substrate 10 .
  • Via 14 is isolated from substrate 10 by barrier layer 26 .
  • the through hole 14 is filled with conductive material 25.
  • the conductive material 25 in the through hole 14 is connected to the functional circuit 11 and the conductive line 15.
  • the functional circuit 11 is connected to the conductive line 15 through the conductive material 25 in the through hole 14, that is, connected to common ground Gnd.
  • the chip 100 provided by the embodiment of the present application opens a through hole 12 in the substrate of the chip 100, and attaches N-type semiconductor material 22 and P-type semiconductor material 22 to the bottom end and side walls of the through hole 12.
  • a PN junction is formed between the semiconductor material 23, the N-type semiconductor material 22 and the P-type semiconductor material 23.
  • the area of the PN junction of the diode P1 in the chip 100 provided by the application embodiment is the area of the bottom end and the side wall of the through hole. Therefore, compared with the existing technology, the area of the PN junction in the chip per unit area can be increased.
  • the N-type semiconductor material 22 and the P-type semiconductor material 23 are both attached to the bottom end and side walls of the through hole 12, that is, there will be no problem due to the substrate 10 of the chip 100 being too thick.
  • the N-type silicon substrate is deposited too thickly, which can reduce the on-resistance of the electrostatic protection transistor, thereby reducing the voltage clamping capability of the electrostatic protection transistor.
  • the diode P1 in the chip 100 provided by the embodiment of the present application can improve the electrostatic protection performance of the chip 100 .
  • FIG. 7 is a schematic diagram of the planar circuit structure of the chip 100 provided by the embodiment of the present application.
  • the chip 100 includes a transistor G1 and a functional circuit 11.
  • Transistor G1 is an NPN transistor.
  • the transistor is arranged between the conductive line 13 and the conductive line 15 .
  • the functional circuit 11 is connected to the common ground Gnd via a conductive line 15 .
  • the structure of the chip 100 shown in FIG. 7 is as shown in FIG. 8 .
  • N-type semiconductor material 32 , P-type semiconductor material 33 and N-type semiconductor material 34 are sequentially deposited on the inner wall and bottom of the through hole 12 .
  • the N-type semiconductor material 32 is close to the inner wall of the through hole 12 (that is, close to the barrier layer 31 ), the P-type semiconductor material 33 is attached to the N-type semiconductor material 32 , and the N-type semiconductor material 34 is attached to the P-type semiconductor material 33 superior. Therefore, a PN junction is formed between the N-type semiconductor material 32 and the P-type semiconductor material 33 , and a PN junction is formed between the P-type semiconductor material 33 and the N-type semiconductor material 34 .
  • N-type semiconductor material 32 and N-type semiconductor material 34 are realized by doping polysilicon with phosphorus element, and P-type semiconductor material 33 is realized by doping polysilicon with boron element.
  • the conductive line 13 in Figure 8 is connected with the conductive material 35 filled in the through hole 12 to lead out the collector of the transistor G1; the conductive line 15 in Figure 8 is in contact with the N-type semiconductor material 32 to lead out The emitter of transistor G1.
  • other structures in the chip 100 shown in FIG. 8 and the connection relationships between the structures are the same as the structure of the chip 200 shown in FIG. 6 and the connection relationships between the structures. Please refer to FIG. 6 for details. The relevant description of the chip 200 shown will not be described again.
  • the electrostatic protection transistor is an NPN transistor. In a possible implementation manner, the electrostatic protection transistor may also be a PNP transistor.
  • the planar circuit structure schematic diagram of the chip 100 is shown in FIG. 9
  • FIG. 10 is a schematic structural diagram of the chip 100 shown in FIG. 9 . Different from the chip 100 shown in FIGS. 7 and 8 , the chip 100 shown in FIGS. 9 and 10 is a PNP transistor. Therefore, in FIG. 10 , P-type semiconductor material 42 , N-type semiconductor material 43 and P-type semiconductor material 44 are sequentially deposited on the inner wall and bottom of the through hole 12 .
  • the P-type semiconductor material 42 is close to the inner wall of the through hole 12 (that is, close to the barrier layer 41 ), the N-type semiconductor material 43 is attached to the P-type semiconductor material 42 , and the P-type semiconductor material 44 is attached to the N-type semiconductor material 43 superior. Therefore, a PN junction is formed between the P-type semiconductor material 42 and the N-type semiconductor material 43 , and a PN junction is formed between the N-type semiconductor material 43 and the P-type semiconductor material 44 .
  • the conductive line 13 in Figure 8 is connected with the conductive material 45 filled in the through hole 12 to lead out the emitter of the transistor G1; the conductive line 15 in Figure 8 is in contact with the P-type semiconductor material 42 to lead out The collector of transistor G1.
  • FIG. 11 is a schematic diagram of the planar circuit structure of the chip 100 provided by the embodiment of the present application.
  • the electrostatic protection transistor is a thyristor G3.
  • the chip 100 includes a thyristor G3 and a functional circuit 11 .
  • SCR G3 includes NPN transistor and PNP transistor.
  • the emitter of the NPN transistor is connected to the common ground Gnd through the conductive line 15, the collector of the NPN transistor is connected to the base of the PNP transistor, and the base of the NPN transistor is connected to the collector of the PNP transistor.
  • the emitter is connected to the functional circuit 11 via a conductive line 13 .
  • FIG. 12 A cross-sectional view of chip 100 is shown in FIG. 12 .
  • the chip 100 shown in Figure 12 includes a substrate 10, a through hole 12 penetrating the upper and lower surfaces of the substrate 10, a through hole 14 penetrating the upper and lower surfaces of the substrate 10, a conductive line 13 provided on the upper surface of the substrate 10, and a conductive line 13 provided on the upper surface of the substrate 10.
  • N-type semiconductor material 52 , P-type semiconductor material 53 , N-type semiconductor material 54 and P-type semiconductor material 55 are deposited in sequence on the inner wall and bottom of the through hole 12 .
  • the N-type semiconductor material 52 is close to the inner wall of the through hole 12 (that is, close to the barrier layer 51 )
  • the P-type semiconductor material 53 is attached to the N-type semiconductor material 52
  • the N-type semiconductor material 54 is attached to Attached to the P-type semiconductor material 53
  • the P-type semiconductor material 55 is attached to the N-type semiconductor material 54 .
  • a PN junction is formed between the N-type semiconductor material 52 and the P-type semiconductor material 53, a PN junction is formed between the P-type semiconductor material 53 and the N-type semiconductor material 54, and a PN junction is formed between the N-type semiconductor material 54 and the P-type semiconductor material 55.
  • N-type semiconductor material 52 and N-type semiconductor material 54 are realized by doping polysilicon with phosphorus element
  • P-type semiconductor material 53 and P-type semiconductor material 55 are realized by doping polysilicon with boron element.
  • the N-type semiconductor material 52 is made by heavily doping polysilicon with phosphorus elements
  • the P-type semiconductor material 55 is made by heavily doping polysilicon with boron elements.
  • the conductive circuit 13 in Figure 12 is connected with the P-type semiconductor material 55 through the conductive material 56 filled in the through hole 12 to lead out the electrode in the thyristor G3 connected to the functional circuit 11; the conductive circuit in Figure 12 The line 15 is in contact with the N-type semiconductor material 52 to lead out the electrode in the thyristor G3 that is connected to the common ground Gnd.
  • other structures in the chip 100 shown in FIG. 12 and the connection relationships between the structures are the same as the structure of the chip 100 shown in FIG. 6 and the connection relationships between the structures. Please refer to FIG. 6 for details. The relevant description of the chip 200 shown will not be described again.
  • embodiments of the present application also provide a method of manufacturing a chip. Taking the preparation of the chip 100 as shown in Figure 6 as an example, the process of preparing the chip will be described in conjunction with the process 1300 shown in Figure 13. The process is described in detail.
  • the process flow 1300 includes the following steps:
  • Step 1301 Provide a substrate 10, and etch the substrate 10 to form deep trenches 1311 and 1312.
  • the material of the substrate 10 may be silicon, which may also be called a wafer.
  • a patterned photoresist 1313 can be deposited on the surface of the substrate 10, and the substrate 10 can be etched using reactive ions or particle beams. Among them, the portion of the substrate 10 that is not coated with the photoresist 1313 is etched to form deep grooves 1311 and 1312 . The photoresist is then removed using an organic solvent. As shown in Figure 14A.
  • Step 1302 Form barrier layers 21 on the side walls of the deep trench 1311 and the deep trench 1312 respectively.
  • the material of the barrier layer 21 may include, but is not limited to: silicon nitride (SiNx), titanium nitride (TiN) or titanium tungsten (TiW) alloy.
  • the barrier layer 21 as TiN as an example, in this step, chemical vapor deposition (CVD, Chemical Vapor Deposition) or physical vapor deposition (PVD, Physical Vapor Deposition) or other processes can be used to deposit TiN on the exposed surface of the substrate 10 ; Then, use a reactive ion or particle beam process to etch away the TiN on the upper surface of the substrate 10, the TiN on the bottom of the deep trench 1311, and the TiN on the bottom of the deep trench 1312, leaving the TiN on the side walls of the deep trench 1311 and the deep trench 1312. , to form the barrier layer 21 . As shown in Figure 14B.
  • CVD Chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • the material of the filling medium 1333 may include but is not limited to SiOx or SiNx.
  • a CVD process is first used to deposit a filling medium 1333 on the deep grooves 1311 and 1312 and the upper surface of the substrate 10; then, a chemical mechanical polishing (CMP, Chemical Mechanical Polishing) process is used to remove the upper surface of the substrate 10
  • CMP Chemical Mechanical Polishing
  • Step 1304 Etch the filling medium 1333 in the deep trench 1311.
  • photoresist 1341 is first coated on the upper surface of substrate 10 .
  • the photoresist 1341 covers the opening of the deep groove 1312, and the opening of the deep groove 1311 is not covered with the photoresist; then, chemical etching is used to etch away the filling medium 1333 in the deep groove 1311. Since the deep groove 1312 The filling medium 1333 is protected by the photoresist 1341 and is not etched away; finally, the photoresist 1341 on the substrate 10 is removed. As shown in Figure 14D.
  • Step 1305 N-type semiconductor material 22 and P-type semiconductor material 23 are formed on the sidewalls and bottom of the deep trench 1311.
  • a low-pressure chemical vapor deposition (LPCVD, low-pressure chemical vapor deposition) or plasma enhanced chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition) process can first be used to deposit the surface and depth of the exposed substrate 10 Polycrystalline silicon or amorphous silicon is deposited on the surface of groove 1311.
  • PECVD plasma enhanced chemical vapor deposition
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • phosphorus-containing gas can be first introduced to form N-type polysilicon, that is, N-type semiconductor material 22, on the side walls and bottom of the deep trench 1311 and the upper surface of the substrate 10, and then the gas containing phosphorus can be introduced.
  • Boron gas is used to form P-type polysilicon, that is, P-type semiconductor material 23, on N-type polysilicon.
  • a CMP process is used to remove excess polysilicon on the upper surface of the substrate 10 , leaving only the polysilicon in the sidewalls and bottom of the deep trench 1311 . Therefore, N-type semiconductor material 22 and P-type semiconductor material 23 are formed on the sidewalls and bottom of the deep trench 1311, that is, a PN junction is formed. As shown in Figure 14E.
  • Step 1306 Etch the filling medium 1333 in the deep trench 1312.
  • chemical etching may be used to etch away the filling medium 1333 in the deep trench 1312 .
  • Figure 14F As shown in Figure 14F.
  • Step 1307 Fill the deep grooves 1311 and 1312 with metal 24 and metal 25 respectively.
  • a sputtering process can first be used to electroplat a layer of titanium seed layer on the upper surface of the deep trench 1311, the deep trench 1312 and the substrate 10, and then electroplating is used to deposit metallic copper; then, the CMP process is used to remove the upper surface of the substrate 10 metal; then the exposed silicon surface and copper surface are oxidized.
  • the P-type semiconductor material and N-type semiconductor material exposed in the deep trench 1311 are oxidized into silicon oxide, and the exposed silicon oxide surface in the deep trench 1311 and the deep trench 1312 are exposed.
  • the copper material produced is oxidized into copper oxide; finally, ferric chloride solution is used to remove the copper chloride and retain silicon oxide 1371.
  • the structure after this step is shown in Figure 14G.
  • Step 1308 Form conductive lines 13 and 15 on the upper surface of the substrate 10 and the lower surface of the substrate 10 respectively.
  • the conductive lines 13 are connected to the metal 24, and the conductive lines 15 are connected to the N-type semiconductor material 22 and the metal 25.
  • a conductive line 13 is first formed on the upper surface of the substrate 10 .
  • the conductive line 13 may be formed by etching copper.
  • the conductive line 13 covers the notch of the deep groove 1311 and is in contact with the metal 24 .
  • the surface of the metal 25 Conductive lines are also provided on it, which are used to connect the metal 25 and the functional circuit 11; then, the lower surface of the substrate 10 is thinned to expose the bottom N-type semiconductor material 22; then, on the substrate 10 Metal copper is deposited on the lower surface to form a conductive line 15; finally, high temperature annealing is performed to form an ohmic contact between the metal 24 and the P-type semiconductor material 23 to lead out the anode of the diode P1, between the conductive line 15 and the N-type semiconductor material 22 An ohmic contact is formed to lead out the cathode of the diode P1 and activate the doping impurities in the N-type semiconductor material 22 and the P-type semiconductor material 23 . As shown in Figure 14H.
  • the through hole 12 and the through hole 14 can be formed on the substrate 10, and the diode P1 is prepared in the through hole 13.
  • Step 1309 the functional circuit 11 is disposed on the upper surface of the substrate 10 .
  • the functional circuit 11 covers the through hole 14 and is connected to the metal 25 in the through hole 14 .
  • the functional circuit 11 is also connected to the conductive line 13 .
  • the functional circuit 11 is in communication with the anode of the diode P1
  • the functional circuit 11 is in communication with the conductive line 15 through the metal 25 in the through hole 14 to be connected to the common ground.
  • the chip 100 shown in Figure 6 can be prepared.
  • N-type semiconductor materials can be sequentially formed on the side walls and bottom of the deep trench 1311. 32.
  • a LPCVD or PECVD process may be first used to deposit polysilicon on the exposed surface of the substrate 10 and the surface of the deep trench 1311 .
  • N-type polysilicon that is, N-type semiconductor material 32
  • P-type semiconductor material 33 is formed on N-type polysilicon
  • phosphorus-containing gas is introduced to form N-type polysilicon, also known as N-type semiconductor material 34, on P-type polysilicon.
  • a CMP process is used to remove excess polysilicon on the upper surface of the substrate 10 , leaving only the polysilicon in the sidewalls and bottom of the deep trench 1311 .
  • N-type semiconductor material 32 , P-type semiconductor material 33 and N-type semiconductor material 34 are formed on the sidewalls and bottom of the deep trench 1311 .
  • Other process steps are the same as those shown in Figure 6 and will not be described again.
  • P-type semiconductor materials can be sequentially formed on the side walls and bottom of the deep trench 1311. 42.
  • a LPCVD or PECVD process may be first used to deposit polysilicon on the exposed surface of the substrate 10 and the surface of the deep trench 1311 .
  • boron-containing gas can be first introduced to form P-type polysilicon, that is, P-type semiconductor material 42, on the sidewalls and bottom of the deep trench 1311 and the upper surface of the substrate 10, and then the phosphorus-containing gas can be introduced to form N-type polysilicon, also known as N-type semiconductor material 43, is formed on P-type polysilicon. Finally, boron-containing gas is introduced to form P-type polysilicon, also known as P-type semiconductor material 44, on N-type polysilicon. Then, a CMP process is used to remove excess polysilicon on the upper surface of the substrate 10 , leaving only the polysilicon in the sidewalls and bottom of the deep trench 1311 . Thus, P-type semiconductor material 42 , N-type semiconductor material 43 and P-type semiconductor material 44 are formed on the sidewalls and bottom of the deep trench 1311 . Other process steps are the same as those shown in Figure 6 and will not be described again.
  • N-type semiconductor materials can be sequentially formed on the side walls and bottom of the deep trench 1311. 52.
  • a LPCVD or PECVD process may be first used to deposit polysilicon on the exposed surface of the substrate 10 and the surface of the deep trench 1311 .
  • the phosphorus-containing gas can be first introduced to form N-type polysilicon, that is, the N-type semiconductor material 52, on the sidewalls and bottom of the deep trench 1311 and the upper surface of the substrate 10, and then the phosphorus-containing gas can be introduced into the polysilicon deposition process.
  • Boron gas is used to form P-type polysilicon, that is, P-type semiconductor material 53, on N-type polysilicon, and then phosphorus-containing gas is introduced to form N-type polysilicon, that is, N-type semiconductor material 54, on P-type polysilicon.
  • boron-containing gas is introduced to form P-type polysilicon, that is, P-type semiconductor material 55, on N-type polysilicon.
  • N-type semiconductor material 52 , P-type semiconductor material 53 , N-type semiconductor material 54 and P-type semiconductor material 55 are formed on the sidewalls and bottom of the deep trench 1311 .
  • Other process steps are the same as those shown in Figure 6 and will not be described again.

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Abstract

本申请实施例提供了一种芯片和制备方法，该芯片包括衬底，衬底中开设有贯穿衬底上下表面的第一通孔，第一通孔的内壁以及底部依次贴附有至少两层掺杂材料，至少两层掺杂材料中包括P型掺杂材料和N型掺杂材料，第一通孔中还填充有第一导电材料，第一导电材料与至少两层掺杂材料中的第一掺杂材料相接触；设置于衬底上表面的第一导电线路以及功能电路，第一导电线路与第一导电材料以及功能电路相连接；设置于衬底下表面的第二导电线路，第二导电线路与至少两层掺杂材料中的第二掺杂材料相接触，本申请实施例提供的芯片，可以提高单位面积的芯片内，静电防护器件中PN结所占面积的比例，以提高静电防护器件的效率。

Description

芯片和制备方法
本申请要求于2022年07月11日提交中国专利局、申请号为202210807986.8、申请名称为“芯片和制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体技术领域，尤其涉及一种芯片和制备方法。
背景技术
随着半导体技术的发展，芯片上晶体管集成度越来越高，从而芯片的单位面积加工成本也随之增加。为了在保证芯片高性能的基础上、降低芯片生产成本，业界提出将生产成本高、用于实现芯片核心功能的模块(例如芯片中实现数字处理功能的模块、或者实现存储功能的模块)，与生产成本低、用于实现芯片辅助功能或外围功能的模块(例如用于抵抗从生产流程到使用过程中随时可能出现的静电放电事件的静电防护模块)分开制备，然后采用先进封装技术将两个模块封装在一起，以形成一个封装系统。
现有技术中，通常采用二极管作为静电防护器件，通常将二极管设置于核心功能模块的信号端与公共信号线(例如公共地线或电源线)之间。通常，二极管的静电防护能力是由生产过程中PN结面积的大小所决定。然而，现有技术中，当采用独立的制备工艺制备静电防护模块时，单位面积的芯片内，PN结所占的面积过小，如果想要增大PN结面积，需要占用芯片更多的面积，降低了芯片利用率。由此，如何提高单位面积的芯片内，静电防护器件中PN结所占面积的比例，以提高静电防护器件的效率，成为需要解决的问题。
发明内容
通过采用本申请所示的芯片和制备方法，可以提高单位面积的芯片内，静电防护器件中PN结所占面积的比例，以提高静电防护器件的效率。
为达到上述目的，本申请采用如下技术方案：
第一方面，本申请实施例提供一种芯片，该芯片包括衬底，所述衬底中开设有贯穿所述衬底上下表面的第一通孔，所述第一通孔的内壁以及底部依次贴附有至少两层掺杂材料，所述至少两层掺杂材料中包括P型掺杂材料和N型掺杂材料，所述第一通孔中还填充有第一导电材料，所述第一导电材料与所述至少两层掺杂材料中的第一掺杂材料相接触；设置于所述衬底上表面的第一导电线路以及功能电路，所述第一导电线路与所述第一导电材料以及所述功能电路相连接；设置于所述衬底下表面的第二导电线路，所述第二导电线路与所述至少两层掺杂材料中的第二掺杂材料相接触。
本申请实施例提供的芯片，通过在芯片衬底中开设通孔，在通孔的底端和侧壁贴附至少两层多晶硅，该至少两层多晶硅中包括P型掺杂多晶硅和N型掺杂多晶硅，P型掺杂多晶硅和N型掺杂多晶硅形成PN结，与现有技术中静电防护二级管的PN结的面积仅为通孔的横截面积相比，本申请实施例提供的芯片中的静电防护晶体管，其PN结的面积为通孔的底端和侧壁的面积，从而与现有技术相比，可以提高单位面积的芯片内PN结的面积。另外，由于本申请实施例中，P型掺杂多晶硅和N型掺杂多晶硅均贴附于衬底上通孔的底端和侧壁，也即不会由于芯片的衬底过厚导致N型掺杂硅衬底过厚的情况，从而可以降低静电防护晶体管的导通电阻，进而可以降低静电防护晶体管的电压钳位能力。综上，本申请实施例提供的芯片中的静电防护晶体管，可以提高静电防护性能。
基于第一方面，在一种可能的实现方式中，所述衬底中还设置有贯穿所述衬底上下表面的第二通孔，所述第二通孔中填充有第二导电材料；所述功能电路通过所述第二导电材料与所述第二导电线路连接。
基于第一方面，在一种可能的实现方式中，所述芯片包括二极管，所述第一通孔的内壁以及底部 依次贴附有两层掺杂材料，所述第一掺杂材料为P型掺杂材料，所述第二掺杂材料为N型掺杂材料。
基于第一方面，在一种可能的实现方式中，所述芯片包括NPN型三极管，所述第一通孔的内壁以及底部依次贴附有三层掺杂材料，所述三层掺杂材料包括N型掺杂材料、P型掺杂材料和N型掺杂材料；其中，所述第一掺杂材料为N型掺杂材料，所述第二掺杂材料为N型掺杂材料。
基于第一方面，在一种可能的实现方式中，所述芯片包括PNP型三极管，所述第一通孔的内壁以及底部依次贴附有三层掺杂材料，所述三层掺杂材料包括P型掺杂材料、N型掺杂材料和P型掺杂材料；其中，所述第一掺杂材料为P型掺杂材料，所述第二掺杂材料为P型掺杂材料。
基于第一方面，在一种可能的实现方式中，所述芯片包括可控硅，所述第一通孔的内壁以及底部依次贴附有四层掺杂材料，所述四层掺杂材料包括N型掺杂材料、P型掺杂材料、N型掺杂材料和P型掺杂材料；其中，所述第一掺杂材料为P型掺杂材料，所述第二掺杂材料为N型掺杂材料。
基于第一方面，在一种可能的实现方式中，所述芯片还包括基板，所述衬底设置于所述基板之上。
基于第一方面，在一种可能的实现方式中，所述N型掺杂材料是通过在硅材料中掺杂磷元素形成的；所述P型掺杂材料是通过在硅材料中掺杂硼元素形成的。
第二方面，本申请实施例提供一种用于制备芯片的方法，该方法包括：提供以衬底；在所述衬底上形成第一通孔，其中，所述第一通孔贯穿所述衬底的上下表面，所述第一通孔的内壁以及底部依次贴附有至少两层掺杂材料，所述至少两层掺杂材料中包括P型掺杂材料和N型掺杂材料，所述第一通孔中还填充有第一导电材料，所述第一导电材料与所述至少两层掺杂材料中的第一掺杂材料相接触；在所述衬底的上表面形成第一导电线路，所述第一导电线路与所述第一导电材料相连接；在所述衬底的下表面形成第二导电线路，所述第二导电线路与所述至少两层掺杂材料中的第二掺杂材料相接触；在所述衬底的上表面设置功能电路，所述功能电路与所述第一导电线路相连接。
基于第二方面，在一种可能的实现方式中，所述在所述衬底上形成第一通孔，包括：在所述衬底上形成第一通孔和第二通孔；其中，所述第二通孔贯穿所述衬底的上下表面，所述第二通孔中填充有第二导电材料，所述功能电路通过所述第二导电材料与所述第二导电线路连接。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1A是本申请实施例提供的现有技术中具有静电防护的芯片的电路图；
图1B是如图1A所示的二极管的结构示意图；
图2是本申请实施例提供的芯片100的一个结构示意图；
图3是本申请实施例提供的如图2所示的芯片100的一个电路图；
图4是本申请实施例提供的芯片200的一个结构示意图；
图5是本申请实施例提供的如图2所示的芯片100所对应的一个具体实施例的结构示意图；
图6是本申请实施例提供的如图5所示的芯片100的电路图；
图7是本申请实施例提供的如图2所示的芯片100所对应的又一个具体实施例的结构示意图；
图8是本申请实施例提供的如图7所示的芯片100的电路图；
图9是本申请实施例提供的如图2所示的芯片100所对应的又一个具体实施例的结构示意图；
图10是本申请实施例提供的如图9所示的芯片100的电路图；
图11是本申请实施例提供的如图2所示的芯片100所对应的又一个具体实施例的结构示意图；
图12是本申请实施例提供的如图11所示的芯片100的电路图；
图13是本申请实施例提供的如图6所示的芯片100的制备方法流程图；
图14A-图14H是如图6所示的芯片100在制备过程中的各结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本文所提及的"第一"、"第二"以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，"一个"或者"一"等类似词语也不表示数量限制，而是表示存在至少一个。"连接"或者"耦合"等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的，等同于广义上的联通。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或两个以上。例如，多个引脚是指两个或两个以上的引脚。
请参考图1A，图1A是本申请实施例提供的现有技术中具有静电防护的芯片的电路图。在图1A中，具有静电防护的芯片包括电源线、地线、信号线、用于静电防护的二级管P1和二极管P2、以及受保护的功能电路。其中，二极管P1和二极管P2，分别设置于地线与信号线、以及信号线与电源线之间。当正向静电脉冲通过信号线进入芯片中时，电流会沿二极管P2泄放至电源线；当负向静电脉冲通过信号线进入芯片时，电流会沿二极管P1从地流出。
现有技术具有静电防护的芯片的具体制备工艺中，通过在芯片的硅衬底中设置通孔，将二极管P1和二极管P2嵌入于通孔(TSV)中，如图1B所示。在图1B中，芯片包括衬底S、嵌入衬底S中的P型掺杂硅衬底和N型掺杂硅衬底。P型掺杂硅衬底和N型掺杂硅衬底之间形成PN结。与P型掺杂硅衬底接触的金属M1，引出二极管的阳极；与N型掺杂硅衬底接触的金属M2，引出二极管的阴极。此外，N型掺杂硅衬底与衬底S之间、以及P型掺杂硅衬底与N型掺杂硅衬底之间，还设置有阻挡层。从图1B中可以看出，现有技术中，P型掺杂硅衬底设置于底部，N型掺杂硅衬底设置于P型掺杂硅衬底之上，P型掺杂硅衬底与N型掺杂硅衬底接触的部分(也即PN结面积)即为通孔的横截面积，这就导致单位面积的芯片内，PN结面积过小，从而降低了二极管的静电防护效率。另外，将P型掺杂硅衬底和N型掺杂硅衬底沿衬底S的厚度方向上下排布，当衬底S过厚时，N型掺杂硅衬底同样过厚，这就导致二极管的导通电阻大，从而降低二极管的电压钳位能力。
基于如上所述的现有技术中，单位面积的芯片内、静电防护二极管的PN结面积过小的问题，以及衬底S过厚时导致N型掺杂硅衬底过厚的问题，本申请实施例提供的芯片，通过在芯片衬底中开设通孔，在通孔的底端和侧壁贴附至少两层多晶硅，该至少两层多晶硅中包括P型掺杂多晶硅和N型掺杂多晶硅，P型掺杂多晶硅和N型掺杂多晶硅形成PN结，与现有技术中静电防护二级管的PN结的面积仅为通孔的横截面积相比，本申请实施例提供的芯片中的静电防护晶体管，其PN结的面积为通孔的底端和侧壁的面积，从而与现有技术相比，可以提高单位面积的芯片内PN结的面积。另外，由于本申请实施例中，P型掺杂多晶硅和N型掺杂多晶硅均贴附于衬底上通孔的底端和侧壁，也即不会由于芯片的衬底过厚导致N型掺杂硅衬底过厚的情况，从而可以降低静电防护晶体管的导通电阻，进而可以降低静电防护晶体管的电压钳位能力。综上，本申请实施例提供的芯片中的静电防护晶体管，可以提高静电防护性能。下面通过图2～图11所示的实施例，对本申请实施例提供的芯片进行详细阐述。
请参考图2，图2是本申请实施例提供的芯片100的结构示意图。如图2所示，芯片100可以为系统级封装(system in package)芯片，芯片100包括衬底10、设置于衬底10之上的功能电路11。衬底10也可以称为硅晶片，衬底10的材料为硅。衬底10上还开设有通孔12，通孔12中用于嵌入静电防护晶体管，以对功能电路11进行保护。另外，衬底10的上表面还设置有导电线路13，以用于将功能电路11和通孔12中的静电防护晶体管连接。此外，衬底10上还开设有用于将功能电路11与公共地连接的通孔，该通孔可以设置于功能电路11下方被功能电路11覆盖。衬底10的下表面还设置有导电线路，以用于将静电防护晶体管以及功能电路11与公共地连接。图2所示的芯片100的平面电路 结构，如图3所示。其中，衬底10上用于将功能电路11与公共地连接的通孔为图3所示的附图标记14，衬底10下表面的导电线路为图3所示的附图标记15。
图2所示的芯片100为直接在衬底10之上形成的裸芯片，本申请实施例提供的芯片还可以是通过基板封装之后形成的芯片封装结构，如图4所示，图4为本申请实施例提供的芯片200的结构示意图。与图2所示的芯片100相比，图4所示的芯片200还包括基板20，图2所示的芯片100设置于基板20上。基板20上设置有多个引脚21，功能电路11的各引出端、嵌入通孔12中的静电防护晶体管的各引出端、衬底10上的上表面导电线路13以及下表面导电线路15分别引至基板20的各引脚21上，从而实现芯片200与其他芯片或部件之间的板级连接。
本申请实施例中，功能电路11可以为存储器(Memory)、分立器件、应用处理芯片(Application Processor,AP)、微机电系统(Micro-Electro-Mechanical System，MEMS)、微波射频芯片、专用集成电路(ApplicationSpecific Integrated Circuit，简称ASIC)等。该功能电路11可以预先集成于一片或多片裸芯片上，然后再设置于芯片100上。上述应用处理芯片或专用集成电路在具体应用中可以是中央处理器(Central Processing Unit,CPU)、图像处理器(Graphics Processing Unit,GPU)、人工智能处理器(例如神经网络处理器)、集成运算放大器、滤波器等。存储器可以是高速缓冲存储器(cache)、随机存取存储器(Random Access Memory，RAM)、只读存储器(Read Only Memory，ROM)或其他存储器。
本申请实施例提供的静电防护晶体管，可以为二极管、三极管或者可控硅。下面通过图5～图11所示的示例，对本申请实施例提供的静电防护晶体管的结构以及与芯片100中功能电路11之间的连接关系进行更为详细的描述。
参考图5，图5是本申请实施例提供的芯片100中，静电防护晶体管为二极管的平面电路结构示意图。在该种情况下，芯片100包括二极管P1和二极管P2，二极管P1设置于导电线路13与导电线路15(也即公共地Gnd)之间，二极管P2设置于导电线路13和电源线Pdd之间。另外，功能电路11分别与导电线路15以及电源线Pdd连接。如图5所示的芯片100的结构，如图6所示。需要说明的是，图6仅示意性的示出了二极管P1的结构以及功能电路11通过通孔与导电线路15连接的情况。二极管P2的结构以及功能电路11通过通孔与电源线Vdd连接的结构，分别与二极管P1的结构以及功能电路11通过通孔与导电线路15连接的结构相同。
请继续参考图6，在图6中，芯片100包括衬底10，衬底10上设置有贯穿衬底10上下表面的通孔12，通孔12是通过对衬底10刻蚀而形成的。通孔12与衬底10之间通过阻挡层21隔离开。阻挡层21的材料可以包括但不限于：氮化硅(SiNx)、氮化钛(TiN)或钛钨合金(TiW)。在通孔12的内壁以及底部依次沉积有N型半导体材料22和P型半导体材料23，N型半导体材料22紧贴通孔12的内壁，也即紧贴阻挡层21，P型半导体材料23贴附于N型半导体材料22上。N型半导体材料22是在多晶硅中掺杂磷元素实现的，P型半导体材料23是在多晶硅中掺杂硼元素实现的。从而，N型半导体材料22和P型半导体材料23之间形成PN结。通孔12中还填充有导电材料24，导电材料24与P型半导体材料23相接触。该导电材料24例如可以包括但不限于：金属材料、重掺杂的多晶硅材料等。衬底10的上表面还设置有导电线路13，导电线路13覆盖通孔12且与导电材料24相连通。导电线路13与N型半导体材料22以及P型半导体材料23之间通过绝缘材料隔离开。该绝缘材料例如为氧化硅。导电线路13既用于引出二极管P1的阳极，还用于与功能电路11连接。另外衬底10的下表面还设置有导电线路15，该导电线路15覆盖通孔12且与N型半导体材料22相接触。导电线路15既用于引出二极管P1的阴极，还作为芯片100的公共地Gnd。在图6中，衬底10的上表面还设置有功能电路11，衬底10中还设置有贯穿衬底10上下表面的通孔14。通孔14与衬底10之间通过阻挡层26隔离开。通孔14中填充有导电材料25，通孔14中的导电材料25与功能电路11以及导电线路15均连通，功能电路11通过通孔14中的导电材料25与导电线路15连接，也即连接至公共地Gnd。
从图6中可以看出，本申请实施例提供的芯片100，通过在芯片100的衬底中开设通孔12，在通孔12的底端和侧壁贴附N型半导体材料22和P型半导体材料23，N型半导体材料22和P型半导体材料23之间形成PN结，与现有技术中静电防护二级管的PN结的面积仅为通孔的横截面积相比，本 申请实施例提供的芯片100中的二极管P1，其PN结的面积为通孔的底端和侧壁的面积，从而与现有技术相比，可以提高单位面积的芯片内PN结的面积。另外，由于本申请实施例中，N型半导体材料22和P型半导体材料23均贴附于通孔12的底端和侧壁，也即不会由于芯片100的衬底10过厚导致现有技术中N型硅衬底沉积过厚的情况，从而可以降低静电防护晶体管的导通电阻，进而可以降低静电防护晶体管的电压钳位能力。综上，本申请实施例提供的芯片100中的二极管P1，可以提高芯片100的静电防护性能。
当静电防护晶体管为三极管时，请继续参考图7，图7是本申请实施例提供的芯片100的平面电路结构示意图。芯片100中，如图7所示，芯片100包括三极管G1和功能电路11。三极管G1为NPN型晶体管。三极管设置于导电线路13和导电线路15之间。功能电路11通过导电线路15与公共地Gnd连接。图7所示的芯片100的结构，如图8。图8所示的芯片100中，包括衬底10、贯穿衬底10上下表面的通孔12、贯穿衬底10上下表面的通孔14、设置于衬底10上表面的导电线路13、设置于衬底10下表面的导电线路15、以及设置于衬底10之上的功能电路11。与图6所示的芯片100不同的是，通孔12的内壁以及底部依次沉积有N型半导体材料32、P型半导体材料33和N型半导体材料34。N型半导体材料32紧贴通孔12的内壁(也即紧贴阻挡层31)，P型半导体材料33贴附于N型半导体材料32上，N型半导体材料34贴附于P型半导体材料33上。从而，N型半导体材料32和P型半导体材料33之间形成PN结，P型半导体材料33和N型半导体材料34之间形成PN结。N型半导体材料32和N型半导体材料34是在多晶硅中掺杂磷元素实现的，P型半导体材料33是在多晶硅中掺杂硼元素实现的。此外，图8中的导电线路13，与通孔12中所填充的导电材料35相连通，以引出三极管G1的集电极；图8中的导电线路15与N型半导体材料32相接触，以引出三极管G1的发射极。除此之外，图8所示的芯片100中的其他结构以及各结构之间的连接关系，与图6所示的芯片200的结构以及各结构之间的连接关系均相同，具体参考图6所示的芯片200中的相关描述，不再赘述。
如图7和图8所示的芯片100中，静电防护晶体管为NPN型三极管。在一种可能的实现方式中，静电防护晶体管也可以为PNP型三极管。当静电防护晶体管为PNP型三极管时，芯片100的平面电路结构示意图如图9所示，图10为图9所示的芯片100的结构示意图。与图7和图8所示的芯片100不同的是，图9和图10所示的芯片100为PNP型三极管。从而，图10中，通孔12的内壁以及底部依次沉积有P型半导体材料42、N型半导体材料43和P型半导体材料44。P型半导体材料42紧贴通孔12的内壁(也即紧贴阻挡层41)，N型半导体材料43贴附于P型半导体材料42上，P型半导体材料44贴附于N型半导体材料43上。从而，P型半导体材料42和N型半导体材料43之间形成PN结，N型半导体材料43和P型半导体材料44之间形成PN结。此外，图8中的导电线路13，与通孔12中所填充的导电材料45相连通，以引出三极管G1的发射极；图8中的导电线路15与P型半导体材料42相接触，以引出三极管G1的集电极。除此之外，图10所示的芯片100中的其他结构以及各结构之间的连接关系，与图7所示的芯片100的结构以及各结构之间的连接关系均相同，具体参考图7所示的芯片100中的相关描述，不再赘述。
请继续参考图11，图11是本申请实施例提供的芯片100的平面电路结构示意图。芯片100中，静电防护晶体管为可控硅G3。如图11所示，芯片100包括可控硅G3和功能电路11。可控硅G3包括NPN型晶体管和PNP型晶体管。NPN型晶体管的发射极通过导电线路15与公共地Gnd连接，NPN型晶体管的集电极与PNP型晶体管的基极连接，NPN型晶体管的基极与PNP型晶体管的集电极连接，PNP型晶体管的发射极通过导电线路13与功能电路11连接。从而，可控硅G3中包括三个PN结。功能电路11通过导电线路15与公共地Gnd连接。芯片100的剖视图如图12所示。图12所示的芯片100，包括衬底10、贯穿衬底10上下表面的通孔12、贯穿衬底10上下表面的通孔14、设置于衬底10上表面的导电线路13、设置于衬底10下表面的导电线路15、以及设置于衬底10之上的功能电路11。与以上各实施例所示的芯片不同的是，通孔12的内壁以及底部依次沉积有N型半导体材料52、P型半导体材料53、N型半导体材料54和P型半导体材料55。N型半导体材料52紧贴通孔12的内壁(也即紧贴阻挡层51)，P型半导体材料53贴附于N型半导体材料52上，N型半导体材料54贴 附于P型半导体材料53上，P型半导体材料55贴附于N型半导体材料54上。从而，N型半导体材料52和P型半导体材料53之间形成PN结，P型半导体材料53和N型半导体材料54之间形成PN结，N型半导体材料54和P型半导体材料55之间形成PN结。N型半导体材料52和N型半导体材料54是在多晶硅中掺杂磷元素实现的，P型半导体材料53和P型半导体材料55是在多晶硅中掺杂硼元素实现的。在一种可能的实现方式中，N型半导体材料52是在多晶硅中重掺杂磷元素实现的，P型半导体材料55是在多晶硅中重掺杂硼元素实现的，上述重掺杂的浓度大于等于1E18cm^-3。此外，图12中的导电线路13，通过通孔12中填充的导电材料56与P型半导体材料55相连通，以引出可控硅G3中、与功能电路11连接的电极；图12中的导电线路15与N型半导体材料52相接触，以引出可控硅G3中、与公共地Gnd连接的电极。除此之外，图12所示的芯片100中的其他结构以及各结构之间的连接关系，与图6所示的芯片100的结构以及各结构之间的连接关系均相同，具体参考图6所示的芯片200中的相关描述，不再赘述。
基于如上所述的芯片的结构，本申请实施例还提供一种制作芯片的方法，下面以制备如图6所示的芯片100为例，结合图13所示的流程1300，对制备芯片的工艺流程进行详细描述。该工艺流程1300包括如下步骤：
步骤1301，提供一衬底10，刻蚀衬底10以形成深槽1311和深槽1312。衬底10的材料可以为硅，也可以称为晶片。该步骤中，可以在衬底10的表面沉积图案化的光刻胶1313，利用反应离子或粒子束实现对衬底10的刻蚀。其中，衬底10上未涂布光刻胶1313的部分被刻蚀，形成深槽1311和深槽1312。然后采用有机溶剂去除光刻胶。如图14A所示。
步骤1302，分别在深槽1311和深槽1312的侧壁形成阻挡层21。阻挡层21的材料可以包括但不限于：氮化硅(SiNx)、氮化钛(TiN)或钛钨(TiW)合金。以阻挡层21为TiN为例，该步骤中，可以采用化学气相淀积(CVD，Chemical Vapor Deposition)或者物理气相沉积(PVD，Physical Vapor Deposition)等工艺，在衬底10暴露出的表面沉积TiN；然后，采用反应离子或粒子束工艺，刻蚀掉衬底10上表面的TiN、深槽1311槽底的TiN以及深槽1312槽底的TiN，保留深槽1311和深槽1312侧壁的TiN，以形成阻挡层21。如图14B所示。
步骤1303，在深槽1311和深槽1312中沉积填充介质1333。填充介质1333的材料可以包括但不限于SiOx或者SiNx等。该步骤中，首先利用CVD工艺，在深槽1311和深槽1312以及衬底10的上表面沉积填充介质1333；然后，采用化学机械抛光(CMP，Chemical Mechanical Polishing)工艺，去除衬底10上表面多余的填充介质1333，仅保留深槽1311和深槽1312中的填充介质1333。如图14C所示。
步骤1304，刻蚀深槽1311中的填充介质1333。该步骤中，首先在衬底10的上表面涂布光刻胶1341。光刻胶1341覆盖深槽1312的槽口，深槽1311的槽口之上未覆盖光刻胶；然后，采用化学刻蚀的方法刻蚀掉深槽1311中的填充介质1333，由于深槽1312中的填充介质1333被光刻胶1341保护起来，未被刻蚀掉；最后，去除衬底10之上的光刻胶1341。如图14D所示。
步骤1305，在深槽1311的侧壁和底部形成N型半导体材料22和P型半导体材料23。该步骤中，首先可以采用低压化学气相沉积(LPCVD，low-pressure chemical vapor deposition)或者等离子体增强化学气相沉积(PECVD，Plasma Enhanced Chemical Vapor Deposition)工艺，在暴露出的衬底10的表面以及深槽1311的表面沉积多晶硅或者非晶硅，多晶硅或者非晶硅沉积过程中，通过控制反应腔体内的杂质源气体含量，即可实现多晶硅或者非晶硅的原位掺杂。具体实现中，多晶硅沉积过程中可以首先通入含磷气体，以在深槽1311的侧壁、底部以及衬底10的上表面形成N型多晶硅，也即N型半导体材料22，再通入含硼气体，以在N型多晶硅之上形成P型多晶硅，也即P型半导体材料23。然后，采用CMP工艺去除衬底10上表面多余的多晶硅，仅保留深槽1311的侧壁和底部中的多晶硅。从而，在深槽1311的侧壁和底部形成N型半导体材料22和P型半导体材料23，也即形成PN结。如图14E所示。
步骤1306，刻蚀深槽1312中的填充介质1333。该步骤中，可以采用化学刻蚀的方法刻蚀掉深槽1312中的填充介质1333。如图14F所示。
步骤1307，在深槽1311和深槽1312中分别填充金属24和金属25。该步骤中，可以首先采用溅射工艺在深槽1311、深槽1312以及衬底10的上表面电镀一层种子层钛，再用电镀沉积金属铜；接着，采用CMP工艺去除衬底10上表面的金属；然后对暴露出的硅表面以及铜表面进行氧化，具体的，深槽1311中暴露出的P型半导体材料和N型半导体材料被氧化成氧化硅，深槽1311和深槽1312中暴露出的铜材料被氧化成氧化铜；最后，采用氯化铁溶液去除氯化铜，保留氧化硅1371。该步骤后的结构如图14G所示。
步骤1308，在衬底10的上表面以及衬底10的下表面分别形成导电线路13和导电线路15，其中，导电线路13与金属24连通，导电线路15与N型半导体材料22和金属25连通。该步骤中，首先在衬底10的上表面形成导电线路13，该导电线路13可以是对铜刻蚀形成的，导电线路13覆盖深槽1311的槽口且与金属24接触，金属25的表面之上也设置有导电线路，该导电线路用于连接金属25与功能电路11；接着，对衬底10的下表面减薄以暴露出底部的N型半导体材料22；然后，在衬底10的下表面沉积金属铜以形成导电线路15；最后，进行高温退火，使得金属24与P型半导体材料23之间形成欧姆接触，以引出二极管P1的阳极，导电线路15与N型半导体材料22之间形成欧姆接触，以引出二极管P1的阴极，并激活N型半导体材料22和P型半导体材料23中的掺杂杂质。如图14H所示。
经过步骤1301～步骤1308，即可在衬底10上形成通孔12和通孔14，并且在通孔13中制备出二极管P1。
步骤1309，将功能电路11设置于衬底10的上表面，功能电路11覆盖通孔14且与通孔14中的金属25连通，此外功能电路11还与导电线路13连通。从而，功能电路11与二极管P1的阳极连通，功能电路11通过通孔14中的金属25与导电线路15连通，以连接至公共地。
经过步骤1301-步骤1309，可以制备出如图6所示的芯片100。
在制备出如图6所示的芯片100的基础上，当需要制备如图8所示的芯片100时，在上述步骤1305中，可以在深槽1311的侧壁和底部依次形成N型半导体材料32、P型半导体材料33和N型半导体材料34。具体的，可以首先可以采用LPCVD或者PECVD工艺，在暴露出的衬底10的表面以及深槽1311的表面沉积多晶硅。多晶硅沉积过程中可以首先通入含磷气体，以在深槽1311的侧壁、底部以及衬底10的上表面形成N型多晶硅，也即N型半导体材料32，再通入含硼气体，以在N型多晶硅之上形成P型多晶硅，也即P型半导体材料33，最后再通入含磷气体，以在P型多晶硅之上形成N型多晶硅，也即N型半导体材料34。然后，采用CMP工艺去除衬底10上表面多余的多晶硅，仅保留深槽1311的侧壁和底部中的多晶硅。从而，在深槽1311的侧壁和底部形成N型半导体材料32、P型半导体材料33和N型半导体材料34。其他工艺步骤与图6所示的其他工艺步骤相同，不再赘述。
在制备出如图6所示的芯片100的基础上，当需要制备如图10所示的芯片100时，在上述步骤1305中，可以在深槽1311的侧壁和底部依次形成P型半导体材料42、N型半导体材料43和P型半导体材料44。具体的，可以首先可以采用LPCVD或者PECVD工艺，在暴露出的衬底10的表面以及深槽1311的表面沉积多晶硅。多晶硅沉积过程中可以首先通入含硼气体，以在深槽1311的侧壁、底部以及衬底10的上表面形成P型多晶硅，也即P型半导体材料42，再通入含磷气体，以在P型多晶硅之上形成N型多晶硅，也即N型半导体材料43，最后再通入含硼气体，以在N型多晶硅之上形成P型多晶硅，也即P型半导体材料44。然后，采用CMP工艺去除衬底10上表面多余的多晶硅，仅保留深槽1311的侧壁和底部中的多晶硅。从而，在深槽1311的侧壁和底部形成P型半导体材料42、N型半导体材料43和P型半导体材料44。其他工艺步骤与图6所示的其他工艺步骤相同，不再赘述。
在制备出如图6所示的芯片100的基础上，当需要制备如图12所示的芯片100时，在上述步骤1305中，可以在深槽1311的侧壁和底部依次形成N型半导体材料52、P型半导体材料53、N型半导体材料54和P型半导体材料55。具体的，可以首先可以采用LPCVD或者PECVD工艺，在暴露出的衬底10的表面以及深槽1311的表面沉积多晶硅。多晶硅沉积过程中可以首先通入含磷气体，以在深槽1311的侧壁、底部以及衬底10的上表面形成N型多晶硅，也即N型半导体材料52，再通入含 硼气体，以在N型多晶硅之上形成P型多晶硅，也即P型半导体材料53，再通入含磷气体，以在P型多晶硅之上形成N型多晶硅，也即N型半导体材料54，最后再通入含硼气体，以在N型多晶硅之上形成P型多晶硅，也即P型半导体材料55。然后，采用CMP工艺去除衬底10上表面多余的多晶硅，仅保留深槽1311的侧壁和底部中的多晶硅。从而，在深槽1311的侧壁和底部形成N型半导体材料52、P型半导体材料53、N型半导体材料54和P型半导体材料55。其他工艺步骤与图6所示的其他工艺步骤相同，不再赘述。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (10)

  1. 一种芯片，其特征在于，包括：
    衬底，所述衬底中开设有贯穿所述衬底上下表面的第一通孔，所述第一通孔的内壁以及底部依次贴附有至少两层掺杂材料，所述至少两层掺杂材料中包括P型掺杂材料和N型掺杂材料，所述第一通孔中还填充有第一导电材料，所述第一导电材料与所述至少两层掺杂材料中的第一掺杂材料相接触；
    设置于所述衬底上表面的第一导电线路以及功能电路，所述第一导电线路与所述第一导电材料以及所述功能电路相连接；
    设置于所述衬底下表面的第二导电线路，所述第二导电线路与所述至少两层掺杂材料中的第二掺杂材料相接触。
  2. 根据权利要求1所述的芯片，其特征在于，所述衬底中还设置有贯穿所述衬底上下表面的第二通孔，所述第二通孔中填充有第二导电材料；
    所述功能电路通过所述第二导电材料与所述第二导电线路连接。
  3. 根据权利要求1或2所述的芯片，其特征在于，所述芯片包括二极管，所述第一通孔的内壁以及底部依次贴附有两层掺杂材料，所述第一掺杂材料为P型掺杂材料，所述第二掺杂材料为N型掺杂材料。
  4. 根据权利要求1或2所述的芯片，其特征在于，所述芯片包括NPN型三极管，所述第一通孔的内壁以及底部依次贴附有三层掺杂材料，所述三层掺杂材料包括N型掺杂材料、P型掺杂材料和N型掺杂材料；其中，
    所述第一掺杂材料为N型掺杂材料，所述第二掺杂材料为N型掺杂材料。
  5. 根据权利要求1或2所述的芯片，其特征在于，所述芯片包括PNP型三极管，所述第一通孔的内壁以及底部依次贴附有三层掺杂材料，所述三层掺杂材料包括P型掺杂材料、N型掺杂材料和P型掺杂材料；其中，
    所述第一掺杂材料为P型掺杂材料，所述第二掺杂材料为P型掺杂材料。
  6. 根据权利要求1或2所述的芯片，其特征在于，所述芯片包括可控硅，所述第一通孔的内壁以及底部依次贴附有四层掺杂材料，所述四层掺杂材料包括N型掺杂材料、P型掺杂材料、N型掺杂材料和P型掺杂材料；其中，
    所述第一掺杂材料为P型掺杂材料，所述第二掺杂材料为N型掺杂材料。
  7. 根据权利要求1-6任一项所述的芯片，其特征在于，所述芯片还包括基板，所述衬底设置于所述基板之上。
  8. 根据权利要求1-7任一项所述的芯片，其特征在于，
    所述N型掺杂材料是通过在硅材料中掺杂磷元素形成的；
    所述P型掺杂材料是通过在硅材料中掺杂硼元素形成的。
  9. 一种用于制备芯片的方法，其特征在于，包括：
    提供以衬底；
    在所述衬底上形成第一通孔，其中，所述第一通孔贯穿所述衬底的上下表面，所述第一通孔的内壁以及底部依次贴附有至少两层掺杂材料，所述至少两层掺杂材料中包括P型掺杂材料和N型掺杂材料，所述第一通孔中还填充有第一导电材料，所述第一导电材料与所述至少两层掺杂材料中的第一 掺杂材料相接触；
    在所述衬底的上表面形成第一导电线路，所述第一导电线路与所述第一导电材料相连接；
    在所述衬底的下表面形成第二导电线路，所述第二导电线路与所述至少两层掺杂材料中的第二掺杂材料相接触；
    在所述衬底的上表面设置功能电路，所述功能电路与所述第一导电线路相连接。
  10. 根据权利要求9所述的方法，其特征在于，所述在所述衬底上形成第一通孔，包括：
    在所述衬底上形成第一通孔和第二通孔；
    其中，所述第二通孔贯穿所述衬底的上下表面，所述第二通孔中填充有第二导电材料，所述功能电路通过所述第二导电材料与所述第二导电线路连接。
PCT/CN2023/106063 2022-07-11 2023-07-06 芯片和制备方法 WO2024012342A1 (zh)

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CN107452622A (zh) * 2016-05-31 2017-12-08 北大方正集团有限公司 双向沟槽tvs二极管及制作方法
CN210443555U (zh) * 2019-11-13 2020-05-01 江苏丽隽功率半导体有限公司 一种集成高密度静电防护芯片

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* Cited by examiner, † Cited by third party
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JP2003282715A (ja) * 2002-03-25 2003-10-03 Matsushita Electric Ind Co Ltd 半導体保護装置
CN104183625A (zh) * 2013-05-10 2014-12-03 英飞凌科技奥地利有限公司 补偿器件
CN107452622A (zh) * 2016-05-31 2017-12-08 北大方正集团有限公司 双向沟槽tvs二极管及制作方法
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