Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/408—Address circuits
  • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C2211/4016—Memory devices with silicon-on-insulator cells

Definitions

• the present invention relates to a memory device using a semiconductor element.
• SGT Short Gate Transistor
• Non-Patent Document 1 is used as a selection transistor to connect a DRAM (Dynamic Random Access Memory, see Non-Patent Document 2) with a capacitor connected, and a variable resistance element.
• PCM Phase Change Memory, see e.g. Non-Patent Document 3
• RRAM Resistive Random Access Memory
• MRAM Magneto-resistive Random Access Memory
• DRAM memory cells (see Patent Document 2 and Non-Patent Documents 6 to 10) that are configured with one MOS transistor and do not have a capacitor. For example, holes, electron groups, or part or all of the hole groups generated in the channel by the impact ionization phenomenon due to the current between the source and drain of an N-channel MOS transistor are held in the channel to store logic storage data. 1” is written. Then, the hole group is removed from the channel to write logical storage data "0". In this memory cell, there are randomly written "1" memory cells and "0" written memory cells for a common selected word line.
• the floating body channel voltage of the selected memory cell connected to the selected word line varies greatly due to capacitive coupling between the gate electrode and the channel.
• the challenges of this memory cell are to improve the reduction in operating margin due to floating body channel voltage fluctuations, and to improve the reduction in data retention characteristics by removing part of the hole group, which is the signal charge accumulated in the channel. It is.
• Twin-Transistor MOS transistor memory element in which one memory cell is formed using two MOS transistors in an SOI layer (see, for example, Patent Documents 3 and 4, and Non-Patent Document 11).
• an N + layer that serves as a source or drain that separates floating body channels of two MOS transistors is formed in contact with an insulating layer on the substrate side.
• This N + layer electrically isolates the floating body channels of the two MOS transistors.
• a group of holes, which are signal charges, are accumulated only in the floating body channel of one MOS transistor.
• the other MOS transistor serves as a switch for reading out the hole group of the signal accumulated in one MOS transistor.
• a group of holes, which are signal charges are accumulated in the channel of one MOS transistor. The problem is to improve the deterioration of data retention characteristics due to the removal of part of the hole group, which is the signal charge.
• a memory 111 shown in FIG. 5 that is configured with MOS transistors and does not have a capacitor (see Patent Document 5 and Non-Patent Document 12).
• a floating body semiconductor matrix 102 is provided on the SiO 2 layer 101 of the SOI substrate.
• the first gate insulating layer 109a is connected to the N + layer 103 and covers the floating body semiconductor base 102, and is connected to the N + layer 104 and the first gate insulating layer 109a, via the slit insulating film 110.
• a second gate insulating layer 109b covering the floating body semiconductor base body 102.
• There is a first gate conductor layer 105a covering the first gate insulating layer 109a and connected to the plate line PL, and a second gate conductor layer covering the second gate insulating layer 109b and connected to the word line WL.
• a memory cell 111 of a DFM (Dynamic Flash Memory) is formed. Note that the configuration may be such that the source line SL is connected to the N + layer 104 and the bit line BL is connected to the N + layer 103.
• DFM Dynamic Flash Memory
• the floating body semiconductor base body 102 covered with the first gate conductor layer 105a is operated in the linear region.
• an inversion layer 107b is formed over the entire surface of the second N-channel MOS transistor region without a pinch-off point.
• the inversion layer 107b formed under the second gate conductor layer 105b connected to the word line WL serves as a substantial drain of the first N-channel MOS transistor region.
• the electric field becomes maximum in the boundary region of the channel region between the first N-channel MOS transistor region and the second N-channel MOS transistor region, and an impact ionization phenomenon occurs in this region.
• the electron group among the electron/hole groups generated by the impact ionization phenomenon is removed from the floating body semiconductor matrix 102, and part or all of the hole group 106 is placed in the floating body.
• a memory write operation is performed by holding it in the body semiconductor matrix 102. This state becomes logical storage data "1".
• the hole group 106 is moved into a floating body. It is removed from the semiconductor matrix 102 to perform an erasing operation. This state becomes logical storage data "0".
• the voltage applied to the first gate conductor layer 105a connected to the plate line PL is set to be higher than the threshold voltage when the logical storage data is "1" and higher than the threshold voltage when the logical storage data is "0".
• the operating margin can be significantly expanded compared to memory cells.
• the channels of the first and second N-channel MOS transistor regions whose gates are the first gate conductor layer 105a connected to the plate line PL and the second gate conductor layer 105b connected to the word line WL are By connecting through the floating body semiconductor base body 102, voltage fluctuations in the floating body semiconductor base body 102 when a selection pulse voltage is applied to the word line WL are greatly suppressed.
• Critoloveanu “A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration,” Electron Device Letters, Vol. 35, No.2, pp. 179-181 (2012) T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao, and K. Sunouchi: “Memory design using a one-transistor gain cell on SOI,” IEEE JSSC, vol.37, No.11, pp1510-1522 (2002). T. Shino, N. Kusunoki, T. Higashi, T. Ohsawa, K. Fujita, K. Hatsuda, N. Ikumi, F.
• a memory device using a semiconductor element includes: A memory device in which a page is configured by a plurality of memory cells arranged in a row direction on a substrate, and the plurality of pages are arranged in a column direction when viewed from above,
• the memory cells included in each page are: a semiconductor body standing vertically or extending horizontally on the substrate; a first impurity layer and a second impurity layer at both ends of the semiconductor matrix; surrounds a part or all of the side surface of the semiconductor matrix on the first impurity layer side between the first impurity layer and the second impurity layer, and is in contact with the first impurity layer, or a first gate insulating layer in close proximity; a second gate insulating layer surrounding the side surface of the semiconductor base body, connected to the first gate insulating layer, and in contact with or close to the second impurity layer; a first gate conductor layer that partially or entirely covers the first gate insulating layer; a second gate conductor layer covering
• One side is connected to the word line, the other side is connected to the plate line, controlling voltages applied to the source line, the bit line, the word line, and the plate line to perform a page write operation, a page erase operation, and a page read operation;
• a page write operation a hole group formed by impact ionization is held inside the channel semiconductor layer at a first time, and the hole group is held at a second time following the first time.
• a page write post-processing operation is performed to eliminate the surplus hole group. (first invention).
• the voltage of the channel semiconductor layer is set to a first data retention voltage higher than the voltage of one or both of the first impurity layer and the second impurity layer.
• voltages applied to the first impurity layer, the second impurity layer, the first gate conductor layer, and the second gate conductor layer are controlled to erase the channel semiconductor. extinguishing the hole group in the layer and setting the voltage of the channel semiconductor layer to a second data retention voltage lower than the first data retention voltage; (Second invention).
• a pulse voltage is applied to at least one of the source line, the bit line, the word line, and the plate line during the page write post-processing operation.
• a higher voltage is applied to at least one of the bit line, the word line, and the plate line than during the page read operation.
• the pulse voltage is applied at least once to the selected page during the page write post-processing operation.
• the word line and the plate line are arranged in parallel in plan view
• the bit line is arranged in a direction perpendicular to the word line and the plate line in a plan view.
• a first gate capacitance between the first gate conductor layer or the second gate conductor layer and the channel semiconductor layer to which the plate line is connected is connected to the word line. is larger than a second gate capacitance between the first gate conductor layer or the second gate conductor layer and the channel semiconductor layer, (Eighth invention).
• the source line is commonly disposed on the adjacent pages in plan view. (10th invention).
• the channel semiconductor layer is a P-type semiconductor layer
• the first impurity layer and the second impurity layer are N-type semiconductor layers. (12th invention).
• the word line and the plate line are connected to a row decoder circuit, a row address is input to the row decoder circuit, and the page is selected according to the row address. (14th invention).
• FIG. 3 is a diagram for explaining a page erase operation mechanism of the memory device according to the first embodiment.
• FIG. 3 is a diagram for explaining a page erase operation mechanism of the memory device according to the first embodiment.
• FIG. 3 is a diagram for explaining a page erase operation mechanism of the memory device according to the first embodiment.
• FIG. 3 is a diagram for explaining a page erase operation mechanism of the memory device according to the first embodiment.
• FIG. 2 is a diagram for explaining a conventional dynamic flash memory.
• a memory device using a semiconductor element (hereinafter referred to as a dynamic flash memory) according to an embodiment of the present invention will be described with reference to the drawings.
• FIGS. 1 to 4 The structure and operating mechanism of a dynamic flash memory cell according to a first embodiment of the present invention will be explained using FIGS. 1 to 4.
• the structure of a dynamic flash memory cell will be explained using FIG. 1.
• a page write operation mechanism will be explained using FIG. 2
• a page write post-processing operation will be explained using FIG. 3
• a page erase operation mechanism will be explained using FIG.
• a first gate insulating layer 4a (which is an example of a “first gate insulating layer” in the claims) and a second gate insulating layer 4b (an example of a “first gate insulating layer” in the claims) surround this channel region 7. 2) is formed.
• the first gate insulating layer 4a and the second gate insulating layer 4b are in contact with or close to the N + layers 3a and 3b, which become the source and drain, respectively.
• a first gate conductor layer 5a (which is an example of a "first gate conductor layer” in the claims) and a second gate conductor layer surround the first gate insulating layer 4a and the second gate insulating layer 4b.
• a gate conductor layer 5b (which is an example of a "second gate conductor layer” in the claims) is formed respectively.
• the first gate conductor layer 5a and the second gate conductor layer 5b are separated by an insulating layer 6.
• the channel region 7 between the N + layers 3a and 3b includes a first channel region 7a surrounded by the first gate insulating layer 4a and a second channel region surrounded by the second gate insulating layer 4b. 7b and more.
• a dynamic flash memory cell 10 is formed.
• the N + layer 3a serving as a source is connected to a source line SL (an example of a "source line” in the claims), and the N + layer 3b serving as a drain is connected to a bit line BL (an example of a "bit line” in the claims).
• the first gate conductor layer 5a is connected to the plate line PL (which is an example of the "plate line” in the claims), and the second gate conductor layer 5b is connected to the word line WL (which is an example of the "plate line” in the claims).
• the first gate capacitance (which is an example of the "first gate capacitance” in the claims) of the first gate conductor layer 5a to which the plate line PL is connected is the same as that of the first gate conductor layer 5a to which the word line WL is connected. It is desirable to have a structure that is larger than the second gate capacitance (which is an example of the "second gate capacitance” in the claims) of the second gate conductor layer 5b.
• FIG. 2A and 2B show a page write operation (which is an example of a "page write operation” in the claims) of the dynamic flash memory cell according to the first embodiment of the present invention.
• FIG. 2A(a) shows the mechanism of the write operation
• FIG. 2A(b) shows the operation waveforms of the bit line BL, source line SL, plate line PL, word line WL, and the channel region 7 serving as the floating body FB.
• the dynamic flash memory cell is in the "0" erased state, and the voltage of the channel region 7 is V FB "0".
• Vss is applied to the bit line BL, source line SL, and word line WL
• V PLL is applied to the plate line PL.
• an annular inversion layer 12b is formed in the channel region 7 on the inner periphery of the second gate conductor layer 5b, and the connection between the word line WL and the channel region 7 is Blocks the capacitive coupling of 2.
• V PLL 2V
• the second gate conductor layer 5b to which the word line WL is connected is , increase V WLH to 4V.
• an annular inversion layer 12a is formed in the channel region 7 on the inner periphery of the first gate conductor layer 5a to which the plate line PL is connected. , there is a pinch-off point 13.
• the first N-channel MOS transistor region having the first gate conductor layer 5a operates in the saturated region.
• the second N-channel MOS transistor region having the second gate conductor layer 5b connected to the word line WL operates in a linear region.
• the inversion layer 12b is formed over the entire inner periphery of the gate conductor layer 5b.
• the inversion layer 12b formed entirely on the inner periphery of the second gate conductor layer 5b connected to the word line WL serves as a substantial drain of the first N-channel MOS transistor region.
• the electric field is at its maximum in the first boundary region, and an impact ionization phenomenon occurs in this region. Since this region is a region on the source side as seen from the second N-channel MOS transistor region having the second gate conductor layer 5b connected to the word line WL, this phenomenon is called a source-side impact ionization phenomenon. Due to this source-side impact ionization phenomenon, electrons flow from the N + layer 3a connected to the source line SL toward the N + layer 3b connected to the bit line.
• the accelerated electrons collide with lattice Si atoms, and their kinetic energy generates electron-hole pairs. A part of the generated electrons flows to the first gate conductor layer 5a and the second gate conductor layer 5b, but most of them flow to the N + layer 3b connected to the bit line BL (not shown).
• the generated hole group 9 (which is an example of the "hole group” in the claims) is the majority carrier in the channel region 7, and Charge to positive bias. Since the N + layer 3a to which the source line SL is connected has a voltage of 0 V, the channel region 7 has a built-in voltage Vb (about 0 V) of the PN junction between the N + layer 3a to which the source line SL is connected and the channel region 7. .7V). When channel region 7 is charged to a positive bias, the threshold voltages of the first N-channel MOS transistor region and the second N-channel MOS transistor region become lower due to the substrate bias effect.
• a memory write operation is performed to set the "1" write state of the channel region 7 as a first data holding voltage (which is an example of the "first data holding voltage” in the claims), and logical storage data "1" is performed. ”. Furthermore, in the "0" erased state of the channel region 7, the first N-channel MOS transistor region of the first channel region 7a connected to the plate line PL and the second channel region 7b connected to the word line WL Since the threshold voltage of the second N-channel MOS transistor region becomes high, if the applied voltage of the plate line PL is set below the threshold voltage, the cell current Icell will not flow even if the voltage of the word line WL is increased. do not have.
• bit line BL bit line
• source line SL word line
• word line WL word line
• plate line PL potential of the floating body
• FIG. 3A shows the operation waveforms of the word line WL, plate line PL, bit line BL, and source line SL during the page write post-processing operation after the page write operation of the dynamic flash memory cell, and the waveforms accumulated in the channel semiconductor layer 7.
• the number Holes of the hole groups 9 and the memory cell current Icell are shown.
• word line WL and plate line PL are selected, first voltage V1 is applied to word line WL, and second voltage V2 is applied to plate line PL, and a page write operation is started.
• a third voltage V3 is applied to the bit line BL connected to the memory cell in which logic "1" is to be written in the selected page (which is an example of a "page” in the claims).
• the first voltage V1, the second voltage V2, and the third voltage V3 are, for example, 1.5V, 1.3V, and 1.0V.
• an impact ionization phenomenon occurs in the channel region 7 near the intermediate layer between the word line WL and the plate line PL, and electron-hole pairs are generated.
• the generated electron group flows to the bit line BL, and the generated hole group 9 is accumulated in the channel semiconductor layer 7. Therefore, the voltage of channel semiconductor layer 7 increases, and the threshold voltages of the MOS transistor regions of word line WL and plate line PL decrease due to this substrate bias effect.
• the number of holes in the hole group 9 changes from the number of holes in the neutral state N1 to N2 at the first time T3 (which is an example of the "first time” in the claims). increases to Furthermore, the memory cell current Icell increases from I0 to I1. Thereafter, the word line WL, plate line PL, and bit line BL return to, for example, the ground voltage Vss, and the operation of accumulating the hole group 9 in the channel semiconductor layer 7 in the page write operation is once completed.
• the fourth voltage V4, the fifth voltage V5, and the sixth voltage V6 may be, for example, the same voltage as in the page read operation.
• the surplus hole group disappears, the number Holes of the hole group 9 decreases from the number N2 to N3, and the memory cell current Icell decreases from I2 to I3.
• Dynamic flash memory cells require stable page write operations and elimination of sense amplifier circuit malfunctions. Therefore, it is necessary to read the stable memory cell current Icell with the sense amplifier circuit SA (which is an example of the "sense amplifier circuit" in the claims) shown in FIG. 4E.
• FIG. 3B shows the voltages applied to the word line WL, plate line PL, and bit line BL during the page write post-processing operation, for example, from the ground voltage Vss to the seventh voltage V7, the eighth voltage V8, and the ninth voltage V8.
• Each voltage is increased to V9.
• These seventh voltage V7, eighth voltage V8, and ninth voltage V9 are the fourth voltage V4, fifth voltage V5, and voltage V5 during the page read operation after the page write post-processing operation shown in FIG. 3A.
• the voltage is higher than the sixth voltage V6. Therefore, the surplus hole group can be efficiently eliminated.
• FIG. 3C shows that the voltages applied to the word line WL, plate line PL, and bit line BL during the page write post-processing operation are set to, for example, a fourth voltage V4, a fifth voltage V5, which is the same voltage as the page read operation.
• An example is shown in which the sixth voltage V6 is input and two pulse voltages are input. From time T4 to time T5, the number Holes of the hole groups 9 decreases from the number N2 to N4, and the memory cell current Icell decreases from I2 to I4. Then, from time T6 to time T7, the number Holes of the hole group 9 decreases from the number N4 to N3, and the memory cell current Icell decreases from I4 to I3. In this way, it is possible to prevent the surplus hole group from rapidly disappearing. In this example, a series of page write operations is performed from time T1 to time T7.
• FIG. 4A shows a memory block circuit diagram for explaining the page erase operation.
• a total of nine memory cells C00 to C22 in 3 rows and 3 columns are shown in a plan view, but the actual memory block is larger than this matrix.
• the "row direction” or “column shape”
• the direction perpendicular to this is called the “column direction” (or “column shape”).
• Source lines SL0 to SL2, bit lines BL0 to BL2, plate lines PL0 to PL2, and word lines WL0 to WL2 are connected to each memory cell.
• source lines SL0 to SL2, plate lines PL0 to PL2, and word lines WL0 to WL2 are arranged in parallel, and bit lines BL0 to BL2 are arranged in a direction perpendicular to them.
• memory cells C10 to C12 to which the plate line PL1, word line WL1, and source line SL1 of an arbitrary page P1 are connected are selected and a page erase operation is performed.
• FIG. 4B shows an operational waveform diagram of a page erase operation.
• a page erase operation starts and, for example, page P1 is selectively erased.
• the word line WL1 and the plate line PL1 rise from the ground voltage Vss to the first voltage V1 and the second voltage V2, respectively.
• the ground voltage Vss is, for example, 0V.
• the first voltage V1 and the second voltage V2 are each 1V, for example.
• the source line SL1 drops from the ground voltage Vss to the third voltage V3.
• the third voltage V3 is a negative voltage (an example of a "negative voltage” in the claims), and is, for example, -1V.
• the source line SL1 returns from the third voltage V3 to the ground voltage Vss at the third time T3, and the word line WL1 returns to the ground voltage Vss at the fourth time T4.
• plate line PL1 return to the ground voltage Vss from the first voltage V1 and the second voltage V2, respectively, and the page erase operation ends.
• one of the word line WL1 and the plate line PL1 may rise from the ground voltage Vss to the first voltage V1 or the second voltage V2 before or after the first time T1. Further, the source line SL1 may drop from the ground voltage Vss to the third voltage V3 before the first time T1. Further, one of the word line WL1 and the plate line PL1 may return to the ground voltage Vss from the first voltage V1 or the second voltage V2 before or after the fourth time T4. Further, the source line SL1 may return from the third voltage V3 to the ground voltage Vss after the fourth time T4.
• FIG. 4C(a) shows a state in which hole groups 9 generated by impact ionization are stored in the channel region 7 before the erase operation.
• the PN junction between the source N + layer 3a and the channel region 7 becomes a forward bias state as shown in FIG. 4C(b), and the hole group 9 in the channel region 7 is It is discharged to the N + layer 3a.
• the voltage V FB of the channel region 7 becomes the built-in voltage Vb of the PN junction formed by the source N + layer 3a and the P layer channel region 7.
• FIG. 4D shows a memory block circuit diagram in which at least two or more plate lines PL of adjacent pages are commonly arranged.
• the plate line PL of the three pages P0 to P2 is common.
• FIG. 4E shows a memory block diagram including main circuits.
• the word lines WL0 to WL2 and the plate lines PL0 to PL2 are connected to a row decoder circuit RDEC (which is an example of a "row decoder circuit” in the claims), and the row decoder circuit has a row address RAD (in the claims). is an example of a "row address"), and pages P0 to P2 are selected according to the row address RAD.
• the bit lines BL0 to BL2 are connected to a sense amplifier circuit SA, and the sense amplifier circuit SA is connected to a column decoder circuit CDEC (which is an example of a "column decoder circuit” in the claims).
• a column address CAD (which is an example of a "column address” in the claims) is input to the CDEC, and the sense amplifier circuit SA operates as an input/output circuit IO (an “input/output circuit” in the claims) according to the column address CAD. example).
• the dynamic flash memory operation described in this embodiment can be performed.
• circular, elliptical, and rectangular dynamic flash memory cells may be mixed on the same chip.
• a first gate insulating layer 4a and a second gate insulating layer 4b are provided that surround the entire side surface of the Si pillar 2 standing vertically on the substrate.
• the dynamic flash memory device has been described using as an example an SGT having a first gate conductor layer 5a and a second gate conductor layer 5b surrounding the entirety of the second gate insulating layer 4b.
• the present dynamic flash memory element may have any structure as long as it satisfies the condition that the hole group 9 generated by the impact ionization phenomenon is retained in the channel region 7.
• the channel region 7 may have a floating body structure separated from the substrate 1.
• the semiconductor matrix of the channel region is formed on the substrate 1.
• GAA Gate All Around: see non-patent document 13
• Nanosheet technology see, for example, non-patent document 14
• the semiconductor matrix of the channel region is formed on the substrate 1.
• the above-mentioned dynamic flash memory operation is possible even if the semiconductor matrix is formed horizontally to the substrate (so that the central axis of the semiconductor matrix is parallel to the substrate).
• a structure in which a plurality of GAA or Nanosheets formed in the horizontal direction are stacked may be used.
• SOI Silicon On Insulator
• the bottom of the channel region is in contact with the insulating layer of the SOI substrate, and the other channel region is surrounded by a gate insulating layer and an element isolation insulating layer.
• the channel region has a floating body structure.
• the dynamic flash memory device provided by this embodiment only needs to satisfy the condition that the channel region has a floating body structure. Further, even in a structure in which a Fin transistor (see, for example, Non-Patent Document 15) is formed on an SOI substrate, this dynamic flash operation can be performed if the channel region has a floating body structure.
• the reset voltages of the word line WL, bit line BL, and source line SL are described as Vss, but each may be set to a different voltage.
• FIGS. 4A to 4E and their explanations examples of page erase operation conditions are shown.
• the voltage applied to the word line WL may be changed.
• a voltage may be applied to the source line SL of the selected page, and the bit line BL may be placed in a floating state.
• a voltage may be applied to the bit line BL of the selected page, and the source line SL may be placed in a floating state.
• the potential distributions of the first channel region 7a and the second channel region 7b are connected in the vertical direction in a region surrounded by the insulating layer 6, which is an insulating layer.
• the vertical length of the first gate conductor layer 5a connected to the plate line PL is made longer than the vertical length of the second gate conductor layer 5b connected to the word line WL, It is desirable that C PL > C WL .
• simply adding the plate line PL reduces the capacitive coupling ratio (C WL /(C PL +C WL +C BL +C SL )) of the word line WL to the channel region 7. As a result, the potential fluctuation ⁇ V FB in the channel region 7 of the floating body becomes smaller.
• the first gate conductor layer 5a entirely surrounds the first gate insulating layer 4a.
• the first gate conductor layer 5a may have a structure in which it partially surrounds the first gate insulating layer 4a in plan view.
• This first gate conductor layer 5a may be divided into at least two gate conductor layers, each of which may be operated as a plate line PL electrode.
• the second gate conductor layer 5b may be divided into two or more parts, each of which may be operated synchronously or asynchronously as a word line conductor electrode. This allows dynamic flash memory operation.
• the first gate conductor layer 5a may be connected to the word line WL, and the second gate conductor layer 5b may be connected to the plate line PL. This also enables the dynamic flash memory operation described above.
• the dynamic flash memory cell according to the first embodiment of the present invention has a feature in the page write operation.
• hole groups 9 are reliably generated in the channel semiconductor layer 7 by the impact ionization phenomenon at the first time T1, although in excess, and then at the second time T2. , performs a page write post-processing operation to eliminate the surplus hole group.
• This enables stable page reading. That is, a stable memory cell current Icell can be obtained by the page write post-processing operation, and accurate data can be read by the sense amplifier circuit SA.
• Si pillars are formed in the present invention, semiconductor pillars made of a semiconductor material other than Si may also be used. This also applies to other embodiments of the present invention.
• Non-Patent Document 10 In addition, in writing "1", electron-hole pairs are generated by the impact ionization phenomenon using the gate induced drain leakage (GIDL) current described in Non-Patent Document 10.
• the inside of the floating body FB may be filled with a group of holes. This also applies to other embodiments of the present invention.
• a dynamic flash memory operation can also be performed in a structure in which the polarities of the conductivity types of the N + layers 3a, 3b and the P layer Si pillar 2 are reversed.
• the majority carriers are electrons. Therefore, a group of electrons generated by impact ionization is stored in the channel region 7, and a "1" state is set.
• a memory block may be formed by arranging the Si columns of memory cells two-dimensionally, in a square lattice shape, or in an orthorhombic lattice shape.
• the Si pillars connected to one word line may be arranged in a zigzag shape or a sawtooth shape, with a plurality of Si pillars on one side. This also applies to other embodiments.
• a dynamic flash memory which is a memory device using a high-density and high-performance SGT, can be obtained.
• Dynamic flash memory cell 2 Si pillars 3a, 3b having conductivity type of P type or i type (intrinsic type): N + layer 7: Channel regions 4a, 4b: Gate insulating layers 5a, 5b: Gate conductor layer 6 : Insulating layer 9 for separating two gate conductor layers: Hole BL: Bit line SL: Source line PL: Plate line WL: Word line FB: Floating body T1 to T9: Time V1 to V9: First voltage to ninth voltage N1: Number of holes in neutral state N2 to N4: Number of holes I0 to I4: Memory cell current C00 to C22: Memory cells SL0 to SL2, SL01, SL23: Source lines BL0 to BL2: Bit lines PL0 to PL2: Plate lines WL0 to WL2: Word lines RDEC: Row address circuit RAD: Row address SA: Sense amplifier circuit CDEC: Column decoder circuit CAD: Column address IO: Input/output circuit 111: DRAM

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Databases & Information Systems (AREA)
• Semiconductor Memories (AREA)

Priority Applications (3)

Applications Claiming Priority (1)

Publications (1)

Family

ID=89076656

Family Applications (1)

Country Status (3)

Families Citing this family (1)

Citations (1)

Family Cites Families (20)

• 2022
  • 2022-06-14 WO PCT/JP2022/023825 patent/WO2023242956A1/ja not_active Ceased
  • 2022-06-14 JP JP2024527957A patent/JPWO2023242956A1/ja not_active Ceased
• 2023
  • 2023-06-13 US US18/333,674 patent/US12362006B2/en active Active

Patent Citations (1)

Also Published As

Similar Documents

Legal Events