WO2023157888A1 - 露光方法、デバイス製造方法、露光装置、及び露光システム - Google Patents

露光方法、デバイス製造方法、露光装置、及び露光システム Download PDF

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Publication number
WO2023157888A1
WO2023157888A1 PCT/JP2023/005314 JP2023005314W WO2023157888A1 WO 2023157888 A1 WO2023157888 A1 WO 2023157888A1 JP 2023005314 W JP2023005314 W JP 2023005314W WO 2023157888 A1 WO2023157888 A1 WO 2023157888A1
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WIPO (PCT)
Prior art keywords
exposure
pattern
region
light modulator
spatial light
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PCT/JP2023/005314
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English (en)
French (fr)
Japanese (ja)
Inventor
渡邉陽司
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Nikon Corp
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Nikon Corp
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Application filed by Nikon Corp filed Critical Nikon Corp
Priority to CN202380019504.5A priority Critical patent/CN118871862A/zh
Priority to KR1020247027066A priority patent/KR20240135813A/ko
Priority to JP2024501412A priority patent/JPWO2023157888A1/ja
Priority to EP23756413.3A priority patent/EP4481498A4/en
Publication of WO2023157888A1 publication Critical patent/WO2023157888A1/ja
Priority to US18/780,663 priority patent/US20240377754A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70475—Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B26/00—Optical devices or arrangements for the control of light using movable or deformable optical elements
    • G02B26/08—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
    • G02B26/0816—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light by means of one or more reflecting elements
    • G02B26/0833—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light by means of one or more reflecting elements the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70216—Mask projection systems
    • G03F7/70275—Multiple projection paths, e.g. array of projection systems, microlens projection systems or tandem projection systems
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70216—Mask projection systems
    • G03F7/70283—Mask effects on the imaging process
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70216—Mask projection systems
    • G03F7/70283—Mask effects on the imaging process
    • G03F7/70291—Addressable masks, e.g. spatial light modulators [SLMs], digital micro-mirror devices [DMDs] or liquid crystal display [LCD] patterning devices
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/708—Construction of apparatus, e.g. environment aspects, hygiene aspects or materials
    • G03F7/7085—Detection arrangement, e.g. detectors of apparatus alignment possibly mounted on wafers, exposure dose, photo-cleaning flux, stray light, thermal load
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps

Definitions

  • It relates to exposure methods, device manufacturing methods, exposure apparatuses, and exposure systems.
  • the interposer is a chip with only wiring built in, and is manufactured using the semiconductor manufacturing process.
  • the photomask used for exposure in the semiconductor manufacturing process has a fixed exposure size, in order to manufacture a large-area interposer, stitching exposure is used to expose a large pattern by joining multiple patterns on a substrate. technology is used (for example, Patent Document 1).
  • an exposure apparatus using a mask is used to form a first exposure pattern in a first region of each of a plurality of pattern formation regions on a substrate with exposure light through a first mask, forming a second exposure pattern with exposure light through a second mask in a second area spaced apart from the first area in each of the pattern formation areas; and modulating the exposure light based on an output from an exposure pattern determination unit.
  • forming a first exposure pattern in a first region within a pattern formation region on a substrate Forming two exposure patterns, and forming an exposure pattern in a third region between the first region and the second region based on measurement results of the position of the first exposure pattern and the position of the second exposure pattern
  • a method of exposure comprising: forming a
  • the surface of the substrate is processed using the first and second exposure patterns formed using the exposure method as masks, and the third region is processed using the exposure method. and processing the surface of the substrate using the exposure pattern formed in the step as a mask.
  • a first exposure pattern is formed in a first area within a pattern formation area, and a second exposure pattern is formed in a second area spaced apart from the first area within the pattern formation area.
  • an exposure pattern determination unit for determining an exposure pattern based on measurement results of the position of the first exposure pattern and the position of the second exposure pattern; and a signal from the exposure pattern determination unit.
  • a spatial light modulator that modulates and emits incident light based on an output; an illumination optical system that irradiates the spatial light modulator with illumination light; and a projection optical system for projecting an image of the light modulating surface of the modulator.
  • a substrate stage on which a substrate having wiring patterns formed in a plurality of areas spaced apart from each other is placed, and an exposure pattern determining apparatus that determines an exposure pattern based on a measurement result of the positions of the wiring patterns.
  • a spatial light modulator that modulates and emits incident light based on the output from the exposure pattern determination unit; an illumination optical system that irradiates the spatial light modulator with illumination light; and the plurality of regions. and a projection optical system for projecting an image of the light modulating surface of the spatial light modulator between adjacent regions of the spatial light modulator.
  • a first exposure device for forming exposure patterns in a plurality of regions separated from each other in a pattern formation region on a substrate with exposure light through each of a plurality of masks; a spatial light modulator that modulates exposure light based on the output from the determination unit, and forms an exposure pattern between adjacent regions of the plurality of regions with the exposure light that has passed through the spatial light modulator; 2.
  • An exposure system is provided comprising: a.
  • FIG. 1 is a block diagram showing the configuration of an exposure system according to an embodiment.
  • FIG. 2 is a diagram showing a schematic configuration of the first exposure device.
  • FIG. 3 is a diagram showing a schematic configuration of the exposure apparatus main body of the second exposure apparatus.
  • FIG. 4 is a diagram showing an example of a spatial light modulator
  • FIG. 5 is a functional block diagram of the pattern determining section of the second exposure apparatus.
  • FIG. 6 is a flowchart (part 1) showing an example of an interposer manufacturing method.
  • FIG. 7 is a flowchart (part 2) showing an example of an interposer manufacturing method.
  • FIG. 8A is a diagram showing an example of an interposer having a line and space (L/S) pattern, FIG.
  • FIG. 8B is a cross-sectional diagram of a wafer
  • FIG. 2 is a diagram showing a plurality of pattern formation regions of FIG.
  • FIG. 9A is a diagram for explaining the first region in the wafer
  • FIG. 9B is a diagram showing an example of the first pattern
  • FIG. 9C is a pattern forming region. It is a figure which shows the state in which the 1st exposure pattern was formed in.
  • FIG. 10A is a diagram for explaining the second region in the wafer
  • FIG. 10B is a diagram showing an example of the second pattern
  • FIG. 10C is a pattern forming region. It is a figure which shows the state in which the 2nd exposure pattern was formed in.
  • FIG. 11A is a diagram for explaining the third region in the wafer
  • FIG. 11A is a diagram for explaining the third region in the wafer
  • FIG. 11B is a diagram showing an example of the third pattern, and FIG. It is a figure which shows the state in which the 3rd exposure pattern was formed in.
  • FIG. 12A is a diagram for explaining the fourth area in the wafer
  • FIG. 12B is a diagram showing an example of the fourth pattern
  • FIG. It is a figure which shows the state in which the 4th exposure pattern was formed in inside.
  • FIG. 13 is a diagram showing an example of a patterned insulating layer.
  • FIG. 14A is a diagram for explaining the first connection region and the second connection region, and FIG. 14B is a diagram showing an example of misalignment of wiring patterns.
  • 15A is a diagram showing an example of a connection pattern
  • FIG. 15B is a diagram showing an example of a design value pattern
  • FIG. 15C is a diagram showing another example of a connection pattern.
  • FIG. 16A is a diagram for explaining the exposure of the first connection region by the second exposure device
  • FIG. 16B is a diagram for explaining the exposure of the second connection region by the second exposure device.
  • It is a diagram for FIG. 17 is a diagram showing an L/S pattern of an interposer formed on a wafer.
  • FIG. 18 is a diagram illustrating the case where the second layer is overlaid on the first layer and exposed.
  • FIG. 19A is a diagram showing an example of a reticle
  • FIG. 19B is a diagram showing an example of an exposure pattern formed by rotating the reticle
  • FIG. FIG. 4 is a diagram showing an example;
  • FIG. 1 The exposure system according to this embodiment will be described below with reference to FIGS. 1 to 17.
  • FIG. 1 The exposure system according to this embodiment will be described below with reference to FIGS. 1 to 17.
  • FIG. 1 is a block diagram showing the configuration of the exposure system ES according to this embodiment.
  • the exposure system ES includes a first exposure device 100, a second exposure device 200, and a control device 400. As shown in FIG. 1, the exposure system ES includes a first exposure device 100, a second exposure device 200, and a control device 400. As shown in FIG. 1, the exposure system ES includes a first exposure device 100, a second exposure device 200, and a control device 400. As shown in FIG.
  • the controller 400 controls overall operations of the exposure system ES.
  • the first exposure apparatus 100 is an exposure apparatus that uses a reticle (photomask). The first exposure device 100 exposes the pattern formed on the reticle onto the photosensitive layer of the wafer W0.
  • FIG. 2 is a diagram showing a schematic configuration of the first exposure apparatus 100.
  • the first exposure apparatus 100 includes an illumination system 110, a reticle stage device 120, a projection optical system 130, a wafer stage device 140, an alignment detection system 150, and a first exposure controller 160.
  • the two directions perpendicular to each other in the horizontal plane are the X1 direction and the Y1 direction, and the vertical direction is the Z1 direction.
  • the rotation (tilt) directions about the X1-axis, Y1-axis, and Z1-axis are defined as the ⁇ x1 direction, the ⁇ y1 direction, and the ⁇ z1 direction, respectively.
  • the illumination system 110 includes a light source and an illumination optical system (both not shown) connected to the light source via a light transmission optical system.
  • the light source is, for example, an ArF excimer laser light source (wavelength 193 nm).
  • the illumination optical system irradiates the illumination area IAR on the reticle R held by the reticle stage 121 of the reticle stage device 120 with the illumination light from the light source with a substantially uniform illuminance.
  • the illumination area IAR is a slit-like area elongated in the X1 direction.
  • the reticle stage device 120 includes a reticle stage 121 and a reticle laser interferometer 122.
  • the reticle stage 121 holds the reticle R via a holder provided on the reticle stage 121 .
  • the reticle stage 121 can be finely driven in the X1 and Z1 directions and can be driven within a predetermined stroke range in the scanning direction (Y1 direction) by a reticle stage driving system (not shown).
  • the reticle laser interferometer 122 irradiates the movable mirrors provided on the X1-direction and Y1-direction end faces of the reticle stage 121 (only the movable mirror MR1 provided on the Y1-direction end face is shown in FIG. 2) with a length-measuring beam.
  • the positions of the reticle stage 121 in the X1 direction, the Y1 direction, and the ⁇ z1 direction are always detected with a resolution of about 0.25 nm, for example.
  • the projection optical system 130 projects the pattern formed on the reticle R onto the wafer W0 placed on the wafer stage 141 (described later) at a predetermined projection magnification (for example, 1 ⁇ 4, 1 ⁇ 5, 1 ⁇ 8 times). etc.).
  • the projection optical system has a lens barrel 130s and a plurality of optical elements (not shown) arranged in a predetermined positional relationship inside the lens barrel 130s.
  • the wafer stage device 140 includes a wafer stage 141 and a laser interferometer 142.
  • Wafer stage 141 holds wafer W0 via a wafer holder (not shown) provided in the center of the upper surface.
  • the wafer stage 141 is driven by a stage driving system 143 in the X1 direction and the Y1 direction with a predetermined stroke, and is finely driven in the Z1 direction, the ⁇ x1 direction, the ⁇ y1 direction, and the ⁇ z1 direction.
  • the laser interferometer 142 irradiates the movable mirrors (only the movable mirror MR2 provided on the end face in the Y1 direction is shown in FIG. 2) respectively provided on the end faces in the X1 direction and the Y1 direction of the wafer stage 141 with the length measuring beam.
  • the positional information of the wafer stage 141 in the X1 direction, Y1 direction, ⁇ z1 direction, ⁇ x1 direction, and ⁇ y1 direction is always detected with a resolution of, for example, about 0.25 nm.
  • the alignment detection system 150 is provided on the side surface of the lens barrel 130 s of the projection optical system 130 .
  • the alignment detection system 150 detects alignment marks and the like formed on the wafer.
  • an FIA (Field Image Alignment) system which is a type of image processing type imaging alignment sensor, can be used.
  • a diffracted light interference type alignment system may be used.
  • the first exposure control unit 160 comprehensively controls the illumination system 110, the reticle stage device 120, the projection optical system 130, and the wafer stage device 140, and displays the image of the pattern formed on the reticle R held by the reticle stage device 120. , through the projection optical system 130 , onto the wafer W 0 held on the wafer stage 141 .
  • the first exposure control unit 160 of this embodiment controls each unit to perform exposure by the step-and-scan method.
  • the exposure apparatus disclosed in US Pat. No. 10684562 may be used as the first exposure apparatus 100 having the above configuration.
  • the second exposure apparatus 200 is an exposure apparatus that uses a spatial light modulator (SLM) that modulates exposure light according to control by a second exposure control section 260, which will be described later.
  • the second exposure apparatus 200 includes an exposure apparatus main body section 200A and a pattern determination section 200B.
  • FIG. 3 is a diagram showing a schematic configuration of the exposure apparatus main body 200A.
  • the exposure apparatus main body section 200A includes an illumination system 210, a pattern generation device 220, a projection optical system 230, a stage device 240, an alignment detection system 250, and a second exposure control section 260.
  • the two directions perpendicular to each other in the horizontal plane are the X2 direction and the Y2 direction, and the vertical direction is the Z2 direction.
  • the rotation (inclination) directions about the X2-axis, the Y2-axis, and the Z2-axis are defined as the ⁇ x2 direction, the ⁇ y2 direction, and the ⁇ z2 direction, respectively.
  • the illumination system 210 includes a light source unit (not shown), an illumination optical system 211, and a reflecting mirror 212.
  • the light source system includes, for example, a solid-state laser light source (DFB semiconductor laser, fiber laser, etc.).
  • the illumination optical system 211 includes a shaping optical system for changing illumination conditions, an optical integrator, a field stop, and a relay lens system (all not shown).
  • the pattern generation device 220 generates a pattern to be projected onto the photosensitive layer of the wafer W0 placed on the stage 241 (described later) of the stage device 240 under the control of the second exposure control unit 260 .
  • the pattern generation device 220 includes a spatial light modulator 221 and a driver 222 .
  • FIG. 4 is a diagram showing an example of the spatial light modulator 221.
  • the spatial light modulator 221 has a plurality of micromirror mechanisms M arranged in a matrix (two-dimensional, array) within the X2-Y2 plane.
  • Each of the micromirror mechanisms M has a micromirror M1 and a driving mechanism M2 provided on the side opposite to the reflecting surface of the micromirror M1.
  • the driving mechanism M2 moves, that is, moves up and down the micromirror M1 along an axis extending in the Z2 direction.
  • the drive unit 222 drives the drive mechanism M2 of each of the plurality of micromirror mechanisms M according to the control signal from the second exposure control unit 260, and turns the micromirror M1 between an on state (on position) and an off state (off position). switch between
  • the micromirror M1 is located within a region of a size that can be resolved by the projection optical system 230.
  • the 0th-order diffracted light IL0 of the illumination light IL from the illumination system 210 entering the region enters the projection optical system 230 .
  • a 2 ⁇ 2 micromirror M1 may be positioned within a region of a size that can be resolved by the projection optical system 230 .
  • the pattern generation device 220 gives a pattern to the illumination light IL by setting each of the plurality of micromirrors M1 to either an ON state or an OFF state.
  • the surface on which the plurality of micromirrors M1 set to either the ON state or the OFF state are arranged may be referred to as the light modulation surface of the spatial light modulator 221.
  • the spatial light modulator 221 is not limited to the piston type described above, and may be, for example, a magneto-optical spatial light modulator (MOSLM) or a DMD (digital mirror device). Further, although the spatial light modulator 221 has been described as a reflection type that reflects the illumination light IL, the spatial light modulator 221 may be a transmission type that transmits the illumination light IL, or a diffraction type that diffracts the illumination light IL. But it's okay. The spatial light modulator 221 may spatially and temporally modulate the illumination light IL.
  • MOSLM magneto-optical spatial light modulator
  • DMD digital mirror device
  • the projection optical system has a lens barrel 230s and a plurality of optical elements (not shown) arranged in a predetermined positional relationship inside the lens barrel 230s.
  • the stage device 240 includes a stage (substrate stage) 241 , a laser interferometer 242 and a stage driving section 243 .
  • the stage 241 holds the wafer W0 via a wafer holder (not shown) provided in the center of the upper surface.
  • the stage 241 can be moved in the X2 direction, the Y2 direction, and the Z2 direction by the stage drive unit 243, and can rotate around the axis extending in the Z2 direction.
  • the laser interferometer 242 irradiates the reflecting surfaces provided on the X2-direction and Y2-direction end faces of the stage 241 with measurement beams, thereby changing the positions of the stage 241 in the X2-direction, Y2-direction, and ⁇ z2-direction to, for example, 0.00. Detection is always performed with a resolution of about 5 to 1 nm.
  • the stage drive section 243 drives the stage 241 in accordance with the control signal from the second exposure control section 260 .
  • the alignment detection system 250 is arranged on the side of the projection optical system 230 .
  • an imaging alignment sensor is used as the alignment detection system 250 .
  • a detailed configuration of the alignment detection system 250 is disclosed, for example, in US Pat. No. 5,637,129.
  • the alignment detection system 250 detects street lines and position detection marks formed on the wafer W0. The results of detection of street lines and position detection marks by the alignment detection system 250 are output to the second exposure control section 260 .
  • the alignment detection system 250 also detects alignment marks included in the wiring pattern formed on the wafer W0.
  • the wiring pattern is formed based on the exposure pattern formed on wafer W ⁇ b>0 by first exposure apparatus 100 . Therefore, it can be said that the alignment detection system 250 detects alignment marks included in the exposure pattern formed on the wafer W0 by the first exposure apparatus 100 .
  • the detection result of the alignment mark by the alignment detection system 250 is output to the pattern determining section 200B.
  • the pattern determination unit 200B determines the pattern to be exposed on the photosensitive layer of the wafer W0 based on the detection result of the alignment marks on the wafer W0 (position of the wiring pattern (exposure pattern)) by the alignment detection system 250.
  • the pattern determination section 200B outputs the determined exposure pattern to the second exposure control section 260.
  • FIG. 5 is a functional block diagram of the pattern determining section 200B.
  • the pattern determining unit 200B is, for example, a personal computer (PC), and includes a storage unit 310, a determining unit 320, and a receiving unit 330.
  • PC personal computer
  • the storage unit 310 stores various data used for determining the pattern to be exposed on the photosensitive layer of the wafer W0.
  • Determination unit 320 determines a pattern to be exposed on the photosensitive layer of wafer W0 based on the data stored in storage unit 310 and the detection result of the alignment marks on wafer W0 by alignment detection system 250 .
  • the receiving section 330 receives the output from the alignment detection system 250 of the second exposure apparatus 200 and sends it to the determining section 320 .
  • the pattern determination unit 200B may be separate from the second exposure apparatus 200 instead of being a part of the second exposure apparatus 200 . That is, the second exposure apparatus 200 does not have to include the pattern determining section 200B.
  • the alignment mark detection result by the alignment detection system 250 is transmitted to a server outside the second exposure apparatus 200, the server determines the pattern, and the determined pattern is sent to the second exposure apparatus 200 (specifically, the second exposure apparatus 200). 2) may be transmitted to the exposure control unit 260).
  • the second exposure control unit 260 controls the operations of the illumination system 210, the pattern generation device 220, the stage device 240, etc. so that the exposure pattern determined by the pattern determination unit 200B is formed on the wafer W0. , the image of the light modulating surface of the spatial light modulator 221 is projected onto the wafer W0 held by the stage 241 via the projection optical system 230.
  • Light IL enters projection optical system 230 and a reduced image (partially inverted image) of the pattern is formed in projection area IA on wafer W 0 held by stage 241 .
  • the second exposure control unit 260 performs exposure using a step-and-scan method.
  • the second exposure control unit 260 moves the stage 241 at an appropriate speed during scan exposure, and in synchronization with this, scrolls the pattern generated by the spatial light modulator 221 (that is, the spatial light modulator change the shape of the pattern generated by H.221).
  • the exposure apparatus disclosed in US Patent No. 8089616, US Patent Publication No. 2020/00257205, or International Publication No. 2005/081034 may be used.
  • Interposer manufacturing method An interposer manufacturing method for manufacturing an interposer using the exposure system ES described above will be described with reference to the flow charts of FIGS. 6 and 7.
  • FIG. 8A a case of manufacturing an interposer IP having a line and space (L/S) pattern LS shown in FIG. 8A will be described below.
  • the area of the interposer IP is larger than the area of the projection area onto which the image of the pattern formed on the reticle R of the first exposure apparatus 100 is projected.
  • wafer W1 a wafer to be exposed (hereinafter referred to as wafer W1) is prepared (step ST1).
  • FIG. 8B is a cross-sectional view of wafer W1
  • FIG. 8C is a plan view of wafer W1.
  • an insulating layer 12 and a photosensitive layer 13 are laminated in this order from the bottom on the surface of the wafer W1.
  • Wafer W1 is made of, for example, silicon, glass, or an organic material.
  • the insulating layer 12 is, for example, an insulating layer such as SiO 2 .
  • the photosensitive layer 13 is, for example, photoresist.
  • a plurality of pattern formation regions PTR are defined on the wafer W1.
  • an interposer IP having an L/S pattern LS can be formed.
  • the lateral direction of pattern formation region PTR is the X direction
  • the longitudinal direction of pattern formation region PTR is the Y direction
  • the normal direction of wafer W1 is the Z direction.
  • the rotation (tilt) directions about the X-axis, Y-axis, and Z-axis are defined as the ⁇ x direction, the ⁇ y direction, and the ⁇ z direction, respectively.
  • the wafer W1 is loaded into the first exposure apparatus 100 (step ST2).
  • Wafer W ⁇ b>1 loaded into first exposure apparatus 100 is placed on wafer stage 141 .
  • wafer W1 is mounted on wafer stage 141 so that the X-axis of wafer W1 and the X1-axis of first exposure apparatus 100 are aligned.
  • first exposure apparatus 100 forms first exposure pattern EPT1 in first region ER1 of each of a plurality of pattern formation regions PTR on wafer W1 with exposure light through first reticle R1 (step ST3). ).
  • FIG. 9(A) is a diagram for explaining the first region ER1.
  • the first region ER1 is, for example, the lower left region within the pattern formation region PTR corresponding to the interposer IP.
  • FIG. 9B is a diagram showing an example of the first pattern PT1 formed on the first reticle R1.
  • the first pattern PT1 includes a first L/S pattern LS1 and alignment marks AM1.
  • the first pattern PT1 may include patterns such as pads.
  • the first exposure apparatus 100 drives the wafer stage 141 to sequentially expose a plurality of first regions ER1 to the image of the first pattern PT1 formed on the first reticle R1. As a result, as shown in FIG. 9C, the first exposure pattern EPT1 is formed in the lower left region (first region ER1) of the pattern formation region PTR.
  • the first exposure apparatus 100 places the second reticle R2 on the second area ER2 separated from the first area ER1 in each of the plurality of pattern formation areas PTR.
  • a second exposure pattern EPT2 is formed by exposure light through (step ST5).
  • FIG. 10(A) is a diagram for explaining the second area ER2.
  • the second region ER2 is, for example, the lower right region within the pattern formation region PTR corresponding to the interposer IP.
  • the first region ER1 and the second region ER2 are adjacent in the X direction.
  • "adjacent" means separated from each other and next to each other. The same applies to the following description.
  • FIG. 10B is a diagram showing an example of the second pattern PT2 formed on the second reticle R2.
  • the second pattern PT2 includes a second L/S pattern LS2 and alignment marks AM2.
  • the second pattern PT2 may include patterns such as pads.
  • the first exposure apparatus 100 includes a reticle changer capable of exchanging a plurality of reticles, and when the formation of the first exposure pattern EPT1 is completed, the reticle changer changes the first reticle R1 to the second exposure pattern. It is assumed that the reticle R2 is replaced with the reticle R2. After the formation of the first exposure pattern EPT1 is completed, the wafer W1 is unloaded from the first exposure apparatus 100, and a second exposure pattern is formed using another first exposure apparatus 100 in which the second reticle R2 is set. EPT2 may be formed in the second region ER2. That is, a plurality of first exposure apparatuses 100 may be provided. Also, a plurality of reticles may be mounted on the reticle stage 121 .
  • the first exposure apparatus 100 drives the wafer stage 141 to sequentially expose a plurality of second areas ER2 in the wafer W1 to images of the second pattern PT2 formed on the second reticle R2.
  • the second exposure pattern EPT2 is formed in the lower right region (second region ER2) of the pattern formation region PTR.
  • the first exposure apparatus 100 exposes the third regions in each of the plurality of pattern formation regions PTR on the wafer W1 with the exposure light through the third reticle R3.
  • a third exposure pattern EPT3 is formed in ER3 (step ST7).
  • FIG. 11(A) is a diagram for explaining the third area ER3.
  • the third region ER3 is, for example, the upper left region within the pattern formation region PTR corresponding to the interposer IP, as shown in FIG. 11(A).
  • the third region ER3 is a region that is different from the first region ER1 and the second region ER2 and that is adjacent to the first region ER1 in the Y direction intersecting the X direction.
  • FIG. 11(B) is a diagram showing an example of the third pattern PT3 formed on the third reticle R3.
  • the third pattern PT3 includes a third L/S pattern LS3 and alignment marks AM3.
  • the third pattern PT3 may include patterns such as pads.
  • the first exposure apparatus 100 drives the wafer stage 141 to place the third reticle R3 in the plurality of third areas ER3 within the wafer W1.
  • the images of the third pattern PT3 formed on R3 are sequentially exposed.
  • the third exposure pattern EPT3 is formed in the upper left region (third region ER3) of the pattern formation region PTR.
  • the first exposure apparatus 100 exposes the fourth area ER4 in each of the plurality of pattern formation areas PTR on the wafer W1 through the fourth reticle R4.
  • a fourth exposure pattern EPT4 is formed with light (step ST8).
  • FIG. 12(A) is a diagram for explaining the fourth area ER4.
  • the fourth region ER4 is, for example, the upper right region within the pattern formation region PTR corresponding to the interposer IP.
  • the fourth region ER4 is a region adjacent to the third region ER3 in the X direction and adjacent to the second region ER2 in the Y direction.
  • FIG. 12(B) is a diagram showing an example of the fourth pattern PT4 formed on the fourth reticle R4.
  • the fourth pattern PT4 includes a fourth L/S pattern LS4 and an alignment mark AM4.
  • the fourth pattern PT4 may include patterns such as pads.
  • the first exposure apparatus 100 drives the wafer stage 141 to change the image of the fourth pattern PT4 formed on the fourth reticle R4. , a plurality of fourth regions ER4 are sequentially exposed. As a result, as shown in FIG. 12C, the fourth exposure pattern EPT4 is formed in the upper right region (fourth region ER4) of the pattern formation region PTR.
  • the wafer W1 is unloaded from the first exposure apparatus 100 and developed and etched (step ST9). Specifically, the insulating layer 12 formed on the surface of the substrate 11 (the surface of the wafer W1) is etched using the first exposure pattern EPT1 to the fourth exposure pattern EPT4 as masks. Thereby, the insulating layer 12 is patterned as shown in FIG. More specifically, wiring patterns WP1 to WP4 for embedding metal in the patterned insulating layer 12 are formed in a process described later. In FIG. 13, the etched insulating layer 12 is indicated by hatching.
  • the width of the wiring included in the wiring patterns WP1 to WP4 is, for example, 200 nm or less.
  • the width of the wiring included in the wiring patterns WP1 to WP4 may be, for example, 400 nm or less.
  • the wafer W1 is again coated with a resist (step ST10).
  • wafer W1 is loaded into exposure apparatus main body 200A of second exposure apparatus 200 (step ST11).
  • wafer W1 is placed on stage 241 after being pre-aligned by a pre-alignment system (not shown).
  • wafer W1 is mounted on stage 241 so that the X-axis of wafer W1 and the X2-axis of second exposure apparatus 200 are aligned.
  • the configuration of the pre-alignment system the configuration described in US Pat. No. 6,624,433 can be adopted.
  • the alignment detection system 250 measures the positions of the alignment marks AM1 to AM4 by detecting the alignment marks AM1 to AM4 formed on the wafer W1 (step ST13).
  • the measurement results of the positions of the alignment marks AM1 to AM4 are output to the pattern determining section 200B.
  • the pattern determination section 200B determines exposure patterns to be formed in the first connection region CR1 and the second connection region CR2 based on the measurement results of the positions of the alignment marks AM1 to AM4 (step ST15). ). More specifically, the exposure pattern formed in the first connection region CR1 and the second connection region CR2 is based on the positions of the wiring patterns WP1 to WP4 obtained from the measurement results of the positions of the alignment marks AM1 to AM4. (hereinafter referred to as a connection pattern) are determined respectively.
  • FIG. 14(A) is a diagram explaining the first connection region CR1 and the second connection region CR2.
  • the first connection region CR1 is a region including a region between the first region ER1 and the second region ER2 and a region between the third region ER3 and the fourth region ER4. be.
  • the second connection region CR2 is a region including a region between the first region ER1 and the third region ER3 and a region between the second region ER2 and the fourth region ER4.
  • the first exposure apparatus 100 when forming the first exposure pattern EPT1 to the fourth exposure pattern EPT4 in the first region ER1 to the fourth region ER4, respectively, the first exposure pattern EPT1 to the fourth exposure pattern EPT4 are formed.
  • the position may deviate from the design position.
  • the wiring patterns WP1 to WP4 are also formed shifted from the designed positions.
  • FIG. 14(B) shows an example of misalignment of the wiring patterns WP1 and WP2.
  • the designed positions of the wiring patterns WP1 and WP2 are indicated by dotted lines, and the actual positions of the wiring patterns WP1 and WP2 are indicated by solid lines.
  • the wiring pattern WP1 is shifted in the -X direction and the -Y direction with respect to the design position
  • the wiring pattern WP2 is shifted in the -X direction and the +Y direction with respect to the design position.
  • the determination unit 320 of the pattern determination unit 200B determines the deviation amounts ⁇ X, Y in the X direction from the design positions of the wiring pattern WP1 and the wiring pattern WP2.
  • a direction deviation amount ⁇ Y and a rotational direction deviation amount ⁇ z about an axis extending in the Z direction are calculated.
  • the determination unit 320 determines a connection pattern that connects the wiring pattern WP1 and the wiring pattern WP2.
  • the connection pattern is a pattern that connects to the wiring pattern WP1 and also connects to the wiring pattern WP2.
  • connection pattern that connects the wiring pattern WP1 and the wiring pattern WP2 is created based on the wiring patterns WP1 and WP2 formed at the design positions. Therefore, for example, when the actual positions of the wiring patterns WP1 and WP2 are shifted from the design positions as shown in FIG. If the connection patterns are formed as they are, there is a risk that a connection failure such as disconnection may occur between the wiring patterns WP1 and WP2.
  • the determination unit 320 calculates the positions of the ends of the wirings included in the wiring patterns WP1 and WP2 from the amounts of deviation from the design positions of the wiring patterns WP1 and WP2. Based on the calculated positions of the wiring ends, the determination unit 320 determines a connection pattern CPT that connects the ends of the wirings included in the wiring pattern WP1 and the wiring pattern WP2, as shown in FIG. 15A, for example. to decide. The same applies to the connection pattern between the wiring pattern WP3 and the wiring pattern WP4, the connection pattern between the wiring pattern WP1 and the wiring pattern WP3, and the connection pattern between the wiring pattern WP2 and the wiring pattern WP4.
  • connection pattern for connecting the ends of the wiring is created by changing the connection pattern based on the design position stored in the storage unit 310 based on the amount of deviation of each of the wiring patterns WP1 to WP4 from the design position.
  • connection pattern CPT-D (design value pattern) based on the wiring patterns WP1 and WP2 formed at the design positions is the pattern shown in FIG. 15(B).
  • the determination unit 320 uses part of the design value pattern CPT-D' for the central portion of the area between the wiring pattern WP1 and the wiring pattern WP2.
  • the connection pattern CPT may be determined by creating connection patterns CPT-1 and CPT-2 that connect the wiring patterns formed in the central portion and the wiring patterns WP1 and WP2. .
  • the design value pattern is used for a predetermined region, and the connection pattern for connecting the design value pattern and the actual wiring pattern is created for the other regions. You may do so. By doing so, it is possible to shorten the time required to create the data as compared with the case where the connection pattern data is created from the beginning.
  • the pattern determination unit 200B determines the first connection pattern formed in the first connection region CR1 and the second connection pattern formed in the second connection region CR2.
  • the first connection pattern includes a connection pattern that connects the wiring pattern WP1 and the wiring pattern WP2, and a connection pattern that connects the wiring pattern WP3 and the wiring pattern WP4.
  • the second connection pattern includes a connection pattern that connects the wiring pattern WP1 and the wiring pattern WP3, and a connection pattern that connects the wiring pattern WP2 and the wiring pattern WP4.
  • the first connection pattern and the second connection pattern are formed using the second exposure apparatus 200 that uses the spatial light modulator 221, so the first connection pattern and the second connection pattern are made different. be able to.
  • the connection pattern connecting the wiring pattern WP1 and the wiring pattern WP2 can be made different from the connection pattern connecting the wiring pattern WP3 and the wiring pattern WP4.
  • the connection pattern connecting the wiring pattern WP1 and the wiring pattern WP3 can be made different from the connection pattern connecting the wiring pattern WP2 and the wiring pattern WP4.
  • the pattern determination unit 200B creates data for forming the first connection pattern and data for forming the second connection pattern, and outputs the data to the second exposure control unit 260.
  • the second exposure control section 260 causes the pattern generation device 220 to generate a pattern based on the data output from the pattern determination section 200B.
  • the second exposure control section 260 first causes the pattern generation device 220 (spatial light modulator 221) to generate a pattern for forming the first connection pattern.
  • the exposure apparatus main body section 200A forms the first connection pattern in the first connection region CR1 with exposure light through the spatial light modulator 221 (step ST17). Specifically, the image generated by the light modulating surface of the spatial light modulator 221 is sequentially exposed to the first connection region CR1 based on the data created by the pattern determination unit 200B, thereby changing the first connection pattern to the first It is formed in the connection region CR1 (see FIG. 16A).
  • step ST17 ends, the orientation of wafer W1 is changed around the axis (Z-axis) that intersects the surface of wafer W1 (step ST19). Specifically, the orientation of wafer W1 is changed by 90 degrees around the Z-axis. By returning wafer W1 from stage 241 to the pre-alignment system and rotating wafer W1 about the Z-axis by 90 degrees, the orientation of wafer W1 can be changed as shown in FIG. 16B. can. As a result, the Y-axis of wafer W1 and the X1-axis of second exposure apparatus 200 are aligned.
  • the second exposure control section 260 causes the pattern generation device 220 to generate a pattern for forming the second connection pattern.
  • the exposure apparatus main body 200A forms the second connection pattern in the second connection region CR2 with exposure light through the spatial light modulator 221 (step ST21). Specifically, the image generated by the light modulating surface of the spatial light modulator 221 is sequentially exposed to the second connection region CR2 based on the data created by the pattern determination unit 200B, thereby changing the second connection pattern to the second It is formed in the connection region CR2 (see FIG. 16B).
  • step ST23 development and etching are performed (step ST23). More specifically, the insulating layer 12 is etched using the first connection pattern and the second connection pattern as masks.
  • the insulating layer 12 etched in step ST23 is the same insulating layer as the insulating layer 12 etched in step ST9.
  • CMP Chemical Mechanical Polishing
  • the interposer IP is singulated by dicing or the like (step ST25). As described above, the interposer IP can be manufactured.
  • the exposure method uses the first exposure apparatus 100 that uses a reticle (photomask) to expose a plurality of beams on wafer W1 with exposure light through first reticle R1.
  • a first exposure pattern EPT1 is formed in a first region ER1 of each of the pattern formation regions PTR, and a second region ER2 separated from the first region ER1 in each of the pattern formation regions PTR is exposed to light through a second reticle R2.
  • the first exposure pattern EPT1 and the second exposure pattern EPT2 are formed using the second exposure apparatus 200 that uses the spatial light modulator 221 that modulates the exposure light based on the output from the pattern determination unit 200B.
  • the throughput is high, but the stitching accuracy is general. becomes larger than 20 nm. Therefore, it is difficult to narrow the width of the wiring (for example, 200 nm or less).
  • the stitching accuracy is high, but the throughput is low.
  • the spatial light modulator It is possible to achieve higher throughput and higher stitching accuracy than when using only an exposure apparatus that uses . Specifically, a stitching accuracy of approximately 10 nm or less can be achieved. This makes it possible to narrow the width of the wiring (for example, 200 nm or less).
  • the exposure method includes changing the connection pattern formed by the exposure light through the spatial light modulator 221 based on the positions of the first exposure pattern EPT1 and the second exposure pattern EPT2. . Since the connection pattern can be changed, the first exposure pattern EPT1 and the second exposure pattern EPT2 are reliably connected even when the formation positions of the first exposure pattern EPT1 and the second exposure pattern EPT2 deviate from the designed positions. It is possible to improve the connection reliability of the wiring.
  • the exposure method measures the position of the first exposure pattern EPT1 and the position of the second exposure pattern EPT2, and the measurement results of the positions of the first exposure pattern EPT1 and the second exposure pattern EPT2. and changing the connection pattern formed by the exposure light through the spatial light modulator 221 based on the exposure light.
  • a connection pattern that connects the first exposure pattern EPT1 and the second exposure pattern EPT2 can be determined based on the actual position of the first exposure pattern EPT1 and the actual position of the second exposure pattern EPT2. Therefore, the first exposure pattern EPT1 and the second exposure pattern EPT2 can be reliably connected, and the connection reliability of the wiring can be improved.
  • the exposure method according to the present embodiment uses the first exposure apparatus 100 that uses a reticle to expose the first regions ER1 and PTR in each of the plurality of pattern formation regions PTR on the wafer W1 with exposure light through the third reticle R3. It further includes forming a third exposure pattern EPT3 in a third area ER3 different from the second area ER2.
  • the first region ER1 and the second region ER2 are adjacent in the X direction along the surface of the wafer W1, and the third region ER3 is adjacent to the first region ER1 in the Y direction crossing the X direction.
  • connection pattern with the exposure light through the spatial light modulator 221 connects between the first region ER1 and the second region ER2 adjacent in the X direction with the exposure light through the spatial light modulator 221.
  • an exposure pattern corresponding to the L/S pattern LS of the interposer IP can be formed in the pattern formation region PTR having an area approximately four times the projected area of the pattern formed on one reticle.
  • the wafer W1 is changed around the axis (Z-axis) intersecting the surface of the wafer W1, and the exposure light through the spatial light modulator 221 is applied between the first region ER1 and the third region ER3 adjacent in the Y direction.
  • Form a connection pattern compared to the case where the stage 241 is driven without changing the orientation of the wafer W1 around the Z-axis and the second connection pattern is formed by the exposure light that has passed through the spatial light modulator 221, the process can be completed in a short time. Since the second connection pattern can be formed, high throughput can be achieved.
  • connection pattern formed by exposure light through the spatial light modulator 221 includes a pattern that connects with the first exposure pattern EPT1 exposed in the first region ER1. Thereby, a wiring pattern connected to the wiring pattern WP1 formed based on the first exposure pattern EPT1 can be formed.
  • the first exposure pattern EPT1 and the second exposure pattern EPT2, and the connection pattern formed by exposure light through the spatial light modulator 221 include an L/S pattern. is 200 nm or less. Since a thin L/S pattern can be formed, high-density wiring can be formed. Therefore, the number of communication channels can be increased, and high-speed communication between the logic circuit and the memory arranged on the interposer can be enabled, for example.
  • the first exposure pattern EPT1 is formed by exposing the image of the first pattern PT1 formed on the first reticle R1 to the first area ER1
  • the second exposure pattern EPT2 is formed by: It is formed by exposing the image of the second pattern formed on the second reticle R2 different from the first reticle R1 to the second area ER2.
  • the method for manufacturing the interposer IP is such that the surface (insulating layer 12) of the wafer W1 is exposed using the first exposure pattern EPT1 and the second exposure pattern EPT2 formed by the first exposure apparatus 100 as masks. and processing (etching) the surface (insulating layer 12) of wafer W1 using the first connection pattern formed in first connection region CR1 by second exposure apparatus 200 as a mask. .
  • an interposer IP having a large area, high wiring density, and high connection reliability can be manufactured with high throughput.
  • the second exposure apparatus 200 includes the stage 241 for mounting the wafer W1 on which the wiring patterns WP1 to WP4 are formed in the plurality of regions ER1 to ER4 separated from each other, and the wiring patterns WP1 to WP4.
  • a pattern determination unit 200B that determines a connection pattern based on the measurement results of the positions of, a spatial light modulator 221 that modulates and emits incident light based on the output from the pattern determination unit 200B, and a spatial light modulator 221, and a projection optical system 230 for projecting an image of the light modulating surface of the spatial light modulator 221 between adjacent regions among the plurality of regions ER1 to ER4.
  • a connection pattern that connects at least any two of the wiring patterns WP1 to WP4 can be formed.
  • the exposure system ES forms exposure patterns in a plurality of regions separated from each other in the pattern formation region PTR on the wafer W1 with exposure light passing through each of the plurality of reticles.
  • a second exposure device 200 that forms an exposure pattern with light.
  • the case where the first exposure apparatus 100 exposes the pattern image using the reticle R is four in the pattern formation region PTR corresponding to the interposer IP. is not limited to In the pattern formation region PTR, the number of regions where the first exposure device 100 exposes the pattern image using the reticle R may be, for example, two, or may be five or more.
  • the pattern determination unit 200B may determine connection patterns so that the wiring patterns formed in each region are connected as designed.
  • the positions of the first exposure pattern EPT1 to the fourth exposure pattern EPT4 are detected by detecting the positions of the alignment marks AM1 to AM4 formed on the wafer W1.
  • it was measured it is not limited to this.
  • the first reticle R1 to the fourth reticle R4 each having a different pattern are used, but the present invention is not limited to this.
  • one reticle R5 having a pattern PT5 as shown in FIG. 19A is rotated as shown in FIG. may be exposed to multiple regions of the
  • one sheet including the first pattern PT1 formed on the first reticle R1 and the second pattern PT2 formed on the second reticle R2 is printed.
  • a single reticle R7 including a reticle R6, a third pattern PT3 formed on the third reticle R3, and a fourth pattern PT4 formed on the fourth reticle R4 is used for the first exposure.
  • the pattern EPT1 to the fourth exposure pattern EPT4 may be formed in the pattern formation region PTR.
  • a reticle including the first pattern PT1 and the third pattern PT3 and a reticle including the second pattern PT2 and the fourth pattern PT4 are used to form the first exposure pattern EPT1 to the fourth exposure pattern EPT4 in the pattern formation area. It may be formed in the PTR.
  • steps ST19 and ST21 in FIG. 7 can be omitted, thereby further improving the throughput.
  • the region including the first region ER1 and the second region ER2 is defined as the first pattern formation region
  • the region including the third region ER3 and the fourth region ER4. is a second pattern formation region
  • a connection pattern connecting the wiring pattern WP1 and the wiring pattern WP2 is formed between the first region ER1 and the second region ER2 in the first pattern formation region
  • the second pattern formation region A connection pattern that connects the wiring pattern WP3 and the wiring pattern WP4 may be formed between the third region ER3 and the fourth region ER4. That is, the first connection region may be divided into two regions and different connection patterns may be formed in each region.
  • connection pattern that matches the actual formation positions of the wiring pattern WP1 and the wiring pattern WP2, and a connection pattern that matches the actual formation positions of the wiring pattern WP3 and the wiring pattern WP4. Reliability can be ensured. The same applies to the second connection area.
  • the first connection pattern determined by the determination unit 320 of the pattern determination unit 200B includes the connection pattern connecting the wiring pattern WP1 and the wiring pattern WP4, and the connection pattern connecting the wiring pattern WP2 and the wiring pattern WP3. and connection patterns.
  • the second connection pattern may include a connection pattern connecting the wiring pattern WP1 and the wiring pattern WP4 and a connection pattern connecting the wiring pattern WP2 and the wiring pattern WP3.
  • the orientation of the wafer W1 is changed by 90 degrees around the Z-axis by the pre-alignment system, and then the second connection patterns are formed.
  • the direction of the spatial light modulator 221 is changed around the axis (Z-axis) that intersects the light modulation surface of the spatial light modulator 221, and the second connection pattern is formed. good too.
  • the orientation of wafer W1 is changed by a predetermined angle around the Z-axis by the pre-alignment system, and the orientation of spatial light modulator 221 is changed by a certain angle around the Z-axis.
  • the angle for changing the orientation of wafer W1 and the angle for changing the orientation of spatial light modulator 221 may be any angle as long as the second connection pattern can be formed in second connection region CR2.
  • connection pattern that connects the wiring pattern WP1 and the wiring pattern WP2 is formed in the first connection region CR1, but the present invention is not limited to this.
  • a connection pattern connected to either one of the wiring pattern WP1 and the wiring pattern WP2 may be formed in the first connection region CR1.
  • the exposure pattern formed in at least one of the first connection region CR1 and the second connection region CR2 may not include a connection pattern.
  • development, etching, and resist coating are performed after the exposure of the images of the first pattern PT1 to the fourth pattern PT4 in the first exposure device 100, but the present invention is not limited to this.
  • the wafer W1 is loaded into the second exposure apparatus 200, and the alignment marks AM1 to AM4 are exposed as latent image patterns on the resist. may be determined and formed to determine and form the first connection pattern and the second connection pattern.
  • the first exposure pattern EPT1 is formed in the first region ER1 within the pattern formation region PTR, and the second region ER2 separated from the first region ER1 within the pattern formation region PTR.
  • a wafer W1 having a second exposure pattern EPT2 formed thereon is placed on the wafer W1, and the pattern determination unit 200B determines a connection pattern based on the measurement results of the positions of the first exposure pattern EPT1 and the second exposure pattern EPT2. good too.
  • step ST10 resist coating in FIG. 6
  • First exposure apparatus 200 Second exposure apparatus 200A Exposure apparatus main body 200B Pattern determination section 221 Spatial light modulator 241 Stage CPT Connection pattern ES Exposure system ER1 to ER4 First to fourth areas EPT1 to EPT4 First to fourth exposure Pattern IP Interposers LS1 to LS4 First to fourth L/S patterns PTR Pattern forming regions PT1 to PT4 First to fourth patterns R, R1 to R7 Reticles W0, W1 Wafers WP1 to WP4 Wiring patterns

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PCT/JP2023/005314 2022-02-17 2023-02-15 露光方法、デバイス製造方法、露光装置、及び露光システム Ceased WO2023157888A1 (ja)

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