WO2022183822A1 - 阵列基板的制备方法及阵列基板 - Google Patents

阵列基板的制备方法及阵列基板 Download PDF

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WO2022183822A1
WO2022183822A1 PCT/CN2021/142755 CN2021142755W WO2022183822A1 WO 2022183822 A1 WO2022183822 A1 WO 2022183822A1 CN 2021142755 W CN2021142755 W CN 2021142755W WO 2022183822 A1 WO2022183822 A1 WO 2022183822A1
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Prior art keywords
layer
photoresist
metal layer
array substrate
region
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PCT/CN2021/142755
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English (en)
French (fr)
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张合静
刘振
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重庆先进光电显示技术研究院
重庆惠科金渝光电科技有限公司
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Publication of WO2022183822A1 publication Critical patent/WO2022183822A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application relates to the technical field of display manufacturing, and in particular, to a method for preparing an array substrate and an array substrate.
  • Amorphous silicon semiconductor TFT Thin Film Transistor, thin film transistor
  • One of the objectives of the embodiments of the present application is to provide a method for preparing an array substrate and an array substrate.
  • a method for preparing an array substrate comprising the following steps:
  • One-time deposition deposit the first metal layer, insulating layer, active layer and doping layer on the substrate in sequence;
  • a photomask a photoresist is formed on the doped layer by a first photomask process, and the first metal layer, the insulating layer, the active layer, the doped layer and the The photoresist is etched to form a gate and a channel;
  • Secondary deposition depositing a second metal layer on the substrate
  • Secondary mask using a second mask process to pattern the second metal layer to form a source-drain metal layer
  • Three depositions depositing a passivation layer on the substrate;
  • the passivation layer is patterned by a third mask process to form a pixel electrode pattern, and a pixel electrode layer is formed on the passivation layer according to the pixel electrode pattern.
  • the first mask step specifically includes the following steps:
  • the photoresist After exposing and developing the photoresist, the photoresist is removed to form the gate and the channel.
  • the etching treatment method of the source layer and the insulating layer is dry etching; the etching method of the first metal layer is wet etching.
  • the step of removing the photoresist to form the gate and the channel specifically includes the following steps:
  • the photoresist remaining on the doped layer is removed twice to form the gate.
  • the photoresist in the step of removing the photoresist once to keep the photoresist on the doped layer facing the thin film transistor region, the photoresist is removed once at completed in the same process.
  • the photoresist on both sides of the channel is irradiated with light by means of a mask.
  • two of the photoresists, and the two photoresists are removed by a developer.
  • the removal of the two photoresists on both sides of the channel is performed in the same process.
  • the method of performing the etching process on the doped layer is dry etching.
  • a thin film transistor area, a storage capacitor area, a pixel area, a through hole area, and a binding area are provided on the substrate at intervals; the thin film transistor area is provided with the first metal layer, the an insulating layer, the active layer, the doped layer and the second metal layer; the first metal layer, the insulating layer, the active layer and the second metal layer are sequentially arranged on the storage capacitor region the second metal layer; the first metal layer, the insulating layer, the active layer and the second metal layer are sequentially arranged on the through hole region; the first metal layer, the insulating layer and the active layer; the passivation layer covers the substrate.
  • a first spacing region is formed between the photoresist facing the thin film transistor region and the photoresist facing the storage capacitor region; the photoresist facing the storage capacitor region
  • a second spacing region is formed between the photoresist and the photoresist facing the through hole region, and the second spacing region is facing the pixel region; the photoresist facing the through hole region is the same as the
  • a third spacer region is formed at intervals between the photoresists for the bonding region, and the etching of the first spacer region, the second spacer region and the third spacer region is performed in the same dry etching process completed in.
  • the first metal layer in the first spacer region, the first metal layer in the second spacer region, and the first metal layer in the third spacer region done in the same wet engraving process.
  • the second metal layer facing the thin film transistor region, the second metal layer facing the storage capacitor region, and two of the second metals facing the via region are formed in the same process.
  • the passivation layer and the pixel electrode layer are formed respectively by a photoresist lift-off technique.
  • the active layer is an amorphous silicon layer.
  • the pixel electrode layer is an indium tin oxide layer.
  • the insulating layer is silicon oxide or silicon nitride.
  • an array substrate which is prepared by the method for preparing an array substrate provided in the above embodiment, the array substrate comprising:
  • a first metal layer disposed on the substrate
  • a doping layer disposed on the insulating layer facing the thin film transistor region;
  • the second metal layer is divided into two groups, one group of the second metal layer is disposed on the doped layer to form a source-drain metal layer, and the other group of the second metal layer is disposed on the active layer ;
  • a passivation layer disposed on the second metal layer, the channel and the active layer;
  • the pixel electrode layer is respectively connected with the first metal layer and the second metal layer.
  • the beneficial effects of the method for fabricating an array substrate are: forming a gate and a channel through a first mask process, forming a source-drain metal layer through a second mask process, and forming a third mask process Passivation layer and pixel electrode layer.
  • a second metal layer is deposited between the first mask process and the second mask process, so as to prevent the active layer from protruding on both sides below the second metal layer, thereby reducing TFT light leakage and improving the resolution of the panel Rate.
  • the present application prepares the array substrate through three photomask manufacturing processes, which can reduce the process flow and improve the production efficiency.
  • the beneficial effect of the array substrate provided by the embodiments of the present application is that the array substrate prepared by the method for preparing the array substrate shortens the process time and helps to improve the production efficiency.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by a comparative example of the present application
  • FIG. 2 is a schematic structural diagram of an array substrate provided in an embodiment of the present application in one deposition step
  • FIG. 3 is a schematic structural diagram 1 of an array substrate provided in an embodiment of the present application in one mask step;
  • FIG. 4 is a second structural schematic diagram of an array substrate provided in an embodiment of the present application in a mask step
  • FIG. 5 is a third structural schematic diagram of an array substrate provided in an embodiment of the present application in a mask step
  • FIG. 6 is a schematic structural diagram of an array substrate provided in an embodiment of the present application in the steps of secondary deposition and secondary mask;
  • FIG. 7 is a schematic structural diagram of the array substrate provided in the embodiment of the present application in the steps of three depositions and three masking steps.
  • the preparation method of the array substrate includes the following steps:
  • a first metal layer 2 , an insulating layer 3 , an active layer 4 and a doping layer 5 are sequentially deposited on the substrate 1 .
  • the insulating layer 3 can be silicon oxide or silicon nitride, etc.
  • the active layer 4 can be an amorphous silicon layer, which is not limited here.
  • a photoresist 6 is formed on the doped layer 5 by the first mask process, and the first metal layer 2 , the insulating layer 3 , the active layer 4 , and the doped layer are respectively applied.
  • the impurity layer 5 and the photoresist 6 are etched to form the gate 61 and the channel 7 .
  • the first mask manufacturing process may be a second-order mask, such as an HTM (halftone mask, halftone mask), a half-gray dimming mask, etc., which is not limited herein.
  • the substrate 1 is divided into a thin film transistor region 11 , a storage capacitor region 12 , a pixel region 13 , a through hole region 14 and a binding region 15 at intervals.
  • the first metal layer 2, the insulating layer 3, the active layer 4 and the doped layer 5 deposited on the substrate 1 in sequence cover the thin film transistor region 11, the storage capacitor region 12, the pixel region 13, On the via area 14 and the bonding area 15.
  • a masking step a first masking process is used to form a photoresist 6 on the doped layer 5.
  • the photoresist 6 is formed on the doped layer 5 opposite to the thin film transistor region 11, respectively.
  • Photoresist 6 is formed on doped layer 5 facing storage capacitor region 12 , photoresist 6 is formed on doped layer 5 facing via region 14 , and photoresist 6 is formed on doped layer 5 facing bonding region 15 Block 6.
  • the adjacent photoresists 6 are arranged at intervals, which facilitates the subsequent etching of the first metal layer 2 , the insulating layer 3 , the active layer 4 and the doped layer 5 respectively.
  • the etching process of the first metal layer 2 , the insulating layer 3 , the active layer 4 , the doped layer 5 and the photoresist 6 respectively is as follows: S21 ) The doped layers 5 , 5 and 6 are respectively etched. The active layer 4 , the insulating layer 3 and the first metal layer 2 are etched; S22 ) After the photoresist 6 is exposed and developed, the photoresist 6 is removed to form the gate 61 and the channel 7 .
  • a first spacer region 16 is formed between the photoresist 6 facing the thin film transistor region 11 and the photoresist 6 facing the storage capacitor region 12; the photoresist 6 facing the storage capacitor region 12 and the photoresist facing the through hole region 14
  • a second spacer area 17 is formed at intervals between the resistors 6, and the second spacer area 17 is opposite to the pixel area 13; Three spaced regions 18 .
  • step S21 the doped layer 5, the active layer 4 and the insulating layer 3 located in the first spacer region 16 are sequentially etched away by dry etching, and the second spacer is located in the second spacer by dry etching.
  • the doped layer 5, the active layer 4 and the insulating layer 3 in the region 17 are etched away in sequence, and the doped layer 5, the active layer 4 and the insulating layer 3 in the third spacer region 18 are etched sequentially by dry etching Lose.
  • the etching of the first spacer region 16 , the second spacer region 17 and the third spacer region 18 can be completed in the same dry etching process, which helps to improve efficiency.
  • the first metal layer 2 located in the first spacing region 16 is etched away by wet etching, the first metal layer 2 located in the second spacing region 17 is etched away, and the first metal layer 2 located in the third spacing region 18 is etched away.
  • the first metal layer 2 is etched away.
  • the first metal layer 2 in the first spacer region 16 , the first metal layer 2 in the second spacer region 17 and the first metal layer 2 in the third spacer region 18 may be completed in the same wet etching process.
  • step S22 the following steps may be specifically included:
  • the photoresist 6 is removed once to keep the photoresist 6 on the doped layer 5 facing the thin film transistor region 11 .
  • the photoresist 6 located in the channel 7 is irradiated with light by means of a mask, and the photoresist 6 is removed by a developer, and the photoresist 6 located on both sides of the channel 7 is reserved;
  • the photoresist 6 facing the storage capacitor region 12 is irradiated with light, and the photoresist 6 is removed by the developer;
  • the photoresist 6 facing the through hole region 14 is irradiated with light by means of a mask, and the photoresist 6 is irradiated by the developer with the developer.
  • the photoresist 6 is removed; the photoresist 6 facing the bonding area 15 is irradiated with light by means of a mask, and the photoresist 6 is removed by a developer.
  • the photoresist 6 located in the channel 7, the photoresist 6 facing the storage capacitor region 12, the photoresist 6 facing the through hole region 14, and the photoresist 6 facing the bonding region 15 can be removed at one time. completed in the same process.
  • the doped layer 5 facing the thin film transistor region 11 is etched to form a channel 7 .
  • the doped layer 5 is etched, due to the shielding of the doped layer 5 by the photoresist 6 located on both sides of the channel 7, the doped layer 5 is blocked by the photoresist 6 on both sides of the channel 7.
  • the doping layer 5 between the photoresists 6 is etched away.
  • the etching method for the doped layer 5 facing the thin film transistor region 11 is dry etching.
  • the photoresist 6 remaining on the doped layer 5 is removed twice to form the gate electrode 61 .
  • the two photoresists 6 located on both sides of the channel 7 are irradiated with light by means of a mask, and the photoresists 6 are removed by a developer.
  • the removal of the two photoresists 6 on both sides of the channel 7 can be completed in the same process.
  • the second metal layer 8 is deposited on the doped layers 5 on both sides of the channel 7 respectively, the second metal layer 8 is deposited on the active layer 4 facing the storage capacitor region 12 , and the Two second metal layers 8 are deposited spaced apart on the active layer 4 facing the via region 14 .
  • the second metal layer 8 facing the thin film transistor region 11 , the second metal layer 8 facing the storage capacitor region 12 , and the two second metal layers 8 facing the through hole region 14 can be formed in the same process.
  • the second metal layer 8 is patterned by a second mask process to form the source-drain metal layer 81 .
  • the second metal layer 8 is exposed, developed and etched through a common mask, and the two second metal layers 8 disposed at intervals facing the thin film transistor region 11 respectively form the source and drain electrodes of the thin film transistor (ie The source and drain metal layer 81), the edge of the source is aligned with the edge of the doped layer 5 arranged opposite to it, and the edge of the drain is aligned with the edge of the doped layer 5 arranged opposite to it, so that the second metal can be avoided.
  • the active layer 4 is protruded from the lower side of the layer 8, thereby reducing the light leakage of the TFT and improving the resolution of the panel.
  • the other pole of the storage capacitor is formed with respect to the second metal layer 8 of the storage capacitor region 12 .
  • the second photomask manufacturing process may be a common photomask, which is not limited herein.
  • a passivation layer 9 is deposited on the substrate 1 .
  • the passivation layer 9 can connect the channel 7 , the first spacer region 16 , the second spacer region 17 , and the second metal layer 8 between the two spaced apart areas opposite to the through hole region 14 .
  • the gaps and third spacer regions 18 are filled.
  • the pixel region 13 generally has an insulating layer 3 and a passivation layer 9. Due to the existence of the two-layer structure, light will be refracted or reflected at the interface joint, thereby affecting the display quality.
  • the pixel region 13 processed by the second mask process and deposited three times in S5) has only the passivation layer 9, so the phenomenon of light refraction or reflection caused by the combination of the passivation layer 9 and other layers can be avoided, and further Helps improve display quality.
  • the material of the passivation layer 9 may be oxide, nitride or oxynitride, which is not limited herein.
  • the passivation layer 9 is patterned by the third mask process to form a pixel electrode pattern, and the pixel electrode layer 10 is formed on the passivation layer 9 according to the pixel electrode pattern.
  • the passivation layer 9 and the pixel electrode layer 10 are respectively formed by the photoresist lift-off technology, and the pixel electrode layer 10 facing the thin film transistor region 11 is connected to the second metal layer 8 on the side of the channel 7;
  • the pixel electrode layer 10 is an indium tin oxide (Indium tin oxide, ITO) layer.
  • the third mask manufacturing process can be a second-order mask, such as HTM, half-gray dimming mask, etc., which is not limited herein.
  • an embodiment of the present application further provides an array substrate, which is prepared by the above-mentioned method for fabricating an array substrate.
  • the array substrate includes a substrate 1 , a first metal layer 2 , an insulating layer 3 , an active layer 4 , a doping layer 5 , a second metal layer 8 , a passivation layer 9 and a pixel electrode layer 10 .
  • the substrate 1 is provided with a thin film transistor region 11 , a first spacer region 16 , a storage capacitor region 12 , a pixel region 13 (opposite the second spacer region 17 ), a through hole region 14 , a third spacer region 18 and a bonding Define area 15.
  • a first metal layer 2 is respectively provided on the thin film transistor region 11 , the storage capacitor region 12 , the through hole region 14 and the binding region 15 , and an insulating layer 3 and an active layer 4 are respectively provided on each first metal layer 2 in sequence. .
  • Two doped layers 5 are provided at intervals on the active layer 4 facing the thin film transistor region 11, and a second metal layer 8 is provided on each of the doped layers 5, and the source and drain electrodes of the thin film transistor ( That is, the source-drain metal layer 81), and a channel 7 is formed between the source and the drain.
  • a second metal layer 8 is provided on the active layer 4 facing the storage capacitor region 12 and forms the other pole of the storage capacitor. Two second metal layers 8 are spaced apart on the active layer 4 facing the through hole region 14 .
  • the passivation layer 9 is disposed on the substrate 1 and covers the first metal layer 2 , the insulating layer 3 , the active layer 4 , the doping layer 5 and the second metal layer 8 .
  • the pixel electrode layer 10 is disposed on the passivation layer 9 and is connected to the first metal layer 2 and the second metal layer 8 through contact holes, respectively.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

本申请公开一种阵列基板的制备方法及阵列基板，该阵列基板的制备方法包括：在基板（1）上依次沉积第一金属层（2）、绝缘层（3）、有源层（4）和掺杂层（5）；采用第一道光罩制程在掺杂层（5）上形成光阻（6），并刻蚀处理形成栅极（61）和沟道（7）；在基板（1）上沉积第二金属层（8）；采用第二道光罩制程形成源漏极金属层（81）；在基板（1）上沉积钝化层（9）；采用第三道光罩制程形成像素电极层（10）。

Description

阵列基板的制备方法及阵列基板
本申请要求于2021年03月01日在中国专利局提交的、申请号为202110223720.4、申请名称为“阵列基板的制备方法及阵列基板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示器制造技术领域，具体涉及一种阵列基板的制备方法及阵列基板。
 背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然构成现有技术。
非晶硅半导体TFT（Thin Film Transistor，薄膜晶体管）显示器由于其成本低、制程稳定，是目前应用最广泛的显示器。
为了降低成本，提高生产效率，目前的TFT显示器由最初的五道光罩制程逐渐向四道光罩制程及三道光罩制程发展。然而，在三道光罩制程中，不可避免地在第二金属层的下方之两侧凸出有源层，从而影响TFT光漏电及面板的分辨率。
 技术问题
本申请实施例的目的之一在于：提供一种阵列基板的制备方法及阵列基板。
 技术解决方案
本申请实施例采用的技术方案是：
第一方面，提供了一种阵列基板的制备方法，包括如下步骤：
一次沉积：在基板上依次沉积第一金属层、绝缘层、有源层和掺杂层；
一次光罩：采用第一道光罩制程在所述掺杂层上形成光阻，分别对所述第一金属层、所述绝缘层、所述有源层、所述掺杂层及所述光阻进行刻蚀处理形成栅极和沟道；
二次沉积：在所述基板上沉积第二金属层；
二次光罩：采用第二道光罩制程对所述第二金属层进行图案化处理形成源漏极金属层；
三次沉积：在所述基板上沉积钝化层；
三次光罩：采用第三道光罩制程对所述钝化层进行图案化处理形成像素电极图案，根据所述像素电极图案形成像素电极层于所述钝化层上。
在一个实施例中，于所述一次光罩步骤中，具体包括如下步骤：
分别对所述掺杂层、所述有源层、所述绝缘层和所述第一金属层进行刻蚀处理；
曝光显影所述光阻后，移除所述光阻以形成所述栅极和所述沟道。
在一个实施例中，于分别对所述掺杂层、所述有源层、所述绝缘层和所述第一金属层进行刻蚀处理步骤中：分别对所述掺杂层、所述有源层和所述绝缘层的刻蚀处理方式为干刻；对所述第一金属层的刻蚀方式为湿刻。
在一个实施例中，于曝光显影所述光阻后，移除所述光阻以形成所述栅极和所述沟道步骤中，具体包括如下步骤：
对所述光阻进行一次移除，以保留正对于薄膜晶体管区域的所述掺杂层上的所述光阻；
对正对于所述薄膜晶体管区域的所述掺杂层进行刻蚀处理形成所述沟道；
将所述掺杂层上剩余的所述光阻进行二次移除以形成所述栅极。
在一个实施例中，于对所述光阻进行一次移除，以保留正对于薄膜晶体管区域的所述掺杂层上的所述光阻步骤中，对所述光阻进行一次移除作业在同一制程中完成。
在一个实施例中，于将所述掺杂层上剩余的所述光阻进行二次移除以形成所述栅极步骤中，借助掩膜板并通过光线照射位于所述沟道两侧的两个所述光阻，并通过显影液将两个所述光阻移除。
在一个实施例中，位于所述沟道两侧的两个所述光阻的移除作业在同一制程中完成。
在一个实施例中，于对正对于薄膜晶体管区域的所述掺杂层进行刻蚀处理形成所述沟道步骤中，对所述掺杂层进行刻蚀处理的方式为干刻。
在一个实施例中，所述基板上间隔设有薄膜晶体管区域、存储电容区域、像素区域、通孔区域和绑定区域；所述薄膜晶体管区域上依次设有所述第一金属层、所述绝缘层、所述有源层、所述掺杂层和所述第二金属层；所述存储电容区域上依次设有所述第一金属层、所述绝缘层、所述有源层和所述第二金属层；所述通孔区域上依次设有所述第一金属层、所述绝缘层、所述有源层和所述第二金属层；所述绑定区域上依次设有所述第一金属层、所述绝缘层和所述有源层；所述钝化层包覆所述基板。
在一个实施例中，正对于所述薄膜晶体管区域的所述光阻与正对于所述存储电容区域的所述光阻之间间隔形成第一间隔区域；正对于所述存储电容区域的所述光阻与正对于所述通孔区域的所述光阻之间间隔形成第二间隔区域，所述第二间隔区域正对于所述像素区域；正对于所述通孔区域的所述光阻与正对于所述绑定区域的所述光阻之间间隔形成第三间隔区域，对于所述第一间隔区域、所述第二间隔区域和所述第三间隔区域的刻蚀在同一干刻制程中完成。
在一个实施例中，所述第一间隔区域中的所述第一金属层、所述第二间隔区域中的所述第一金属层和所述第三间隔区域中的所述第一金属层在同一湿刻制程中完成。
在一个实施例中，正对于所述薄膜晶体管区域的所述第二金属层、正对于所述存储电容区域的所述第二金属层和正对于所述通孔区域的两个所述第二金属层在同一制程中形成。
在一个实施例中，于所述三次光罩步骤中：通过光阻剥离技术分别形成所述钝化层和所述像素电极层。
在一个实施例中，所述有源层为非晶硅层。
在一个实施例中，所述像素电极层为氧化铟锡层。
在一个实施例中，所述绝缘层为氧化硅或氮化硅。
第二方面，提供了一种阵列基板，由上述实施例提供的阵列基板的制备方法制得，所述阵列基板包括：
基板；
第一金属层，设于所述基板上；
绝缘层，设于所述第一金属层上；
有源层，设于所述绝缘层上；
掺杂层，设于正对薄膜晶体管区域之所述绝缘层上；
第二金属层，分为两组，一组所述第二金属层设于所述掺杂层上形成源漏极金属层，另一组所述第二金属层设于所述有源层上；
钝化层，设于所述第二金属层、所述沟道和所述有源层上；
像素电极层，分别与所述第一金属层和所述第二金属层连接。
 有益效果
本申请实施例提供的阵列基板的制备方法的有益效果在于：通过第一道光罩制程形成栅极及沟道，通过第二道光罩制程形成源漏极金属层，通过第三道光罩制程形成钝化层及像素电极层。在第一道光罩制程与第二道光罩制程之间沉积第二金属层，从而可避免第二金属层的下方之两侧凸出有源层，从而减小TFT光漏电，提高面板的分辨率。而且，本申请通过三道光罩制程制备阵列基板，可减少工艺流程，提高生产效率。
本申请实施例提供的阵列基板的有益效果在于：由阵列基板的制备方法制得的阵列基板缩短了制程时间，有助于提高生产效率。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或示范性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本申请对比例提供的阵列基板的结构示意图；
图2为本申请实施例提供的阵列基板在一次沉积步骤中的结构示意图；
图3为本申请实施例提供的阵列基板在一次光罩步骤中的结构示意图一；
图4为本申请实施例提供的阵列基板在一次光罩步骤中的结构示意图二；
图5为本申请实施例提供的阵列基板在一次光罩步骤中的结构示意图三；
图6为本申请实施例提供的阵列基板在二次沉积和二次光罩步骤中的结构示意图；
图7为本申请实施例提供的阵列基板在三次沉积和三次光罩步骤中的结构示意图。
其中，图中各附图主要标记：
1-基板；11-薄膜晶体管区域；12-存储电容区域；13-像素区域；14-通孔区域；15-绑定区域；16-第一间隔区域；17-第二间隔区域；18-第三间隔区域；2-第一金属层；3-绝缘层；4-有源层；5-掺杂层；6-光阻；61、栅极；7-沟道；8-第二金属层；81-源漏极金属层；9-钝化层；10-像素电极层。
 本发明的实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
需说明的是，当部件被称为“固定于”或“设置于”另一个部件，它可以直接在另一个部件上或者间接在该另一个部件上。当一个部件被称为是“连接于”另一个部件，它可以是直接或者间接连接至该另一个部件上。
术语“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。
术语“第一”、“第二”、“第三”仅用于便于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明技术特征的数量。“多个”的含义是两个或两个以上，除非另有明确具体的限定。
为了说明本申请所提供的技术方案，以下结合具体附图及实施例进行详细说明。请参阅图1，在目前的三道光罩制程中，不可避免地在第二金属层8的下方之两侧凸出有源层4，从而影响TFT光漏电及面板的分辨率。基于此，本申请实施例提供一种阵列基板的制备方法来解决上述问题。
现对本申请实施例提供的阵列基板的制备方法进行说明。该阵列基板的制备方法包括如下步骤：
S1）一次沉积：请参阅图2，在基板1上依次沉积第一金属层2、绝缘层3、有源层4和掺杂层5。其中，绝缘层3可为氧化硅或氮化硅等；有源层4可为非晶硅层，在此都不作唯一限定。
S2）一次光罩：请参阅图3至图5，采用第一道光罩制程在掺杂层5上形成光阻6，分别对第一金属层2、绝缘层3、有源层4、掺杂层5及光阻6进行刻蚀处理形成栅极61及沟道7。其中，第一道光罩制程可为二阶式光罩，如HTM（halftone mask，半色调掩膜），半灰色调光罩等，在此不作唯一限定。
具体地，基板1上间隔划分有薄膜晶体管区域11、存储电容区域12、像素区域13、通孔区域14和绑定区域15。在S1）一次沉积步骤中，基板1上依次沉积的第一金属层2、绝缘层3、有源层4和掺杂层5均覆盖于薄膜晶体管区域11、存储电容区域12、像素区域13、通孔区域14和绑定区域15上。在S2）一次光罩步骤中，采用第一道光罩制程在掺杂层5上形成光阻6，具体是分别在正对于薄膜晶体管区域11的掺杂层5上形成光阻6，在正对于存储电容区域12的掺杂层5上形成光阻6，在正对于通孔区域14的掺杂层5上形成光阻6，以及在正对于绑定区域15的掺杂层5上形成光阻6。相邻光阻6之间间隔设置，便于后续分别对第一金属层2、绝缘层3、有源层4和掺杂层5的刻蚀处理。
请参阅图4和图5，分别对第一金属层2、绝缘层3、有源层4、掺杂层5及光阻6进行刻蚀处理过程具体为：S21）分别对掺杂层5、有源层4、绝缘层3和第一金属层2进行刻蚀处理；S22）曝光显影光阻6后，移除该光阻6以形成栅极61和沟道7。正对于薄膜晶体管区域11的光阻6与正对于存储电容区域12的光阻6之间间隔形成第一间隔区域16；正对于存储电容区域12的光阻6与正对于通孔区域14的光阻6之间间隔形成第二间隔区域17，该第二间隔区域17正对于像素区域13；正对于通孔区域14的光阻6与正对于绑定区域15的光阻6之间间隔形成第三间隔区域18。
请参阅3和图4，在S21步骤中，通过干刻将位于第一间隔区域16中的掺杂层5、有源层4和绝缘层3依次刻蚀掉，通过干刻将位于第二间隔区域17中的掺杂层5、有源层4和绝缘层3依次刻蚀掉，通过干刻将位于第三间隔区域18中的掺杂层5、有源层4和绝缘层3依次刻蚀掉。其中，对于第一间隔区域16、第二间隔区域17和第三间隔区域18的刻蚀可在同一干刻制程中完成，有助于提高效率。随后，通过湿刻将位于第一间隔区域16中的第一金属层2刻蚀掉，将位于第二间隔区域17中的第一金属层2刻蚀掉，将位于第三间隔区域18中的第一金属层2刻蚀掉。其中，第一间隔区域16中的第一金属层2、第二间隔区域17中的第一金属层2和第三间隔区域18中的第一金属层2可在同一湿刻制程中完成。
请参阅图4和图5，在S22步骤中，具体可包括以下步骤：
S221）对光阻6进行一次移除，以保留正对于薄膜晶体管区域11的掺杂层5上的光阻6。具体地，借助掩膜板并通过光线照射位于沟道7中的光阻6，并通过显影液将该光阻6移除，预留位于沟道7两侧的光阻6；借助掩膜板并通过光线照射正对于存储电容区域12的光阻6，并通过显影液将光阻6移除；借助掩膜板并通过光线照射正对于通孔区域14的光阻6，并通过显影液将光阻6移除；借助掩膜板并通过光线照射正对于绑定区域15的光阻6，并通过显影液将光阻6移除。其中，位于沟道7中的光阻6、正对于存储电容区域12的光阻6、正对于通孔区域14的光阻6和正对于绑定区域15的光阻6的一次移除作业可在同一制程中完成。
S222）对正对于薄膜晶体管区域11的掺杂层5进行刻蚀处理形成沟道7。请参阅图4和图5，具体地，在薄膜晶体管区域11中，在对掺杂层5进行刻蚀时，由于位于沟道7两侧的光阻6对掺杂层5的遮挡，位于两个光阻6之间的掺杂层5被刻蚀掉。其中，对正对于薄膜晶体管区域11的掺杂层5的刻蚀方式为干刻。
S223）将掺杂层5上剩余的光阻6进行二次移除以形成栅极61。具体地，借助掩膜板并通过光线照射位于沟道7两侧的两个光阻6，并通过显影液将该光阻6移除。位于沟道7两侧的两个光阻6的移除作业可在同一制程中完成。
通过S2）一次光罩步骤，在薄膜晶体管区域11形成栅极61及沟道7，完善了存储电容区域12、像素区域13、通孔区域14和绑定区域15的制程结构。
S3）二次沉积：在基板1上沉积第二金属层8。请参阅图6，具体地，在位于沟道7两侧的掺杂层5上分别沉积第二金属层8，在正对于存储电容区域12的有源层4上沉积第二金属层8，在正对于通孔区域14的有源层4上间隔沉积两个第二金属层8。其中，正对于薄膜晶体管区域11的第二金属层8、正对于存储电容区域12的第二金属层8和正对于通孔区域14的两个第二金属层8可在同一制程中形成。
S4）二次光罩：采用第二道光罩制程对第二金属层8进行图案化处理形成源漏极金属层81。具体地，通过普通光罩对第二金属层8进行曝光、显影并刻蚀，正对薄膜晶体管区域11的两个间隔设置的第二金属层8分别形成薄膜晶体管的源极和漏极（即源漏极金属层81），源极的边缘和与之相对设置的掺杂层5的边缘对齐，漏极的边缘和与之相对设置的掺杂层5的边缘对齐，从而可避免第二金属层8的下方之两侧凸出有源层4，从而减小TFT光漏电，提高面板的分辨率。正对于存储电容区域12的第二金属层8形成存储电容的另一极。其中，第二道光罩制程可为普通光罩，在此不作唯一限定。
S5）三次沉积：在基板1上沉积钝化层9。请参阅图7，具体地，钝化层9可将沟道7、第一间隔区域16、第二间隔区域17、正对于通孔区域14的两个间隔设置的第二金属层8之间的间隙和第三间隔区域18填充。在传统的光罩制程中，像素区域13上一般有绝缘层3和钝化层9，由于有两层结构的存在，光会在界面结合处发生折射或反射，进而影响显示品质。然而此结构，由第二道光罩制程处理并经S5）三次沉积后的像素区域13仅有钝化层9，因此可避免钝化层9与其它层结合而导致光折射或反射的现象，进而有助于提高显示品质。其中，钝化层9的材料可为氧化物、氮化物或者氮氧化合物，在此不作唯一限定。
S6）三次光罩：采用第三道光罩制程对钝化层9进行图案化处理形成像素电极图案，根据像素电极图案形成像素电极层10于钝化层9上。请参阅图7，具体地，通过光阻剥离技术分别形成钝化层9和像素电极层10，正对于薄膜晶体管区域11的像素电极层10与沟道7一侧的第二金属层8连接；正对于通孔区域14的像素电极层10有两个，一个像素电极层10的一端与第一金属层2连接，该像素电极层10的另一端与其中一个第二金属层8连接，另一个像素电极层10与另一个第二金属层8连接；正对于绑定区域15的像素电极层10与第一金属层2连接。
其中，像素电极层10为氧化铟锡（Indium tin oxide，ITO）层。第三光罩制程可为二阶式光罩，如HTM，半灰色调光罩等，在此不作唯一限定。
请参阅图7，本申请实施例还提供了一种阵列基板，由上述阵列基板的制备方法制得。该阵列基板包括基板1、第一金属层2、绝缘层3、有源层4、掺杂层5、第二金属层8、钝化层9和像素电极层10。具体地，基板1上间隔设置有薄膜晶体管区域11、第一间隔区域16、存储电容区域12、像素区域13（正对于第二间隔区域17）、通孔区域14、第三间隔区域18和绑定区域15。在薄膜晶体管区域11、存储电容区域12、通孔区域14和绑定区域15上分别设置有第一金属层2，在各第一金属层2上分别依次设置有绝缘层3和有源层4。在正对于薄膜晶体管区域11的有源层4上间隔设置有两个掺杂层5，在各掺杂层5上设置有第二金属层8，并分别形成薄膜晶体管的源极和漏极（即源漏极金属层81），源极与漏极之间形成沟道7。在正对于存储电容区域12的有源层4上设置有第二金属层8，并形成存储电容的另一极。在正对于通孔区域14的有源层4上间隔设置有两个第二金属层8。钝化层9设置于基板1上，并将第一金属层2、绝缘层3、有源层4、掺杂层5和第二金属层8包覆。像素电极层10设置于钝化层9上，并分别通过接触孔与第一金属层2和第二金属层8连接。
应理解，上述实施例中各步骤的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
以上仅为本申请的可选实施例而已，并不用于限制本申请。对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (17)

  1. 阵列基板的制备方法，其中，包括如下步骤：
    一次沉积：在基板上依次沉积第一金属层、绝缘层、有源层和掺杂层；
    一次光罩：采用第一道光罩制程在所述掺杂层上形成光阻，分别对所述第一金属层、所述绝缘层、所述有源层、所述掺杂层及所述光阻进行刻蚀处理形成栅极和沟道；
    二次沉积：在所述基板上沉积第二金属层；
    二次光罩：采用第二道光罩制程对所述第二金属层进行图案化处理形成源漏极金属层；
    三次沉积：在所述基板上沉积钝化层；
    三次光罩：采用第三道光罩制程对所述钝化层进行图案化处理形成像素电极图案，根据所述像素电极图案形成像素电极层于所述钝化层上。
  2. 根据权利要求1所述的阵列基板的制备方法，其中，于所述一次光罩步骤中，具体包括如下步骤：
    分别对所述掺杂层、所述有源层、所述绝缘层和所述第一金属层进行刻蚀处理；
    曝光显影所述光阻后，移除所述光阻以形成所述栅极和所述沟道。
  3. 根据权利要求2所述的阵列基板的制备方法，其中，于分别对所述掺杂层、所述有源层、所述绝缘层和所述第一金属层进行刻蚀处理步骤中：分别对所述掺杂层、所述有源层和所述绝缘层的刻蚀处理方式为干刻；对所述第一金属层的刻蚀方式为湿刻。
  4. 根据权利要求2所述的阵列基板的制备方法，其中，于曝光显影所述光阻后，移除所述光阻以形成所述栅极和所述沟道步骤中，具体包括如下步骤：
    对所述光阻进行一次移除，以保留正对于薄膜晶体管区域的所述掺杂层上的所述光阻；
    对正对于所述薄膜晶体管区域的所述掺杂层进行刻蚀处理形成所述沟道；
    将所述掺杂层上剩余的所述光阻进行二次移除以形成所述栅极。
  5. 根据权利要求4所述的阵列基板的制备方法，其中，于对所述光阻进行一次移除，以保留正对于薄膜晶体管区域的所述掺杂层上的所述光阻步骤中，对所述光阻进行一次移除作业在同一制程中完成。
  6. 根据权利要求4所述的阵列基板的制备方法，其中，于将所述掺杂层上剩余的所述光阻进行二次移除以形成所述栅极步骤中，借助掩膜板并通过光线照射位于所述沟道两侧的两个所述光阻，并通过显影液将两个所述光阻移除。
  7. 根据权利要求6所述的阵列基板的制备方法，其中，位于所述沟道两侧的两个所述光阻的移除作业在同一制程中完成。
  8. 根据权利要求4所述的阵列基板的制备方法，其中，于对正对于薄膜晶体管区域的所述掺杂层进行刻蚀处理形成所述沟道步骤中，对所述掺杂层进行刻蚀处理的方式为干刻。
  9. 根据权利要求1所述的阵列基板的制备方法，其中，所述基板上间隔设有薄膜晶体管区域、存储电容区域、像素区域、通孔区域和绑定区域；所述薄膜晶体管区域上依次设有所述第一金属层、所述绝缘层、所述有源层、所述掺杂层和所述第二金属层；所述存储电容区域上依次设有所述第一金属层、所述绝缘层、所述有源层和所述第二金属层；所述通孔区域上依次设有所述第一金属层、所述绝缘层、所述有源层和所述第二金属层；所述绑定区域上依次设有所述第一金属层、所述绝缘层和所述有源层；所述钝化层包覆所述基板。
  10. 根据权利要求9所述的阵列基板的制备方法，其中，正对于所述薄膜晶体管区域的所述光阻与正对于所述存储电容区域的所述光阻之间间隔形成第一间隔区域；正对于所述存储电容区域的所述光阻与正对于所述通孔区域的所述光阻之间间隔形成第二间隔区域，所述第二间隔区域正对于所述像素区域；正对于所述通孔区域的所述光阻与正对于所述绑定区域的所述光阻之间间隔形成第三间隔区域，对于所述第一间隔区域、所述第二间隔区域和所述第三间隔区域的刻蚀在同一干刻制程中完成。
  11. 根据权利要求10所述的阵列基板的制备方法，其中，所述第一间隔区域中的所述第一金属层、所述第二间隔区域中的所述第一金属层和所述第三间隔区域中的所述第一金属层在同一湿刻制程中完成。
  12. 根据权利要求9所述的阵列基板的制备方法，其中，正对于所述薄膜晶体管区域的所述第二金属层、正对于所述存储电容区域的所述第二金属层和正对于所述通孔区域的两个所述第二金属层在同一制程中形成。
  13. 根据权利要求1所述的阵列基板的制备方法，其中，于所述三次光罩步骤中：通过光阻剥离技术分别形成所述钝化层和所述像素电极层。
  14. 根据权利要求1所述的阵列基板的制备方法，其中，所述有源层为非晶硅层。
  15. 根据权利要求1所述的阵列基板的制备方法，其中，所述像素电极层为氧化铟锡层。
  16. 根据权利要求1所述的阵列基板的制备方法，其中，所述绝缘层为氧化硅或氮化硅。
  17. 阵列基板，其中，由如权利要求1所述的阵列基板的制备方法制得，所述阵列基板包括：
    基板；
    第一金属层，设于所述基板上；
    绝缘层，设于所述第一金属层上；
    有源层，设于所述绝缘层上；
    掺杂层，设于正对薄膜晶体管区域之所述绝缘层上；
    第二金属层，分为两组，一组所述第二金属层设于所述掺杂层上形成源漏极金属层，另一组所述第二金属层设于所述有源层上；
    钝化层，设于所述第二金属层、所述沟道和所述有源层上；
    像素电极层，分别与所述第一金属层和所述第二金属层连接。
PCT/CN2021/142755 2021-03-01 2021-12-29 阵列基板的制备方法及阵列基板 WO2022183822A1 (zh)

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