WO2022064306A1 - 強誘電体デバイス、および半導体装置 - Google Patents

強誘電体デバイス、および半導体装置 Download PDF

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Publication number
WO2022064306A1
WO2022064306A1 PCT/IB2021/058179 IB2021058179W WO2022064306A1 WO 2022064306 A1 WO2022064306 A1 WO 2022064306A1 IB 2021058179 W IB2021058179 W IB 2021058179W WO 2022064306 A1 WO2022064306 A1 WO 2022064306A1
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Prior art keywords
insulator
conductor
oxide
oxygen
film
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
神保安弘
國武寛司
大嶋和晃
太田将志
古谷一馬
青木健
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to KR1020237009129A priority Critical patent/KR20230069933A/ko
Priority to DE112021005000.1T priority patent/DE112021005000T5/de
Priority to JP2022551438A priority patent/JPWO2022064306A1/ja
Priority to CN202180064527.9A priority patent/CN116171484A/zh
Priority to US18/245,757 priority patent/US12550332B2/en
Publication of WO2022064306A1 publication Critical patent/WO2022064306A1/ja
Anticipated expiration legal-status Critical
Priority to US19/428,503 priority patent/US20260113951A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H10D1/684—Capacitors having no potential barriers having dielectrics comprising perovskite structures the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/701—IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs

Definitions

  • One aspect of the present invention relates to a metal oxide, a ferroelectric device using the metal oxide, and a method for producing the same.
  • one aspect of the invention relates to transistors, semiconductor devices, and electronic devices.
  • one aspect of the present invention relates to a method for manufacturing a semiconductor device.
  • one aspect of the present invention relates to a semiconductor wafer and a module.
  • the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics.
  • a semiconductor circuit, an arithmetic unit, and a storage device, including a semiconductor element such as a transistor, are one aspect of a semiconductor device. It may be said that a display device (liquid crystal display device, light emission display device, etc.), projection device, lighting device, electro-optic device, power storage device, storage device, semiconductor circuit, image pickup device, electronic device, and the like have a semiconductor device.
  • One aspect of the present invention is not limited to the above technical fields.
  • One aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Also, one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter).
  • a CPU is an aggregate of semiconductor elements formed by processing a semiconductor wafer, having a chipped semiconductor integrated circuit (at least a transistor and a memory), and forming an electrode as a connection terminal.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, for example, printed wiring boards, and are used as one of various electronic device components.
  • transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also referred to simply as display devices).
  • ICs integrated circuits
  • image display devices also referred to simply as display devices.
  • Silicon-based semiconductor materials, oxide semiconductors, and the like are known as semiconductor thin films applicable to transistors.
  • Non-Patent Document 1 research and development of a memory array using a ferroelectric substance (ferroelectric) are being actively carried out. Further, for the next-generation ferroelectric memory, research on ferroelectric HfO 2 -based materials (Non-Patent Document 2), research on ferroelectricity of hafnium oxide thin films (Non-Patent Document 3), HfO 2 Hafnium oxide-related studies such as the ferroelectricity of thin films (Non-Patent Document 4) and the demonstration of integration between FeRAM and CMOS using the ferroelectric Hf 0.5 Zr 0.5 O 2 (Non-Patent Document 5). Is also actively carried out.
  • Non-Patent Documents 1 to 5 various researches and developments have been carried out on ferroelectrics.
  • Non-Patent Document 1 As shown in FIG. 8 (A), it is reported that the sign of polarization (P) changes depending on the movement of oxygen atoms at the time of "Orthorhombic phase Ferroelectric".
  • Non-Patent Document 2 As shown in FIG. 8 (B), it is reported that the magnitude of polarization and the dielectric constant ( ⁇ r ) change depending on the composition of Hf and Zr.
  • Non-Patent Document 3 As shown in FIG. 9 , it is reported that the rewrite resistance, which is one of the reliability tests of the ferroelectric substance, is about 109 times. Further, Non-Patent Document 4 reports on the diffraction intensity, polarization, and crystal structure of HfO 2 as shown in FIGS. 10 (A), 10 (B), and 10 (C).
  • one aspect of the present invention is to provide a material having good ferroelectricity, that is, a metal oxide film having ferroelectricity.
  • one aspect of the present invention is to provide a capacitive element using a material capable of having ferroelectricity.
  • one aspect of the present invention is to provide a transistor using a material capable of having ferroelectricity.
  • one aspect of the present invention is to provide a capacitive element and a diode using a material capable of having ferroelectricity.
  • one aspect of the present invention is to provide an element using a material capable of having ferroelectricity and using a tunnel junction.
  • One aspect of the present invention includes a first conductor, a metal oxide film on the first conductor, and a second conductor on the metal oxide film, and the metal oxide film is a metal oxide film. It has a strong dielectric property, the metal oxide film has a crystal structure, the crystal structure has a first layer and a second layer, and the first layer has a first oxygen. , Hafnium, and the second layer has a second oxygen and zirconium, hafnium, and zirconium are bonded to each other via the first oxygen, and the second oxygen is. A strong dielectric device that bonds to zirconium.
  • Another aspect of the present invention is a first conductor, a metal oxide film on the first conductor, a second conductor on the metal oxide film, and a seal on the second conductor.
  • the metal oxide film has a waterproof film
  • the metal oxide film has a strong dielectric property
  • the metal oxide film has a crystal structure
  • the crystal structure has a first layer and a second layer.
  • the first layer has a first oxygen and hafnium
  • the second layer has a second oxygen and zirconium
  • hafnium and zirconium are the first.
  • the second oxygen is a strong dielectric device that bonds to each other via oxygen and to zirconium.
  • the sealing film has a first sealing film and a second sealing film on the first sealing film, and the first sealing film includes oxygen, aluminum, and the like. It is preferable that the second sealing film has nitrogen and silicon, and the first sealing film has a function of adsorbing or capturing hydrogen.
  • Another aspect of the present invention comprises a transistor and a capacitive element electrically connected to the transistor, wherein the capacitive element is a first conductor and a metal oxide film on the first conductor.
  • the metal oxide film has a strong dielectric property
  • the metal oxide film has a crystal structure
  • the crystal structure is the first.
  • the first layer has a first oxygen and hafnium
  • the second layer has a second oxygen and zirconium.
  • hafnium and zirconium are semiconductor devices that are bonded to each other via the first oxygen, and the second oxygen is bonded to zirconium.
  • the transistor has silicon in the channel forming region.
  • the transistor has an oxide semiconductor in the channel forming region.
  • One aspect of the present invention includes a semiconductor film, a metal oxide film on the semiconductor film, and a second conductor on the metal oxide film, and the metal oxide film has strong dielectric properties.
  • the metal oxide film has a crystal structure, the crystal structure has a first layer and a second layer, and the first layer has a first oxygen and a hafnium.
  • the second layer has a second oxygen and zirconium, hafnium and zirconium are bonded to each other via the first oxygen, and the second oxygen is bonded to zirconium. It is a semiconductor device.
  • the semiconductor film has a silicon or an oxide semiconductor and has a source electrode and a drain electrode that are electrically connected to the semiconductor film.
  • another aspect of the present invention is the first conductor, the metal oxide film on the first conductor, the second conductor on the metal oxide film, and the first conductor. It has an insulator located on one or both of the upper surface and the lower surface of the second conductor, the metal oxide film has a strong dielectric property, and the metal oxide film has a crystal structure.
  • the crystal structure has a first layer and a second layer, the first layer has a first oxygen and a hafnium, and the second layer has a second layer.
  • a semiconductor device having oxygen and zirconium, hafnium and zirconium bonded to each other via a first oxygen and a second oxygen bonded to zirconium.
  • the insulator has nitrogen and silicon.
  • the concentration of at least one of hydrogen and carbon contained in the metal oxide film is preferably 5 ⁇ 10 20 atoms / cm 3 or less in the SIMS analysis. Further, in each of the above embodiments, the concentration of at least one of hydrogen and carbon contained in the metal oxide film is more preferably 1 ⁇ 10 20 atoms / cm 3 or less in the SIMS analysis. Further, in each of the above embodiments, the concentration of chlorine contained in the metal oxide film is preferably 5 ⁇ 10 21 atoms / cm 3 or less in the SIMS analysis. Further, in each of the above embodiments, the concentration of chlorine contained in the metal oxide film is more preferably 1 ⁇ 10 21 atoms / cm 3 or less in the SIMS analysis.
  • a material having good ferroelectricity that is, a metal oxide film having ferroelectricity.
  • a capacitive element using a material that may have ferroelectricity.
  • a transistor using a material that may have ferroelectricity.
  • a capacitive element and a diode using a material capable of having ferroelectricity.
  • an element using a material capable of having ferroelectricity and using a tunnel junction it is possible to provide
  • FIG. 1A1, FIG. 1B1, and FIG. 1C1 are circuit diagrams of a semiconductor device according to an aspect of the present invention.
  • 1A2, 1B2, 1C2, 1C3, and 1C4 are diagrams illustrating a cross-sectional structure of a semiconductor device according to an aspect of the present invention.
  • 2A and 2B are schematic views of a capacitive element according to an aspect of the present invention.
  • FIG. 2C is a schematic diagram of a ferroelectric substance contained in a capacitive element, which is one aspect of the present invention.
  • 3A to 3C are model diagrams of the crystal structure of HfZrOX , which is one aspect of the present invention.
  • FIG. 3D is a graph showing an example of the hysteresis characteristics of the ferroelectric layer.
  • FIG. 4A to 4C are schematic views of the ferroelectric substance contained in the capacitive element.
  • 5A to 5C are cross-sectional views showing a method of manufacturing a capacitive element according to one aspect of the present invention.
  • FIG. 6 is a model diagram illustrating the crystal structure of hafnium oxide according to one aspect of the present invention.
  • FIG. 7A is a diagram showing a film formation sequence of a metal oxide film according to one aspect of the present invention.
  • FIG. 7B is a cross-sectional view of the metal oxide film manufacturing apparatus according to one aspect of the present invention.
  • FIG. 7C is a diagram showing an oxide film formation sequence.
  • FIG. 8A is a diagram illustrating the polarization of the ferroelectric substance disclosed in Non-Patent Document 1, and FIG.
  • FIG. 8B is a diagram showing the polarization due to the composition of Hf and Zr disclosed in Non-Patent Document 2. It is a figure explaining the change of the size and the dielectric constant.
  • FIG. 9 is a diagram illustrating the rewrite resistance of the ferroelectric substance disclosed in Non-Patent Document 3.
  • 10A to 10C are diagrams illustrating the diffraction intensity, polarization, and crystal structure of HfO 2 disclosed in Non-Patent Document 4.
  • FIG. 11A is a top view of a semiconductor device according to an aspect of the present invention.
  • 11B to 11D are cross-sectional views of a semiconductor device according to an aspect of the present invention.
  • 12A and 12B are cross-sectional views of a semiconductor device according to an aspect of the present invention.
  • FIG. 13A is a diagram illustrating the classification of the crystal structure of IGZO.
  • FIG. 13B is a diagram illustrating an XRD spectrum of a CAAC-IGZO film.
  • FIG. 13C is a diagram illustrating a microelectron diffraction pattern of a CAAC-IGZO film.
  • FIG. 14A is a top view of a semiconductor device according to an aspect of the present invention.
  • FIG. 14B is a cross-sectional view of a semiconductor device according to an aspect of the present invention.
  • FIG. 15A is a top view of a semiconductor device according to an aspect of the present invention.
  • FIG. 15B is a cross-sectional view of a semiconductor device according to an aspect of the present invention.
  • FIG. 16A is a top view of a semiconductor device according to an aspect of the present invention.
  • FIG. 16B is a cross-sectional view of a semiconductor device according to an aspect of the present invention.
  • FIG. 17A is a plan view of the semiconductor device according to one aspect of the present invention.
  • 17B and 17C are cross-sectional views of a semiconductor device according to an aspect of the present invention.
  • FIG. 18 is a cross-sectional view showing the configuration of a storage device according to an aspect of the present invention.
  • FIG. 19 is a cross-sectional view showing the configuration of a storage device according to an aspect of the present invention.
  • 20A and 20B are sectional views showing a configuration of a storage device according to an aspect of the present invention.
  • 21A to 21C are sectional views showing a configuration of a storage device according to an aspect of the present invention.
  • 22A to 22C are cross-sectional views showing the configuration of the storage device according to one aspect of the present invention.
  • 23A to 23D are cross-sectional views showing a method of manufacturing a storage device according to one aspect of the present invention.
  • FIG. 24 is a cross-sectional view showing the configuration of the storage device according to one aspect of the present invention.
  • FIG. 25 is a cross-sectional view showing the configuration of the storage device according to one aspect of the present invention.
  • 26A and 26B are cross-sectional views showing the configuration of a storage device according to an aspect of the present invention.
  • 27A to 27C are cross-sectional views of a semiconductor device according to an aspect of the present invention.
  • FIG. 28A is a block diagram showing a configuration example of a storage device according to an aspect of the present invention.
  • FIG. 28B is a perspective view showing a configuration example of a storage device according to an aspect of the present invention.
  • FIG. 29A is a circuit diagram showing a configuration example of a memory cell.
  • FIG. 29B1 is a graph showing an example of the hysteresis characteristics of the ferroelectric layer.
  • FIG. 29B2 is a graph showing an example of the hysteresis characteristics of an ideal ferroelectric layer.
  • FIG. 29C is a timing chart showing an example of a memory cell driving method.
  • 30A to 30E are schematic views of a storage device according to an aspect of the present invention.
  • FIG. 32A is an optical micrograph showing the appearance of the sample.
  • FIG. 32B is a schematic cross-sectional view of the sample.
  • FIG. 32C is a diagram showing an input voltage waveform.
  • 33A to 33F are diagrams illustrating a method of acquiring PE characteristics using a triangular wave.
  • FIG. 34A is a diagram showing the measurement results of the PE characteristics.
  • FIG. 34B is a diagram showing a GIXD measurement result.
  • 35A is a cross-sectional TEM image of the sample, and FIGS. 35B and 35C are FFT diagrams of the sample.
  • 36A is a cross-sectional TEM image of the sample, and FIGS.
  • FIGS. 37B and 37C are FFT diagrams of the sample.
  • 37A is a cross-sectional TEM image of the sample
  • FIGS. 37B and 37C are FFT diagrams of the sample.
  • 38A to 38C are cross-sectional TEM images of the sample.
  • FIG. 39 is a diagram showing the analysis results of the line EDX analysis.
  • FIG. 40A is a diagram showing a measurement result of Ra
  • FIG. 40B is a diagram showing a measurement result of RMS.
  • FIG. 41 is a diagram showing the results of SIMS analysis.
  • FIG. 42 is a diagram showing the results of SIMS analysis.
  • FIG. 43 is a diagram showing the results of SIMS analysis.
  • FIG. 44 is a diagram showing the results of SIMS analysis.
  • FIG. 45A and 45B are diagrams showing the measurement results of fatigue characteristics.
  • FIG. 46A is a diagram showing PE characteristics.
  • FIG. 46B is a diagram showing the measurement results of fatigue characteristics.
  • FIG. 47 is a diagram showing PE characteristics.
  • FIG. 48 is a diagram showing IV characteristics.
  • FIG. 49 is a diagram showing XRD measurement results.
  • FIG. 50 is a diagram showing PE characteristics.
  • FIG. 51 is a diagram showing IV characteristics.
  • FIG. 52 is a diagram showing an XRD measurement result.
  • FIG. 53 is a diagram showing fatigue characteristics.
  • FIG. 54 is a diagram showing PE characteristics.
  • 55A and 55B are diagrams showing PE characteristics.
  • 55C and 55D are diagrams showing the relationship between the polarization and the frequency of the triangular wave.
  • FIG. 56A is a diagram showing a calculation model.
  • FIG. 56B is a diagram showing a calculation model after calculation.
  • 57A and 57B are diagrams illustrating retention measurement.
  • 58A to 58C are diagrams showing the retention measurement results.
  • FIG. 59A is a diagram showing the PV characteristic
  • FIG. 59B is a diagram showing the IV characteristic.
  • 60A and 60B are diagrams showing the electrical characteristics of the transistor.
  • FIG. 61A is an example of an equivalent circuit diagram
  • FIG. 61B is a top view showing an example of a layout.
  • 62A is a diagram showing a timing chart
  • FIG. 62B1 is a circuit diagram showing a write operation (Write)
  • FIG. 62B2 is a diagram showing a hysteresis characteristic for explaining the write operation
  • FIG. 62C1 is a read operation.
  • (Read) is a circuit diagram
  • FIG. 62C2 is a diagram showing a hysteresis characteristic for explaining a read operation.
  • FIG. 63A is a diagram showing the measurement results obtained by repeating the writing operation and the reading operation 40 times
  • FIG. 63B is a comparative example.
  • 64A, 64B, 64C and 64D are diagrams showing a method for measuring the f characteristic.
  • FIG. 65 is a diagram showing the measurement results of the f characteristic.
  • 66A, 66B, 66C and 66D are views showing a method of retention measurement.
  • FIG. 67 is a diagram showing the results of retention measurement.
  • the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.
  • the drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, and the like may be unintentionally reduced due to processing such as etching, but they may not be reflected in the figure for ease of understanding.
  • the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions, and the repeated description thereof may be omitted.
  • the hatch pattern may be the same and no particular reference numeral may be added.
  • a top view also referred to as a "plan view”
  • a perspective view etc.
  • the description of some components may be omitted.
  • some hidden lines may be omitted.
  • the ordinal numbers attached as the first, second, etc. are used for convenience, and do not indicate the process order or the stacking order. Therefore, for example, the "first” can be appropriately replaced with the “second” or “third” for explanation.
  • the ordinal numbers described in the present specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.
  • X and Y are connected, the case where X and Y are electrically connected and the case where X and Y function. It is assumed that the case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification and the like. Therefore, it is not limited to the predetermined connection relationship, for example, the connection relationship shown in the figure or text, and the connection relationship other than the connection relationship shown in the figure or text is also disclosed in the figure or text.
  • X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • a transistor is an element having at least three terminals including a gate, a drain, and a source. Further, it has a region (hereinafter, also referred to as a channel forming region) in which a channel is formed between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode). A current can flow between the source and the drain through the channel formation region.
  • the channel forming region means a region in which a current mainly flows.
  • the function of the source or drain may be switched when a transistor with a different polarity is adopted, or when the direction of the current changes in the circuit operation. Therefore, in the present specification and the like, the terms source and drain may be used interchangeably.
  • the channel length is, for example, a source in a region where a semiconductor (or a portion where a current flows in a semiconductor when the transistor is on) and a gate electrode overlap each other in a top view of a transistor, or a channel formation region.
  • the channel length does not always take the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in the present specification, the channel length is any one value, the maximum value, the minimum value, or the average value in the channel formation region.
  • the channel width is, for example, the channel length direction in the region where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap each other in the top view of the transistor, or in the channel formation region. Refers to the length of the channel formation region in the vertical direction with respect to. In one transistor, the channel width does not always take the same value in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in the present specification, the channel width is any one value, the maximum value, the minimum value, or the average value in the channel formation region.
  • the channel width in the region where the channel is actually formed (hereinafter, also referred to as “effective channel width”) and the channel width shown in the top view of the transistor. (Hereinafter, also referred to as “apparent channel width”) and may be different.
  • the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible.
  • the ratio of the channel forming region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.
  • channel width may refer to an apparent channel width.
  • channel width may refer to an effective channel width.
  • the channel length, channel width, effective channel width, apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.
  • the semiconductor impurities are, for example, other than the main components constituting the semiconductor.
  • an element having a concentration of less than 0.1 atomic% can be said to be an impurity.
  • the inclusion of impurities may result in, for example, an increase in the defect level density of the semiconductor, a decrease in crystallinity, and the like.
  • the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and oxide semiconductors.
  • transition metals other than the main component such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water may also function as an impurity.
  • oxygen deficiency VO: oxygen vacancy
  • silicon oxide nitriding has a higher oxygen content than nitrogen as its composition. Further, silicon nitride oxide has a higher nitrogen content than oxygen in its composition.
  • the term “insulator” can be paraphrased as an insulating film or an insulating layer.
  • the term “conductor” can be paraphrased as a conductive film or a conductive layer.
  • the term “semiconductor” can be paraphrased as a semiconductor film or a semiconductor layer.
  • parallel means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included.
  • approximately parallel means a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • vertical means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included.
  • approximately vertical means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used for the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when it is described as an OS transistor, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.
  • normally off means that when a potential is not applied to the gate or a ground potential is applied to the gate, the drain current per 1 ⁇ m of the channel width flowing through the transistor is 1 ⁇ 10 ⁇ at room temperature. It means that it is 20 A or less, 1 ⁇ 10 -18 A or less at 85 ° C, or 1 ⁇ 10 -16 A or less at 125 ° C.
  • FIG. 1A1, FIG. 1B1, and FIG. 1C1 are circuit diagrams of a semiconductor device according to one aspect of the present invention, respectively.
  • the circuit diagram shown in FIG. 1A1 has one transistor (also referred to as a field effect transistor or FET) and one capacitive element, one capacitive element containing a material capable of having ferroelectricity.
  • the circuit diagram shown in FIG. 1B1 has one transistor and includes a material capable of having ferroelectricity in the gate insulating film of the transistor.
  • the circuit diagram shown in FIG. 1C1 includes one capacitive element, a diode, and the capacitive element includes a material capable of having ferroelectricity.
  • FIG. 1A1 has one transistor (also referred to as a field effect transistor or FET) and one capacitive element, one capacitive element containing a material capable of having ferroelectricity.
  • the circuit diagram shown in FIG. 1B1 has one transistor and includes a material capable of having ferroelectricity in the gate insul
  • one capacitive element and one diode are described separately, but the present invention is not limited to this.
  • one element has both the functions of one capacitive element and one diode, it is not necessary to separate the respective functions.
  • an element configuration in which an insulator is provided between a pair of electrodes and a tunnel junction is used between the insulator and the electrodes can be used. ..
  • the circuit diagram shown in FIG. 1A1 can be regarded as an element configuration of 1Tr1C (1 transistor, 1 capacitor), and may be referred to as FeRAM (Ferroelectric Random Access Memory) or Type 1 structure.
  • the circuit diagram shown in FIG. 1B1 can be regarded as an element configuration of 1Tr (1 transistor), and may be referred to as a FeFET (Ferroelectric Field Effect Transistor) or a Type 2 structure.
  • the circuit diagram shown in FIG. 1C1 can be regarded as an element configuration of one capacitor using a tunnel junction, and may be referred to as an FTJ (Feroelectric Tunnel Junction) or a Type 3 structure.
  • FIG. 1A2, FIG. 1B2, FIG. 1C2, FIG. 1C3, and FIG. 1C4 show an example of a semiconductor device of one aspect of the present invention applicable to the configuration shown in the circuit diagram shown in FIGS. It will be explained using. 1A2, 1B2, 1C2, 1C3, and 1C4 are cross-sectional views showing an example of a semiconductor device according to an aspect of the present invention, respectively.
  • white circles represent terminals.
  • FIG. 1A2 is a cross-sectional view corresponding to the capacitive element shown in FIG. 1A1
  • FIG. 1B2 is a cross-sectional view corresponding to a transistor including a material capable of having strong dielectric property shown in FIG. 1B1
  • FIG. 1C4 are cross-sectional views corresponding to the capacitive element and the diode shown in FIG. 1C1, respectively.
  • FIG. 1A2 has a conductor 110, an insulator 130 on the conductor 110, and a conductor 120 on the insulator 130.
  • the insulator 130 preferably uses a material that can have ferroelectricity.
  • the insulator 130 may be read as a dielectric or a ferroelectric substance.
  • the conductor 120 may be configured to be connected to the source or drain of the transistor.
  • FIG. 1B2 has an oxide 230, an insulator 130 on the oxide 230, and a conductor 120 on the insulator 130.
  • the insulator 130 preferably uses a material that can have ferroelectricity. Further, in FIG. 1B2, it can be said that the oxide 230 and the insulator 130, that is, a material having a ferroelectricity, are in contact with each other.
  • FIG. 1C2 has a conductor 110, an insulator 115a on the conductor 110, an insulator 130 on the insulator 115a, and a conductor 120 on the insulator 130. It can be said that FIG. 1C2 has a structure having an insulator 115a between the conductor 110 of FIG. 1A2 and the insulator 130. Further, FIG. 1C3 has a conductor 110, an insulator 130 on the conductor 110, an insulator 115b on the insulator 130, and a conductor 120 on the insulator 115b.
  • FIG. 1C4 shows the conductor 110, the insulator 115a on the conductor 110, the insulator 130 on the insulator 115a, the insulator 115b on the insulator 130, and the conductor 120 on the insulator 115b.
  • PE Polyization density-Electric field
  • the first section is 0 (V) to 3 (V)
  • the second section is 3 (V) to 0 (V)
  • the third section is -Va (V) to Va.
  • Va is preferably a voltage equal to or lower than the coercive electric field (Ec) in this circuit diagram.
  • the insulator 115a and the insulator 115b may have different configurations in at least one of the film type, the film quality, and the film thickness.
  • the conductor 110 has a function as a lower electrode. Further, the conductor 110 includes a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, and an atomic layer.
  • a film can be formed by using a (ALD: Atomic Layer Deposition) method or the like. Examples of the ALD method include a thermal ALD (Thermal ALD) method in which the reaction of the precursor and the reactor is performed only by thermal energy, and a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactor.
  • the conductor 110 By forming the conductor 110 by using the ALD method, it may be possible to relatively easily form a conductive film having good flatness.
  • titanium nitride may be formed by using the thermal ALD method.
  • the conductor 110 may be appropriately patterned by using a lithography method or the like.
  • the surface on which the conductor 110 is formed also referred to as the formed surface
  • the upper surface of the conductor 110 has high flatness.
  • the surface on which the conductor 110 is formed or the upper surface of the conductor 110 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.
  • CMP chemical mechanical polishing
  • the crystallinity of the insulator 130 can be enhanced above the surface or, more specifically, the crystallinity of the insulator 130.
  • Insulator 130 It is preferable to use a material capable of having ferroelectricity for the insulator 130. Details of the insulator 130 will be described later.
  • the conductor 120 has a function as an upper electrode.
  • the conductor 120 is disposed apart from the conductor 110 via the insulator 130. Details of the conductor 120 will be described later.
  • the insulator 115a and the insulator 115b may be of normal dielectric materials, respectively, and for example, silicon oxide, silicon nitride, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, and the like may be used. Can be done. In particular, as the insulators 115a and 115b, silicon nitride films are preferable. Further, the insulator 115a and the insulator 115b can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, respectively.
  • the insulator 115a and the insulator 115b it is preferable to form a film by using the PEALD method.
  • a precursor containing halogens such as fluorine, chlorine, bromine and iodine.
  • plasma treatment is performed in an atmosphere in which a nitride such as N 2 , N 2 O, NH 3 , NO, NO 2 , and N 2 O 2 is introduced to obtain a high-quality silicon nitride film. Can be formed.
  • a material capable of having ferroelectricity that is, a metal oxide film having ferroelectricity.
  • a ferroelectric device using a material that may have ferroelectricity.
  • a capacitive element using a material that may have ferroelectricity.
  • a transistor using a material that may have ferroelectricity.
  • a capacitive element and a diode using a material capable of having ferroelectricity.
  • the metal oxide film of one aspect of the present invention can be used for one or more semiconductor devices of a capacitive element, a transistor, and a diode.
  • FIGS. 1A1 and 1A2 are exemplified, but the configurations shown in FIGS. 1B1 and 1B2, and FIGS. 1C1, 1C2, 1C3, and 1C4 are also one of them. It can be applied by changing the composition of the part (for example, oxide 230, insulator 115a, insulator 115b, etc.).
  • the capacitive element 100 has a conductor 110, a conductor 120, and an insulator 130 sandwiched between the conductor 110 and the conductor 120.
  • the conductor 110 may be arranged on a substrate (not shown), the insulator 130 may be arranged on the conductor 110, and the conductor 120 may be arranged on the insulator 130.
  • the conductor 110 functions as a lower electrode of the capacitive element 100
  • the conductor 120 functions as an upper electrode of the capacitive element 100
  • the insulator 130 functions as a dielectric of the capacitive element 100.
  • the insulator 130 It is preferable to use a material capable of having ferroelectricity for the insulator 130.
  • the material capable of having ferroelectricity include hafnium oxide, zirconium oxide, HfZrOX ( X is a real number larger than 0) and the like.
  • the element J1 is added to hafnium oxide (the element J1 here is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y)). , One or more selected from lanthanum (La), strontium (Sr) and the like).
  • the ratio of the number of atoms of the hafnium atom and the element J1 can be appropriately set, and for example, the number of atoms of the hafnium atom and the element J1 may be 1: 1 or in the vicinity thereof.
  • zirconium oxide is added to the element J2 (the element J2 here is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y)). , One or more selected from lanthanum (La), strontium (Sr) and the like, and the like.
  • the ratio of the number of atoms of the zirconium atom to the element J2 can be appropriately set, and for example, the number of atoms of the zirconium atom to the element J2 may be 1: 1 or close to it.
  • materials capable of having strong dielectric property PbTIO X , barium titanate strontium (BST), barium titanate, lead zirconate titanate (PZT), strontium bismuthate tantanate (SBT), bismuth ferrite (BFO). , Barium titanate, and the like, and a piezoelectric ceramic having a perovskite structure may be used.
  • the material capable of having ferroelectricity for example, a mixture or compound composed of a plurality of materials selected from the materials listed above can be used.
  • the insulator 130 may have a laminated structure composed of a plurality of materials selected from the materials listed above.
  • the crystal structure (characteristics) of hafnium oxide, zirconium oxide, HfZrOX , and materials obtained by adding the element J1 to hafnium oxide may change not only depending on the film forming conditions but also depending on various processes.
  • a material exhibiting ferroelectricity is not only referred to as a ferroelectric substance, but also as a material capable of having ferroelectricity.
  • hafnium oxide, or a material having hafnium oxide and zirconium oxide as a material capable of having ferroelectricity is preferable because it can have ferroelectricity even when processed into a thin film of several nm.
  • the capacitive element 100 can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device.
  • a layered material capable of having ferroelectricity may be referred to as a ferroelectric layer or a metal oxide film.
  • such a device having a ferroelectric layer (metal oxide film) may be referred to as a ferroelectric device in the present specification and the like.
  • the insulator 130 preferably has a film-like shape.
  • the x-axis and the y-axis are parallel to the film surface of the insulator 130, and the z-axis is parallel to the film thickness direction of the insulator 130.
  • the insulator 130 preferably has a film-like shape, the width w x in the x direction and the width wy in the y direction of the insulator 130 are preferably larger than the film thickness t, which is three times the film thickness t. The above is more preferable.
  • the film thickness t of the insulator 130 when the film thickness t of the insulator 130 is 3 nm, at least one of the width w x and the width wy of the insulator 130 is preferably 3 nm or more, and more preferably 10 nm or more.
  • the film thickness t of the insulator 130 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, still more preferably 10 nm or less (typically 2 nm or more and 9 nm or less).
  • the film thickness t is preferably 8 nm or more and 12 nm or less.
  • the insulator 130 shown in FIG. 2C has a shape in which the upper surface and the lower surface are parallel over the entire surface, but the present invention is not limited to this.
  • the insulator 130 may have irregularities reflecting the shape of the surface to be formed. In this case, if a groove is formed on the surface to be formed, the region of the insulator 130 overlapping the groove may have a concave shape.
  • a non-volatile storage element can be formed by using a capacitive element (hereinafter, may be referred to as a ferroelectric capacitor) using the material as a dielectric.
  • a non-volatile storage element using a ferroelectric capacitor may be referred to as a FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, or the like.
  • a ferroelectric memory may have a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor may be electrically connected to one terminal of the ferroelectric capacitor. Therefore, the capacitive element 100 shown in the present embodiment and the semiconductor device using the transistor can function as a ferroelectric memory.
  • FIG. 6 is a model diagram illustrating the crystal structure of hafnium oxide (HfO 2 in this embodiment).
  • Hafnium oxide is known to have various crystal structures.
  • the cubic system (cubic, space group: Fm-3m) and the tetragonal system (tetragonal, space group: P4 2 / nmc) shown in FIG. 6 are known to have various crystal structures.
  • monoclinic, space group: P2 1 / c As shown in FIG.
  • each of the above-mentioned crystal structures can undergo a phase change.
  • the crystal structure of hafnium oxide mainly composed of monoclinic crystals can be changed to the crystal structure mainly composed of orthorhombic crystals.
  • the composite material when hafnium oxide and zirconium oxide are alternately formed so as to have a composition of about 1: 1 by using the ALD method or the like, the composite material has an orthorhombic crystal structure.
  • the composite material has an amorphous structure. Then, by applying heat treatment or the like to the composite material, the amorphous structure can be made into an orthorhombic crystal structure.
  • the crystal structure of the orthorhombic system may change to the crystal structure of the monoclinic system.
  • an orthorhombic crystal structure is preferable to a monoclinic crystal structure.
  • FIG. 3A is a model diagram of the crystal structure of HfZrOx, here Hf 0.5 Zr 0.5 O 2 . Further, in FIG. 3A, the directions of the a-axis, the b-axis, and the c-axis are also shown.
  • FIG. 3A is a structure in which Zr is arranged in layers with respect to the optimized structure including the cell by the first-principles calculation regarding the orthorhombic structure (Pca2 1 ) of HfO 2 .
  • hafnium and zirconium are in a state of being bonded to each other via oxygen. This can be formed by alternately forming hafnium and zirconium by the ALD method, as in the film formation sequence described later.
  • a part of oxygen shown in FIG. 3A is displaced, and polarization occurs inside.
  • a part of oxygen is displaced in the c-axis direction, and polarization also occurs in the c-axis direction.
  • 3B and 3C are model diagrams of the crystal structure of HfZrOx, here Hf 0.5 Zr 0.5 O 2 .
  • 3B and 3C are models in which the arrangement of atoms is optimized by first-principles calculation.
  • the model shown in FIG. 3A and the model shown in FIG. 3B differ only in the method of displaying atoms, and the arrangement of atoms is almost the same.
  • HfZrOx can take either the atomic arrangement shown in FIG. 3B and the atomic arrangement shown in FIG. 3C in the orthorhombic structure. Therefore, a part of the oxygen atom in HfZrOx is displaced by the electric field applied from the outside, so that the inside is polarized. Further, by changing the direction or strength of the electric field, a part of the oxygen atom in HfZrOx moves, and the sign of the polarization generated inside is changed.
  • FIG. 3D is a graph showing an example of the hysteresis characteristics of the ferroelectric layer.
  • the horizontal axis represents the electric field strength applied to the ferroelectric layer
  • the vertical axis represents the amount of polarization of the ferroelectric layer.
  • the point 61 shown in FIG. 3D is the minimum polarization when the electric field strength is 0, and the point 62 shown in FIG. 3D is the maximum polarization when the electric field strength is 0.
  • the atoms in HfZrOx are arranged as shown in FIG. 3B.
  • the maximum polarization point 62 shown in FIG. 3D
  • the atoms in HfZrOx are arranged as shown in FIG. 3C.
  • the insulator 130 As shown in FIG. 2A, a crystal structure in which crystals form a layer and the layers are laminated is preferable. Further, the layer preferably contains a single crystal structure as shown in FIG. 3A.
  • the broken line of the insulator 130 shown in FIG. 2A indicates the layer of the crystal, and the c-axis 132 indicates the c-axis of the crystal.
  • the crystal layer contained in the insulator 130 extends in the ab plane direction. Further, the crystal layer contained in the insulator 130 grows in the c-axis direction (sometimes called axial growth), and a plurality of crystal layers are laminated in the c-axis direction. It is preferable that the c-axis is oriented substantially perpendicular to the surface to be formed or the upper surface of the insulator 130.
  • the angle ⁇ formed by the normal 134 and the c-axis 132 with respect to the upper surface of the conductor 110 is preferably 30 ° or less, and more preferably 5 ° or less.
  • FIG. 2A shows a state in which an electric field E is applied between the lower electrode (conductor 110) and the upper electrode (conductor 120) of the capacitive element 100.
  • the direction of the electric field E is preferably substantially parallel to the c-axis 132.
  • the angle ⁇ formed by the direction of the electric field E and the c-axis 132 is 30 ° or less, more preferably 5 ° or less, which is preferable.
  • the c-axis 132 of the insulator 130 and the direction E of the electric field are substantially parallel to each other, so that the displacement direction of oxygen in the orthorhombic crystal and the direction E of the electric field are substantially parallel. Therefore, the electric field E can efficiently cause the insulator 130 to be polarized. This makes it possible to increase the polarization of the insulator 130.
  • the flatness of the upper surface of the conductor 110 is good.
  • the roughness of the upper surface of the substrate conductor 110 is an arithmetic mean roughness (Ra) or a root mean square roughness (RMS: Root Mean Square) of 2 nm or less, preferably 1 nm or less, more preferably 0. It may be 8 nm or less, more preferably 0.5 nm or less, still more preferably 0.4 nm or less.
  • a different layer is not formed at the interface between the insulator 130 and the conductor 110 or the interface between the insulator 130 and the conductor 120. ..
  • TiNx is used for the conductor 110 (conductor 120) and HfZrOx is used for the insulator 130
  • oxygen contained in the insulator 130 or the like diffuses into the conductor 110 (conductor 120), and the insulator 130 and the conductor are conductive.
  • TiOx may be formed as a different layer at the interface of the body 110 (conductor 120).
  • the film thickness of such a different layer is preferably 1 nm or less, more preferably 0.4 nm or less, and even more preferably 0.2 nm or less.
  • FIGS. 4A to 4C show enlarged views of the vicinity of the insulator 130 functioning as the ferroelectric layer, which is shown in FIGS. 2A and the like.
  • FIG. 4A is a diagram showing an insulator 130 having a single crystal structure described with reference to FIGS. 2A to 2C.
  • the insulator 130 shown in FIG. 4A has a structure in which a plurality of crystal layers are laminated. Further, it is preferable that the layers of the plurality of crystals contained in the insulator 130 are oriented along the c-axis 132.
  • the insulator 130 may have a polycrystalline structure having a plurality of grains 136 having different crystallinity.
  • the insulator 130 may have a polycrystalline structure having a plurality of grains 136 having different crystallinity.
  • the insulator 130 may have a structure having a layer 138a having a single crystal structure and a layer 138b having a polycrystal structure.
  • a layer 138a having a plurality of single crystal structures and a plurality of polycrystalline layers 138b may be laminated on the conductor 110.
  • the crystal structure of the insulator 130 may have at least a part having a single crystal structure.
  • the crystal structure of the insulator 130 may be one or more selected from a cubic system, a tetragonal system, an orthorhombic system, and a monoclinic system. In particular, it is preferable that the insulator 130 has an orthorhombic crystal structure because it exhibits ferroelectricity.
  • the crystal structure of the insulator 130 may be an amorphous structure.
  • the insulator 130 may have a composite structure having an amorphous structure and a crystal structure.
  • impurities such as hydrogen, carbon, hydrocarbon, and chlorine in the insulator 130 are reduced.
  • the inclusion of these impurities in the insulator 130 may inhibit the crystallization of the insulator 130.
  • these impurities may form oxygen deficiencies in the crystals in the insulator 130.
  • ferroelectricity is exhibited by displacement of oxygen by an external electric field. Therefore, in order to improve the ferroelectricity of the insulator 130, it is preferable to reduce impurities such as hydrogen, carbon, hydrocarbons, and chlorine to reduce oxygen deficiency.
  • the concentration of hydrogen contained in the insulator 130 is preferably 5 ⁇ 10 20 atoms / cm 3 or less, and more preferably 1 ⁇ 10 20 atoms / cm 3 or less.
  • the concentration of the hydrocarbon contained in the insulator 130 is preferably 5 ⁇ 10 20 atoms / cm 3 or less, more preferably 1 ⁇ 10 20 atoms / cm 3 or less, and 5 ⁇ 10 19 atoms / cm 3 or less. Is even more preferable.
  • the concentration of carbon contained in the insulator 130 is preferably 5 ⁇ 10 20 atoms / cm 3 or less, more preferably 1 ⁇ 10 20 atoms / cm 3 or less, and 5 ⁇ 10 19 atoms / cm 3 or less. More preferred. Further, for example, the concentration of chlorine contained in the insulator 130 is preferably 5 ⁇ 10 21 atoms / cm 3 or less, more preferably 1 ⁇ 10 21 atoms / cm 3 or less, and 5 ⁇ 10 20 atoms / cm 3 or less. More preferred.
  • SIMS Secondary Ion Mass Spectrometry
  • XPS X-ray Photoelectron Spectroscopy
  • AES Auger Electrospectry
  • the conductor 110 includes aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, and strontium. It is preferable to use a metal element selected from a lantern or the like, an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used.
  • tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferable.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
  • a plurality of conductive layers formed of the above materials may be laminated and used.
  • a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined.
  • a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined.
  • a laminated structure may be formed in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.
  • a conductive material that can be used for the conductor 110 may be used.
  • the conductor 110 is formed on a substrate (not shown).
  • the film formation of the conductor 110 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • ALD method By forming the conductor 110 by using the ALD method, it may be possible to relatively easily form a conductive film having good flatness.
  • titanium nitride may be formed by using the thermal ALD method.
  • the conductor 110 may be appropriately patterned by using a lithography method or the like.
  • the insulator 130 is formed on the conductor 110.
  • the film formation of the insulator 130 can be performed by using a sputtering method, a CVD method, an ALD method, or the like.
  • the insulator 130 can be formed on the conductor 110 with good coverage. As a result, it is possible to suppress the generation of a leak current between the upper electrode and the lower electrode of the capacitive element 100.
  • the insulator 130 It is preferable to use a material capable of having ferroelectricity for the insulator 130.
  • the material capable of having ferroelectricity the above-mentioned material can be used.
  • the film thickness of the insulator 130 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, still more preferably 10 nm or less (typically 2 nm or more and 9 nm or less).
  • the insulator 130 When a material having hafnium oxide and zirconium oxide (HfZrO x ) is used as the insulator 130, it is preferable to form a film by using the thermal ALD method.
  • HfZrO x hafnium oxide and zirconium oxide
  • the insulator 130 when the insulator 130 is formed into a film by using the thermal ALD method, it is preferable to use a material containing no hydrocarbon (hydrocarbon, also referred to as HC) as a precursor. If the insulator 130 contains one or both of hydrogen and carbon, it may inhibit the crystallization of the insulator 130. Therefore, as described above, it is preferable to reduce the concentration of either one or both of hydrogen and carbon in the insulator 130 by using a precursor containing no hydrocarbon. For example, as a precursor containing no hydrocarbon, a chlorine-based material can be mentioned. When a material having hafnium oxide and zirconium oxide (HfZrO x ) is used as the insulator 130, HfCl 4 and ZrCl 4 may be used as the precursor.
  • HfZrO x hafnium oxide and zirconium oxide
  • the oxidizing agent of the thermal ALD method it is preferable to use O3 rather than H2O because the hydrogen concentration in the membrane can be reduced.
  • the oxidizing agent of the thermal ALD method is not limited to this.
  • the oxidizing agent in the thermal ALD method may contain one or more selected from O 2 , O 3 , N 2 O, NO 2 , H 2 O, and H 2 O 2 .
  • the conductor 120 is formed on the insulator 130.
  • the conductor 120 is arranged apart from the conductor 110 via the insulator 130.
  • the conductor 120 may have a laminated structure of a conductor 120a provided in contact with the insulator 130 and a conductor 120b provided in contact with the conductor 120a.
  • the conductor 120a may be formed into a film by using an ALD method, a CVD method, or the like.
  • titanium nitride may be formed by using the thermal ALD method.
  • the film formation of the conductor 120a is preferably a method of forming a film while heating the substrate, such as the thermal ALD method.
  • the film may be formed by setting the substrate temperature to room temperature or higher, preferably 300 ° C. or higher, more preferably 325 ° C. or higher, and further preferably 350 ° C. or higher.
  • the film may be formed by setting the substrate temperature to 500 ° C. or lower, preferably 450 ° C. or lower.
  • the substrate temperature may be set to about 400 ° C.
  • insulation is performed without performing high-temperature baking treatment (for example, heat treatment temperature of 400 ° C. or higher or 500 ° C. or higher) after the formation of the conductor 120a.
  • Ferroelectricity can be imparted to the body 130.
  • the conductor 120a by using the ALD method, which causes relatively little damage to the substrate as described above, it is possible to prevent the crystal structure of the insulator 130 from being excessively destroyed.
  • the ferroelectricity of the insulator 130 can be increased.
  • the conductor 120a when the conductor 120a is formed by a sputtering method or the like, damage may enter the base film, here, the insulator 130.
  • a material having hafnium oxide and zirconium oxide (HfZrO x ) is used as the insulator 130 and the conductor 120a is formed by a sputtering method, the underlying film HfZrO x is damaged by the sputtering method, and crystals of HfZrO x are formed.
  • the structure typically a crystal structure such as an orthorhombic system
  • the dangling bond (for example, O * ) in HfZrO x and the hydrogen contained in HfZrO x may be bonded to each other, and the damage in the crystal structure of HfZrO x may not be recovered.
  • the dangling bond in HfZrO x is formed, for example, by the damage obtained by forming the conductor 120a into a film by a sputtering method.
  • the insulator 130 here HfZrO x , it is preferable to use a material that does not contain hydrogen or has an extremely low hydrogen content.
  • the concentration of hydrogen contained in the insulator 130 is preferably 5 ⁇ 10 20 atoms / cm 3 or less, and more preferably 1 ⁇ 10 20 atoms / cm 3 or less.
  • the insulator 130 may become a film that does not contain hydrocarbons as a main component or has an extremely low content of hydrocarbons.
  • the concentration of the hydrocarbon contained in the insulator 130 is preferably 5 ⁇ 10 20 atoms / cm 3 or less, more preferably 1 ⁇ 10 20 atoms / cm 3 or less, and further preferably 5 ⁇ 10 19 atoms / cm 3 . It becomes as follows.
  • the insulator 130 may be a film containing no carbon as a main component or having an extremely low carbon content.
  • the concentration of carbon contained in the insulator 130 is preferably 5 ⁇ 10 20 atoms / cm 3 or less, more preferably 1 ⁇ 10 20 atoms / cm 3 , and even more preferably 5 ⁇ 10 19 atoms / cm 3 or less.
  • the insulator 130 it is preferable to use a material having an extremely low content of at least one of hydrogen, hydrocarbon, and carbon, but in particular, the content of hydrocarbon and carbon should be extremely reduced. is important. Hydrocarbons and carbon are heavier molecules or atoms than hydrogen and are difficult to remove in later steps. Therefore, it is preferable to thoroughly eliminate hydrocarbons and carbon when forming the insulator 130.
  • the insulator 130 is insulated by using a material that does not contain at least one or more of hydrogen, hydrocarbon, and carbon, or has an extremely low content of at least one or more of hydrogen, hydrocarbon, and carbon. It is possible to improve the crystallinity of the body 130, and it is possible to form a structure having high strong dielectric properties.
  • the chlorine content in the insulator 130 is also reduced.
  • the concentration of chlorine contained in the insulator 130 is preferably 5 ⁇ 10 21 atoms / cm 3 or less, more preferably 1 ⁇ 10 21 atoms / cm 3 or less, and even more preferably 5 ⁇ 10 20 atoms / cm 3 or less. ..
  • a film having high purity and intrinsic ferroelectricity by thoroughly removing at least one of impurities, here hydrogen, hydrocarbon, carbon and chlorine in the film of the insulator 130, here. It is possible to form a high-purity intrinsic capacitive element. It should be noted that the consistency of the manufacturing process is very high between the capacitive element having high-purity intrinsic ferroelectricity and the high-purity intrinsic oxide semiconductor shown in the embodiment described later. Therefore, it is possible to provide a method for manufacturing a semiconductor device having high productivity.
  • a hydrocarbon-free precursor typically a chlorine-based precursor
  • an oxidizing agent typically, using the thermal ALD method
  • an oxidizing agent typically
  • the conductor 120b may be formed into a film by using a sputtering method, an ALD method, a CVD method, or the like.
  • tungsten may be formed by using a metal CVD method.
  • the capacitive element 100 having the insulator 130 between the conductor 110 and the conductor 120 shown in FIG. 5C can be manufactured.
  • the capacitive element 100 according to the present embodiment can enhance the ferroelectricity of the insulator 130 without performing a high-temperature baking treatment after the conductor 120a is formed. As a result, the process of manufacturing the ferroelectric capacitor can be reduced, so that the productivity of the ferroelectric capacitor and the semiconductor device including the ferroelectric capacitor can be improved.
  • the present invention is not limited to this.
  • heat treatment may be performed after the formation of the conductor 120.
  • the substrate temperature may be set to room temperature or higher, preferably 300 ° C. or higher, more preferably 325 ° C. or higher, and further preferably 350 ° C. or higher to form a film.
  • the film may be formed by setting the substrate temperature to 500 ° C. or lower, preferably 450 ° C. or lower.
  • the substrate temperature may be set to about 400 ° C.
  • the heat treatment can be performed in an atmosphere containing oxygen gas, nitrogen gas, or an inert gas.
  • the ALD method utilizes the characteristics of atoms, which are self-regulating properties, and allows atoms to be deposited layer by layer, so ultra-thin film formation is possible, film formation into structures with a high aspect ratio is possible, pinholes, etc. It has the effects of being able to form a film with few defects, being able to form a film with excellent coverage, and being able to form a film at a low temperature.
  • the ALD method is carried out by alternately introducing a first raw material gas (also called a precursor) and a second raw material gas (also called an oxidizing gas) for the reaction into the chamber and repeating the introduction of these raw material gases. Make a membrane. Further, when introducing the precursor or the oxidizing gas, N2 , Ar or the like may be introduced into the reaction chamber together with the precursor or the oxidizing gas as a carrier purge gas. By using the carrier purge gas, it is possible to suppress the adsorption of the precursor or oxidizing gas inside the pipe and the inside of the valve, and to introduce the precursor or oxidizing gas into the reaction chamber (also called carrier gas). ).
  • the precursor or oxidizing gas remaining in the reaction chamber can be quickly exhausted (also called purge gas). Since it has two roles of introduction (carrier) and exhaust (purge) in this way, it is sometimes called a carrier purge gas. Further, it is preferable to use the carrier purge gas because the uniformity of the formed film is improved.
  • FIG. 7A shows a film formation sequence of a film of a material capable of having ferroelectricity (hereinafter referred to as a ferroelectric layer) using the ALD method.
  • a ferroelectric layer a film formation sequence of a film of a material capable of having ferroelectricity (hereinafter referred to as a ferroelectric layer) using the ALD method.
  • the insulator 130 a film formation of a ferroelectric layer having hafnium oxide and zirconium oxide will be shown as an example.
  • a precursor containing hafnium and further containing one or more selected from chlorine, fluorine, bromine, iodine, and hydrogen can be used.
  • a precursor containing zirconium and further containing one or more selected from chlorine, fluorine, bromine, iodine, and hydrogen can be used.
  • HfCl 4 is used as the precursor 401 containing hafnium
  • ZrCl 4 is used as the precursor 402 containing zirconium.
  • the precursor 401 and the precursor 402 are formed by heating and gasifying a liquid raw material or a solid raw material.
  • the precursor 401 is formed from a solid raw material of HfCl 4
  • the precursor 402 is formed from a solid raw material of ZrCl 4 .
  • the precursor 401 and the precursor 402 have reduced impurities, and it is preferable that these solid raw materials also have reduced impurities.
  • the impurities include Ba, Cd, Co, Cr, Cu, Fe, Ga, Li, Mg, Mn, Na, Ni, Sr, V, Zn and the like.
  • the above impurities are preferably less than 1000 wppb.
  • wppb is a unit in which the concentration of impurities converted by mass is expressed in parts per billion.
  • any one or a plurality selected from O 2 , O 3 , N 2 O, NO 2 , H 2 O, and H 2 O 2 can be used.
  • a gas containing H2O is used as the oxidizing gas 403.
  • the carrier purge gas 404 any one or a plurality selected from N2 , He, Ar, Kr, and Xe can be used.
  • N 2 is used as the carrier purge gas 404.
  • the oxidizing gas 403 is introduced into the reaction chamber (step S01).
  • the introduction of the oxidizing gas 403 is stopped, only the carrier purge gas 404 is used, and the oxidizing gas 403 remaining in the reaction chamber is purged (step S02).
  • a precursor 401 and a carrier purge gas 404 are introduced into the reaction chamber to keep the pressure in the reaction chamber constant (step S03). In this way, the precursor 401 is adsorbed on the surface to be formed.
  • the introduction of the precursor 401 is stopped, only the carrier purge gas 404 is used, and the precursor 401 remaining in the reaction chamber is purged (step S04).
  • the oxidizing gas 403 is introduced into the reaction chamber.
  • the precursor 401 is oxidized to form hafnium oxide (step S05).
  • the introduction of the oxidizing gas 403 is stopped, only the carrier purge gas 404 is used, and the oxidizing gas 403 remaining in the reaction chamber is purged (step S06).
  • a precursor 402 and a carrier purge gas 404 are introduced into the reaction chamber to keep the pressure in the reaction chamber constant (step S07). In this way, the precursor 402 is adsorbed on the oxygen layer of hafnium oxide.
  • the introduction of the precursor 402 is stopped, only the carrier purge gas 404 is used, and the precursor 402 remaining in the reaction chamber is purged (step S08).
  • the oxidizing gas 403 is introduced into the reaction chamber. By introducing the oxidizing gas 403, the precursor 402 is oxidized and zirconium oxide is formed on hafnium oxide.
  • steps S01 to S08 are set as one cycle (cycle), and the cycle is repeated until a desired film thickness is reached. It should be noted that steps S01 to S08 may be performed in a temperature range of 250 ° C. or higher and 450 ° C. or lower, and preferably in a temperature range of 350 ° C. or higher and 400 ° C. or lower.
  • the insulator 130 by forming a film using the ALD method, it is possible to form a layered crystal structure in which a hafnium layer, an oxygen layer, a zirconium layer, and an oxygen layer are repeated as shown in FIG. .. Further, as described above, by forming a film using a precursor having reduced impurities, it is possible to prevent impurities from being mixed in during the film formation and hindering the formation of the layered crystal structure. As described above, by forming the insulator 130 into a layered crystal structure having high crystallinity, the insulator 130 can be given high ferroelectricity.
  • the insulator 130 does not necessarily exhibit ferroelectricity immediately after film formation. As described above, the insulator 130 may exhibit ferroelectricity not immediately after film formation but after forming the conductor 120 on the insulator 130.
  • FIG. 7B is a schematic view of the manufacturing apparatus 900 by the ALD method.
  • the manufacturing apparatus 900 has a reaction chamber 901, a gas introduction port 903, a reaction chamber inlet 904, an exhaust port 905, a wafer stage 907, and a shaft 908.
  • the wafer 950 is arranged on the wafer stage 907.
  • the reaction chamber 901 may be provided with a heater system for heating the inside of the reaction chamber 901, the precursor 401, the precursor 402, the oxidizing gas 403, and the carrier purge gas 404.
  • the wafer stage 907 may be provided with a heater system for heating the wafer 950.
  • the wafer stage 907 may be provided with a rotation mechanism that rotates horizontally with the shaft 908 as a rotation axis.
  • the precursor 401, the precursor 402, the oxidizing gas 403, and the carrier purge gas 404 are introduced into the gas inlet 903 at the appropriate timing and at the appropriate flow rate in front of the gas inlet.
  • Gas supply system is installed.
  • an exhaust system having a vacuum pump is installed at the end of the exhaust port 905.
  • the manufacturing device 900 shown in FIG. 7B is an ALD device called a cross-flow method.
  • the flow of the precursor 401, the precursor 402, the oxidizing gas 403, and the carrier purge gas 404 in the cross-flow method will be described below.
  • the precursor 401, the precursor 402, the oxidizing gas 403, and the carrier purge gas 404 flow from the gas inlet 903 to the reaction chamber 901 via the reaction chamber inlet 904, reach the wafer 950, and are exhausted through the exhaust port 905. .
  • the arrow shown in FIG. 7B schematically indicates the direction in which the gas flows.
  • step S05 for introducing the oxidizing gas 403 into the reaction chamber 901 as shown in FIG. 7A the precursor 401 adsorbed on the wafer 950 is oxidized by the oxidizing gas 403 to form hafnium oxide. Due to the structure of the manufacturing apparatus 900 of the cross-flow method, the oxidizing gas 403 reaches the wafer 950 after being in contact with the heated reaction chamber member for a long time. Therefore, for example , when O3 is used as the oxidizing gas 403, the oxidizing gas 403 is decomposed by the reaction between the high temperature solid surface and the oxidizing gas 403 by the time it reaches the state, and the oxidizing power is lowered.
  • the film formation rate of hafnium oxide depends on the reach of the oxidizing gas from the reaction chamber inlet 904 to the wafer 950.
  • the peripheral portion of the wafer 950 reaches the oxidizing gas 403 first, so that the film thickness of hafnium oxide becomes thicker toward the peripheral portion of the wafer 950 and the central portion. Is thinner than the peripheral part.
  • the heating temperature of the reaction chamber it is necessary to set the heating temperature of the reaction chamber to an appropriate temperature in order to suppress the decomposition of the oxidizing gas 403 and the decrease in the oxidizing power.
  • the oxidation of the precursor 401 has been described as an example, but the same applies to the oxidation of the precursor 402.
  • the oxidizing gas 403 forms a layer of oxygen having excellent uniformity, so that a more regular layered crystal structure can be formed.
  • the insulator 130 by forming the insulator 130 into a highly regular, layered crystal structure, the insulator 130 can be given high ferroelectricity.
  • an insulator 130 made of a material capable of having ferroelectricity can be formed.
  • the capacitive element 100 can be made into a ferroelectric capacitor.
  • the capacitive element containing a material that may have ferroelectricity.
  • the capacitive element can be provided with good productivity.
  • FIG. 11A to 11D are a top view and a cross-sectional view of a semiconductor device having a transistor 200 and a capacitive element 100.
  • FIG. 11A is a top view of the semiconductor device.
  • 11B to 11D are cross-sectional views of the semiconductor device.
  • FIG. 11B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 11A, and is also a cross-sectional view of the transistor 200 in the channel length direction.
  • FIG. 11C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG.
  • 11A is also a cross-sectional view of the transistor 200 in the channel width direction.
  • 11D is a cross-sectional view of the portion shown by the alternate long and short dash line in A5-A6 in FIG. 11A.
  • FIG. 11A some elements are omitted for the purpose of clarifying the figure.
  • the semiconductor device of one aspect of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, and an insulator provided on the transistor 200.
  • the insulator 212, the insulator 214, the insulator 216, the insulator 275, the insulator 280, the insulator 282, the insulator 283, the insulator 285, and the insulator 274 function as an interlayer film.
  • the insulator 283 is in contact with a part of the upper surface of the insulator 214, the side surface of the insulator 216, the side surface of the insulator 222, the side surface of the insulator 275, the side surface of the insulator 280, and the side surface and the upper surface of the insulator 282. ..
  • the transistor 200 has a semiconductor layer, a first gate, a second gate, a source, and a drain.
  • the other of the source and drain of the transistor 200 is above the semiconductor layer and in contact with one of the electrodes of the capacitive element 100.
  • Insulator 271 (insulator 271a and insulator 271b) is provided in contact with the source and drain of the transistor 200.
  • the capacitive element 100 is provided in an opening reaching one of the source and drain of the transistor 200 formed in the insulator 271, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285.
  • the capacitive element 100 is placed on the conductor 110, which is in contact with the upper surface of one of the source and drain of the transistor 200 at the opening, the insulator 130 arranged on the conductor 110 and the insulator 285, and the insulator 130.
  • It has a conductor 120 (conductor 120a and conductor 120b) to be arranged.
  • the conductor 110 is arranged along the side surface and the bottom surface of the opening.
  • the insulator 245 is provided between the conductor 110 and the insulator 280.
  • the insulator 245 preferably has a function of suppressing the diffusion of hydrogen (for example, at least one hydrogen atom, hydrogen molecule, etc.).
  • the insulator 245 preferably has a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.).
  • the insulator 245 is preferably less permeable to one or both of oxygen and hydrogen than the insulator 280.
  • the transistor 200 is an insulator 216 on the insulator 214 and a conductor 205 (conductor 205a, and a conductor 205a) arranged to be embedded in the insulator 214 and / or the insulator 216.
  • Conductor 205b) insulator 222 on insulator 216, and insulator 205, insulator 224 on insulator 222, oxide 230a on insulator 224, and oxide 230b on oxide 230a.
  • the insulator 252 includes an upper surface of the insulator 222, a side surface of the insulator 224, a side surface of the oxide 230a, a side surface and an upper surface of the oxide 230b, and a side surface of the conductor 242. It is in contact with the side surface of the insulator 271, the side surface of the insulator 275, the side surface of the insulator 280, and the lower surface of the insulator 250.
  • the upper surface of the conductor 260 is arranged so as to substantially coincide in height with the uppermost portion of the insulator 254, the uppermost portion of the insulator 250, the uppermost portion of the insulator 252, and the upper surface of the insulator 280. Further, the insulator 282 is in contact with at least a part of the upper surface of each of the conductor 260, the insulator 252, the insulator 250, the insulator 254, and the insulator 280.
  • the oxide 230a and the oxide 230b may be collectively referred to as the oxide 230.
  • the conductor 242a and the conductor 242b may be collectively referred to as a conductor 242.
  • the insulator 271a and the insulator 271b may be collectively referred to as an insulator 271.
  • the insulator 280 and the insulator 275 are provided with an opening reaching the oxide 230b.
  • Insulator 252, insulator 250, insulator 254, and conductor 260 are arranged in the opening. Further, in the channel length direction of the transistor 200, the conductor 260, the insulator 252, the insulator 250, and the insulator 254 are placed between the insulator 271a and the conductor 242a and the insulator 271b and the conductor 242b. It is provided.
  • the insulator 254 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260.
  • the oxide 230 preferably has an oxide 230a arranged on the insulator 224 and an oxide 230b arranged on the oxide 230a.
  • the oxide 230a By having the oxide 230a under the oxide 230b, it is possible to suppress the diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b.
  • the transistor 200 shows a configuration in which the oxide 230 is laminated with two layers of the oxide 230a and the oxide 230b
  • the present invention is not limited to this.
  • a single layer of the oxide 230b or a laminated structure of three or more layers may be provided, or each of the oxide 230a and the oxide 230b may have a laminated structure.
  • the conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode.
  • the insulator 252, the insulator 250 and the insulator 254 function as the first gate insulator, and the insulator 222 and the insulator 224 function as the second gate insulator.
  • the gate insulator may be referred to as a gate insulating layer or a gate insulating film.
  • the conductor 242a functions as one of the source or the drain, and the conductor 242b functions as the other of the source or the drain. Further, at least a part of the region overlapping with the conductor 260 of the oxide 230 functions as a channel forming region.
  • FIG. 12A an enlarged view of the vicinity of the channel formation region in FIG. 11B is shown in FIG. 12A.
  • the oxide 230b is provided so as to sandwich the region 230bc that functions as a channel forming region of the transistor 200, and the region 230ba and the region 230bb that function as a source region or a drain region. , Have.
  • At least a part of the region 230bc overlaps with the conductor 260.
  • the region 230bc is provided in the region between the conductor 242a and the conductor 242b.
  • the region 230ba is provided so as to be superimposed on the conductor 242a
  • the region 230bb is provided so as to be superimposed on the conductor 242b.
  • the region 230bc that functions as a channel forming region is a high resistance region having a low carrier concentration because it has less oxygen deficiency or a lower impurity concentration than the regions 230ba and 230bb. Therefore, it can be said that the region 230bc is i-type (intrinsic) or substantially i-type.
  • the region 230bc can be easily formed by performing microwave treatment in an atmosphere containing oxygen, for example.
  • the microwave processing refers to processing using, for example, a device having a power source for generating high-density plasma using microwaves. Further, in the present specification and the like, microwave refers to an electromagnetic wave having a frequency of 300 MHz or more and 300 GHz or less.
  • the region 230ba and the region 230bb that function as the source region or the drain region are regions where the carrier concentration is increased and the resistance is lowered due to a large oxygen deficiency or a high concentration of impurities such as hydrogen, nitrogen and metal elements. be. That is, the region 230ba and the region 230bb are n-type regions having a high carrier concentration and low resistance as compared with the region 230bc.
  • the carrier concentration of the region 230 bc that functions as the channel forming region is preferably 1 ⁇ 10 18 cm -3 or less, more preferably less than 1 ⁇ 10 17 cm -3 , and 1 ⁇ 10 16 cm. It is more preferably less than -3 , still more preferably less than 1 ⁇ 10 13 cm -3 , and even more preferably less than 1 ⁇ 10 12 cm -3 .
  • the lower limit of the carrier concentration in the region 230 bc that functions as the channel forming region is not particularly limited, but may be, for example, 1 ⁇ 10 -9 cm -3 .
  • the carrier concentration is equal to or lower than the carrier concentration of the region 230 ba and the region 230 bb, and equal to or higher than the carrier concentration of the region 230 bc.
  • Regions may be formed. That is, the region functions as a junction region between the region 230 bc and the region 230 ba or the region 230 bb.
  • the hydrogen concentration may be equal to or lower than the hydrogen concentration of the region 230ba and the region 230bb, and may be equal to or higher than the hydrogen concentration of the region 230bc.
  • the junction region may have an oxygen deficiency equal to or less than that of the region 230ba and the region 230bb, and may be equal to or greater than the oxygen deficiency of the region 230bc.
  • FIG. 12A shows an example in which the region 230ba, the region 230bb, and the region 230bc are formed on the oxide 230b, but the present invention is not limited thereto.
  • each of the above regions may be formed not only with the oxide 230b but also with the oxide 230a.
  • the concentrations of the metal elements detected in each region and the impurity elements such as hydrogen and nitrogen are not limited to the stepwise changes in each region, but may be continuously changed in each region. That is, the closer the region is to the channel formation region, the lower the concentration of the metal element and the impurity elements such as hydrogen and nitrogen is sufficient.
  • a metal oxide hereinafter, also referred to as an oxide semiconductor that functions as a semiconductor for the oxide 230 (oxide 230a and oxide 230b) containing a channel forming region.
  • the metal oxide that functions as a semiconductor it is preferable to use a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more. As described above, by using a metal oxide having a large bandgap, the off-current of the transistor can be reduced.
  • an In-M-Zn oxide having indium, element M and zinc (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium).
  • Zinc, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. (one or more) and the like may be used.
  • an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used as the oxide 230.
  • the atomic number ratio of In to the element M in the metal oxide used for the oxide 230b is larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 230a.
  • the oxide 230a under the oxide 230b By arranging the oxide 230a under the oxide 230b in this way, it is possible to suppress the diffusion of impurities and oxygen from the structure formed below the oxide 230a to the oxide 230b. ..
  • the oxide 230a and the oxide 230b have a common element (main component) other than oxygen, the defect level density at the interface between the oxide 230a and the oxide 230b can be lowered. Since the defect level density at the interface between the oxide 230a and the oxide 230b can be lowered, the influence of the interfacial scattering on the carrier conduction is small, and a high on-current can be obtained.
  • the oxide 230b preferably has crystallinity.
  • CAAC-OS c-axis aligned crystalline semiconductor semiconductor
  • CAAC-OS is a metal oxide having a highly crystalline and dense structure and having few impurities and defects (for example, oxygen deficiency (VO, etc.).
  • the metal By heat-treating at a temperature at which the oxide does not polycrystallize (for example, 400 ° C. or higher and 600 ° C. or lower), CAAC-OS can be made into a more crystalline and dense structure.
  • a temperature at which the oxide does not polycrystallize for example, 400 ° C. or higher and 600 ° C. or lower
  • CAAC-OS By increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.
  • the metal oxide having CAAC-OS has stable physical properties. Therefore, the metal oxide having CAAC-OS is resistant to heat and has high reliability.
  • a transistor using an oxide semiconductor if impurities and oxygen deficiencies are present in the region where a channel is formed in the oxide semiconductor, the electrical characteristics are liable to fluctuate and the reliability may be deteriorated. Further, hydrogen in the vicinity of the oxygen deficiency may form a defect in which hydrogen is contained in the oxygen deficiency (hereinafter, may be referred to as VOH) to generate an electron as a carrier. Therefore, if oxygen deficiency is contained in the region where the channel is formed in the oxide semiconductor, the transistor has normal-on characteristics (the channel exists even if no voltage is applied to the gate electrode, and the current is applied to the transistor. Flowing characteristics).
  • the region in which the channel is formed in the oxide semiconductor is preferably i-type (intrinsic) or substantially i-type with a reduced carrier concentration.
  • excess oxygen an insulator containing oxygen desorbed by heating
  • the oxide semiconductor is removed from the insulator.
  • the on-current of the transistor 200 may decrease or the field effect mobility may decrease.
  • the oxygen supplied to the source region or the drain region varies in the surface of the substrate, so that the characteristics of the semiconductor device having the transistor vary.
  • the region 230bac that functions as a channel forming region preferably has a reduced carrier concentration and is i-type or substantially i-type, but the region 230ba that functions as a source region or a drain region and The region 230bb has a high carrier concentration and is preferably n-type. That is, it is preferable to reduce oxygen deficiency and VOH in the region 230bc of the oxide semiconductor so that an excessive amount of oxygen is not supplied to the region 230ba and the region 230bb.
  • microwave treatment is performed in an atmosphere containing oxygen to reduce oxygen deficiency and VOH in the region 230bc . Try.
  • oxygen gas By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be turned into plasma by using a high frequency such as microwave or RF, and the oxygen plasma can be allowed to act.
  • the region 230bc can be irradiated with a high frequency such as microwaves or RF.
  • the VO H of the region 230 bc can be divided, the hydrogen H can be removed from the region 230 bc, and the oxygen -deficient VO can be supplemented with oxygen. That is, in the region 230bc , the reaction “VOH ⁇ H + VO” occurs, and the hydrogen concentration in the region 230bc can be reduced. Therefore, oxygen deficiency and VOH in the region 230bc can be reduced, and the carrier concentration can be lowered.
  • the action of microwaves, high frequencies such as RF, oxygen plasma, etc. is shielded by the conductors 242a and 242b and does not reach the regions 230ba and 230bb. ..
  • the action of the oxygen plasma can be reduced by the insulator 271 and the insulator 280 provided overlying the oxide 230b and the conductor 242.
  • the reduction of VOH and the supply of an excessive amount of oxygen do not occur in the region 230ba and the region 230bb , so that the reduction of the carrier concentration can be prevented.
  • microwave treatment in an atmosphere containing oxygen after the film formation of the insulating film to be the insulator 252 or the film formation of the insulating film to be the insulator 250.
  • microwave treatment in an atmosphere containing oxygen through the insulator 252 or the insulator 250 in this way, oxygen can be efficiently injected into the region 230 bc.
  • the insulator 252 so as to be in contact with the side surface of the conductor 242 and the surface of the region 230 bc, the injection of more oxygen than necessary into the region 230 bc is suppressed, and the oxidation of the side surface of the conductor 242 is suppressed. be able to.
  • oxidation of the side surface of the conductor 242 can be suppressed when the insulating film to be the insulator 250 is formed.
  • the oxygen injected into the region 230bc has various forms such as an oxygen atom, an oxygen molecule, and an oxygen radical (also called an O radical, an atom or molecule having an unpaired electron, or an ion).
  • the oxygen injected into the region 230bc may be any one or more of the above-mentioned forms, and it is particularly preferable that it is an oxygen radical.
  • the film quality of the insulator 252 and the insulator 250 can be improved, the reliability of the transistor 200 is improved.
  • oxygen deficiency and VOH can be selectively removed in the region 230 bc of the oxide semiconductor to make the region 230 bc i-type or substantially i-type. Further, it is possible to suppress the supply of excess oxygen to the region 230ba and the region 230bb that function as the source region or the drain region, and maintain the n-type. As a result, it is possible to suppress fluctuations in the electrical characteristics of the transistor 200 and suppress variations in the electrical characteristics of the transistor 200 within the substrate surface.
  • a curved surface may be provided between the side surface of the oxide 230b and the upper surface of the oxide 230b in a cross-sectional view of the transistor 200 in the channel width direction. That is, the end portion of the side surface and the end portion of the upper surface may be curved (hereinafter, also referred to as a round shape).
  • the radius of curvature on the curved surface is preferably larger than 0 nm, smaller than the film thickness of the oxide 230b in the region overlapping the conductor 242, or smaller than half the length of the region having no curved surface.
  • the radius of curvature on the curved surface is larger than 0 nm and 20 nm or less, preferably 1 nm or more and 15 nm or less, and more preferably 2 nm or more and 10 nm or less.
  • the oxide 230 preferably has a laminated structure of a plurality of oxide layers having different chemical compositions.
  • the atomic number ratio of the element M to the metal element as the main component is the ratio of the element M to the metal element as the main component in the metal oxide used for the oxide 230b. It is preferably larger than the atomic number ratio.
  • the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 230b.
  • the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 230a.
  • the oxide 230b is preferably an oxide having crystallinity such as CAAC-OS.
  • Crystalline oxides such as CAAC-OS have a dense structure with high crystallinity with few impurities and defects (oxygen deficiency, etc.). Therefore, it is possible to suppress the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode. As a result, oxygen can be reduced from being extracted from the oxide 230b even if heat treatment is performed, so that the transistor 200 is stable against a high temperature (so-called thermal budget) in the manufacturing process.
  • the lower end of the conduction band changes gently.
  • the lower end of the conduction band at the junction between the oxide 230a and the oxide 230b is continuously changed or continuously bonded. In order to do so, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b.
  • the oxide 230a and the oxide 230b have a common element other than oxygen as a main component, so that a mixed layer having a low defect level density can be formed.
  • the oxide 230b is an In-M-Zn oxide
  • the oxide 230a is an In-M-Zn oxide, an M-Zn oxide, an element M oxide, an In-Zn oxide, or an indium oxide. Etc. may be used.
  • the composition in the vicinity includes a range of ⁇ 30% of the desired atomic number ratio. Further, it is preferable to use gallium as the element M.
  • the oxide 230a and the oxide 230b are preferably formed by a sputtering method.
  • Oxygen or a mixed gas of oxygen and noble gas is used as the sputtering gas.
  • the film forming method of the oxide 230a and the oxide 230b is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be appropriately used.
  • the above-mentioned atomic number ratio is not limited to the atomic number ratio of the formed metal oxide, but is the atomic number ratio of the sputtering target used for forming the metal oxide. May be.
  • the oxide 230 may be formed by using the ALD method.
  • a method for forming an oxide 230 using the ALD method will be described. Since the film formation method using the ALD method is also described in the previous embodiment, different parts can be mainly described, and the common parts can be referred to the description of the previous embodiment. ..
  • the In-M-Zn oxide that can be used for the oxide 230 includes a layer having indium (In) and oxygen (hereinafter referred to as "In layer”) and a layer having element M, zinc (Zn), and oxygen (hereinafter referred to as "In layer”).
  • In layer a layer having indium (In) and oxygen
  • In layer a layer having element M, zinc (Zn), and oxygen
  • (M, Zn) layers a layer having element M, zinc (Zn), and oxygen
  • FIG. 7C shows an example of a film forming sequence using the precursors 411 to 413 and the oxidizing gas 414 to form a film.
  • the film formation sequence includes steps S11 to S13.
  • a precursor containing indium can be used.
  • a precursor containing the element M can be used.
  • a precursor containing zinc can be used.
  • a precursor formed of an inorganic substance (sometimes referred to as an inorganic precursor) may be used, or a precursor formed of an organic substance (sometimes referred to as an organic precursor). May be used.
  • oxidizing gas 414 a gas applicable to the oxidizing gas 403 described in the previous embodiment can be used.
  • step S11 a step of introducing the precursor 411 and adsorbing the precursor having indium to the surface to be formed, a step of stopping the introduction of the precursor 411 and purging the excess precursor 411 in the chamber, and an oxidizing gas 414 are introduced.
  • the step of oxidizing the precursor 411 to form an In layer, the step of stopping the introduction of the oxidizing gas 414, and the step of purging the excess oxidizing gas 414 in the chamber are performed in this order.
  • step S12 is performed.
  • step S12 a step of introducing the precursor 412 and adsorbing the precursor having the element M on the surface of the In layer, a step of stopping the introduction of the precursor 413 and purging the excess precursor 412 in the chamber, and introducing an oxidizing gas 414. Then, the steps of oxidizing the precursor 412 to form the M layer, stopping the oxidizing gas 414, and purging the excess oxidizing gas in the chamber are performed in this order.
  • step S13 is performed.
  • a step of introducing the precursor 413 to adsorb the zinc-containing precursor to the surface of the M layer, a step of stopping the introduction of the precursor 413, and a step of purging the excess precursor 413 in the chamber, and introducing an oxidizing gas 414 are introduced.
  • the step of oxidizing the precursor 413 to form a Zn layer, the step of stopping the introduction of the oxidizing gas 414, and the step of purging the excess oxidizing gas 414 in the chamber are performed in this order.
  • an In—M—Zn oxide having a desired film thickness can be formed.
  • the element M or Zn may be mixed in the In layer during the film formation or due to the heat treatment after the film formation.
  • In or Zn may be mixed in the M layer.
  • In or Ga may be mixed in the Zn layer.
  • steps S11 to S13 are performed in one cycle is not limited to one.
  • the number of steps S11 to S13 in one cycle may be set so as to obtain an In—M—Zn oxide having a desired composition.
  • the cycle is set to step S11, step S13, step S12, and step S13 as one cycle. It is good to repeat.
  • the In—Zn oxide can be formed by repeating the cycle composed of steps S11 and S12.
  • the (M, Zn) layer may be formed in step S12 by also introducing the precursor 413.
  • the precursor 412 or the precursor 413 may also be introduced to form an In layer containing the element M or Zn in step S11. By appropriately combining these, a desired oxide 230 can be formed into a film.
  • the manufacturing apparatus used for the film formation by the ALD method can take into consideration the explanation of the above-described embodiment.
  • the manufacturing apparatus can be standardized.
  • the insulator 130 can be continuously formed on the oxide 230 by switching the precursor and the oxidizing gas after forming the oxide 230. Therefore, the oxide 230 and the insulator 130 can be formed without opening to the atmosphere, and the vicinity of the interface between the oxide 230 and the insulator 130 can be kept clean.
  • two or more manufacturing devices used for film formation by the ALD method may be incorporated in the multi-chamber type film forming device.
  • the oxide 230 and the ferroelectric layer are continuously formed without switching between the precursor and the oxidizing gas. Can be filmed.
  • the interface between the oxide 230 and the insulator 252 and its vicinity thereof can be provided.
  • Indium contained in the oxide 230 may be unevenly distributed.
  • the vicinity of the surface of the oxide 230 has an atomic number ratio close to that of indium oxide or an atomic number ratio close to that of In—Zn oxide.
  • the atomic number ratio of indium in the vicinity of the surface of the oxide 230, particularly the oxide 230b, is increased, so that the field effect mobility of the transistor 200 can be improved.
  • the defect level density at the interface between the oxide 230a and the oxide 230b can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 200 can obtain a large on-current and high frequency characteristics.
  • At least one of the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 has impurities such as water and hydrogen from the substrate side or the transistor 200. It is preferable to function as a barrier insulating film that suppresses diffusion from above to the transistor 200.
  • At least one of insulator 212, insulator 214, insulator 271, insulator 275, insulator 282, insulator 283, and insulator 285 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, It is preferable to use an insulating material having a function of suppressing the diffusion of impurities such as nitrogen oxide molecules ( N2O, NO, NO2, etc.) and copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom and an oxygen molecule) (the above-mentioned oxygen is difficult to permeate).
  • the barrier insulating film refers to an insulating film having a barrier property.
  • the barrier property is a function of suppressing the diffusion of the corresponding substance (also referred to as low permeability).
  • the corresponding substance has a function of capturing and fixing (also referred to as gettering).
  • the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 are insulators having a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.
  • impurities such as water and hydrogen, and oxygen.
  • silicon nitride having a higher hydrogen barrier property it is preferable to use silicon nitride having a higher hydrogen barrier property.
  • the insulator 214 it is preferable to use aluminum oxide or magnesium oxide having a high function of capturing hydrogen and fixing hydrogen. This makes it possible to prevent impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200 side via the insulator 212 and the insulator 214. Alternatively, it is possible to prevent impurities such as water and hydrogen from diffusing to the transistor 200 side from the interlayer insulating film or the like arranged outside the insulator 285. Alternatively, it is possible to prevent oxygen contained in the insulator 224 or the like from diffusing toward the substrate side via the insulator 212 and the insulator 214.
  • the transistor 200 has an insulator 212, an insulator 214, an insulator 271, an insulator 275, an insulator 282, an insulator 283, and an insulator 212 having a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. It is preferable to have a structure surrounded by an insulator 285.
  • an oxide having an amorphous structure as the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285.
  • a metal oxide such as AlO x (x is an arbitrary number larger than 0) or MgO y (y is an arbitrary number larger than 0).
  • an oxygen atom has a dangling bond, and the dangling bond may have a property of capturing or fixing hydrogen.
  • a metal oxide having such an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, hydrogen contained in the transistor 200 or hydrogen existing around the transistor 200 is captured or fixed. be able to. In particular, it is preferable to capture or fix hydrogen contained in the channel forming region of the transistor 200.
  • a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, it is possible to manufacture the transistor 200 having good characteristics and high reliability, and a semiconductor device.
  • the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 preferably have an amorphous structure, but a region of a polycrystal structure is partially formed. It may be formed. Further, the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 are multi-layered in which a layer having an amorphous structure and a layer having a polycrystal structure are laminated. It may be a structure. For example, a laminated structure in which a layer having a polycrystalline structure is formed on a layer having an amorphous structure may be used.
  • the film formation of the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 may be performed by using, for example, a sputtering method. Since the sputtering method does not require the use of molecules containing hydrogen in the film forming gas, the hydrogen concentrations of the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285. Can be reduced.
  • the film forming method is not limited to the sputtering method, and includes chemical vapor deposition (CVD) method, molecular beam epitaxy (MBE) method, pulsed laser deposition (PLD) method, atomic layer deposition (ALD) method, and the like. It may be used as appropriate.
  • CVD chemical vapor deposition
  • MBE molecular beam epitaxy
  • PLD pulsed laser deposition
  • ALD atomic layer deposition
  • the insulator 283 may be able to mitigate the charge-up of the conductor 205, the conductor 242, the conductor 260, or the conductor 110.
  • the resistivity of the insulator 212, the insulator 275, and the insulator 283 is preferably 1 ⁇ 10 10 ⁇ cm or more and 1 ⁇ 10 15 ⁇ cm or less.
  • the insulator 216, the insulator 274, the insulator 280, and the insulator 285 have a lower dielectric constant than the insulator 214.
  • a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.
  • the conductor 205 is arranged so as to overlap the oxide 230 and the conductor 260.
  • the conductor 205 is embedded in the opening formed in the insulator 216. Further, a part of the conductor 205 may be embedded in the insulator 214.
  • the conductor 205 has a conductor 205a and a conductor 205b.
  • the conductor 205a is provided in contact with the bottom surface and the side wall of the opening.
  • the conductor 205b is provided so as to be embedded in the recess formed in the conductor 205a.
  • the height of the upper surface of the conductor 205b is substantially the same as the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216.
  • the conductor 205a has a function of suppressing the diffusion of impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule ( N2O, NO, NO2 , etc.) and copper atom. It is preferable to use a conductive material having. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom and an oxygen molecule).
  • the conductor 205a By using a conductive material having a function of reducing the diffusion of hydrogen in the conductor 205a, impurities such as hydrogen contained in the conductor 205b are prevented from diffusing into the oxide 230 via the insulator 224 and the like. Can be prevented. Further, by using a conductive material having a function of suppressing the diffusion of oxygen for the conductor 205a, it is possible to prevent the conductor 205b from being oxidized and the conductivity from being lowered. As the conductive material having a function of suppressing the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used. Therefore, the conductive material 205a may be a single layer or a laminated material. For example, titanium nitride may be used for the conductor 205a.
  • a conductive material containing tungsten, copper, or aluminum as a main component for the conductor 205b.
  • tungsten may be used for the conductor 205b.
  • the conductor 205 may function as a second gate electrode.
  • the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without interlocking with the potential applied to the conductor 260.
  • Vth threshold voltage
  • by applying a negative potential to the conductor 205 it is possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be made smaller than when it is not applied.
  • the electrical resistivity of the conductor 205 is designed in consideration of the potential applied to the above-mentioned conductor 205, and the film thickness of the conductor 205 is set according to the electrical resistivity.
  • the film thickness of the insulator 216 is substantially the same as that of the conductor 205.
  • the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, so that the impurities can be reduced from diffusing into the oxide 230. ..
  • the conductor 205 may be provided larger than the size of the region that does not overlap with the conductor 242a and the conductor 242b of the oxide 230.
  • the conductor 205 is also stretched in a region outside the ends of the oxides 230a and 230b in the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 are superimposed via an insulator on the outside of the side surface of the oxide 230 in the channel width direction.
  • the channel forming region of the oxide 230 is electrically surrounded by the electric field of the conductor 260 that functions as the first gate electrode and the electric field of the conductor 205 that functions as the second gate electrode. Can be done.
  • the structure of the transistor that electrically surrounds the channel forming region by the electric fields of the first gate and the second gate is called a curved channel (S-channel) structure.
  • the transistor having an S-channel structure represents the structure of a transistor that electrically surrounds the channel formation region by the electric fields of one and the other of the pair of gate electrodes.
  • the S-channel structure disclosed in the present specification and the like is different from the Fin type structure and the planar type structure.
  • the conductor 205 is stretched to function as wiring.
  • the present invention is not limited to this, and a conductor that functions as wiring may be provided under the conductor 205. Further, it is not always necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by a plurality of transistors.
  • the conductor 205 shows a configuration in which the conductor 205a and the conductor 205b are laminated, but the present invention is not limited to this.
  • the conductor 205 may be provided as a single layer or a laminated structure having three or more layers.
  • the insulator 222 and the insulator 224 function as a gate insulator.
  • the insulator 222 preferably has a function of suppressing the diffusion of hydrogen (for example, at least one hydrogen atom, hydrogen molecule, etc.). Further, it is preferable that the insulator 222 has a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.
  • the insulator 222 it is preferable to use an insulator containing oxides of one or both of aluminum and hafnium, which are insulating materials.
  • the insulator it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like.
  • an oxide containing hafnium and zirconium for example, hafnium zirconium oxide.
  • the insulator 222 impurities such as hydrogen can be suppressed from diffusing into the inside of the transistor 200, and the generation of oxygen deficiency in the oxide 230 can be suppressed. Further, it is possible to suppress the conductor 205 from reacting with the oxygen contained in the insulator 224 and the oxide 230.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to the insulator.
  • these insulators may be nitrided.
  • the insulator 222 may be used by laminating silicon oxide, silicon oxide or silicon nitride on these insulators.
  • an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, and hafnium zirconium oxide may be used in a single layer or in a laminated state.
  • a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, and hafnium zirconium oxide.
  • a substance having a high dielectric constant such as lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), (Ba, Sr) TiO 3 (BST) may be used.
  • silicon oxide, silicon oxynitride, or the like may be appropriately used.
  • the heat treatment may be performed, for example, at 100 ° C. or higher and 600 ° C. or lower, more preferably 350 ° C. or higher and 550 ° C. or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more of an oxidizing gas, 1% or more, or 10% or more.
  • the heat treatment is preferably performed in an oxygen atmosphere.
  • oxygen can be supplied to the oxide 230 to reduce oxygen deficiency (VO).
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an atmosphere of nitrogen gas or an inert gas. good.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas, 1% or more, or 10% or more, and then continuously heat-treated in an atmosphere of nitrogen gas or an inert gas.
  • the oxygen deficiency in the oxide 230 can be repaired by the supplied oxygen, in other words, the reaction of "VO + O ⁇ null" can be promoted. .. Further, the oxygen supplied to the hydrogen remaining in the oxide 230 reacts, so that the hydrogen can be removed (dehydrated) as H2O . As a result, it is possible to suppress the hydrogen remaining in the oxide 230 from being recombined with the oxygen deficiency to form VOH.
  • the insulator 222 and the insulator 224 may have a laminated structure of two or more layers.
  • the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
  • the insulator 224 may be formed in an island shape by superimposing on the oxide 230a. In this case, the insulator 275 is in contact with the side surface of the insulator 224 and the upper surface of the insulator 222.
  • the conductor 242a and the conductor 242b are provided in contact with the upper surface of the oxide 230b.
  • the conductor 242a and the conductor 242b function as a source electrode or a drain electrode of the transistor 200, respectively.
  • Examples of the conductor 242 include a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, and the like. It is preferable to use a nitride containing titanium and aluminum. In one aspect of the invention, a nitride containing tantalum is particularly preferred. Further, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when oxygen is absorbed.
  • hydrogen contained in the oxide 230b or the like may diffuse into the conductor 242a or the conductor 242b.
  • hydrogen contained in the oxide 230b or the like is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen is the conductor. It may bind to the nitrogen contained in the 242a or the conductor 242b. That is, hydrogen contained in the oxide 230b or the like may be absorbed by the conductor 242a or the conductor 242b.
  • the conductor 242 it is preferable that no curved surface is formed between the side surface of the conductor 242 and the upper surface of the conductor 242.
  • the cross-sectional area of the conductor 242 in the cross section in the channel width direction as shown in FIG. 11D can be increased.
  • the conductivity of the conductor 242 can be increased and the on-current of the transistor 200 can be increased.
  • the insulator 271a is provided in contact with the upper surface of the conductor 242a, and the insulator 271b is provided in contact with the upper surface of the conductor 242b.
  • the insulator 271 preferably functions as a barrier insulating film against at least oxygen. Therefore, it is preferable that the insulator 271 has a function of suppressing the diffusion of oxygen.
  • the insulator 271 preferably has a function of suppressing the diffusion of oxygen more than the insulator 280.
  • an insulator such as aluminum oxide or magnesium oxide may be used.
  • the insulator 275 is provided so as to cover the insulator 224, the oxide 230a, the oxide 230b, the conductor 242, and the insulator 271. It is preferable that the insulator 275 has a function of capturing hydrogen and fixing hydrogen. In that case, the insulator 275 preferably contains an insulator such as silicon nitride or a metal oxide having an amorphous structure, for example, aluminum oxide or magnesium oxide. Further, for example, as the insulator 275, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used.
  • the conductor 242 can be wrapped with the insulator having a barrier property against oxygen. That is, it is possible to prevent oxygen contained in the insulator 224 and the insulator 280 from diffusing into the conductor 242. As a result, the conductor 242 is directly oxidized by the oxygen contained in the insulator 224 and the insulator 280 to increase the resistivity and suppress the decrease in the on-current.
  • the insulator 252 functions as a part of the gate insulator. As the insulator 252, it is preferable to use a barrier insulating film against oxygen. As the insulator 252, an insulator that can be used for the above-mentioned insulator 282 may be used. As the insulator 252, an insulator containing an oxide of one or both of aluminum and hafnium may be used. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate) and the like can be used. In this embodiment, aluminum oxide is used as the insulator 252. In this case, the insulator 252 is an insulator having at least oxygen and aluminum.
  • the insulator 252 is provided in contact with the upper surface and the side surface of the oxide 230b, the side surface of the oxide 230a, the side surface of the insulator 224, and the upper surface of the insulator 222. That is, the region overlapping the oxide 230a, the oxide 230b, and the conductor 260 of the insulator 224 is covered with the insulator 252 in the cross section in the channel width direction. Thereby, when the heat treatment or the like is performed, the desorption of oxygen by the oxide 230a and the oxide 230b can be blocked by the insulator 252 having a barrier property against oxygen.
  • the insulator 280 and the insulator 250 contain an excessive amount of oxygen, it is possible to suppress the excessive supply of the oxygen to the oxide 230a and the oxide 230b. Therefore, it is possible to prevent the region 230ba and the region 230bb from being excessively oxidized through the region 230bc to cause a decrease in the on-current of the transistor 200 or a decrease in the field effect mobility.
  • the insulator 252 is provided in contact with the side surfaces of the conductor 242, the insulator 271, the insulator 275, and the insulator 280. Therefore, it is possible to reduce the oxidation of the side surface of the conductor 242 and the formation of an oxide film on the side surface. As a result, it is possible to suppress a decrease in the on-current of the transistor 200 or a decrease in the field effect mobility.
  • the insulator 252 needs to be provided in the opening formed in the insulator 280 or the like together with the insulator 254, the insulator 250, and the conductor 260. In order to miniaturize the transistor 200, it is preferable that the film thickness of the insulator 252 is thin.
  • the film thickness of the insulator 252 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less.
  • the insulator 252 may have a region having the above-mentioned film thickness at least in a part thereof.
  • the film thickness of the insulator 252 is preferably thinner than the film thickness of the insulator 250. In this case, the insulator 252 may have a region having a film thickness thinner than that of the insulator 250, at least in part.
  • the insulator 252 In order to form the insulator 252 with a thin film thickness as described above, it is preferable to form the insulator by using the ALD method.
  • the ALD method include a thermal ALD (Thermal ALD) method in which the reaction of the precursor and the reactor is performed only by thermal energy, and a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactor.
  • a thermal ALD Thermal ALD
  • PEALD Laser ALD
  • the ALD method utilizes the characteristics of atoms, which are self-regulating properties, and can deposit atoms layer by layer, so ultra-thin film formation is possible, film formation into structures with a high aspect ratio is possible, pinholes, etc. It has the effects of being able to form a film with few defects, being able to form a film with excellent coverage, and being able to form a film at a low temperature. Therefore, the insulator 252 can be formed on the side surface of the opening formed in the insulator 280 or the like with good coverage and with a thin film thickness as described above.
  • the film provided by the ALD method may contain a large amount of impurities such as carbon as compared with the film provided by other film forming methods.
  • the quantification of impurities can be performed by using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).
  • the insulator 250 functions as a part of the gate insulator.
  • the insulator 250 is preferably arranged in contact with the upper surface of the insulator 252.
  • the insulator 250 includes silicon oxide, silicon nitriding, silicon nitride, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having holes, and the like. Can be used.
  • silicon oxide and silicon nitride nitride are preferable because they are heat-stable.
  • the insulator 250 is an insulator having at least oxygen and silicon.
  • the insulator 250 preferably has a reduced concentration of impurities such as water and hydrogen in the insulator 250.
  • the film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less, and more preferably 0.5 nm or more and 15.0 nm or less. In this case, the insulator 250 may have, at least in part, a region having the above-mentioned film thickness.
  • FIGS. 11A to 11D show a configuration in which the insulator 250 is a single layer
  • the present invention is not limited to this, and a laminated structure of two or more layers may be used.
  • the insulator 250 may have a two-layer laminated structure of the insulator 250a and the insulator 250b on the insulator 250a.
  • the lower insulator 250a is formed by using an insulator that easily permeates oxygen
  • the upper insulator 250b is a diffusion of oxygen. It is preferable to use an insulator having a function of suppressing the above. With such a configuration, oxygen contained in the insulator 250a can be suppressed from diffusing into the conductor 260. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230. Further, it is possible to suppress the oxidation of the conductor 260 by the oxygen contained in the insulator 250a.
  • the insulator 250a may be provided by using a material that can be used for the above-mentioned insulator 250, and the insulator 250b may be an insulator containing an oxide of one or both of aluminum and hafnium.
  • the insulator aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate) and the like can be used.
  • hafnium oxide is used as the insulator 250b.
  • the insulator 250b is an insulator having at least oxygen and hafnium.
  • the film thickness of the insulator 250b is 0.5 nm or more and 5.0 nm or less, preferably 1.0 nm or more and 5.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less.
  • the insulator 250b may have, at least in part, a region having the above-mentioned film thickness.
  • an insulating material which is a high-k material having a high relative permittivity may be used for the insulator 250b.
  • the gate insulator By forming the gate insulator into a laminated structure of the insulator 250a and the insulator 250b, it is possible to obtain a laminated structure that is stable against heat and has a high relative permittivity. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Further, it is possible to reduce the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator. Therefore, the withstand voltage of the insulator 250 can be increased.
  • EOT equivalent oxide film thickness
  • the insulator 254 functions as a part of the gate insulator.
  • silicon nitride formed by the PEALD method may be used as the insulator 254.
  • the insulator 254 is an insulator having at least nitrogen and silicon.
  • the insulator 254 may further have a barrier property against oxygen. As a result, oxygen contained in the insulator 250 can be suppressed from diffusing into the conductor 260.
  • the insulator 254 needs to be provided in the opening formed in the insulator 280 or the like together with the insulator 252, the insulator 250, and the conductor 260. In order to miniaturize the transistor 200, it is preferable that the film thickness of the insulator 254 is thin.
  • the film thickness of the insulator 254 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less.
  • the insulator 254 may have, at least in part, a region having the above-mentioned film thickness.
  • the film thickness of the insulator 254 is preferably thinner than the film thickness of the insulator 250. In this case, the insulator 254 may have a region having a film thickness thinner than that of the insulator 250, at least in part.
  • the conductor 260 functions as the first gate electrode of the transistor 200.
  • the conductor 260 preferably has a conductor 260a and a conductor 260b arranged on the conductor 260a.
  • the conductor 260a is preferably arranged so as to wrap the bottom surface and the side surface of the conductor 260b.
  • the upper surface of the conductor 260 substantially coincides with the upper surface of the insulator 250.
  • the conductor 260 is shown as a two-layer structure of the conductor 260a and the conductor 260b in FIGS. 11B and 11C, it may be a single-layer structure or a laminated structure of three or more layers.
  • the conductor 260a it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule and copper atom.
  • a conductive material having a function of suppressing the diffusion of oxygen for example, at least one such as an oxygen atom and an oxygen molecule.
  • the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress that the conductor 260b is oxidized by the oxygen contained in the insulator 250 and the conductivity is lowered.
  • the conductive material having a function of suppressing the diffusion of oxygen for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • the conductor 260 also functions as wiring, it is preferable to use a conductor having high conductivity.
  • a conductor having high conductivity for example, as the conductor 260b, a conductive material containing tungsten, copper, or aluminum as a main component can be used.
  • the conductor 260b may have a laminated structure, for example, titanium or a laminated structure of titanium nitride and the conductive material.
  • the conductor 260 is self-aligned so as to fill the opening formed in the insulator 280 or the like.
  • the conductor 260 can be reliably arranged in the region between the conductor 242a and the conductor 242b without aligning the conductor 260.
  • the height is preferably lower than the height of the bottom surface of the oxide 230b.
  • the conductor 260 which functions as a gate electrode, covers the side surface and the upper surface of the channel forming region of the oxide 230b via an insulator 250 or the like, so that the electric field of the conductor 260 can be applied to the channel forming region of the oxide 230b. It becomes easier to act on the whole. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved.
  • the difference is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.
  • the insulator 280 is provided on the insulator 275, and an opening is formed in the region where the insulator 250 and the conductor 260 are provided. Further, the upper surface of the insulator 280 may be flattened.
  • the insulator 280 that functions as an interlayer film preferably has a low dielectric constant.
  • a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.
  • the insulator 280 is provided by using the same material as the insulator 216, for example.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because they can easily form a region containing oxygen desorbed by heating.
  • the insulator 280 preferably has an excess oxygen region or excess oxygen. Further, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced.
  • impurities such as water and hydrogen in the insulator 280
  • silicon oxide, silicon oxynitride, or the like may be appropriately used for the insulator 280.
  • the insulator 280 By providing an insulator having excess oxygen in contact with the oxide 230, oxygen deficiency in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.
  • the insulator 280 containing excess oxygen can be formed.
  • the hydrogen concentration in the insulator 280 can be reduced.
  • the insulator 282 in contact with the upper surface of the insulator 280 may be formed into a film by a sputtering method in an atmosphere containing oxygen, and oxygen may be added to the insulator 280.
  • oxygen may be added to the insulator 280 in the film formation of the insulator 282
  • the film forming method of the insulator 280 is not limited to the sputtering method, and the CVD method, MBE method, PLD method, ALD method and the like are appropriately used. You may.
  • the insulator 280 may have a laminated structure of silicon oxide formed by a sputtering method and silicon oxide formed on the insulator by a CVD method. Further, silicon nitride may be further laminated on top of the silicon nitride.
  • the insulator 282 preferably functions as a barrier insulating film that suppresses impurities such as water and hydrogen from diffusing into the insulator 280 from above, and preferably has a function of capturing impurities such as hydrogen. Further, the insulator 282 preferably functions as a barrier insulating film that suppresses the permeation of oxygen.
  • a metal oxide having an amorphous structure for example, an insulator such as aluminum oxide may be used. In this case, the insulator 282 is an insulator having at least oxygen and aluminum.
  • the insulator 282 which has a function of capturing impurities such as hydrogen in contact with the insulator 280 in the region sandwiched between the insulator 212 and the insulator 283, hydrogen contained in the insulator 280 and the like can be obtained. Impurities can be captured and the amount of hydrogen in the region can be kept constant. In particular, it is preferable to use aluminum oxide having an amorphous structure as the insulator 282 because hydrogen may be captured or fixed more effectively. This makes it possible to manufacture a transistor 200 having good characteristics and high reliability, and a semiconductor device.
  • the insulator 282 is preferably formed by using a sputtering method. Oxygen can be added to the insulator 280 by forming the insulator 282 by the sputtering method.
  • the film forming method of the insulator 282 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be appropriately used.
  • the insulator 283 functions as a barrier insulating film that suppresses impurities such as water and hydrogen from diffusing into the insulator 280 from above.
  • the insulator 283 is placed on top of the insulator 282.
  • a nitride containing silicon such as silicon nitride or silicon nitride oxide.
  • silicon nitride formed by a sputtering method may be used as the insulator 283.
  • a silicon nitride film having a high density can be formed.
  • silicon nitride formed by the PEALD method or the CVD method may be further laminated on the silicon nitride formed by the sputtering method.
  • the capacitive element 100 is arranged in the openings formed in the insulator 271, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285, and is in contact with the upper surface of the conductor 242b. It has an insulator 110, an insulator 130 on the insulator 283, and a conductor 120 on the insulator 130.
  • the conductor 120 has a laminated structure of the conductor 120a on the insulator 130 and the conductor 120b on the conductor 120a.
  • the part is arranged.
  • the conductor 110 functions as a lower electrode of the capacitive element 100
  • the conductor 120 functions as an upper electrode of the capacitive element 100
  • the insulator 130 functions as a dielectric of the capacitive element 100.
  • the upper electrode and the lower electrode are dielectrics not only on the bottom surface but also on the side surface at the openings of the insulator 271, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285. It is configured to face each other with a., And the capacitance per unit area can be increased. Therefore, the deeper the depth of the opening, the larger the capacitance of the capacitive element 100 can be. By increasing the capacitance per unit area of the capacitive element 100 in this way, it is possible to promote miniaturization or high integration of the semiconductor device.
  • the shape of the openings formed in the insulator 271, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285 as viewed from the upper surface may be a quadrangle or a polygonal shape other than the quadrangle. It may be a polygonal shape with curved corners, or a circular shape including an ellipse.
  • it is preferable that the area where the opening and the transistor 200 overlap is large in the top view.
  • it is preferable to provide the capacitive element 100 so that the capacitive element 100 is within the range of the conductor 242b in the top view.
  • the length of the conductor 110 in the channel width direction is smaller than the length of the conductor 242b in the channel width direction.
  • the occupied area of the semiconductor device having the capacitive element 100 and the transistor 200 can be reduced.
  • the present invention is not limited to this, and the length of the conductor 110 in the channel width direction may be larger than the length of the conductor 242b in the channel width direction.
  • the conductor 110 is arranged along the openings formed in the insulator 271, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285.
  • the side surface and the bottom surface of the opening have a shape joined by a curved surface. With such a configuration, the conductor 110 can be formed into a film with good coverage at the opening.
  • the height of a part of the upper surface of the conductor 110 substantially coincides with the height of the upper surface of the insulator 285. Further, the upper surface of the conductor 242b is in contact with the lower surface of the conductor 110.
  • the conductor 110 is preferably formed into a film by using an ALD method, a CVD method, or the like, and the conductor shown in the previous embodiment may be used.
  • the conductor 110 titanium nitride formed by using the thermal ALD method can be used as the conductor 110.
  • the insulator 130 is arranged so as to cover a part of the conductor 110, the insulator 245, and the insulator 285.
  • the height of the upper surface of the region that overlaps with the insulator 130 may be higher than the height of the upper surface of the region that does not overlap with the insulator 130.
  • the insulator 130 is preferably formed into a film by using an ALD method, a CVD method, or the like. It is preferable to use a material capable of having ferroelectricity for the insulator 130.
  • Materials that can have strong dielectric properties include hafnium oxide, zirconium oxide, HfZrOX ( X is a real number larger than 0), hafnium oxide and element J1 (here, element J1 is zirconium (Zr), silicon. (Si), aluminum (Al), gadrinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) added to zirconium oxide with element J2 (element J2 here is hafnium) (Hf), silicon (Si), aluminum (Al), gadrinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) are added to the material.
  • PbTIO X barium titanate strontium (BST), barium titanate, lead zirconate titanate (PZT), strontium bismuthate tantanate (SBT), bismuth ferrite (BFO).
  • BST barium titanate strontium
  • PZT barium titanate
  • SBT strontium bismuthate tantanate
  • BFO bismuth ferrite
  • Barium titanate, and the like, and a piezoelectric ceramic having a perovskite structure may be used.
  • the material capable of having ferroelectricity for example, a mixture or compound composed of a plurality of materials selected from the materials listed above can be used.
  • the insulator 130 may have a laminated structure composed of a plurality of materials selected from the materials listed above.
  • the crystal structure (characteristics) of hafnium oxide, zirconium oxide, HfZrOX , and materials obtained by adding the element J1 to hafnium oxide may change not only depending on the film forming conditions but also depending on various processes.
  • a material exhibiting ferroelectricity is not only referred to as a ferroelectric substance, but also as a material capable of having ferroelectricity.
  • hafnium oxide, or a material having hafnium oxide and zirconium oxide as a material capable of having ferroelectricity is preferable because it can have ferroelectricity even when processed into a thin film of several nm.
  • the film thickness of the insulator 130 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and further preferably 10 nm or less.
  • the capacitive element 100 can be combined with the miniaturized transistor 200 to form a semiconductor device.
  • a layered material capable of having ferroelectricity may be referred to as a ferroelectric layer or a metal oxide film.
  • a non-volatile storage element can be formed by using a capacitive element (hereinafter, may be referred to as a ferroelectric capacitor) using the material as a dielectric.
  • a non-volatile storage element using a ferroelectric capacitor may be referred to as a FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, or the like.
  • a ferroelectric memory may have a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor may be electrically connected to one terminal of the ferroelectric capacitor. Therefore, the semiconductor device having the capacitive element 100 and the transistor 200 shown in the present embodiment can function as a ferroelectric memory.
  • the insulator 130 may have a laminated structure of the above-mentioned material having ferroelectricity and a material having a large dielectric strength.
  • Materials with high dielectric strength include silicon oxide, silicon nitride, silicon nitride, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, and oxidation with pores. There are silicon or resin.
  • the conductor 120 is arranged so as to fill the openings formed in the insulator 271, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285.
  • the conductor 120 has a region overlapping with the insulator 285 via the insulator 130.
  • the conductor 120 can be insulated from the conductor 110 via the insulator 130.
  • the portion of the conductor 120 above the insulator 283 may be routed and formed in a wiring shape.
  • the conductor 120 preferably has a conductor 120a and a conductor 120b on the conductor 120a.
  • the conductor 120a may be provided with a thin conductive film having a good covering property on the insulator 130.
  • the conductor 120b may be arranged so as to embed an opening on the conductor 120a.
  • the conductor 120a is preferably formed into a film by using an ALD method, a CVD method, or the like, and the conductor shown in the previous embodiment may be used.
  • the conductor 120a titanium nitride formed by the ALD method can be used as the conductor 120a.
  • the conductor 120b is preferably formed into a film by using an ALD method, a CVD method, a sputtering method, or the like, and the conductor shown in the previous embodiment may be used.
  • As the conductor 120b tungsten formed by a sputtering method can be used.
  • the conductor 120 is not limited to the two-layer structure, and may be a single-layer structure or a laminated structure having three or more layers.
  • a conductor that functions as wiring may be arranged in contact with the upper surface of the conductor 120.
  • the conductor it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.
  • the conductor may be formed so as to be embedded in an opening provided in the insulator.
  • the insulator 245 is arranged in contact with the side surfaces of the insulator 271, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285.
  • the conductor 110 is provided in contact with the inner side surface of the insulator 245, the insulator 130 is provided in contact with the inner side surface of the conductor 110, and the conductor 120 is provided in contact with the inner side surface of the insulator 130. ..
  • a barrier insulating film that can be used for the insulator 275 or the like may be used.
  • an insulator such as silicon nitride, aluminum oxide, or silicon nitride may be used. Since the insulator 245 is provided in contact with the insulator 283, the insulator 282, the insulator 275, and the insulator 271, impurities such as water and hydrogen contained in the insulator 280 or the insulator 285 are contained in the conductor 110. It can be suppressed from being mixed in the oxide 230 through.
  • silicon nitride is suitable because it has a high blocking property against hydrogen. Further, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductor 110.
  • the first insulator in contact with the inner wall of the opening such as the insulator 280 and the second insulator inside thereof are a barrier insulating film against oxygen.
  • a barrier insulating film against hydrogen it is preferable to use a barrier insulating film against hydrogen in combination.
  • aluminum oxide formed by the ALD method may be used as the first insulator, and silicon nitride formed by the PEALD method may be used as the second insulator.
  • the insulator 2445 the configuration in which the first insulator and the second insulator are laminated is shown, but the present invention is not limited to this.
  • the insulator 245 may be provided as a single layer or a laminated structure having three or more layers.
  • an insulator substrate for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), a resin substrate, and the like.
  • the semiconductor substrate include a semiconductor substrate made of silicon and germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide.
  • the conductor substrate includes a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate and the like.
  • the substrate having a metal nitride there are a substrate having a metal oxide, and the like.
  • a substrate in which a conductor or a semiconductor is provided in an insulator substrate a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like.
  • those on which an element is provided may be used.
  • Elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a storage element, and the like.
  • Insulator examples include oxides having insulating properties, nitrides, nitride oxides, nitride oxides, metal oxides, metal oxide nitrides, metal nitride oxides and the like.
  • Examples of the insulator having a high specific dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, nitrides having aluminum and hafnium, oxides having silicon and hafnium, silicon and hafnium. There are nitrides having oxides, or nitrides having silicon and hafnium.
  • Examples of the insulator having a low relative permittivity include silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and empty. There are silicon oxide with pores, resin, and the like.
  • the transistor using a metal oxide can stabilize the electrical characteristics of the transistor by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen.
  • the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, tantalum, and zirconium. Insulations containing, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in layers.
  • an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen
  • Metal oxides such as tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride, and silicon nitride can be used.
  • the insulator that functions as a gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating.
  • the oxygen deficiency of the oxide 230 can be compensated by having the structure in which silicon oxide or silicon oxide having a region containing oxygen desorbed by heating is in contact with the oxide 230.
  • Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, berylium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from the above, an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like.
  • tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferable.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
  • a plurality of conductive layers formed of the above materials may be laminated and used.
  • a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined.
  • a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined.
  • a laminated structure may be formed in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.
  • a laminated structure in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined is used for the conductor functioning as a gate electrode.
  • a conductive material containing oxygen may be provided on the channel forming region side.
  • the conductor that functions as the gate electrode it is preferable to use a conductive material containing a metal element and oxygen contained in the metal oxide in which the channel is formed.
  • the above-mentioned conductive material containing a metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride and tantalum nitride may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added.
  • Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • Metal Oxide As the oxide 230, it is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor.
  • a metal oxide oxide semiconductor
  • the metal oxide applicable to the oxide 230 according to the present invention will be described.
  • the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, it is preferable that aluminum, gallium, yttrium, tin and the like are contained. Further, one or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt and the like may be contained.
  • the metal oxide is an In-M-Zn oxide having indium, the element M, and zinc.
  • the element M is aluminum, gallium, yttrium, or tin.
  • Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt and the like.
  • the element M a plurality of the above-mentioned elements may be combined in some cases.
  • a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, the metal oxide having nitrogen may be referred to as a metal oxide.
  • FIG. 13A is a diagram illustrating the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).
  • IGZO a metal oxide containing In, Ga, and Zn
  • oxide semiconductors are roughly classified into “Amorphous”, “Crystalline”, and “Crystal”.
  • Amorphous includes “completable amorphous”.
  • Crystalline includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned crystal) (exclusion single crystal).
  • single crystal, poly crystal, and single crystal amorphous are excluded from the classification of "Crystalline”.
  • “Crystal” includes single crystal and poly crystal.
  • the structure in the thick frame shown in FIG. 13A is an intermediate state between "Amorphous” and “Crystal", and belongs to a new boundary region (New crystal line phase). .. That is, the structure can be rephrased as a structure completely different from the energetically unstable "Amorphous” and "Crystal".
  • the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum.
  • XRD X-ray diffraction
  • the GIXD method is also referred to as a thin film method or a Seemann-Bohlin method.
  • the XRD spectrum obtained by the GIXD measurement shown in FIG. 13B may be simply referred to as an XRD spectrum in the present specification.
  • the thickness of the CAAC-IGZO film shown in FIG. 13B is 500 nm.
  • the horizontal axis is 2 ⁇ [deg. ], And the vertical axis is intensity [a. u. ].
  • a peak showing clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film.
  • the crystal structure of the film or the substrate can be evaluated by a diffraction pattern (also referred to as a microelectron diffraction pattern) observed by a micro electron diffraction method (NBED: Nano Beam Electron Diffraction).
  • the diffraction pattern of the CAAC-IGZO film is shown in FIG. 13C.
  • FIG. 13C is a diffraction pattern observed by the NBED in which the electron beam is incident parallel to the substrate.
  • electron diffraction is performed with the probe diameter set to 1 nm.
  • oxide semiconductors may be classified differently from FIG. 13A.
  • oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
  • the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS.
  • the non-single crystal oxide semiconductor includes a polycrystal oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: atomous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.
  • CAAC-OS CAAC-OS
  • nc-OS nc-OS
  • a-like OS the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.
  • CAAC-OS is an oxide semiconductor having a plurality of crystal regions, the plurality of crystal regions having the c-axis oriented in a specific direction.
  • the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface to be formed of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film.
  • the crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region in which the lattice arrangement is aligned. Further, the CAAC-OS has a region in which a plurality of crystal regions are connected in the ab plane direction, and the region may have distortion.
  • the strain refers to a region in which a plurality of crystal regions are connected in which the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another grid arrangement is aligned. That is, CAAC-OS is an oxide semiconductor that is c-axis oriented and not clearly oriented in the ab plane direction.
  • Each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystal region is less than 10 nm.
  • the size of the crystal region may be about several tens of nm.
  • CAAC-OS has indium (In) and oxygen. It tends to have a layered crystal structure (also referred to as a layered structure) in which a layer (hereinafter, In layer) and a layer having elements M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are laminated. There is. Indium and element M can be replaced with each other. Therefore, the (M, Zn) layer may contain indium. In addition, the In layer may contain the element M. The In layer may contain Zn.
  • the layered structure is observed as a grid image, for example, in a high-resolution TEM image.
  • the position of the peak indicating the c-axis orientation may vary depending on the type and composition of the metal elements constituting CAAC-OS.
  • a plurality of bright spots are observed in the electron diffraction pattern of the CAAC-OS film. Note that a certain spot and another spot are observed at point-symmetrical positions with the spot of the incident electron beam transmitted through the sample (also referred to as a direct spot) as the center of symmetry.
  • the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit lattice is not limited to a regular hexagon and may be a non-regular hexagon. Further, in the above strain, it may have a lattice arrangement such as a pentagon or a heptagon.
  • a clear grain boundary cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between the atoms changes due to the replacement of metal atoms. it is conceivable that.
  • CAAC-OS for which no clear crystal grain boundary is confirmed, is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor.
  • a configuration having Zn is preferable.
  • In-Zn oxide and In-Ga-Zn oxide are more suitable than In oxide because they can suppress the generation of grain boundaries.
  • CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries can be confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries. Further, since the crystallinity of the oxide semiconductor may be deteriorated due to the mixing of impurities, the generation of defects, etc., CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability. CAAC-OS is also stable against high temperatures (so-called thermal budgets) in the manufacturing process. Therefore, if CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be expanded.
  • nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
  • nc-OS has tiny crystals. Since the size of the minute crystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystal is also referred to as a nanocrystal.
  • nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film.
  • nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductor depending on the analysis method.
  • a peak indicating crystallinity is not detected in the Out-of-plane XRD measurement using a ⁇ / 2 ⁇ scan.
  • electron beam diffraction also referred to as selected area electron diffraction
  • a diffraction pattern such as a halo pattern is performed. Is observed.
  • electron diffraction also referred to as nanobeam electron diffraction
  • an electron beam having a probe diameter for example, 1 nm or more and 30 nm or less
  • An electron diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be acquired.
  • the a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a void or low density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.
  • a-like OS has a higher hydrogen concentration in the membrane than nc-OS and CAAC-OS.
  • CAC-OS relates to the material composition.
  • CAC-OS is, for example, a composition of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size in the vicinity thereof.
  • the mixed state is also called a mosaic shape or a patch shape.
  • the CAC-OS has a structure in which the material is separated into a first region and a second region to form a mosaic, and the first region is distributed in the film (hereinafter, also referred to as a cloud shape). It is said.). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.
  • the atomic number ratios of In, Ga, and Zn to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are expressed as [In], [Ga], and [Zn], respectively.
  • the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film.
  • the second region is a region in which [Ga] is larger than [Ga] in the composition of the CAC-OS film.
  • the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region.
  • the second region is a region in which [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.
  • the first region is a region in which indium oxide, indium zinc oxide, or the like is the main component.
  • the second region is a region containing gallium oxide, gallium zinc oxide, or the like as a main component. That is, the first region can be rephrased as a region containing In as a main component. Further, the second region can be rephrased as a region containing Ga as a main component.
  • a region containing In as a main component (No. 1) by EDX mapping acquired by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region (1 region) and the region containing Ga as a main component (second region) are unevenly distributed and have a mixed structure.
  • CAC-OS When CAC-OS is used for a transistor, the conductivity caused by the first region and the insulating property caused by the second region act in a complementary manner to switch the switching function (On / Off function). Can be added to CAC-OS. That is, the CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS for the transistor, high on -current (Ion), high field effect mobility ( ⁇ ), and good switching operation can be realized.
  • Ion on -current
  • ⁇ high field effect mobility
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor of one aspect of the present invention has two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS. You may.
  • the oxide semiconductor as a transistor, a transistor with high field effect mobility can be realized. In addition, a highly reliable transistor can be realized.
  • the carrier concentration in the channel formation region of the oxide semiconductor is 1 ⁇ 10 17 cm -3 or less, preferably 1 ⁇ 10 15 cm -3 or less, more preferably 1 ⁇ 10 13 cm -3 or less, and more preferably 1 ⁇ . It is 10 11 cm -3 or less, more preferably 1 ⁇ 10 10 cm -3 or less, and 1 ⁇ 10 -9 cm -3 or more.
  • the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
  • a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • An oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • the trap level density may also be low.
  • the charge captured at the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel forming region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • the concentration of silicon and carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon near the interface with the channel formation region of the oxide semiconductor is 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor contains an alkali metal or an alkaline earth metal
  • defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less. ..
  • the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms. / Cm 3 or less, more preferably 5 ⁇ 10 17 atoms / cm 3 or less.
  • hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency.
  • oxygen deficiency When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated.
  • a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the channel forming region of the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 5 ⁇ 10 19 atoms / cm 3 , more preferably 1 ⁇ 10. It should be less than 19 atoms / cm 3 , more preferably less than 5 ⁇ 10 18 atoms / cm 3 , and even more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • the semiconductor material that can be used for the oxide 230 is not limited to the above-mentioned metal oxide.
  • a semiconductor material having a bandgap (a semiconductor material that is not a zero-gap semiconductor) may be used.
  • a semiconductor of a simple substance element such as silicon, a compound semiconductor such as gallium arsenide, a layered substance (also referred to as an atomic layer material, a two-dimensional material, etc.) that functions as a semiconductor, and the like as a semiconductor material.
  • the layered substance is a general term for a group of materials having a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent or ionic bonds are laminated via bonds that are weaker than covalent or ionic bonds, such as van der Waals forces.
  • the layered material has high electrical conductivity in the unit layer, that is, high two-dimensional electrical conductivity.
  • Chalcogenides are compounds containing chalcogens. Chalcogen is a general term for elements belonging to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and group 13 chalcogenides.
  • oxide 230 for example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor.
  • Specific transition metal chalcogenides applicable as oxide 230 include molybdenum sulfide (typically MoS 2 ), molybdenum selenate (typically MoSe 2 ), and molybdenum tellurium (typically MoTe 2 ).
  • Tungsten disulfide typically WS 2
  • Tungsten disulfide typically WSe 2
  • Tungsten tellurium typically WTe 2
  • Hafnium sulfide typically HfS 2
  • Hafnium serene typically typically
  • Typical examples include HfSe 2 ), zirconium sulfide (typically ZrS 2 ), and zirconium selenium (typically ZrSe 2 ).
  • FIG. A shows a top view of the semiconductor device.
  • FIG. B is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A1-A2 shown in each FIG. A.
  • some elements are omitted for the sake of clarity of the figure.
  • the same reference numerals are added to the structures having the same functions as the structures constituting the semiconductor devices shown in ⁇ Semiconductor device configuration example>.
  • the materials described in detail in ⁇ Semiconductor device configuration example> can be used as the constituent materials of the semiconductor device.
  • the semiconductor device shown in FIGS. 14A and 14B is a modification of the semiconductor device shown in FIGS. 11A to 11D.
  • the semiconductor device shown in FIGS. 14A and 14B is different from the semiconductor device shown in FIGS. 11A to 11D in that the conductor 240 and the conductor 246 are provided.
  • the conductor 240 functions as a plug electrically connected to one of the source and drain of the transistor 200
  • the conductor 246 functions as a wiring connected to the plug.
  • the conductor 240 is provided so as to embed the openings formed in the insulator 271, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285.
  • the lower surface of the conductor 240 is in contact with the upper surface of the conductor 242a.
  • the conductor 240 it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor 240 may have a laminated structure of a first conductor having a thin film thickness provided along the side surface and the bottom surface of the opening and the second conductor on the first conductor.
  • a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen is used for the first conductor arranged in the vicinity of the insulator 285 and the insulator 280.
  • a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen is used for the first conductor arranged in the vicinity of the insulator 285 and the insulator 280.
  • tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminated manner.
  • impurities such as water and hydrogen contained in the layer above the insulator 283 can be suppressed from being mixed into the oxide 230 through the conductor 240.
  • the above-mentioned conductive material containing tungsten, copper, or aluminum as a main component may be used.
  • the conductor 240 shown in FIG. 14B shows a configuration in which the first conductor and the second conductor are laminated, but the present invention is not limited to this.
  • the conductor 240 may be provided as a single layer or a laminated structure having three or more layers.
  • the conductor 246 may be arranged in contact with the upper surface of the conductor 240.
  • the conductor 246 it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor 246 may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.
  • the height of the upper surface of the region that overlaps with the conductor 246 may be higher than the height of the upper surface of the region that does not overlap with the conductor 246.
  • the conductor 246 may be formed so as to be embedded in an opening provided in the insulator.
  • an insulator 241 that functions as a barrier insulating film is provided between the conductor 240 and the insulator 280.
  • the insulator 245 is preferably arranged in contact with the side surfaces of the openings formed in the insulator 271, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285.
  • the insulator 241 preferably has the same structure as the above-mentioned insulator 245.
  • the insulator 286 is provided so as to cover the conductor 246 and the insulator 285.
  • the insulator 286 may be formed by using an insulating material that can be used for the insulator 285.
  • This modification is a configuration in which the capacitive element 100 is formed after the conductor 240 and the conductor 246 are formed. Therefore, unlike the semiconductor devices shown in FIGS. 11A to 11D, a part of the lower surface of the insulator 130 and a part of the side surface of the insulator 245 are in contact with the insulator 286. That is, the opening in which the capacitive element 100 is embedded is deepened corresponding to the thickness of the insulator 286. As a result, the capacitance of the capacitive element 100 can be increased without increasing the occupied area of the semiconductor device.
  • the semiconductor device shown in FIGS. 15A and 15B is a modification of the semiconductor device shown in FIGS. 11A to 11D.
  • the semiconductor device shown in FIGS. 15A and 15B has an insulator 241a, a conductor 240a, and a conductor 246a on the conductor 242a, similarly to the semiconductor device shown in FIGS. 16A and 16B. Further, on the conductor 120, the insulator 241b, the conductor 240b and the conductor 246b are provided.
  • the conductor 240b functions as a plug electrically connected to one of the terminals of the capacitive element 100, and the conductor 246b functions as a wiring connected to the plug.
  • the same conductive material as the above-mentioned insulator 241 can be used.
  • the conductor 240a and the conductor 240b the same conductive material as the above-mentioned conductor 240 can be used.
  • the conductor 246a and the conductor 246b the same conductive material as the conductor 246 described above can be used.
  • the semiconductor devices shown in FIGS. 15A and 15B have a configuration in which the conductor 240a and the conductor 240b are formed after the capacitive element 100 is formed. Therefore, the lower surfaces of the conductor 246a and the conductor 246b come into contact with the upper surface of the insulator 285 formed by covering the conductor 120.
  • the semiconductor devices shown in FIGS. 15A and 15B do not have an interlayer insulating film between the insulator 283 and the insulator 130, and the lower surface of the insulator 130 is not provided.
  • the upper surface of the insulator 283 is in contact with the insulator 283.
  • the semiconductor device shown in FIGS. 16A and 16B is a modification of the semiconductor device shown in FIGS. 15A and 15B.
  • the semiconductor device shown in FIGS. 16A and 16B is different from the semiconductor device shown in FIGS. 15A and 15B in that the insulator 283 is in contact with a part of the upper surface of the insulator 212. Therefore, the transistor 200 is arranged in the region sealed by the insulator 283 and the insulator 212. With the above configuration, it is possible to prevent hydrogen contained outside the sealed region from being mixed into the sealed region. Further, in the transistor 200 shown in FIGS.
  • the configuration in which the insulator 212 and the insulator 283 are provided as a single layer is shown, but the present invention is not limited thereto.
  • the insulator 212 and the insulator 283 may each be provided as a laminated structure having two or more layers.
  • FIG. 17A shows a top view of the semiconductor device 500.
  • the x-axis shown in FIG. 17A is parallel to the channel length direction of the transistor 200, and the y-axis is perpendicular to the x-axis.
  • FIG. 17B is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line of A1-A2 shown in FIG. 17A, and is also a cross-sectional view of the transistor 200 in the channel length direction.
  • FIG. 17C is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A3-A4 shown in FIG. 17A, and is also a cross-sectional view of the opening region 400 and its vicinity.
  • some elements are omitted for the purpose of clarifying the figure.
  • the same reference numerals are added to the structures having the same functions as the structures constituting the semiconductor devices shown in ⁇ Semiconductor device configuration example>.
  • the materials described in detail in ⁇ Semiconductor device configuration example> can be used as the constituent materials of the semiconductor device.
  • the semiconductor device 500 shown in FIGS. 17A to 17C is a modification of the semiconductor device shown in FIGS. 11A to 11D.
  • the semiconductor device 500 shown in FIGS. 17A to 17C is different from the semiconductor device shown in FIGS. 11A to 11D in that the opening region 400 is formed in the insulator 282 and the insulator 280. Further, it differs from the semiconductor device shown in FIGS. 11A to 11D in that the sealing portion 265 is formed so as to surround the plurality of transistors 200 and the capacitive element 100.
  • the semiconductor device 500 has a plurality of transistors 200, a plurality of capacitive elements 100, and a plurality of aperture regions 400 arranged in a matrix. Further, a plurality of conductors 260 that function as gate electrodes of the transistor 200 are provided so as to extend in the y-axis direction.
  • the opening region 400 is formed in a region that does not overlap with the oxide 230 and the conductor 260. Further, the sealing portion 265 is formed so as to surround the plurality of transistors 200, the plurality of capacitive elements 100, the plurality of conductors 260, and the plurality of opening regions 400.
  • the number, arrangement, and size of the transistor 200, the capacitive element 100, the conductor 260, and the opening region 400 are not limited to the structure shown in FIG. 17, and may be appropriately set according to the design of the semiconductor device 500. good.
  • the sealing portion 265 is provided so as to surround the plurality of transistors 200, the insulator 216, the insulator 222, the insulator 275, the insulator 280, and the insulator 282.
  • the insulator 283 is provided so as to cover the insulator 216, the insulator 222, the insulator 275, the insulator 280, and the insulator 282.
  • the insulator 283 is in contact with the upper surface of the insulator 214.
  • an insulator 274 is provided between the insulator 283 and the insulator 285.
  • the height of the upper surface of the insulator 274 is substantially the same as that of the uppermost surface of the insulator 283.
  • the same insulator as the insulator 280 can be used.
  • a plurality of transistors 200 can be wrapped (sealed) with the insulator 283, the insulator 214, and the insulator 212.
  • one or more of the insulator 283, the insulator 214, and the insulator 212 preferably functions as a barrier insulating film against hydrogen.
  • the insulator 283, the insulator 214, and the insulator 212 having such a function may be referred to as a sealing film.
  • the insulator 282 has an opening. Further, in the opening region 400, the insulator 280 may overlap with the opening of the insulator 282 and have a groove portion. The depth of the groove portion of the insulator 280 may be set so that the upper surface of the insulator 275 is exposed at the deepest, and may be, for example, about 1/4 or more and 1/2 or less of the maximum film thickness of the insulator 280.
  • the insulator 283 is in contact with the side surface of the insulator 282, the side surface of the insulator 280, and the upper surface of the insulator 280 inside the opening region 400. Further, in the opening region 400, a part of the insulator 274 may be formed so as to embed the recess formed in the insulator 283. At this time, the height of the upper surface of the insulator 274 formed in the opening region 400 and the height of the uppermost surface of the insulator 283 may be substantially the same.
  • hydrogen contained in the insulator 280 can be combined with oxygen and released to the outside through the opening region 400. Hydrogen combined with oxygen is released as water. Therefore, it is possible to reduce the hydrogen contained in the insulator 280 and reduce the hydrogen contained in the insulator 280 from being mixed in the oxide 230.
  • the shape of the opening region 400 in the top view is substantially rectangular, but the present invention is not limited to this.
  • the shape of the opening region 400 in the top view may be a rectangle, an ellipse, a circle, a rhombus, or a combination thereof.
  • the area of the opening region 400 and the arrangement interval can be appropriately set according to the design of the semiconductor device including the transistor 200. For example, in a region where the density of the transistor 200 is low, the area of the opening region 400 may be increased or the arrangement interval of the opening regions 400 may be narrowed. Further, for example, in a region where the density of the transistor 200 is high, the area of the opening region 400 may be narrowed or the arrangement interval of the opening region 400 may be widened.
  • a new transistor can be provided.
  • a semiconductor device having little variation in transistor characteristics Alternatively, one aspect of the present invention can provide a semiconductor device having good electrical characteristics. Alternatively, one aspect of the present invention can provide a semiconductor device with good reliability.
  • a semiconductor device having low power consumption can be provided.
  • a capacitive element containing a material capable of having ferroelectricity it is possible to provide a capacitive element containing a material capable of having ferroelectricity.
  • the capacitive element can be provided with good productivity.
  • the semiconductor device capable of miniaturization or high integration can be provided.
  • FIG. 18 shows an example of a semiconductor device (storage device) according to one aspect of the present invention.
  • the transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above the transistor 300 and the transistor 200.
  • the transistor 200 the transistor 200 described in the previous embodiment can be used.
  • the capacitive element 100 the capacitive element 100 described in the previous embodiment can be used.
  • FIG. 18 shows an example in which the capacitive element 100 and the transistor 200 shown in FIG. 14 are used, the present invention is not limited to this, and the capacitive element 100 and the transistor 200 can be appropriately selected.
  • the capacitive element 100 is made of a material capable of having a ferroelectricity, which has a property that polarization is generated inside by applying an electric field from the outside and the polarization remains even if the electric field is set to zero. This makes it possible to form a non-volatile storage element using the capacitive element 100. That is, a 1-transistor 1-capacitor type ferroelectric memory can be formed by using a capacitive element that functions as a ferroelectric capacitor and a transistor 200.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor.
  • the transistor 200 has a characteristic of having a high withstand voltage. Therefore, by using an oxide semiconductor for the transistor 200, a high voltage can be applied to the transistor 200 even if the transistor 200 is miniaturized. By miniaturizing the transistor 200, the occupied area of the semiconductor device can be reduced.
  • the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Further, the wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to one of the first gates of the transistor 200, and the wiring 1005 is electrically connected to one of the electrodes of the capacitive element 100. The wiring 1006 is electrically connected to the second gate of the transistor 200, and the wiring 1007 is electrically connected to the gate of the transistor 300.
  • the storage devices shown in FIG. 18 can form a memory cell array by arranging them in a matrix.
  • the transistor 300 is provided on the substrate 311 and has a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is a part of the substrate 311 and a low that functions as a source region or a drain region. It has a resistance region 314a and a low resistance region 314b.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • the semiconductor region 313 (a part of the substrate 311) in which the channel is formed has a convex shape. Further, the side surface and the upper surface of the semiconductor region 313 are provided so as to be covered by the conductor 316 via the insulator 315.
  • the conductor 316 may be made of a material that adjusts the work function. Since such a transistor 300 utilizes a convex portion of a semiconductor substrate, it is also called a FIN type transistor. In addition, it may have an insulator that is in contact with the upper part of the convex portion and functions as a mask for forming the convex portion. Further, although the case where a part of the semiconductor substrate is processed to form a convex portion is shown here, the SOI substrate may be processed to form a semiconductor film having a convex shape.
  • the transistor 300 shown in FIG. 18 is an example, and the transistor 300 is not limited to the structure thereof, and an appropriate transistor may be used according to the circuit configuration or the driving method.
  • a wiring layer provided with an interlayer film, wiring, a plug, and the like may be provided between the structures. Further, a plurality of wiring layers can be provided according to the design.
  • the conductor having a function as a plug or wiring may collectively give a plurality of structures the same reference numeral. Further, in the present specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated in this order on the transistor 300 as an interlayer film. Further, the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a capacitive element 100, a conductor 328 electrically connected to the transistor 200, a conductor 330, and the like. The conductor 328 and the conductor 330 function as a plug or wiring.
  • the insulator that functions as an interlayer film may function as a flattening film that covers the uneven shape below the insulator.
  • the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.
  • CMP chemical mechanical polishing
  • a wiring layer may be provided on the insulator 326 and the conductor 330.
  • the insulator 350, the insulator 352, and the insulator 354 are laminated in this order.
  • a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring.
  • the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are embedded with a conductor 218, a conductor (conductor 205) constituting the transistor 200, and the like.
  • the conductor 218 has a function as a plug or wiring for electrically connecting to the capacitive element 100 or the transistor 300.
  • the insulator 217 is provided in contact with the side surface of the conductor 218 that functions as a plug.
  • the insulator 217 is provided in contact with the inner wall of the opening formed in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. That is, the insulator 217 is provided between the conductor 218 and the insulator 210, the insulator 212, the insulator 214, and the insulator 216. Since the conductor 205 can be formed in parallel with the conductor 218, the insulator 217 may be formed in contact with the side surface of the conductor 205.
  • an insulator such as silicon nitride, aluminum oxide, or silicon nitride may be used. Since the insulator 217 is provided in contact with the insulator 210, the insulator 212, the insulator 214, and the insulator 222, impurities such as water or hydrogen from the insulator 210 or the insulator 216 or the like are oxidized through the conductor 218. It is possible to suppress mixing with the object 230. In particular, silicon nitride is suitable because it has a high blocking property against hydrogen. Further, it is possible to prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.
  • the insulator 217 can be formed in the same manner as the insulator 241.
  • silicon nitride may be formed into a film by using the PEALD method, and an opening reaching the conductor 356 may be formed by anisotropic etching.
  • the conductor 112 is provided on the insulator 285 and the conductor 240.
  • the conductor 112 has a function as a plug or wiring for electrically connecting to the transistor 200 or the transistor 300.
  • An insulator 286 is provided so as to cover the insulator 285 and the conductor 112.
  • An insulator 150 is provided so as to cover the insulator 286 and the capacitive element 100.
  • the insulator 285 and the conductor 112 may be covered with a barrier insulating film against hydrogen.
  • a barrier insulating film against hydrogen it is preferable to provide an insulator 152a that covers the insulator 285 and the conductor 112, and an insulator 152b on the insulator 152a.
  • a barrier insulating film that can be used for the above-mentioned insulator 283 or the like may be used.
  • the film of the insulator 152a may be formed by using a sputtering method.
  • a sputtering method silicon nitride formed by a sputtering method can be used. Since the sputtering method does not require the use of molecules containing hydrogen in the film-forming gas, the hydrogen concentration of the insulator 152a can be reduced. By reducing the hydrogen concentration of the insulator 152a in contact with the conductor 112 and the insulator 285 in this way, it is possible to suppress the diffusion of hydrogen from the insulator 152a to the conductor 112 and the insulator 285.
  • the insulator 152b is formed by using the ALD method, particularly the PEALD method.
  • the insulator 152b silicon nitride formed by the PEALD method can be used.
  • the insulator 152b can be formed into a film with good coverage. Therefore, even if pinholes or step breaks are formed in the insulator 152a due to the unevenness of the base, hydrogen can be formed by covering them with the insulator 152b. Can be reduced from diffusing into the conductor 112 and the insulator 285.
  • the film forming method of the insulator 152a and the insulator 152b is not limited to the sputtering method and the ALD method, and the CVD method, the MBE method, the PLD method and the like can be appropriately used. Further, although the two-layer structure of the insulator 152a and the insulator 152b is shown above, the present invention is not limited to this, and a single-layer structure or a laminated structure of three or more layers may be used.
  • the insulator 283 and the insulator 212 may also be a barrier insulating film having a laminated structure, similarly to the insulator 152a and the insulator 152b.
  • the insulator 286 and the capacitive element 100 may be covered with a barrier insulating film against hydrogen.
  • a barrier insulating film against hydrogen it is preferable to provide an insulator 154a that covers the insulator 286 and the capacitive element 100, and an insulator 154b on the insulator 154a.
  • the capacitive element 100 is sealed in the insulator 154a and the insulator 154b, and the insulator 154a and the insulator 154b function as a sealing film.
  • the insulator 154a can use the same barrier insulating film as the insulator 152a, and the insulator 154b can use the same barrier insulating film as the insulator 152b.
  • the insulator 154a and an insulator 154b it is possible to reduce the diffusion of impurities such as hydrogen contained in the insulator 150 and the like to the transistor 200 via the capacitive element 100.
  • Examples of the insulator that can be used as the interlayer film include oxides having insulating properties, nitrides, nitride oxides, nitride oxides, metal oxides, metal oxide nitrides, and metal nitride oxides.
  • the material may be selected according to the function of the insulator.
  • the insulator 150, the insulator 210, the insulator 352, the insulator 354, and the like have an insulator having a low relative permittivity.
  • the insulator preferably has silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having pores, or a resin.
  • the insulator may be silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, silicon oxide with carbon and nitrogen, or silicon oxide with pores.
  • silicon oxide and silicon oxide nitride are thermally stable, they can be combined with a resin to form a laminated structure that is thermally stable and has a low relative permittivity.
  • the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.
  • a transistor using an oxide semiconductor can stabilize the electrical characteristics of the transistor by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, for the insulator 214, the insulator 212, the insulator 350, and the like, an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used.
  • Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, tantalum, and zirconium. Insulations containing, lanthanum, neodymium, hafnium or tantalum may be used in a single layer or in layers.
  • an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or Metal oxides such as tantalum oxide, silicon nitride oxide, silicon nitride and the like can be used.
  • Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, berylium, and indium.
  • a material containing one or more metal elements selected from ruthenium and the like can be used.
  • a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and a silicide such as nickel silicide may be used.
  • the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, and the like include a metal material, an alloy material, a metal nitride material, a metal oxide material, and the like formed of the above materials.
  • a metal material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten.
  • it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.
  • the capacitive element 100 is insulated by forming the conductor 120a by a method involving substrate heating such as a thermal ALD method, so that the conductor 120a is not baked at a high temperature after formation.
  • the ferroelectricity of the body 130 can be increased. Therefore, since the semiconductor device can be manufactured without baking at a high temperature, a low resistance conductive material such as copper having a low melting point can be used.
  • an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor. In that case, it is preferable to provide an insulator having a barrier property between the insulator having the excess oxygen region and the conductor provided in the insulator having the excess oxygen region.
  • an insulator 241 between the insulator 224 and the insulator 280 having excess oxygen and the conductor 240.
  • the insulator 241 is provided in contact with the insulator 222, the insulator 282, and the insulator 283, so that the insulator 224 and the transistor 200 are sealed by an insulator having a barrier property. Can be done.
  • the insulator 241 it is possible to prevent the excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 240. Further, by having the insulator 241, it is possible to suppress the diffusion of hydrogen, which is an impurity, to the transistor 200 via the conductor 240.
  • an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide and the like.
  • silicon nitride is preferable because it has a high blocking property against hydrogen.
  • metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide can be used.
  • the transistor 200 may be configured to be sealed with an insulator 212, an insulator 214, an insulator 282, and an insulator 283.
  • an insulator 212, an insulator 214, an insulator 282, and an insulator 283 With such a configuration, it is possible to reduce the mixing of hydrogen contained in the insulator 274, the insulator 285, the insulator 150 and the like into the insulator 280 and the like.
  • the insulator 212, the insulator 214, the insulator 282, and the insulator 283 function as a sealing film.
  • the conductor 240 penetrates the insulator 283 and the insulator 282, and the conductor 218 penetrates the insulator 214 and the insulator 212.
  • the insulator 241 is in contact with the conductor 240.
  • the insulator 217 is provided in contact with the conductor 218.
  • the transistor 200 is sealed with the insulator 212, the insulator 214, the insulator 282, the insulator 283, the insulator 241 and the insulator 217, and impurities such as hydrogen contained in the insulator 274 and the like are outside. It is possible to reduce contamination from.
  • one transistor 200 is shown in the region sealed by the insulator 212, the insulator 283, and the like, but the present invention is not limited to this, and the sealed region is not limited to this.
  • a plurality of transistors 200 can be provided.
  • a dicing line (sometimes referred to as a scribe line, a division line, or a cutting line) provided when a plurality of semiconductor devices are taken out in the form of chips by dividing a large-area substrate into semiconductor elements will be described. ..
  • a dividing method for example, there is a case where a groove (dicing line) for dividing a semiconductor element is first formed on a substrate, then the dicing line is cut, and the semiconductor device is divided (divided) into a plurality of semiconductor devices.
  • the region where the insulator 283 and the insulator 214 are in contact overlap with the dicing line it is preferable to design so that the region where the insulator 283 and the insulator 214 are in contact overlap with the dicing line. That is, openings are provided in the insulator 282, the insulator 280, the insulator 275, the insulator 222, and the insulator 216 in the vicinity of the region serving as the dicing line provided on the outer edge of the memory cell having the plurality of transistors 200.
  • the insulator 214 and the insulator 283 come into contact with each other at the openings provided in the insulator 282, the insulator 280, the insulator 275, the insulator 222, and the insulator 216.
  • openings may be provided in the insulator 282, the insulator 280, the insulator 275, the insulator 222, the insulator 216, and the insulator 214.
  • the insulator 212 and the insulator 283 come into contact with each other at the openings provided in the insulator 282, the insulator 280, the insulator 275, the insulator 222, the insulator 216, and the insulator 214. ..
  • the insulator 212 and the insulator 283 may be formed by using the same material and the same method. By providing the insulator 212 and the insulator 283 with the same material and the same method, the adhesion can be enhanced. For example, it is preferable to use silicon nitride.
  • the transistor 200 can be wrapped by the insulator 212, the insulator 214, the insulator 282, and the insulator 283. Since at least one of the insulator 212, the insulator 214, the insulator 282, and the insulator 283 has a function of suppressing the diffusion of oxygen, hydrogen, and water, the semiconductor element shown in the present embodiment is formed. By dividing the substrate for each circuit region, even if it is processed into a plurality of chips, impurities such as hydrogen or water are prevented from being mixed in from the side surface direction of the divided substrate and diffused to the transistor 200. Can be done.
  • the structure can prevent the excess oxygen of the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen of the insulator 280 and the insulator 224 is efficiently supplied to the oxide in which the channel is formed in the transistor 200.
  • the oxygen can reduce the oxygen deficiency of the oxide in which the channel is formed in the transistor 200.
  • the oxide in which the channel is formed in the transistor 200 can be made into an oxide semiconductor having a low defect level density and stable characteristics. That is, it is possible to suppress fluctuations in the electrical characteristics of the transistor 200 and improve reliability.
  • the capacitive element 100 is formed so as to be embedded in the insulator 285, the insulator 280, or the like, but the present invention is not limited thereto. As shown in FIG. 19, the planar type capacitive element 100 may be provided on the insulator 285.
  • the capacitive element 100 has a conductor 110, an insulator 130 that covers the conductor 110, and a conductor 120 (conductor 120a and conductor 120b) that covers the insulator 130.
  • the insulator 130 covers the upper surface and the side surface of the conductor 110 to separate the conductor 110 from the conductor 120.
  • the conductor 110, the insulator 130, and the conductor 120 [constituent example of the storage device] and the description of the previous embodiment can be referred to.
  • the conductor 110 is formed in the same layer as the conductor 112 and is in contact with the upper surface of the conductor 240.
  • the conductor 110 is electrically connected to one of the source and drain of the transistor 200 via the conductor 240.
  • the insulator 155 is provided so as to cover the conductor 120, the insulator 130, and the conductor 112.
  • an insulator having a function of capturing and fixing hydrogen which can be used for the insulator 214, the insulator 282, or the like.
  • aluminum oxide AlO x (x is an arbitrary number larger than 0)
  • the AlO x preferably has an amorphous structure. In such a metal oxide having an amorphous structure, the oxygen atom has a dangling bond, and the dangling bond may have a property of capturing or fixing hydrogen.
  • the insulator 155 aluminum oxide formed by the ALD method or an aluminum oxide film formed by the sputtering method can be used. Further, for example, the insulator 155 may be a laminated film of aluminum oxide formed by the ALD method and aluminum oxide formed on the aluminum oxide by the sputtering method.
  • the insulator 155 By providing such an insulator 155 so as to cover the capacitance element 100, hydrogen contained in the insulator 130 of the capacitance element 100 can be captured and fixed, and the hydrogen concentration in the insulator 130 can be reduced. As a result, the crystallinity of the insulator 130 can be improved, and the ferroelectricity of the insulator 130 can be enhanced. Further, the leakage current between the conductor 110 and the conductor 120 can be reduced.
  • the configuration is not limited to this, and the insulator 155 may not be provided.
  • the insulator 152a and the insulator 152b which function as a barrier insulating film against hydrogen, on the conductor 112 and the conductor 120.
  • the insulator 152a and the insulator 152b are provided on the insulator 155.
  • an insulator 287 that functions as a barrier insulating film against hydrogen on the insulator 285.
  • a conductor 112, a conductor 110, and an insulator 155 are provided in contact with the insulator 287.
  • the insulator 287 the same barrier insulating film as the insulator 283 can be used.
  • the insulator 155 and the insulator 287 are in contact with each other in a region that does not overlap with the capacitive element 100. That is, the capacitive element 100 is sealed by the insulator 155, the insulator 152a, the insulator 152b, and the insulator 287.
  • the insulator 155, the insulator 152a, the insulator 152b, and the insulator 287 function as a sealing film.
  • the insulator 287 and the insulator 152a are in contact with each other in a region that does not overlap with the capacitance element 100, and the insulator 152a, the insulator 152b, and the insulator 287 make the capacitance element 100. Is sealed.
  • the transistor 200 is also sealed with an insulator 283, an insulator 214, and an insulator 212, which function as a barrier insulating film against hydrogen.
  • an insulator 283, an insulator 214, and an insulator 212 which function as a barrier insulating film against hydrogen.
  • the storage device shown in FIG. 19 has a configuration in which the transistor 200 and the capacitive element 100 are electrically connected, but the present invention is not limited to this. As shown in FIG. 20A, the transistor 200 and the capacitive element 100 may be configured not to be electrically connected.
  • the storage device shown in FIG. 20A has the same configuration as the storage device shown in FIG. 19 for the transistor 200 and the capacitive element 100 above the insulator 212.
  • the structure below the insulator 212 may be the same as that of the storage device shown in FIG. 19, or the substrate 311 may be provided in contact with the bottom of the insulator 212.
  • an opening may be formed in the insulator 286, the insulator 152b, the insulator 152a, and the insulator 155, and the conductor 288 and the insulator 289 may be provided so as to embed the opening. good.
  • the conductor 288 has the same configuration as the conductor 240, and the insulator 289 has the same configuration as the insulator 241.
  • one of the source and drain of the transistor 200 is electrically connected to the wiring 1003 via the conductor 288, and the other of the source and drain of the transistor 200 is electrically connected to the wiring 1008 via the conductor 288. Be connected.
  • one of the electrodes (conductor 120) of the capacitive element 100 is electrically connected to the wiring 1005 via the conductor 288. Further, the other electrode (conductor 110) of the capacitive element 100 is electrically connected to the wiring 1009 via the conductor 240, the conductor 255 in the same layer as the conductor 205, the conductor 112, and the conductor 288. Ru.
  • the transistor 200 and the capacitive element 100 may be configured to be individually sealed by a sealing film.
  • the transistor 200 is sealed by an insulator 283, an insulator 214, and an insulator 212.
  • the conductor 240 and the conductor 255 which function as wirings or plugs connected to the capacitive element 100, may be individually sealed from the transistor 200.
  • a region in contact between the insulator 283 and the insulator 214 is formed between the transistor 200, the conductor 240, and the conductor 255.
  • an insulator 285 and an insulator 287 are provided between the transistor 200 and the capacitive element 100, but the present invention is not limited to this.
  • the insulator 285 and the insulator 287 may not be provided, and the lower surfaces of the conductor 112, the conductor 110, and the insulator 155 may be in contact with the insulator 283.
  • the capacitive element 100 is sealed with the insulator 152a, the insulator 152b, the insulator 155, and the insulator 283. This eliminates the need to provide the insulator 285 and the insulator 287, so that the productivity of the storage device can be improved.
  • FIG. 21A An enlarged view of the capacitive element 100 shown in FIG. 20A is shown in FIG. 21A.
  • the capacitive element 100 is sealed by the insulator 287, the insulator 152a, the insulator 152b, and the insulator 155, similarly to the capacitive element 100 shown in FIG.
  • the insulator 155, the insulator 152a, the insulator 152b, and the insulator 287 function as a sealing film.
  • the insulator 130 is configured to be in contact with the upper surface of the insulator 287, the upper surface and the side surface of the conductor 110, but the present invention is not limited to this.
  • the insulator 115a may be provided between the insulator 130 and the insulator 287 and the conductor 110. That is, the insulator 130 is in contact with the upper surface of the insulator 115a, and the insulator 287 and the conductor 110 are in contact with the lower surface of the insulator 115a.
  • the insulator 115a the insulator 115a shown in FIG. 1C2 or the like can be used in the above embodiment.
  • the film thickness of the insulator 115a may be 0.2 nm or more and 2 nm or less, preferably 0.5 nm or more and 1 nm or less.
  • the insulator 130 is configured to be in contact with the lower surface of the conductor 120, but the present invention is not limited to this.
  • the insulator 115b may be provided between the insulator 130 and the conductor 120. That is, the insulator 130 is in contact with the lower surface of the insulator 115b, and the conductor 120 is in contact with the upper surface of the insulator 115b.
  • the insulator 115b the insulator 115b shown in FIG. 1C3 or the like can be used in the above embodiment.
  • the film thickness of the insulator 115b may be 0.2 nm or more and 2 nm or less, preferably 0.5 nm or more and 1 nm or less.
  • the capacitive element 100 may have a polycrystalline region formed in the insulator 130.
  • FIG. 22A shows an example in which the polycrystalline region 131a and the polycrystalline region 131b are formed on the upper side of the side end portion of the conductor 110.
  • the insulator 130 shown in FIG. 22A is formed along a step on the surface to be formed formed by the conductor 110, and the polycrystalline region 131a and the polycrystalline region 131b are formed in the vicinity of the upper part of the step. There is.
  • the polycrystal region 131a and the polycrystal region 131b are regions in which a large number of grains or grain boundaries are formed as shown in FIG. 4B.
  • the polycrystalline region 131a and the polycrystalline region 131b can be said to be a region in contact with the highly flat upper surface of the conductor 110 (a region sandwiched between the polycrystalline region 131a and the polycrystalline region 131b). ), It contains more grains.
  • the region sandwiched between the polycrystal region 131a and the polycrystal region 131b contains more single crystals as shown in FIG. 3 than the polycrystal region 131a and the polycrystal region 131b.
  • the capacitive element 100 shown in FIG. 22A shows a configuration in which the insulator 155 is provided in contact with the lower surface of the insulator 152a
  • the present invention is not limited to this.
  • the lower surface of the insulator 152a is in contact with the upper surface of the insulator 287, the side surface of the insulator 130, the side surface of the conductor 120, and the upper surface of the conductor 120 without providing the insulator 155. It may be configured.
  • the insulator 130 and the conductor 120 are configured to cover up to the side surface of the conductor 110, but the present invention is not limited to this.
  • the side surface of the insulator 130 and the side surface of the conductor 120 may be located inside the side surface of the conductor 110.
  • the outer circumferences of the insulator 130 and the conductor 120 are located inside the outer circumference of the conductor 110 in the top view.
  • the insulator 130 and the conductor 120 are not formed in the vicinity of the step of the surface to be formed formed by the conductor 110. Therefore, the polycrystalline region 131a and the polycrystalline region 131a shown in FIG. 22A and The polycrystalline region 131b is not formed on the insulator 130 shown in FIG. 22C. Therefore, the insulator 130 shown in FIG. 22C is in contact with the highly flat upper surface of the conductor 110 as a whole, and contains a large amount of single crystals as shown in FIG. As a result, the insulator 130 of FIG. 22C may have a structure in which a plurality of crystal layers are laminated in the c-axis direction as shown in FIG. 4A, and the polarization may be increased. In this way, the insulator 130 shown in FIG. 22C has good ferroelectricity, and the capacitive element 100 can function as a ferroelectric device.
  • the insulator 155 may be formed so that its side surface is located inside the side surface of the conductor 110. At this time, it is preferable that the side surfaces of the insulator 130, the conductor 120, and the insulator 155 are flush with each other. Further, the insulator 152a is provided so as to cover the conductor 110, the insulator 130, the conductor 120, and the insulator 155. The insulator 152b is provided on the insulator 152a.
  • the insulator 286 is provided on the insulator 152b, and the insulator 155, the insulator 152a, the insulator 152b, and the insulator 286 have openings reaching the conductor 120. Has been done. Similar to FIG. 20A, the conductor 288 and the insulator 289 are arranged in the opening.
  • the conductor 162 is provided in contact with the conductor 288, and the insulator 166 is provided on the conductor 162 to cover the conductor 162 and the insulator 166.
  • the insulator 168a is provided, and the insulator 168b is provided on the insulator 168a.
  • the capacitive element 100, the conductor 288, the conductor 162, and the like are shown on the same cross section, but the present invention is not limited thereto.
  • a contact between the conductor 162 and the conductor 120 may be formed at a place different from the place where the capacitive element 100 and the conductor 162 are superimposed.
  • the conductor 162 is a conductor that functions as a wiring, and may be electrically connected to the wiring 1005 in the same manner as the conductor 288 shown in FIG. 20A.
  • a conductive material that can be used for the conductor 112 may be used.
  • the insulator 166 can use the same insulator as the insulator 155, the insulator 168a can use the same insulator as the insulator 152a, and the insulator 168b uses the same insulator as the insulator 152b. be able to.
  • the insulator 286, the conductor 288, and the conductor 162 can be sandwiched between the insulator 168a and the insulator 152b, which function as a barrier insulating film against hydrogen.
  • an insulator 166 having a function of capturing and fixing hydrogen is arranged in a region sandwiched between the insulator 168a and the insulator 152b.
  • the conductor 110 is formed on the insulator 287.
  • the film formation of the conductor 110 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • titanium nitride can be used as the conductor 110.
  • CMP treatment or the like on the upper surface of the conductor 110 to improve the flatness of the conductor 110.
  • the roughness of the upper surface of the conductor 110 is an arithmetic mean roughness (Ra) or a root mean square roughness (RMS: Root Mean Square) of 2 nm or less, preferably 1 nm or less, more preferably 0.8 nm or less.
  • It may be more preferably 0.5 nm or less, further preferably 0.4 nm or less, still more preferably 0.2 nm or less.
  • the conductor 110 is patterned by using a photolithography method or the like (see FIG. 23A). Here, it is preferable that the conductor 110 is patterned so as to cover the conductor 288.
  • the insulator 130 is formed by covering the conductor 110 (see FIG. 23A).
  • the film formation of the insulator 130 can be performed by using a sputtering method, a CVD method, an ALD method, or the like.
  • the film may be formed by using the thermal ALD method.
  • HfZrO x can be used as the insulator 130.
  • HfCl 4 and / or ZrCl 4 may be used as the precursor.
  • H2O or O3 can be used as the oxidizing agent.
  • the chlorine contained in the insulator 130 is reduced as much as possible. For example, by setting the substrate temperature during thermal ALD to 400 ° C. or higher, chlorine contained in the insulator 130 can be reduced. Further, when the film formation is performed according to the film formation sequence shown in FIG. 7A, it is preferable to lengthen the introduction time of the oxidizing agent H2O . As a result, the chlorine bonded to the surface to be formed can be sufficiently separated, so that the chlorine concentration contained in the insulator 130 can be sufficiently reduced.
  • the polycrystalline region 131a and the polycrystalline region 131b may be formed on the upper side of the side end portion of the conductor 110 in the insulator 130.
  • a conductor 120a is formed on the insulator 130 (see FIG. 23A).
  • the film formation of the conductor 120a can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a sputtering method a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductor 110 titanium nitride formed by an ALD method or a sputtering method can be used as the conductor 110.
  • the conductor 120b is formed on the conductor 120a (see FIG. 23A).
  • the film formation of the conductor 120b can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a sputtering method e.g., a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • tungsten formed by the metal CVD method can be used as the conductor 110.
  • the conductor 120b does not necessarily have to be formed into a film, and for example, the conductor 120 may have a single-layer structure containing only the conductor 120a.
  • the film may be formed by setting the substrate temperature to 300 ° C. or higher, preferably 325 ° C. or higher, and more preferably 350 ° C. or higher. Further, for example, the film may be formed by setting the substrate temperature to 600 ° C. or lower, preferably 500 ° C. or lower, and more preferably 450 ° C. or lower. For example, the substrate temperature may be set to about 500 ° C.
  • the heat treatment time may be, for example, about 30 seconds or more and 120 seconds or less.
  • the heat treatment can be performed in an atmosphere containing at least one of oxygen gas, nitrogen gas and an inert gas.
  • the crystallization of the insulator 130 can be promoted and the crystallinity can be improved. In other words, the single crystal region contained in the insulator 130 can be increased.
  • the insulator 130 may be sufficiently crystallized without performing the above heat treatment.
  • an insulator 155 is formed on the conductor 120b (see FIG. 23B).
  • the film formation of the insulator 155 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 155 it is preferable to use an insulator having a function of capturing and fixing hydrogen, which can be used for the insulator 214, the insulator 282, or the like.
  • the insulator 155 aluminum oxide formed by an ALD method or a sputtering method can be used.
  • the film thickness of the insulator 155 may be, for example, about 20 nm or more and 40 nm or less.
  • the insulator 130, the conductor 120a, the conductor 120b, and the insulator 155 are patterned by using a photolithography method or the like (see FIG. 23C).
  • the side surfaces of the insulator 130, the conductor 120a, the conductor 120b, and the insulator 155 are located inside the side surface of the conductor 110.
  • the polycrystal region 131a and the polycrystal region 131b formed on the insulator 130 can be removed, and the insulator 130 containing a large amount of single crystals and having high crystallinity can be formed.
  • the insulator 152a is formed by covering the insulator 287, the conductor 110, the insulator 130, the conductor 120, and the insulator 155, and the insulator 152b is formed on the insulator 152a (FIG. 23D). reference.).
  • a barrier insulating film that can be used for the above-mentioned insulator 283 or the like may be used.
  • the film thickness of the insulator 152a can be, for example, about 10 nm or more and 40 nm or less. Further, the film thickness of the insulator 152b can be, for example, about 3 nm or more and 10 nm or less.
  • the film of the insulator 152a may be formed by using a sputtering method.
  • a sputtering method silicon nitride formed by a sputtering method can be used. Since the sputtering method does not require the use of molecules containing hydrogen in the film-forming gas, the hydrogen concentration of the insulator 152a can be reduced. By reducing the hydrogen concentration of the insulator 152a in contact with the conductor 112 and the insulator 285 in this way, it is possible to suppress the diffusion of hydrogen from the insulator 152a to the conductor 112 and the insulator 285.
  • the insulator 152b is formed by using the ALD method, particularly the PEALD method.
  • the insulator 152b silicon nitride formed by the PEALD method can be used.
  • the insulator 152b can be formed into a film with good coverage. Therefore, even if pinholes or step breaks are formed in the insulator 152a due to the unevenness of the base, hydrogen can be formed by covering them with the insulator 152b. Can be reduced from diffusing into the conductor 112 and the insulator 285.
  • the capacitance element 100 can be sealed by the insulator 155, the insulator 152a and the insulator 152b, and the insulator 287.
  • an insulator 286 is formed on the insulator 152b (see FIG. 23D).
  • An opening reaching the conductor 120 is formed in the insulator 286, the insulator 152b, the insulator 152a, and the insulator 155, and the conductor 288 and the insulator 289 are formed in the opening (see FIG. 22C).
  • the conductor 162 is formed on the conductor 288 by the same method as the conductor 110, and the insulator 166 is formed on the conductor 162 by the same method as the insulator 155 (see FIG. 22C).
  • the insulator 168a is formed by covering the insulator 286, the conductor 162, and the insulator 166 in the same manner as the insulator 152a, and the insulator 168b is formed on the insulator 168a in the same manner as the insulator 152b.
  • Membrane see FIG. 22C).
  • the film may be formed by setting the substrate temperature to 300 ° C. or higher, preferably 325 ° C. or higher, and more preferably 350 ° C. or higher. Further, for example, the film may be formed by setting the substrate temperature to 600 ° C. or lower, preferably 500 ° C. or lower, and more preferably 450 ° C. or lower. For example, the substrate temperature may be set to about 400 ° C.
  • the heat treatment time may be, for example, about 1 hour or more and 10 hours or less.
  • the heat treatment can be performed in an atmosphere containing at least one of oxygen gas, nitrogen gas and an inert gas. The heat treatment is not limited to the film formation of the insulator 168b, and can be appropriately performed after the film formation of the insulator 152b.
  • an insulator 166 having a function of capturing and fixing hydrogen is arranged in a region sandwiched between the insulator 168a and the insulator 152b.
  • the hydrogen inside the insulator 168b and the insulator 152a is further captured and fixed, and the insulator 286 is conductive.
  • the hydrogen concentration of the body 288, the conductor 162, and the like can be reduced.
  • any one or more of the wiring 1003, the wiring 1004, the wiring 1006, and the wiring 1008 electrically connected to the transistor 200 are electrically connected to the capacitance element 100, and the wiring 1005 and the wiring. It may be configured to be electrically connected to either or both of 1009. Further, a part or all of the above-mentioned description relating to the storage device shown in FIGS. 20A to 22C may be used for the device shown in FIGS. 18, 19, 24 to 27 and the like.
  • the transistor 200 and the capacitive element 100 are individually sealed by a barrier insulating film against hydrogen, but the present invention is not limited to this. As shown in FIG. 24, the transistor 200 and the capacitive element 100 may be collectively sealed by a barrier insulating film (insulator 212, insulator 152a, and insulator 152b) against hydrogen.
  • a barrier insulating film insulator 212, insulator 152a, and insulator 152b
  • the insulator 214, the insulator 216, the insulator 222, the insulator 275, the insulator 280, the insulator 282, the insulator 283, the insulator 285, and the insulator 155 reach the insulator 212.
  • An opening is formed.
  • the insulator 152a and the insulator 152b on the insulator 155 are formed along the side surface and the bottom surface of the opening.
  • the insulator 152a is in contact with the upper surface of the insulator 212 at the bottom surface of the opening.
  • the transistor 200 and the capacitive element 100 can be collectively sealed by the insulator 212, the insulator 152a, and the insulator 152b.
  • hydrogen is suppressed from diffusing from the outside of the insulator 212 and the insulator 152b to the capacitive element 100 and the transistor 200, and the hydrogen concentration of the insulator 130 of the capacitive element 100 and the oxide semiconductor film of the transistor 200 is increased.
  • the capacitive element 100 is provided on the transistor 200, but the present invention is not limited to this. As shown in FIG. 25, the capacitive element 100 may be provided on the same layer as the transistor 200.
  • the conductor 110 that functions as the lower electrode of the capacitive element 100 is preferably formed of the same layer of conductor as the conductor 205 that functions as the back gate of the transistor 200.
  • the insulator 130 is arranged on the conductor 110, and the conductor 120 (conductor 120a and conductor 120b) is arranged on the insulator 130.
  • the insulator 130 covers the upper surface of the conductor 110 and separates the conductor 110 from the conductor 120.
  • the insulator 130 and the conductor 120 may have the same configuration as that shown in FIG. 19 and the like, and for details, the description of [configuration example of the storage device] and the previous embodiment may be taken into consideration. can.
  • the insulator 222 is arranged so as to cover the insulator 130 and the conductor 120.
  • the conductor 240 is provided in contact with the upper surface of the conductor 120a, and the conductor 112 is provided in contact with the upper surface of the conductor 240.
  • the conductor 112 is in contact with a conductor 240 electrically connected to one of the source and drain of the transistor 200. That is, the conductor 120 that functions as the upper electrode of the capacitive element 100 shown in FIG. 25 is electrically connected to one of the source and drain of the transistor 200. Further, the conductor 110 that functions as the lower electrode of the capacitive element 100 is electrically connected to the wiring 1005.
  • the transistor 200 and the capacitive element 100 can be collectively sealed by the insulator 212, the insulator 152a, and the insulator 152b.
  • hydrogen is suppressed from diffusing from the outside of the insulator 212 and the insulator 152b to the capacitive element 100 and the transistor 200, and the hydrogen concentration of the insulator 130 of the capacitive element 100 and the oxide semiconductor film of the transistor 200 is increased.
  • the storage device shown in FIG. 19 and the like has a configuration in which the transistor 200 is provided on the transistor 300 and the capacitive element 100 is connected to the transistor 200, but the present invention is not limited to this. As shown in FIG. 26A, the capacitive element 100 may be connected to the transistor 300 without providing the transistor 200.
  • the insulator 320, the insulator 322, and the insulator 287 are formed with an opening reaching the low resistance region 314a of the transistor 300, and the conductor 357 is formed so as to embed the opening. ..
  • the same conductor as the conductor 328 can be used.
  • the upper surface of the conductor 357 is in contact with the lower surface of the conductor 110 of the capacitive element 100. In this way, the conductor 110 that functions as the lower electrode of the capacitive element 100 and the low resistance region 314a that functions as one of the source and drain of the transistor 300 are connected via the conductor 357.
  • the configurations of the transistor 300, the capacitive element 100, and the layer including them are the same as those shown in FIG. 19, and the description related to the configuration shown in FIG. 19 can be taken into consideration.
  • the capacitive element 100 can be sealed with the insulator 287, the insulator 152a, and the insulator 152b in the same manner as in the storage device shown in FIG. As a result, it is possible to suppress the diffusion of hydrogen from the outside of the insulator 287 and the insulator 152b to the capacitive element 100, and reduce the hydrogen concentration of the oxide semiconductor film of the insulator 130 of the capacitive element 100. Therefore, the ferroelectricity of the insulator 130 can be enhanced.
  • the low resistance region 314a of the transistor 300 and the conductor 110 of the capacitive element 100 are directly connected by the conductor 357, but the present invention is not limited to this.
  • a plurality of wiring layers shown in FIG. 19 or the like may be provided between the capacitive element 100 and the transistor 300.
  • the conductor 328 is formed on the transistor 300
  • the conductor 330 is formed on the conductor 328
  • the conductor 356 is formed on the conductor 330
  • the conductor 356 is formed.
  • a conductor 357 may be formed on the conductor.
  • the low resistance region 314a of the transistor 300 and the conductor 110 of the capacitive element 100 are electrically connected by the conductor 328, the conductor 330, the conductor 356, and the conductor 357.
  • the description of [Structure example of storage device] can be referred to.
  • FIG. 19 and the like show a configuration in which the transistor 200 is connected to the capacitive element 100 including a material that may have ferroelectricity
  • the present invention is not limited to this.
  • a material capable of having ferroelectricity may be used as the transistor 200 and the insulator provided around the transistor 200.
  • a transistor having such a configuration will be described with reference to FIGS. 27A to 27C.
  • the transistor 200 shown in FIGS. 27A to 27C is the transistor 200 shown in FIG. 11, instead of the capacitive element 100, the conductor 240a, the conductor 240b, the conductor 246a, the conductor 246b, the insulator 241a, and the insulator. 241b is provided.
  • the transistor 200 shown in FIG. 27A uses an insulator 130a instead of the insulator 222.
  • As the insulator 130a a material that can have the same ferroelectricity as that of the insulator 130 can be used. That is, the transistor 200 shown in FIG. 27A uses a material capable of having ferroelectricity for the second gate insulator.
  • the transistor 200 shown in FIG. 27B uses an insulator 130b instead of the insulator 252, the insulator 250, and the insulator 254.
  • As the insulator 130b a material that can have the same ferroelectricity as that of the insulator 130 can be used. That is, the transistor 200 shown in FIG. 27B uses a material capable of having ferroelectricity for the first gate insulator. With such a configuration, the transistor 200 shown in FIG. 27B can function as the FeFET shown in FIG. 1B1.
  • all the first gate insulators are made of ferroelectric materials, but the present invention is not limited to this.
  • one or more of the insulator 252, the insulator 250a, the insulator 250b, and the insulator 254 shown in FIG. 12B may be configured by using a material capable of having ferroelectricity.
  • an insulator 130c is provided on the conductor 260, and a conductor 262 is provided on the insulator 130c.
  • a material that can have the same ferroelectricity as that of the insulator 130 can be used.
  • a conductive material that can be used for the conductor 260 can be used.
  • An insulator 282 is provided so as to cover the insulator 130c and the conductor 262. In the semiconductor device shown in FIG. 27C, it can be considered that one terminal of the ferroelectric capacitor is provided on the gate electrode of the transistor 200.
  • the present invention is not limited to this.
  • a material capable of having ferroelectricity can be used as in the transistor 200 shown in FIGS. 27A to 27C.
  • the Si transistor can function as a FeFET.
  • a transistor using an oxide as a semiconductor hereinafter, may be referred to as an OS transistor
  • a ferroelectric capacitor according to one aspect of the present invention
  • the applied storage device will be described.
  • the device according to the present embodiment is a storage device having at least a capacitive element and an OS transistor for controlling charge / discharge of the capacitive element.
  • the apparatus according to this embodiment functions as a 1-transistor 1-capacitor type ferroelectric memory using a ferroelectric capacitor.
  • FIG. 28A shows an example of the configuration of the storage device.
  • the storage device 1400 has a peripheral circuit 1411 and a memory cell array 1470.
  • the peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.
  • the column circuit 1430 includes, for example, a column decoder, a bit line driver circuit, a precharge circuit, a sense amplifier, a write circuit, and the like.
  • the precharge circuit has a function of precharging the wiring.
  • the sense amplifier has a function of amplifying a data signal read from a memory cell.
  • the wiring is the wiring connected to the memory cell of the memory cell array 1470, and will be described in detail later.
  • the amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440.
  • the row circuit 1420 has, for example, a row decoder, a word line driver circuit, and the like, and the row to be accessed can be selected.
  • the storage device 1400 is supplied with a low power supply voltage (VSS) as a power supply voltage, a high power supply voltage (SiO) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from the outside. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside.
  • the address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.
  • the control logic circuit 1460 processes the control signals (CE, WE, RE) input from the outside to generate the control signals of the row decoder and the column decoder.
  • the control signal CE is a chip enable signal
  • the control signal WE is a write enable signal
  • the control signal RE is a read enable signal.
  • the signal processed by the control logic circuit 1460 is not limited to this, and other control signals may be input as needed.
  • the memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings.
  • the number of wires connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cell MC, the number of memory cell MCs in one column, and the like. Further, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cell MCs in one row, and the like.
  • FIG. 28A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane
  • the present embodiment is not limited to this.
  • the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411.
  • a sense amplifier may be provided so as to overlap under the memory cell array 1470.
  • the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in the present embodiment are not limited to the above.
  • the arrangement or function of these circuits and the wiring, circuit elements, etc. connected to the circuits may be changed, deleted, or added as necessary.
  • the storage device of one aspect of the present invention has a high operating speed and can retain data for a long period of time.
  • the circuit diagram shown in FIG. 29A shows a configuration example of the above-mentioned memory cell MC.
  • the memory cell MC has a transistor Tr and a capacitance Fe.
  • the semiconductor device having the transistor 200 and the capacitive element 100 shown in the previous embodiment can be used.
  • the transistor Tr corresponds to the transistor 200
  • the capacitance Fe corresponds to the capacitance element 100.
  • the transistor Tr may or may not have a back gate in addition to the gate.
  • the transistor Tr is an n-channel type transistor in FIG. 29A, it may be a p-channel type transistor.
  • One of the source and drain of the transistor Tr is electrically connected to the wiring BL.
  • the other of the source or drain of the transistor Tr is electrically connected to one electrode of the capacitance Fe.
  • the gate of the transistor Tr is electrically connected to the wiring WL.
  • the other electrode of the capacitance Fe is electrically connected to the wiring PL.
  • the wiring WL has a function as a word line, and the on / off of the transistor Tr can be controlled by controlling the potential of the wiring WL. For example, by setting the potential of the wiring WL to a high potential, the transistor Tr can be turned on, and by setting the potential of the wiring WL to a low potential, the transistor Tr can be turned off.
  • the wiring WL is electrically connected to the word line driver circuit included in the row circuit 1420, and the potential of the wiring WL can be controlled by the word line driver circuit.
  • the wiring BL has a function as a bit line, and when the transistor Tr is in the ON state, a potential corresponding to the potential of the wiring BL is supplied to one electrode of the capacitance Fe.
  • the wiring BL is electrically connected to the bit line driver circuit of the column circuit 1430.
  • the bit line driver circuit has a function of generating data to be written to the memory cell MC. Further, the bit line driver circuit has a function of reading the data output from the memory cell MC. Specifically, the bit line driver circuit is provided with a sense amplifier, and the data output from the memory cell MC can be read out by using the sense amplifier.
  • the wiring PL has a function as a plate wire, and the potential of the wiring PL can be the potential of the other electrode of the capacitance Fe.
  • the OS transistor has a characteristic of having a high withstand voltage. Therefore, by using the transistor Tr as an OS transistor, a high voltage can be applied to the transistor Tr even if the transistor Tr is miniaturized. By miniaturizing the transistor Tr, the occupied area of the memory cell MC can be reduced. For example, the occupied area per memory cell MC shown in FIG. 29A can be 1/3 to 1/6 of the occupied area per SRAM cell. Therefore, the memory cells MC can be arranged at a high density. Thereby, the storage device according to one aspect of the present invention can be a storage device having a large storage capacity.
  • the capacitive Fe has a material that can have ferroelectricity as a dielectric layer between the two electrodes.
  • the dielectric layer having the capacitance Fe is referred to as a ferroelectric layer.
  • a material that can have ferroelectricity a material that can be used for the above-mentioned insulator 130 may be used.
  • a material capable of having ferroelectricity hafnium oxide, or a material having hafnium oxide and zirconium oxide is preferable because it can have ferroelectricity even when processed into a thin film of several nm.
  • the ferroelectric layer has a hysteresis characteristic.
  • FIG. 29B1 is a graph showing an example of the hysteresis characteristic.
  • the horizontal axis represents the voltage applied to the ferroelectric layer.
  • the voltage can be, for example, the difference between the potential of one electrode of the capacitance Fe and the potential of the other electrode of the capacitance Fe.
  • the vertical axis indicates the amount of polarization of the ferroelectric layer, and when the value is positive, the negative charge is biased to one electrode side of the capacitance Fe, and the positive charge is biased to the other electrode side of the capacitance Fe. Show that it is.
  • the amount of polarization is a negative value, it indicates that the negative charge is biased toward the other electrode side of the capacitance Fe and the positive charge is biased toward one electrode side of the capacitance Fe.
  • the voltage shown on the horizontal axis of the graph of FIG. 29B1 may be the difference between the potential of the other electrode of the capacitance Fe and the potential of one electrode of the capacitance Fe.
  • the amount of polarization (also referred to as polarization) shown on the vertical axis of the graph of FIG. 29B1 is when the negative charge is biased toward the other electrode side of the capacitance Fe and the positive charge is biased toward one electrode side of the capacitance Fe. It may be a positive value, and may be a negative value when the negative charge is biased to one electrode side of the capacitance Fe and the positive charge is biased to the other electrode side of the capacitance Fe.
  • the hysteresis characteristic of the ferroelectric layer can be represented by the curve 51 and the curve 52.
  • VSP and ⁇ VSP can be said to be saturated polarization voltages.
  • VSP may be referred to as a first saturated polarization voltage
  • ⁇ VSP may be referred to as a second saturation polarization voltage.
  • the absolute value of the first saturated polarization voltage and the absolute value of the second saturated polarization voltage are equal to each other, but they may be different.
  • the voltage applied to the ferroelectric layer when the polarization amount of the ferroelectric layer changes according to the curve 51 and the polarization amount of the ferroelectric layer is 0 is defined as Vc.
  • the voltage applied to the ferroelectric layer when the polarization amount of the ferroelectric layer changes according to the curve 52 and the polarization amount of the ferroelectric layer is 0 is defined as ⁇ Vc.
  • Vc and -Vc can be said to be withstand voltage. It can be said that the value of Vc and the value of -Vc are values between -VSP and VSP.
  • Vc may be referred to as a first coercive voltage
  • ⁇ Vc may be referred to as a second coercive voltage.
  • the absolute value of the first coercive voltage and the absolute value of the second coercive voltage are equal to each other, but they may be different.
  • the voltage applied to the ferroelectric layer of the capacitance Fe can be expressed by the difference between the potential of one electrode of the capacitance Fe and the potential of the other electrode of the capacitance Fe. Further, as described above, the other electrode of the capacitance Fe is electrically connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, the voltage applied to the ferroelectric layer of the capacitance Fe can be controlled.
  • FIG. 29B2 is a graph showing an example of hysteresis characteristics showing an ideal amount of polarization of the ferroelectric layer.
  • the straight line 52i and the straight line 51i shown in FIG. 29B2 are ideal polarization amounts of the ferroelectric layer.
  • the crystallinity of the ferroelectric material is improved, the leak component from the vicinity of the ferroelectric material and the material is eliminated, and the impurity concentration of the ferroelectric material is eliminated. It may be done to reduce. Since the metal oxide film of one aspect of the present invention is highly purified, it can be expected to approach an example of the hysteresis characteristic showing the ideal polarization amount of the ferroelectric layer shown in FIG. 29B2.
  • the voltage applied to the ferroelectric layer of the capacitance Fe indicates the difference between the potential of one electrode of the capacitance Fe and the potential of the other electrode (wiring PL) of the capacitance Fe. do.
  • the transistor Tr is an n-channel type transistor.
  • FIG. 29C is a timing chart showing an example of the driving method of the memory cell MC shown in FIG. 29A.
  • FIG. 29C shows an example of writing and reading binary digital data to the memory cell MC. Specifically, in FIG. 29C, data "1" is written to the memory cell MC at time T01 to time T02, read and rewritten at time T03 to time T05, read out at time T11 to time T13, and the memory cell. An example of writing data "0" to the MC, reading and rewriting at time T14 to time T16, reading from time T17 to time T19, and writing data "1" to the memory cell MC is shown. ing.
  • Vref is supplied as a reference potential to the sense amplifier electrically connected to the wiring BL.
  • Vref is supplied as a reference potential to the sense amplifier electrically connected to the wiring BL.
  • the potential of the wiring BL is higher than Vref, it is assumed that the data “1” is read by the bit line driver circuit.
  • the potential of the wiring BL is lower than Vref, it is assumed that the data "0" is read by the bit line driver circuit.
  • the potential of the wiring WL is set to a high potential.
  • the transistor Tr is turned on.
  • the potential of the wiring BL is Vw.
  • the potential of one electrode of the capacitance Fe is Vw.
  • the potential of the wiring PL is set to GND. From the above, the voltage applied to the ferroelectric layer of the capacitance Fe becomes "Vw-GND". As a result, the data "1" can be written to the memory cell MC. Therefore, it can be said that the time T01 to the time T02 is a period during which the writing operation is performed.
  • Vw is preferably VSP or higher, and is preferably equal to, for example, VSP.
  • the GND can be set to, for example, a ground potential, but it does not necessarily have to be a ground potential as long as the memory cell MC can be driven so as to satisfy the gist of one aspect of the present invention.
  • GND can be a potential other than ground.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND.
  • the voltage applied to the ferroelectric layer of the capacitance Fe becomes 0V. Since the voltage "Vw-GND" applied to the ferroelectric layer of the capacitance Fe at time T01 to time T02 can be equal to or higher than VSS, the amount of polarization of the ferroelectric layer of the capacitance Fe at time T02 to time T03. Changes according to the curve 52 shown in FIG. 29B. From the above, at time T02 to time T03, the polarization inversion does not occur in the ferroelectric layer having the capacitance Fe.
  • the potential of the wiring WL is set to a high potential.
  • the transistor Tr is turned on.
  • the potential of the wiring PL is Vw.
  • the voltage applied to the ferroelectric layer of the capacitance Fe becomes “GND-Vw”.
  • the voltage applied to the ferroelectric layer of the capacitance Fe at time T01 to time T02 is “Vw-GND”. Therefore, the polarization inversion occurs in the ferroelectric layer having the capacitance Fe.
  • a current flows through the wiring BL, and the potential of the wiring BL becomes higher than Vref.
  • the bit line driver circuit can read the data "1" held in the memory cell MC. Therefore, it can be said that the time T03 to the time T04 is a period during which the read operation is performed.
  • Vref is higher than GND and lower than Vw, it may be higher than Vw, for example.
  • the time T04 to the time T05 is a period during which the rewrite operation is performed.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND.
  • the potential of the wiring WL is set to a low potential. As a result, the rewrite operation is completed, and the data "1" is held in the memory cell MC.
  • the potential of the wiring WL is set to a high potential, and the potential of the wiring PL is set to Vw. Since the data "1" is held in the memory cell MC, the potential of the wiring BL becomes higher than Vref, and the data "1" held in the memory cell MC is read out. Therefore, it can be said that the time T11 to the time T12 is a period during which the read operation is performed.
  • the potential of the wiring BL is set to GND. Since the transistor Tr is in the ON state, the potential of one electrode of the capacitance Fe is GND. Further, the potential of the wiring PL is Vw. From the above, the voltage applied to the ferroelectric layer of the capacitance Fe is "GND-Vw". As a result, the data "0" can be written to the memory cell MC. Therefore, it can be said that the time T12 to the time T13 is a period during which the writing operation is performed.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND.
  • the voltage applied to the ferroelectric layer of the capacitance Fe becomes 0V. Since the voltage "GND-Vw" applied to the ferroelectric layer of the capacitance Fe at time T12 to T13 can be -VSP or less, the polarization of the ferroelectric layer of the capacitance Fe from time T13 to time T14. The amount varies according to the curve 51 shown in FIG. 29B. From the above, at time T13 to time T14, the polarization inversion does not occur in the ferroelectric layer having the capacitance Fe.
  • the potentials of the wiring BL and the wiring PL are such that the polarization inversion does not occur in the ferroelectric layer of the capacitance Fe, that is, the voltage applied to the ferroelectric layer of the capacitance Fe is Vc or less, which is the first coercive voltage. If so, it can be any potential.
  • the potential of the wiring WL is set to a high potential.
  • the transistor Tr is turned on.
  • the potential of the wiring PL is Vw.
  • the voltage applied to the ferroelectric layer of the capacitance Fe becomes “GND-Vw”.
  • the voltage applied to the ferroelectric layer of the capacitance Fe at time T12 to time T13 is “GND-Vw”. Therefore, the polarization inversion does not occur in the ferroelectric layer having the capacitance Fe. Therefore, the amount of current flowing through the wiring BL is smaller than the case where the polarization inversion occurs in the ferroelectric layer having the capacitance Fe.
  • the increase width of the potential of the wiring BL becomes smaller than that in the case where the polarization inversion occurs in the ferroelectric layer of the capacitance Fe, and specifically, the potential of the wiring BL becomes Vref or less. Therefore, the bit line driver circuit can read the data “0” held in the memory cell MC. Therefore, it can be said that the time T14 to the time T15 is a period during which the read operation is performed.
  • the potential of the wiring BL is set to GND, and the potential of the wiring PL is set to Vw.
  • the data "0" is rewritten to the memory cell MC. Therefore, it can be said that the time T15 to the time T16 is a period during which the rewrite operation is performed.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND.
  • the potential of the wiring WL is set to a low potential. As a result, the rewrite operation is completed, and the data "0" is held in the memory cell MC.
  • the potential of the wiring WL is set to a high potential, and the potential of the wiring PL is set to Vw. Since the data "0" is held in the memory cell MC, the potential of the wiring BL becomes lower than Vref, and the data "0" held in the memory cell MC is read out. Therefore, it can be said that the time T17 to the time T18 is a period during which the read operation is performed.
  • the potential of the wiring BL is Vw. Since the transistor Tr is in the ON state, the potential of one electrode of the capacitance Fe is Vw. Further, the potential of the wiring PL is set to GND. From the above, the voltage applied to the ferroelectric layer of the capacitance Fe becomes "Vw-GND". As a result, the data "1" can be written to the memory cell MC. Therefore, it can be said that the time T18 to the time T19 is a period during which the writing operation is performed.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND.
  • the potential of the wiring WL is set to a low potential. As a result, the writing operation is completed, and the data "1" is held in the memory cell MC.
  • the semiconductor device shown in the above embodiment is, for example, a storage device for various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book terminal, a digital camera (including a video camera), a recording / playback device, a navigation system, etc.).
  • the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • the semiconductor device shown in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive).
  • 30A to 30E schematically show some configuration examples of the removable storage device.
  • the semiconductor device shown in the above embodiment is processed into a packaged memory chip and used for various storage devices and removable memories.
  • FIG. 30A is a schematic diagram of a USB memory.
  • the USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104.
  • the board 1104 is housed in the housing 1101.
  • a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104.
  • the semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 or the like. As a result, the storage capacity of the USB memory 1100 can be further increased.
  • FIG. 30B is a schematic diagram of the appearance of the SD card
  • FIG. 30C is a schematic diagram of the internal structure of the SD card.
  • the SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113.
  • the board 1113 is housed in the housing 1111.
  • a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113.
  • a wireless chip having a wireless communication function may be provided on the substrate 1113.
  • the data of the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110.
  • the semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1114 or the like. As a result, the storage capacity of the SD card 1110 can be further increased.
  • FIG. 30D is a schematic diagram of the appearance of the SSD
  • FIG. 30E is a schematic diagram of the internal structure of the SSD.
  • the SSD 1150 has a housing 1151, a connector 1152 and a substrate 1153.
  • the substrate 1153 is housed in the housing 1151.
  • a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153.
  • the memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used.
  • the capacity of the SSD 1150 can be increased.
  • the semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1154 or the like. As a result, the storage capacity of the SSD 1150 can be further increased.
  • the semiconductor device according to one aspect of the present invention can be used for a processor such as a CPU or GPU, or a chip.
  • a processor such as a CPU or GPU, or a chip
  • these can be miniaturized and the storage capacity can be further increased.
  • 31A to 31H show specific examples of electronic devices including a processor such as a CPU, GPU, or a chip according to one aspect of the present invention.
  • the GPU or chip according to one aspect of the present invention can be mounted on various electronic devices.
  • electronic devices include relatively large screens such as television devices, monitors for desktop or notebook information terminals, digital signage (electronic signage), large game machines such as pachinko machines, and the like.
  • digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, mobile information terminals, sound reproduction devices, and the like can be mentioned.
  • artificial intelligence can be mounted on the electronic device.
  • the electronic device of one aspect of the present invention may have an antenna.
  • the display unit can display images, information, and the like.
  • the antenna may be used for non-contact power transmission.
  • the electronic device of one aspect of the present invention includes sensors (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, It may have the ability to measure voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays).
  • the electronic device of one aspect of the present invention can have various functions. For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function to display a date or time, a function to execute various software (programs), wireless communication. It can have a function, a function of reading a program or data recorded on a recording medium, and the like.
  • 31A to 31H show examples of electronic devices.
  • FIG. 31A illustrates a mobile phone (smartphone) which is a kind of information terminal.
  • the information terminal 5100 has a housing 5101 and a display unit 5102, and a touch panel is provided in the display unit 5102 and a button is provided in the housing 5101 as an input interface.
  • the information terminal 5100 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention.
  • Examples of the application using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5102, and recognizes characters and figures input by the user on the touch panel provided in the display unit 5102.
  • Examples include an application displayed on the display unit 5102, an application for performing biometric authentication such as a fingerprint and a voice print, and the like.
  • FIG. 31B illustrates a notebook type information terminal 5200.
  • the notebook type information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.
  • the note-type information terminal 5200 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention.
  • applications using artificial intelligence include design support software, text correction software, menu automatic generation software, and the like. Further, by using the notebook type information terminal 5200, it is possible to develop a new artificial intelligence.
  • a smartphone and a notebook-type information terminal are taken as examples as electronic devices, and although they are shown in FIGS. 31A and 31B, respectively, information terminals other than the smartphone and the notebook-type information terminal can be applied.
  • information terminals other than smartphones and notebook-type information terminals include PDAs (Personal Digital Assistants), desktop-type information terminals, workstations, and the like.
  • FIG. 31C shows a portable game machine 5300, which is an example of a game machine.
  • the portable game machine 5300 has a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, an operation key 5306, and the like.
  • the housing 5302 and the housing 5303 can be removed from the housing 5301.
  • the connection unit 5305 provided in the housing 5301 to another housing (not shown)
  • the video output to the display unit 5304 can be output to another video device (not shown). can.
  • the housing 5302 and the housing 5303 can each function as an operation unit. This allows multiple players to play the game at the same time.
  • the chips shown in the previous embodiment can be incorporated into the chips provided on the substrates of the housing 5301, the housing 5302, and the housing 5303.
  • FIG. 31D shows a stationary game machine 5400, which is an example of a game machine.
  • a controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.
  • a low power consumption game machine By applying the GPU or chip of one aspect of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400, a low power consumption game machine can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • the portable game machine 5300 having artificial intelligence can be realized.
  • expressions such as the progress of the game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are determined by the program that the game has, but by applying artificial intelligence to the handheld game machine 5300.
  • Expressions that are not limited to game programs are possible. For example, it is possible to express what the player asks, the progress of the game, the time, and the behavior of the characters appearing in the game.
  • the game player can be configured anthropomorphically by artificial intelligence. Therefore, by setting the opponent as a game player by artificial intelligence, even one person can play the game. You can play the game.
  • FIGS. 31C and 31D a portable game machine and a stationary game machine are illustrated as examples of the game machine, but the game machine to which the GPU or chip of one aspect of the present invention is applied is not limited to this.
  • Examples of the game machine to which the GPU or chip of one aspect of the present invention is applied include an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a pitching machine for batting practice installed in a sports facility, and the like. Can be mentioned.
  • the GPU or chip of one aspect of the present invention can be applied to a large computer.
  • FIG. 31E is a diagram showing a supercomputer 5500, which is an example of a large computer.
  • FIG. 31F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.
  • the supercomputer 5500 has a rack 5501 and a plurality of rack mount type computers 5502.
  • the plurality of computers 5502 are stored in the rack 5501. Further, the computer 5502 is provided with a plurality of substrates 5504, and the GPU or the chip described in the above embodiment can be mounted on the substrate.
  • the supercomputer 5500 is a large computer mainly used for scientific and technological calculations. In scientific and technological calculations, it is necessary to process a huge amount of calculations at high speed, so power consumption is high and the heat generated by the chip is large.
  • the GPU or chip of one aspect of the present invention to the supercomputer 5500, a supercomputer having low power consumption can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • a supercomputer is illustrated as an example of a large computer, but the large computer to which the GPU or chip of one aspect of the present invention is applied is not limited to this.
  • Examples of the large-scale computer to which the GPU or chip of one aspect of the present invention is applied include a computer (server) for providing a service, a large-scale general-purpose computer (mainframe), and the like.
  • the GPU or chip of one aspect of the present invention can be applied to a moving vehicle and around the driver's seat of the vehicle.
  • FIG. 31G is a diagram showing the periphery of the windshield in the interior of an automobile, which is an example of a moving body.
  • the display panel 5701 attached to the dashboard, the display panel 5702, the display panel 5703, and the display panel 5704 attached to the pillar are illustrated.
  • the display panel 5701 to the display panel 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear status, an air conditioner setting, and the like.
  • the display items, layout, and the like displayed on the display panel can be appropriately changed according to the user's preference, and the design can be improved.
  • the display panel 5701 to 5703 can also be used as a lighting device.
  • the display panel 5704 can supplement the field of view (blind spot) blocked by the pillars by projecting an image from an image pickup device (not shown) provided in the automobile. That is, by displaying the image from the image pickup device provided on the outside of the automobile, the blind spot can be supplemented and the safety can be enhanced. In addition, by projecting an image that complements the invisible part, it is possible to confirm safety more naturally and without discomfort.
  • the display panel 5704 can also be used as a lighting device.
  • the GPU or chip of one aspect of the present invention can be applied as a component of artificial intelligence
  • the chip can be used, for example, in an automatic driving system of an automobile.
  • the chip can be used in a system for performing road guidance, danger prediction, and the like.
  • the display panel 5701 to the display panel 5704 may be configured to display information such as road guidance and danger prediction.
  • moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc., and the chip of one aspect of the present invention is applied to these moving objects. Therefore, it is possible to provide a system using artificial intelligence.
  • FIG. 31H shows an electric freezer / refrigerator 5800 which is an example of an electric appliance.
  • the electric freezer / refrigerator 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
  • the electric refrigerator-freezer 5800 By applying the chip of one aspect of the present invention to the electric refrigerator-freezer 5800, it is possible to realize the electric refrigerator-freezer 5800 having artificial intelligence.
  • the electric refrigerator-freezer 5800 has a function to automatically generate foods based on the foodstuffs stored in the electric refrigerator-freezer 5800, the expiration date of the foodstuffs, etc., and the foodstuffs stored in the electric food-freezer refrigerator 5800. It can have a function of automatically adjusting the temperature according to the above.
  • electric refrigerator / freezer has been described as an example of electric appliances
  • other electric appliances include, for example, vacuum cleaners, microwave ovens, microwave ovens, rice cookers, water heaters, IH cookers, water servers, and air conditioners. Examples include washing machines, dryers, and audiovisual equipment.
  • the electronic device described in this embodiment the function of the electronic device, the application example of artificial intelligence, its effect, etc. can be appropriately combined with the description of other electronic devices.
  • hafnium oxide zirconium (HfZrOx) is produced as an insulator exhibiting ferroelectricity, and measurement results such as voltage-polarization characteristics and fatigue characteristics of the insulator will be described.
  • FIG. 32A is an optical micrograph showing the appearance of the sample 800 used for evaluation.
  • FIG. 32B shows a schematic cross-sectional view of the sample 800.
  • the sample 800 was formed by using single crystal silicon as the substrate 801. Specifically, a thermal oxide film having a thickness of 100 nm is formed as an insulator 802 on the substrate 801 and a conductor 803 (conductor 803a and conductor 803b) functioning as a lower electrode is formed on the insulator 802. An insulator 804 was formed on the conductor 803, and a conductor 805 (conductor 805a and a conductor 805b) functioning as an upper electrode was formed on the insulator 804.
  • the insulator 806 was formed on the conductor 803, the insulator 804, and the conductor 805. Further, a conductor 807 that is electrically connected to the conductor 803 and a conductor 808 that is electrically connected to the conductor 805 are formed on the insulator 806. The conductor 807 and the conductor 808 function as electrodes to which the measurement signal is input.
  • the formation of the conductor 803, the conductor 805, the conductor 807, and the conductor 808, the formation of the contact holes provided in the insulator 806 and the insulator 804, and the like were performed using known photolithography methods and etching methods. ..
  • sample 800 three samples (Sample 800A, Sample 800B, and Sample 800C) having different formation conditions of the conductor 805 functioning as the upper electrode and heat treatment conditions after the formation of the upper electrode were prepared.
  • Table 1 shows the film forming conditions of the conductor 803a, the conductor 803b, the insulator 804, the conductor 805a, and the conductor 805b provided in each of the sample 800A, the sample 800B, and the sample 800C.
  • silicon oxide having a thickness of 200 nm was formed as an insulator 806 by the PECVD method. Further, as the conductor 807 and the conductor 808, a three-layer laminated film of Ti having a thickness of 50 nm, Al having a thickness of 200 nm, and Ti having a thickness of 50 nm was formed by a sputtering (SP) method.
  • SP sputtering
  • the conductor 805a is formed by a sputtering method, and in the sample 800C, the conductor 805a is formed by a metal CVD (MCVD) method. Further, the sample 800B is heat-treated by the RTA method after the sample is prepared. Table 1 also shows the heat treatment conditions.
  • FIG. 32C shows an input voltage waveform.
  • the HfZrOx film corresponding to the insulator 804 of each of the sample 800A, the sample 800B, and the sample 800C is crystallized by using the oblique incident X-ray diffraction method (GIXD), which is a kind of XRD analysis method. The condition was investigated.
  • GXD oblique incident X-ray diffraction method
  • an input voltage V which is a triangular wave
  • a current (output current I) flowing between the electrodes is measured (FIG. 33B).
  • the horizontal axis of FIGS. 33A and 33B is the elapsed time t.
  • the IV characteristic showing the relationship between the input voltage V and the output current I is obtained (FIG. 33C).
  • the PE characteristic is acquired by converting the output current I into the polarization P using the mathematical formula (1) (FIG. 33D).
  • A is the area where the two electrodes of the capacitive element overlap.
  • FIG. 34A shows the measurement results of the PE characteristics of the sample 800A, the sample 800B, and the sample 800C.
  • FIG. 34A shows the relationship between the electric field strength E applied to the insulator 804 and the polarization P for each sample.
  • FIG. 34B shows the GIXD measurement result.
  • FIG. 34B shows the relationship between the X-ray diffraction angle (2 ⁇ ) and the detected signal intensity for each sample.
  • sample 800A has a smaller amount of polarization (difference between the maximum polarization and the minimum polarization when the electric field strength E is 0 in the PE characteristics) than the sample 800B and the sample 800C, and is close to a normal dielectric.
  • a cross-sectional TEM image was taken of the insulator 804 of the samples 800A to 800C prepared as described above and its vicinity using "H-9500" manufactured by Hitachi High-Tech, with an acceleration voltage of 300 kV.
  • 35A shows a cross-sectional TEM image of the sample 800A
  • FIG. 36A shows a cross-sectional TEM image of the sample 800B
  • FIG. 37A shows a cross-sectional TEM image of the sample 800C.
  • FFT Fast Fourier Transform
  • FIGS. 35B, 36B, and 37B are shown in FIGS. 35B, 36B, and 37B.
  • 35B is an FFT figure of area A1
  • FIG. 35C is an FFT figure of area A2
  • FIG. 36B is an FFT figure of area B1
  • FIG. 36C is an FFT figure of area B2
  • FIG. 37B is an FFT figure of area C1. It is an FFT figure
  • FIG. 37C is an FFT figure of the area C2.
  • sample 800B the presence of a plurality of strong spots can be confirmed in regions B1 and B2.
  • sample 800C the presence of a plurality of strong spots can be confirmed in the regions C1 and C2.
  • the sample 800A the spot can be confirmed in the region A1, but the spot cannot be confirmed in the region A2. That is, it was found that the sample 800B and the sample 800C had higher crystallinity than the sample 800A. Therefore, it was found that the sample 800B and the sample 800C, which have a large amount of polarization and a high ferroelectricity, have high crystallinity.
  • FIGS. 38A to 38C a cross-sectional TEM image was taken of the vicinity of the interface between the insulator 804 and the conductor 805a using "H-9500" manufactured by Hitachi High-Tech, with an acceleration voltage of 300 kV.
  • 38A shows a cross-sectional TEM image of the sample 800A
  • FIG. 38B shows a cross-sectional TEM image of the sample 800B
  • FIG. 38C shows a cross-sectional TEM image of the sample 800C.
  • the lattice fringes of the crystal of interest are shown in an enlarged manner with solid lines.
  • lattice fringes derived from TiNx crystals were observed on the conductor 805a.
  • FIG. 38B in the sample 800B, plaids derived from crystals of HfZrOx were observed in the insulator 804.
  • FIG. 38C in the sample 800C, lattice fringes derived from the crystals of TiNx were observed on the conductor 805a, and lattice fringes derived from the crystals of HfZrOx were observed on the insulator 804.
  • energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy) is performed on the vicinity of the interface between the insulator 804 and the conductor 805a and the vicinity of the interface between the insulator 804 and the conductor 803b. ) was analyzed.
  • the EDX analysis was performed at each point on a straight line traversing the above interface. In the present specification and the like, such EDX analysis may be referred to as line EDX analysis.
  • the line EDX analysis was performed using "HD-2700" manufactured by Hitachi High-Tech, with an acceleration voltage of 200 kV.
  • oxygen atoms [atomic%] and hafnium atoms [atomic%] are detected, and oxygen atoms are detected near the interface between the insulator 804 and the conductor 805a, and near the interface between the insulator 804 and the conductor 803b.
  • Half values of [atomic%] and hafnium atom [atomic%] were calculated.
  • a different layer such as TiOx is not formed near the interface between the insulator 804 and the conductor 805a (or near the interface between the insulator 804 and the conductor 803b)
  • the half value of the oxygen atom [atomic%] and the hafnium atom [atomic%] are not formed.
  • the half value of the oxygen atom [atomic%] shifts to the conductor 805a (or conductor 803b) side. That is, the difference between the half value of the oxygen atom [atomic%] and the half value of the hafnium atom [atomic%] is presumed to be the film thickness of TiOx.
  • FIG. 39 The result of line EDX analysis is shown in FIG. In FIG. 39, the film thickness [nm] of TiOx is taken on the vertical axis.
  • the vicinity of the interface between the insulator 804 and the conductor 805a of each sample is defined as the upper part of 800A, the upper part of 800B, and the upper part of 800C, respectively.
  • the vicinity of the interface between the insulator 804 and the conductor 803b of each sample is defined as the lower part of 800A, the lower part of 800B, and the lower part of 800C, respectively.
  • the TiOx film thickness was 0.2 nm at the upper part, and no different layer of the TiOx film was detected at the lower part.
  • the TiOx film thickness was 0.2 nm at the upper part, and no different layer of the TiOx film was detected at the lower part.
  • the TiOx film thickness was 0.4 nm at the upper part and 0.3 nm at the lower part. That is, the sample 800B and the sample 800C tended to have a thinner different layer of the TiOx film than the sample 800A. Therefore, it was found that in Sample 800B and Sample 800C, which have a large amount of polarization and higher ferroelectricity, the different layer of the TiOx film may become thin.
  • the surface roughness of the conductor 803b which is the base of the insulator 804, was evaluated.
  • a Z contrast image (ZC image: Z Contrust Image) was taken with respect to the cross sections N1 to N6 using the dark field STEM function of "HD-2700" manufactured by Hitachi High-Tech. Image analysis was performed on the ZC images of the cross sections N1 to N6, and the line of the interface between the insulator 804 and the conductor 803b of each ZC image was drawn.
  • “ImageJ” was used as image processing software for interface extraction. Arithmetic mean roughness (Ra) and root mean square roughness (RMS: Root Mean Square) were calculated for the interface lines of the cross sections N1 to N6.
  • Ra [nm] of cross sections N1 to N6 is shown in FIG. 40A
  • RMS [nm] of cross sections N1 to N6 is shown in FIG. 40B.
  • the roughness of the upper surface of the sample 800C is 1 nm or less in Ra and RMS in the cross sections N1 to N6.
  • Ra and RMS are 0.4 nm or less. Therefore, in order to improve the crystallinity and develop the ferroelectricity in the insulator 804, the roughness of the upper surface of the underlying conductor 803b is set to 2 nm or less, preferably 1 nm or less, more preferably Ra or RMS. May be 0.8 nm or less, more preferably 0.5 nm or less, still more preferably 0.4 nm or less.
  • FIGS. 41 to 44 show the SIMS analysis results.
  • the horizontal axis of FIGS. 41 to 44 shows the depth from the surface of the conductor 805b
  • the vertical axis of FIG. 41 shows the hydrogen concentration in the insulator 804
  • the vertical axis of FIG. 42 shows the carbon concentration in the insulator 804.
  • the vertical axis of FIG. 43 shows the nitrogen concentration in the insulator 804, and the vertical axis of FIG. 44 shows the chlorine concentration in the insulator 804.
  • the positions of the conductor 805b, the conductor 805a, the insulator 804, the conductor 803b, and the conductor 803a in the depth direction specified from the film thickness and the SIMS profile are added.
  • the curve 811A shows the SIMS analysis result of the sample 800A
  • the curve 811B shows the SIMS analysis result of the sample 800B
  • the curve 811C shows the SIMS analysis result of the sample 800C.
  • the hydrogen concentration of the insulator 804 was about 4 ⁇ 10 20 atoms / cm 3 for the sample 800A, about 2 ⁇ 10 20 atoms / cm 3 for the sample 800B, and about 9 ⁇ 10 19 atoms / cm 3 for the sample 800C.
  • the curve 812A shows the SIMS analysis result of the sample 800A
  • the curve 812B shows the SIMS analysis result of the sample 800B
  • the curve 812C shows the SIMS analysis result of the sample 800C.
  • the carbon concentration of the insulator 804 was about 9 ⁇ 10 18 atoms / cm 3 for sample 800A, about 1 ⁇ 10 19 atoms / cm 3 for sample 800B, and about 6 ⁇ 10 18 atoms / cm 3 for sample 800C (sample 800C). See FIG. 42).
  • the curve 813A shows the SIMS analysis result of the sample 800A
  • the curve 813B shows the SIMS analysis result of the sample 800B
  • the curve 813C shows the SIMS analysis result of the sample 800C. It is considered that the nitrogen concentration of the insulator 804 of the sample 800A, the sample 800B, and the sample 800C is about 8 ⁇ 10 20 atoms / cm 3 or less.
  • the curve 814A shows the SIMS analysis result of the sample 800A
  • the curve 814B shows the SIMS analysis result of the sample 800B
  • the curve 814C shows the SIMS analysis result of the sample 800C.
  • the chlorine concentration of the insulator 804 was about 1 ⁇ 10 21 atoms / cm 3 .
  • both the hydrogen concentration of the insulator 804 and the carbon concentration of the insulator 804 are the lowest in the sample 800C in which the conductor 805a is formed by the thermal ALD method.
  • the nitrogen concentration of the insulator 804 may be affected by the adjacent titanium nitride (TiNx), but is about 8 ⁇ 10 20 atoms / cm 3 or less.
  • TiNx adjacent titanium nitride
  • FIGS. 44 and 34 it can be seen that even if chlorine is present in the insulator 804 at about 1 ⁇ 10 21 atoms / cm3 , it does not hinder the development of ferroelectricity.
  • the hydrogen concentration in the insulator 804 is preferably 5 ⁇ 10 20 atoms / cm 3 or less, and more preferably 1 ⁇ 10 20 atoms / cm 3 or less.
  • the carbon concentration in the insulator 804 is preferably 5 ⁇ 10 19 atoms / cm 3 or less, and more preferably 1 ⁇ 10 19 atoms / cm 3 or less.
  • the results of fatigue characteristic measurement performed on the sample 800B and the sample 800C shown in the first embodiment will be described.
  • the measurement of fatigue characteristics was performed on two samples 800B (sample 800B_1, sample 800B_2) and three samples 800C (sample 800C_1, sample 800C_2, sample 800C_3).
  • the sample 800B_1 and the sample 800B_2 are different elements on the same substrate manufactured under the same conditions as the sample 800B.
  • Sample 800C_1, Sample 800C_2, and Sample 800C_3 are different elements on the same substrate manufactured under the same conditions as Sample 800B.
  • FIG. 45A shows the measurement results of the fatigue characteristics of the sample 800B_1 and the sample 800B_2.
  • FIG. 45B shows the measurement results of the fatigue characteristics of the sample 800C_1 and the sample 800C_2.
  • FIG. 46B shows the measurement results of the fatigue characteristics of the sample 800C_3.
  • the horizontal axis shows the number of cycles, and the vertical axis shows the polarization P.
  • one cycle is to apply a rectangular angular wave having a voltage amplitude of 3 V and a frequency of 100 Hz as one cycle, and the PE characteristics are measured using the triangular wave shown in Example 1 every specified number of cycles to measure the electric field.
  • the minimum polarization and the maximum polarization when the intensity E was 0 were obtained.
  • FIGS. 45A and 45B show the values of the minimum polarization and the maximum polarization when the electric field strength E is 0, which are acquired every specified number of cycles.
  • Samples 800B_1 and 800C_1 were discontinued after 1 ⁇ 108 cycles.
  • Sample 800B_2 and Sample 800C_2 continued to be measured after 1 ⁇ 108 cycles.
  • Sample 800B_2 shows the measurement results up to 8.6 ⁇ 10 10 cycles, but the measurement was continued thereafter.
  • sample 800C_2 was destroyed after the end of 4.6 ⁇ 109 cycles.
  • FIG. 46A shows the initial PE characteristics (curve 821) of the sample 800C_3 and the PE characteristics (curve 822) after the end of the 1 ⁇ 10 10 cycle. Further, as compared with FIG. 9 (fatigue characteristics described in Non-Patent Document 2), it can be seen that the changes in the fatigue characteristics of the sample 800B_1, the sample 800B_2, the sample 800C_1, the sample 800C_2, and the sample 800C_3 are gentle. Therefore, it can be expected to realize fatigue resistance of 1 ⁇ 10 15 cycles or more.
  • hafnium oxide zirconium (HfZrOx) is produced as an insulator exhibiting ferroelectricity, and the results of evaluating the voltage-polarization characteristics, fatigue characteristics, etc. of the insulator will be described.
  • sample structure As the appearance and the schematic cross-sectional view of the sample 830 used for the evaluation can refer to the description relating to the sample 800 of the first embodiment, detailed description thereof will be omitted.
  • the sample 830 was formed by using single crystal silicon as the substrate 801. Specifically, a thermal oxide film having a thickness of 100 nm is formed as an insulator 802 on the substrate 801 and a conductor 803 (conductor 803a and conductor 803b) functioning as a lower electrode is formed on the insulator 802. An insulator 804 was formed on the conductor 803, and a conductor 805 (conductor 805a and a conductor 805b) functioning as an upper electrode was formed on the insulator 804.
  • the insulator 806 was formed on the conductor 803, the insulator 804, and the conductor 805. Further, a conductor 807 that is electrically connected to the conductor 803 and a conductor 808 that is electrically connected to the conductor 805 are formed on the insulator 806. The conductor 807 and the conductor 808 function as electrodes to which the measurement signal is input.
  • the formation of the conductor 803, the conductor 805, the conductor 807, and the conductor 808, the formation of the contact holes provided in the insulator 806 and the insulator 804, and the like were performed using known photolithography methods and etching methods. ..
  • sample 830 16 samples (samples 830A to 830P) having different formation conditions and thickness of the insulator 804, formation conditions of the conductor 805 functioning as the upper electrode, and heat treatment conditions after the formation of the upper electrode were prepared. ..
  • Tables 2 to 5 show the film forming conditions of the conductor 803a, the conductor 803b, the insulator 804, the conductor 805a, and the conductor 805b provided in each of the samples 830A to 830P.
  • silicon oxide having a thickness of 200 nm was formed as an insulator 806 by the PECVD method. Further, as the conductor 807 and the conductor 808, a three-layer laminated film of Ti having a thickness of 50 nm, Al having a thickness of 200 nm, and Ti having a thickness of 50 nm was formed by a sputtering (SP) method.
  • SP sputtering
  • the insulator 804 was formed into a film by the ALD method using an inorganic precursor. Specifically, in Samples 830A to 830H, HfCl 4 (hafnium chloride) and ZrCl 4 (zirconium chloride) were used as inorganic precursors, and H2O (water) was used as an oxidizing agent.
  • HfCl 4 hafnium chloride
  • ZrCl 4 zirconium chloride
  • Samples 830I to 830P are Hf [N (CH 3 ) 2 ] 4 (TEMAH: Tetracis (ethylmethyramino) hafnium) and Zr (Cp) [(N (CH 3 ) 2 ] 3 ) as organic precursors. (Cyclopentadienyltris (dimethylamino) zirconium) was used, and O3 ( ozone) was used as an oxidizing agent.
  • TEMAH Tetracis (ethylmethyramino) hafnium)
  • Zr (Cp) [(N (CH 3 ) 2 ] 3 ) as organic precursors.
  • O3 ozone
  • the thickness of the insulator 804 was set to 4 nm.
  • the thickness of the insulator 804 was set to 6 nm.
  • the thickness of the insulator 804 was set to 8 nm.
  • the thickness of the insulator 804 was set to 10 nm.
  • the conductor 805a was formed into a film by a metal CVD (MCVD) method.
  • MCVD metal CVD
  • the conductor 805a was formed into a film by a sputtering method.
  • the samples 830E to 830H and the samples 830M to 830P were heat-treated by the RTA method after the samples were prepared. Tables 2 to 5 also show the heat treatment conditions.
  • ⁇ PE characteristics> A triangular wave having a voltage amplitude of 3 V and a frequency of 100 Hz was applied between the conductor 807 and the conductor 803, and the change in spontaneous polarization (PE characteristic) of the insulator 804 was measured.
  • the description of the first embodiment can be referred to, and detailed description thereof will be omitted.
  • FIG. 47 shows the measurement results of PE characteristics of Samples 830A to 830H.
  • FIG. 48 shows the measurement results of the PE characteristics of the samples 830I to 830P. 47 and 48 show the relationship between the electric field strength E and the polarization P applied to the insulator 804 for each sample, respectively.
  • FIG. 49 shows the results of measuring the IV characteristics of Samples 830A to 830H.
  • FIG. 50 shows the results of measuring the IV characteristics of Samples 830I to 830P. 49 and 50 show the relationship between the applied voltage and the flowing current for each sample, respectively.
  • FIG. 51 shows the GIXD measurement results of Samples 830A to 830H.
  • FIG. 52 shows the GIXD measurement results of Samples 830I to 830P.
  • 51 and 52 show the relationship between the X-ray incident angle (2 ⁇ ) and the detected signal intensity for each sample, respectively.
  • the peak position of the HfZrOx crystal is shown by a broken line, the peak position of the monoclinic crystal is m, the peak position of the orthorhombic crystal is o, and the tetragonal crystal (orthorhombic crystal).
  • the peak position of the monoclinal crystal is described as t, and the peak position of the cubic crystal is described as c. It is difficult to discriminate between orthorhombic (o), tetragonal (t), and cubic (c) by XRD.
  • the fatigue characteristics are measured by applying a rectangular angular wave with a voltage amplitude of 3 V and a frequency of 100 Hz for one cycle, and measuring the PE characteristics using the above-mentioned triangular wave every specified number of cycles to determine the electric field strength E.
  • the minimum and maximum polarizations at 0 were obtained.
  • FIG. 53 shows the measurement results of the fatigue characteristics of the sample 830H and the sample 830P.
  • the first stage of FIG. 53 shows the PE characteristics at the initial stage and the end of the fatigue characteristic measurement.
  • the second stage of FIG. 53 shows the measurement result of the fatigue characteristic, the horizontal axis shows the number of cycles, and the vertical axis shows the polarization P.
  • the third stage of FIG. 53 shows the value normalized by the initial polarization P of the fatigue characteristic measurement.
  • hafnium oxide zirconium (HfZrOx) is produced as an insulator exhibiting ferroelectricity, and the result of evaluating the frequency dependence of the input voltage (triangular wave) on the voltage-polarization characteristic of the insulator will be described.
  • Example structure As for the appearance and the schematic cross-sectional view of the sample used for the evaluation, the description relating to the sample 800 of Example 1 can be referred to, and therefore detailed description thereof will be omitted.
  • the sample was formed using single crystal silicon as the substrate 801. Specifically, a thermal oxide film having a thickness of 100 nm is formed as an insulator 802 on the substrate 801 and a conductor 803 (conductor 803a and conductor 803b) functioning as a lower electrode is formed on the insulator 802. An insulator 804 was formed on the conductor 803, and a conductor 805 (conductor 805a and a conductor 805b) functioning as an upper electrode was formed on the insulator 804.
  • W having a thickness of 30 nm was formed into a film by a sputtering (SP) method.
  • MCVD metal CVD
  • hafnium oxide zirconium (HfZrOx) having a thickness of 10 nm was formed into a film by the ALD method using an inorganic precursor. Specifically, HfCl 4 (hafnium chloride) and ZrCl 4 (zirconium chloride) were used as the inorganic precursor, and H2O (water) was used as the oxidizing agent.
  • the substrate temperature at the time of film formation of hafnium oxide zirconium (HfZrOx) was set to 300 ° C.
  • TiNx having a thickness of 10 nm was formed into a film by a sputtering (SP) method.
  • W having a thickness of 20 nm was formed into a film by a sputtering (SP) method.
  • the insulator 806 was formed on the conductor 803, the insulator 804, and the conductor 805. Further, a conductor 807 that is electrically connected to the conductor 803 and a conductor 808 that is electrically connected to the conductor 805 are formed on the insulator 806. The conductor 807 and the conductor 808 function as electrodes to which the measurement signal is input.
  • the formation of the conductor 803, the conductor 805, the conductor 807, and the conductor 808, the formation of the contact holes provided in the insulator 806 and the insulator 804, and the like were performed using known photolithography methods and etching methods. ..
  • heat treatment was performed by the RTA method.
  • the heat treatment was carried out at 500 ° C. for 60 sec in a nitrogen atmosphere.
  • ⁇ PE characteristics> A triangular wave having a voltage amplitude of 3 V was applied between the conductor 807 and the conductor 803, and the change in spontaneous polarization (PE characteristic) of the insulator 804 was measured. The evaluation was performed by making the frequency of the triangular wave different from 1 kHz, 100 Hz, and 10 Hz.
  • the description of the first embodiment can be referred to, and detailed description thereof will be omitted.
  • FIG. 54 shows the measurement results of PE characteristics.
  • FIG. 54 shows the relationship between the electric field strength E applied to the insulator 804 and the polarization P.
  • the solid line 831 shows the data of the frequency 10 Hz
  • the broken line 832 shows the data of 100 Hz
  • the dotted line 833 shows the data of 1 kHz.
  • FIGS. 55A and 55B show enlarged views of the region shown by the alternate long and short dash line in FIG. 54.
  • FIGS. 55C and 55D show the relationship between the polarization P and the frequency of the triangular wave.
  • FIG. 55C shows the polarization P when the electric field E is 0 MV / cm
  • FIG. 55D shows the polarization P when the electric field E is 3 MV / cm (voltage 3 V).
  • the single crystal model was used as a calculation model used for first-principles calculation.
  • the calculation model is shown in FIG. 56A. Some of the atoms are omitted to make the drawings easier to see.
  • the potential generated by the Projector Augmented Wave (PAW) method was used for the electronic state pseudopotential, and GGA / PBE (Generalized-Gradient-Perdewation / Perdew-Burke-Ernzerhof) was used for the functional.
  • the size of the calculation model (lattice constant and inter-axis angle) was constant.
  • Figure 56B shows the calculation model after performing the calculation to optimize the atomic arrangement. Some of the atoms are omitted to make the drawings easier to see.
  • the distance between the carbon atom and each of the three oxygen atoms coordinated to the carbon atom is about 0.13 nm, and the carbon atom and the carbon thereof.
  • the distance from each of the four oxygen atoms away from the atom was 0.30 nm or more and 0.35 nm or less.
  • the oxygen atom coordinated to the carbon atom does not have inversion symmetry, that is, it is an oxygen atom that exhibits ferroelectricity.
  • the oxygen atom is strongly bound to the carbon atom, which may be affected by the displacement due to the electric field.
  • the oxygen atom separated from the carbon atom (the oxygen atom in the region surrounded by the one-point chain line in FIG. 56B) has the number of bonds with the hafnium atom or the zirconium atom as the single crystal model of hafnium oxide zirconium. It is decreasing compared to. Therefore, it is presumed that the oxygen atom is easily deleted.
  • FIG. 57A shows a measurement system for retention measurement.
  • FIG. 57B shows an operation sequence of retention measurement.
  • 58A, 58B and 58C show the results of retention measurement.
  • At least a pulse generator and an ammeter are provided as a measurement system for retention measurement.
  • the measurement was performed at room temperature.
  • a pulse generator is used to apply a potential to the sample and measure the current flowing at that time.
  • the operation sequence of the retention measurement shown in FIG. 57B will be described.
  • a negative potential is applied to the sample to bring it into a polarized state on the negative potential side.
  • a pulse of a positive potential (3V, a rectangular wave of 5sec) is applied twice to bring the polarization state on the negative potential side.
  • the reason for giving two pulses in the period T3 is to cancel the steady-state leak, and then in the period T4 of about 10 seconds, after passing through the potential of 0V, in the period T5, with the period T3.
  • the same positive potential pulse is given twice. Since the period T4 is short and the polarization of the sample is maintained, the current due to the displacement of the polarization does not flow in the period T5, but the current due to the leak exists.
  • a two-condition holding period of 10 minutes and 10 hours for retention measurement is held at a potential of 0 V.
  • the same positive potential pulses as those in the period T3 and the period T5 are applied twice, and the currents flowing through the sample are compared.
  • the current flowing in the period T7 is larger than the current flowing in the period T5, it is highly likely that the polarization is reduced in the period T6.
  • FIG. 58A shows the current change in the period T5
  • FIG. 58B shows the current change in the period T7 after holding 10 minutes as the period T6
  • FIG. 58C shows the current change in the period T7 after holding 10 hours as the period T6. Comparing FIGS. 58A, 58B, and 58C, it is considered that the sample 800B can retain the polarized state for at least 10 hours because the current in the period T7 does not increase even after the retention time of 10 hours.
  • a triangular wave having a voltage amplitude of 3 V and a frequency of 100 Hz was applied between a pair of electrodes of one capacitor, and a change in spontaneous polarization (PV characteristic) of an insulator or a dielectric was measured.
  • the horizontal axis is the input voltage V, which is a triangular wave, and the vertical axis is the value obtained by converting the output current I into the polarization P using the mathematical formula (1).
  • the transistor may be manufactured by the manufacturing method shown in the second embodiment, and the transistor structure is not particularly limited. Using a configuration in which a transistor 200 as shown in FIG. 20A, specifically, a planar type capacitive element 100 is provided on the insulator 285, comparative examples, CVD-TiN, and SP-TiN PV characteristic measurement results are shown. FIG. 59A shows. Further, FIG. 59B shows the measurement result of the IV characteristic.
  • the electrode size was set to 300 parallels of 1.265 ⁇ m ⁇ 1.05 ⁇ m, the total is 398.5 ⁇ m 2 .
  • the lower electrode is a laminate of a tungsten film (substrate temperature 130 ° C., film thickness: 30 nm) obtained by a sputtering method and a titanium nitride film (substrate temperature 400 ° C., film thickness: 10 nm) obtained by a metal CVD method.
  • An aluminum oxide film obtained by the ALD method (substrate temperature 250 ° C., film thickness: 14 nm) and a silicon nitride film obtained by the PECVD method (substrate temperature 350 ° C., film thickness: 7 nm) are laminated on the lower electrode.
  • a titanium nitride film (substrate temperature 400 ° C., film thickness: 10 nm) obtained by the metal CVD method and a tungsten film (substrate temperature 130 ° C., film thickness: 20 nm) obtained by the sputtering method are laminated on the upper electrode.
  • the sample described as CVD-TiN has a different film sandwiched between the lower electrode and the upper electrode from the comparative example, and is an HfZrOx film having a film thickness of 10 nm.
  • the film forming conditions of the HfZrOx film are the same as those of the insulator 804 of Example 1, and the ALD method is used, a chloride-based precursor is used, the substrate temperature is 300 ° C., and H2O is used as the oxidizing agent.
  • the residual polarization amount Pr per unit area of the sample expressed as CVD-TiN is approximately 12.1.
  • the film sandwiched between the lower electrode and the upper electrode is an HfZrOx film having a film thickness of 10 nm, and a titanium nitride film obtained by a sputtering method and a tungsten film obtained by a sputtering method (titanium nitride film obtained by a sputtering method) are placed on the HfZrOx film.
  • the thickness is 20 nm).
  • the film forming conditions for the titanium nitride film obtained by the sputtering method were such that the substrate temperature was room temperature.
  • the residual polarization amount Pr per unit area of the sample expressed as SP-TiN is about 12.8.
  • FIGS. 60A and 60B show measurement results of the ID - VG characteristics of the transistors used in the comparative examples, CVD-TiN and SP-TiN samples, respectively.
  • the horizontal axis is the top gate potential VG [V]
  • the first vertical axis is the drain current ID [A]
  • the shift voltage Vsh of the transistor was calculated from the result of the above ID -VG measurement, and the standard deviation ⁇ (Vsh) was obtained.
  • the standard deviation ⁇ (Vsh) of the SP-TiN sample of FIG. 60A was 64 mV, which was a good value.
  • the field effect mobility ⁇ FE of the SP-TiN sample of FIG. 60A was 14 cm 2 / Vs.
  • the shift voltage ( Vsh ) and subthreshold swing value (S value) of the transistor were calculated.
  • the S value of the SP-TiN sample of FIG. 60A was 107 mV / dec.
  • FIG. 60B shows the electrical characteristics of one of the measurement circuits in which the elements of 1Tr1C (1 transistor, 1 capacitor) are arranged at a density of 8.4 / ⁇ m 2 .
  • FIG. 60A is an electrical characteristic of one transistor when the layout of the arrangement of the measurement circuit is different from that of FIG. 60B.
  • the element configuration of 3Tr1C (3 transistors, 1 capacitor) is manufactured, the writing operation and the reading operation are performed, and the results of measuring the electrical characteristics are shown below.
  • the transistor OS1 is connected to the gate line WWL, the signal line WBL, and the node SN. Further, in the transistor OS2, the gate is connected to the node SN and is connected to the source line SL. Further, the transistor OS3 is connected to the gate line RWL and the signal line RBL. The drain electrode (or source electrode) of the transistor OS2 and the source electrode (or drain electrode) of the transistor OS3 are electrically connected.
  • the back gate potential BG1 of the transistor OS1 and the back gate potential BG2 of the transistor OS2 and the transistor OS3 are fixed potentials, specifically 0V.
  • FIG. 61A shows an example in which the capacitive element MFM is used as 1C.
  • the capacitive element MFM has a structure in which a lower electrode, an HfZrOx film having a film thickness of 10 nm, and an upper electrode are laminated.
  • the area of the capacitive element MFM is 0.25 ⁇ m 2 .
  • the capacitive element MFM is electrically connected to the node SN and the signal line C.
  • the lower electrode is a laminate of a tungsten film (substrate temperature 130 ° C., film thickness: 30 nm) obtained by the sputtering method and a titanium nitride film (substrate temperature 400 ° C., film thickness: 10 nm) obtained by the metal CVD method, and the upper electrode is formed.
  • Example 7 uses the same manufacturing process as the transistor and the capacitive element.
  • FIG. 62A An example of a timing chart for measurement is shown in FIG. 62A.
  • the names such as WWL, WBL, C, RWL, SN, and RBL in the timing chart indicate the wiring to which the potential shown in the timing chart is given.
  • the source line SL is not shown in the timing chart, it is assumed that a predetermined potential (constant potential) is applied.
  • FIGS. 62B1 and 62B2 The equivalent circuit shown in FIG. 62B1 is the same as that in FIG. 61A, but since BG1 and BG2 are 0V, the description of BG1 and BG2 is omitted.
  • the potential of the gate line WWL is set to the potential at which the transistor OS1 is turned on, and the transistor OS1 is turned on.
  • the potential of the signal line WBL is given to the gate electrode of the transistor OS2.
  • 3V is applied to the signal line C during 10 ms while the transistor OS1 is in the ON state.
  • the period in which 3V is applied to the capacitive element MFM is called a Pr + set period.
  • a predetermined charge is given to the gate electrode of the transistor OS2, but in this measurement method, the potential of the signal line WBL is always set to 0V as shown in the timing chart of FIG. 62A. Then, as shown on the right half side of FIG.
  • the positive residual polarization (Pr +) direction is given to the capacitive element MFM (first writing).
  • the arrow shown on the right half side of FIG. 62B2 corresponds to the arrow of the Pr + set period in FIG. 62A.
  • the potential of the gate line WWL is set to the potential at which the transistor OS1 is turned off, and the transistor OS1 is turned off.
  • the gate line RWL corresponds to a read word line
  • the gate line WWL corresponds to a write word line
  • the signal line WBL corresponds to a write bit line
  • the signal line RBL corresponds to a read bit line.
  • the transistor OS1 is turned off and the signal line WBL gives a potential instead of 0V, the charge given to the gate electrode of the transistor OS2 can be retained (retention).
  • the off current of the transistor OS1 is extremely small, so that the charge of the gate electrode of the transistor OS2 is retained for a long time.
  • the transistor OS3 is kept off.
  • the node SN is set to a floating potential
  • the transistor OS3 is turned on, and the signal line C is swept from 0V to 3V (potential sweep), so that the current value I of the signal line RBL is set.
  • the electrical characteristics (Pr +) in which the RBL is measured and the vertical axis at that time is the current value I RBL and the horizontal axis is the voltage VC of the signal line C are shown in FIG. 63A.
  • the potential of the gate line WWL is set to the potential at which the transistor OS1 is in the ON state, and -3V is applied to the signal line C during 10 ms while the transistor OS1 is in the ON state.
  • the period in which -3V is applied to the capacitive element MFM is called a Pr-set period. That is, a predetermined charge is given to the gate electrode of the transistor OS2, and a negative residual polarization (Pr ⁇ ) direction is given to the capacitive element MFM as shown on the left half side of FIG. 62B2 (second writing). ..
  • the arrow shown on the left half side of FIG. 62B2 corresponds to the arrow of the Pr-set period in FIG. 62A.
  • the transistor OS3 is kept off.
  • the transistor OS1 is turned off to make the node SN a floating potential, the transistor OS3 is turned on, and the signal line C is swept from 0V to 3V to cause the current of the signal line RBL.
  • the electrical characteristics (Pr ⁇ ) in which the value I RBL is measured and the vertical axis at that time is the current value I RBL and the horizontal axis is the voltage VC of the signal line C are shown as dotted lines in FIG. 63A.
  • the equivalent circuit shown in FIG. 62C1 is the same as that in FIG. 61A, but since BG1 and BG2 are 0V, the description of BG1 and BG2 is omitted.
  • the sweep after applying 3V to the capacitive element MFM is displayed 20 times, and the sweep after applying -3V to the capacitive element MFM is displayed 20 times, for a total of 40 times.
  • FIG. 63B shows the results obtained by using the same measurement method and using the same element configuration as that of the comparative example of Example 7.
  • the measurement results are repeated four times, two times for sweeping after applying 3V to the capacitive element MFM and two times for sweeping after applying -3V to the capacitive element.
  • the electrical characteristics (Pr +) are shown as solid lines, and the electrical characteristics (Pr ⁇ ) are shown as dotted lines in FIG. 63A.
  • the comparative example is the same process as the comparative example shown in Example 7.
  • the lower electrode is formed by laminating a tungsten film (substrate temperature 130 ° C., film thickness: 30 nm) obtained by a sputtering method and a titanium nitride film (substrate temperature 400 ° C., film thickness: 10 nm) obtained by a metal CVD method, and on the lower electrode.
  • An aluminum oxide film (substrate temperature 250 ° C., film thickness: 14 nm) obtained by the ALD method and a silicon nitride film (substrate temperature 350 ° C., film thickness: 7 nm) obtained by the PECVD method are laminated on the upper electrode.
  • the titanium nitride film (substrate temperature 400 ° C., film thickness: 10 nm) obtained by the metal CVD method and the tungsten film (substrate temperature 130 ° C., film thickness: 20 nm) obtained by the sputtering method are laminated.
  • the structure of the sample whose characteristics were measured is a capacitive element 100 as shown in FIG. 20, and 300 elements having an electrode size of 1.265 ⁇ m ⁇ 1.05 ⁇ m are connected via a wiring layer and have an area. A is 398.5 ⁇ m 2 in total.
  • FIG. 64A shows the measurement system of the f characteristic.
  • FIG. 64B shows an operation sequence for measuring the f characteristic.
  • Figures 64C and 64D show hypothetical views of changes in polarization.
  • FIG. 65 shows the result of retention measurement.
  • At least a pulse generator and an ammeter are provided as a measurement system for the f characteristic.
  • the measurement was performed at room temperature.
  • DG2020A manufactured by Tektronix Co., Ltd. was used as the pulse generator
  • semiconductor parameter analyzer B1500A manufactured by KEYSIGHT Co., Ltd. was used as the ammeter.
  • a pulse generator is used to apply a potential to the sample and measure the current flowing at that time.
  • the operation sequence of the measurement of the f characteristic shown in FIG. 64B will be described.
  • a pulse of a negative potential is applied to the sample to bring it into a polarization state on the negative potential side.
  • a pulse of a positive potential is applied in the period T3, and the current flowing through the sample is measured.
  • the pulse width (time) of the positive potential given in the period T3 under a plurality of conditions, the time required for reversing the polarization can be evaluated.
  • the measurement was performed under a plurality of conditions, from the condition that the width of the rectangular wave pulse of the positive potential was 1 sec to the condition that the width was 5 nsec, as the condition of the period T3.
  • the condition of 1 sec can be called 0.5 Hz
  • the condition of 5 n sec can be called 100 MHz.
  • a positive potential pulse of a sufficient length is applied in the period T5, and the current flowing through the sample is measured.
  • the sufficient length is the time until the change in the current value flowing through the sample disappears, and is set to 1 sec in this embodiment.
  • a pulse having the same positive potential as in the period T5 is applied, and the current flowing through the sample is measured.
  • the amount of charge derived from the reversal of the polarization in the period T5 and another factor such as a leak component is possible to separate the amount of electric charge derived from.
  • ⁇ Pr which is an index of polarization
  • the area A is the area where the two electrodes of the capacitive element overlap.
  • FIGS. 64B, 64C, and 64D a case where the polarization can be reversed in the measurement of the f characteristic and a case where the polarization cannot be reversed will be described.
  • FIG. 64C is an assumed diagram of the change in polarization between the period T1 and the period T5 when the polarization can be reversed in the period T3, showing a positive polarization state in the period T4 as shown by P4a.
  • FIG. 64D is an assumed diagram of the change in polarization between the period T1 and the period T5 when the polarization cannot be reversed in the period T3, and in the period T4, it reverses to the positive polarization state as shown by P4b. Indicates a state in which it cannot be done.
  • Whether or not the polarization could be reversed in the period T3 can be judged by the amount of charge flowing in the period T5, and if the polarization can be maintained, the amount of charge flowing in the period T5 is small and the polarization cannot be maintained. In that case, the amount of charge flowing during the period T5 increases.
  • the measurement result of the f characteristic is shown in FIG. 65.
  • the conditions for the period T3 measurements were performed under four conditions of 1 sec (0.5 Hz), 100 nsec (5 MHz), 10 nsec (50 MHz), and 5 nsec (100 MHz).
  • the measurement result when the writing is not performed in the period T3 is also shown.
  • ⁇ Pr was sufficiently small as compared with the case where the writing was not performed, and it was a value that can be judged that the polarization could be reversed in the writing in the period T3. Therefore, it can be said that the sample of this example is a result showing that the rewriting operation at at least 100 MHz is possible.
  • FIG. 66A shows a measurement system for retention measurement.
  • FIG. 66B shows an operation sequence of retention measurement.
  • FIGS. 66C and 66D show an assumed diagram of the change in polarization.
  • FIG. 67A shows the result of retention measurement.
  • a pulse generator and an ammeter are provided as a measurement system for retention measurement.
  • the measurement was performed at room temperature.
  • M9185B manufactured by KEYSIGHT was used as the pulse generator
  • semiconductor parameter analyzer B1500A manufactured by KEYSIGHT was used as the ammeter.
  • a prober equipped with a stage with a temperature adjustment function was used in order to perform retention measurement under a plurality of temperature conditions.
  • a pulse generator is used to apply a potential to the sample and measure the current flowing at that time.
  • the operation sequence of the retention measurement shown in FIG. 66B will be described.
  • a pulse of a negative potential is applied to the sample to bring it into a polarization state on the negative potential side.
  • the retention period described later is held at a potential of 0 V for retention measurement.
  • a positive potential pulse is applied and the current flowing through the sample is measured.
  • a pulse having the same positive potential as in the period T3 is applied, and the current flowing through the sample is measured.
  • the amount of charge derived from the reversal of the polarization in the period T3 and another factor such as a leak component can be obtained.
  • ⁇ Pr which is an index of polarization
  • the area A is the area where the two electrodes of the capacitive element overlap.
  • FIGS. 66B, 66C and 66D a case where the polarization can be maintained by the retention measurement and a case where the polarization cannot be maintained will be described.
  • FIG. 66C is a hypothetical diagram of the change in polarization between the period T1 and the period T3 when the polarization can be maintained in the period T2, and as shown by P2a even at the end of the period T2, the polarization. Holds.
  • FIG. 66D is a hypothetical diagram of the change in polarization between period T1 and period T3 when the polarization could not be retained during period T2, and at the end of period T2, the polarization is reduced, as shown by P2b. There is.
  • Whether or not the polarization could be maintained in the period T2 can be judged by the amount of charge flowing in the period T3, and if the polarization can be maintained, the amount of charge flowing in the period T3 is large and the polarization could not be maintained. In that case, the amount of charge flowing in the period T3 decreases.
  • FIG. 67 shows the result of the retention measurement performed on the sample 800B.
  • the temperature conditions were 85 ° C, 150 ° C, and 200 ° C.
  • ⁇ Pr was a value that could be judged to be able to maintain the polarization.

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JP2020102623A (ja) * 2018-12-21 2020-07-02 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

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WO2023231480A1 (zh) * 2022-05-30 2023-12-07 华为技术有限公司 铁电单元、三维铁电结构和铁电存储器
CN117241589A (zh) * 2022-06-02 2023-12-15 华为技术有限公司 铁电存储器及其制备方法、电子设备
CN117794250A (zh) * 2022-09-19 2024-03-29 华为技术有限公司 铁电存储阵列及其制备方法、存储器、电子设备
WO2024134407A1 (ja) * 2022-12-22 2024-06-27 株式会社半導体エネルギー研究所 半導体装置
WO2024252246A1 (ja) * 2023-06-09 2024-12-12 株式会社半導体エネルギー研究所 半導体装置、半導体装置の作製方法

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