WO2021208757A1 - 图形片、半导体中间产物及孔刻蚀方法 - Google Patents

图形片、半导体中间产物及孔刻蚀方法 Download PDF

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WO2021208757A1
WO2021208757A1 PCT/CN2021/085171 CN2021085171W WO2021208757A1 WO 2021208757 A1 WO2021208757 A1 WO 2021208757A1 CN 2021085171 W CN2021085171 W CN 2021085171W WO 2021208757 A1 WO2021208757 A1 WO 2021208757A1
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layer
mask layer
mask
substrate
thickness
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PCT/CN2021/085171
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English (en)
French (fr)
Inventor
谢秋实
史小平
周清军
李东三
王春
张轶铭
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北京北方华创微电子装备有限公司
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Priority to JP2022563055A priority Critical patent/JP7372482B2/ja
Priority to EP21789169.6A priority patent/EP4138125A4/en
Priority to US17/919,520 priority patent/US12106970B2/en
Priority to KR1020227035582A priority patent/KR102586690B1/ko
Publication of WO2021208757A1 publication Critical patent/WO2021208757A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

Definitions

  • the invention relates to the technical field of semiconductor manufacturing, in particular to a pattern sheet, semiconductor intermediate product and a hole etching method.
  • CMOS complementary metal oxide semiconductor
  • the mask used in the etching process is generally a photoresist mask. Since the photoresist mask is usually formed on the side of the CMOS dielectric layer away from the substrate, the photoresist mask has to bear the responsibility of the CMOS dielectric layer and the substrate.
  • the two-layer etching mask of the substrate but due to the limitation of the exposure energy and accuracy of the photolithography technology, the thickness of the photoresist mask must be smaller than the size of the mask opening, resulting in the existence of the thickness of the photoresist mask The upper limit may not meet the thickness requirement of the photoresist mask for holes with a small diameter (for example, 2-5 ⁇ m) and a large depth.
  • the invention discloses a pattern sheet and a hole etching method, which can form a hole with a larger depth on a substrate, thereby meeting the use requirement.
  • the present invention adopts the following technical solutions:
  • An embodiment of the present invention provides a graphic sheet, which includes a substrate and a dielectric layer and a mask structure sequentially arranged on the substrate in a direction away from the substrate, the mask structure including a substrate from the dielectric layer A side far away from the substrate, and in a direction away from the substrate, a plurality of mask layers are stacked in sequence, wherein the mask layer of the uppermost layer is a photoresist layer; and, each layer of the mask layer
  • the thickness of the mask layer and the etching selection ratio between each layer below the mask layer meet the following requirements: the mask structure is used to form holes in the substrate and the dielectric layer correspondingly.
  • the lower mask layer is etched to form through holes penetrating the thickness, while the remaining thickness of the upper mask layer is greater than or equal to zero; While the dielectric layer is etched to form a through hole penetrating its thickness, the remaining thickness of all mask layers located above the dielectric layer is greater than zero; a hole with a set depth is formed in the substrate At the same time, the remaining thickness of all mask layers located above the dielectric layer is greater than or equal to zero.
  • the mask layer is composed of two layers, which are respectively a second mask layer and a first mask layer stacked in sequence along a direction away from the substrate, wherein the first mask layer is a light A resist layer; and, the respective thicknesses of the first mask layer and the second mask layer and the etching selection ratios between the respective layers below each meet the following conditions:
  • d1 ⁇ S5 d2, and d2>(d1-d4/S3) ⁇ S2/S1+d4/S4;
  • d1 is the thickness of the first mask layer
  • d2 is the thickness of the second mask layer
  • d4 is the thickness of the dielectric layer
  • S1 is the thickness of the substrate and the first mask layer Etching selection ratio
  • S2 is the etching selection ratio of the substrate and the second mask layer
  • S3 is the etching selection ratio of the dielectric layer and the first mask layer
  • S4 is the dielectric The etching selection ratio of the layer to the second mask layer
  • S5 is the etching selection ratio of the second mask layer to the first mask layer.
  • the second mask layer includes a material containing silicon.
  • the second mask layer is a silicon dioxide layer.
  • the mask layer has three layers, which are respectively a third mask layer, a second mask layer, and a first mask layer that are sequentially stacked in a direction away from the substrate, wherein the first mask layer A mask layer is a photoresist layer; and, the thickness of each of the first mask layer, the second mask layer, and the third mask layer and the thickness between the layers below each
  • the etching selection ratio satisfies the following conditions:
  • d1' is the thickness of the first mask layer
  • d2' is the thickness of the second mask layer
  • d3' is the thickness of the third mask layer
  • d4' is the thickness of the dielectric layer
  • S1' is the etching selection ratio of the substrate and the first mask layer
  • S2' is the etching selection ratio of the substrate and the third mask layer
  • S3' is the dielectric layer
  • S4' is the selection ratio between the dielectric layer and the third mask layer
  • S5' is the second mask layer and the first mask layer
  • S6' is the etching selection ratio of the third mask layer and the second mask layer.
  • the second mask layer is a silicon dioxide layer.
  • the third mask layer is an APF ⁇ -C layer.
  • the thickness of the first mask layer is 1 ⁇ m-2 ⁇ m; the thickness of the second mask layer is 400 nm-700 nm; and the thickness of the third mask layer is 6 ⁇ m-7 ⁇ m.
  • an embodiment of the present invention provides a semiconductor intermediate product.
  • the above-mentioned pattern provided by the embodiment of the present invention is formed by an etching process.
  • the semiconductor intermediate product includes a substrate and a medium disposed on the substrate. Layer; or, including a substrate and a dielectric layer sequentially disposed on the substrate along a direction away from the substrate and at least one mask layer remaining after etching, wherein the at least one mask layer
  • a through hole is formed in the dielectric layer to penetrate through the thickness; a hole with a set depth is formed in the substrate.
  • an embodiment of the present invention provides a hole etching method, which uses the above-mentioned pattern sheet provided by the embodiment of the present invention to form corresponding holes in a substrate and a dielectric layer disposed on the substrate.
  • the hole etching method includes:
  • the dielectric layer is etched to form a through hole penetrating its thickness, and a hole with a set depth is formed in the substrate.
  • the hole etching method is applied to the TSV etching process.
  • the invention discloses a technical scheme for a pattern sheet, a semiconductor intermediate product and a hole etching method, by using a mask structure of a composite film layer, that is, from the side of the dielectric layer away from the substrate and along the direction away from the substrate Laminate multiple mask layers in sequence, and make the thickness of each mask layer and the etching selection ratio between each layer below the mask layer meet:
  • the lower mask layer is etched to form a through hole penetrating its thickness, while the upper mask layer
  • the remaining thickness is greater than or equal to zero; while the dielectric layer is etched to form a through hole through its thickness, the remaining thickness of all mask layers located above the dielectric layer is greater than zero; a hole with a set depth is formed in the substrate
  • the remaining thickness of all mask layers located above the dielectric layer is greater than or equal to zero.
  • the use of the pattern sheet with the above-mentioned mask structure with the composite film layer can form holes with a greater depth on the substrate compared with the use of a photoresist mask alone in the prior art, so as to meet the requirements of use.
  • FIG. 1 is a schematic cross-sectional view of the graphic sheet disclosed in the first embodiment of the present invention
  • 2A is a schematic cross-sectional view of the pattern sheet disclosed in the first embodiment of the present invention after the second mask layer is etched to form through holes;
  • 2B is a schematic cross-sectional view of the pattern sheet disclosed in the first embodiment of the present invention after the dielectric layer is etched to form through holes;
  • 2C is a schematic cross-sectional view of the semiconductor intermediate product disclosed in the first embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional view of the graphic sheet disclosed in the second embodiment of the present invention.
  • 4A is a schematic cross-sectional view of the pattern sheet disclosed in the second embodiment of the present invention after the second mask layer is etched to form through holes;
  • 4B is a schematic cross-sectional view of the pattern sheet disclosed in the second embodiment of the present invention after the third mask layer is etched to form through holes;
  • 4C is a schematic cross-sectional view of the pattern sheet disclosed in the second embodiment of the present invention after the dielectric layer is etched to form through holes;
  • 4D is a schematic cross-sectional view of the semiconductor intermediate product disclosed in the second embodiment of the present invention.
  • the present invention discloses a graphic sheet, which includes a substrate and a dielectric layer and a mask structure sequentially arranged on the substrate along the direction of the substrate.
  • the mask structure is used to perform an etching process, and the dielectric layer and the liner can be used for etching.
  • a pattern composed of holes is formed on the bottom.
  • the etching process is, for example, a Through Silicon Via (TSV) process, where the substrate is a silicon substrate; the dielectric layer is, for example, a CMOS dielectric layer, and a CMOS circuit is disposed on the dielectric layer.
  • TSV Through Silicon Via
  • the above-mentioned mask structure includes a multi-layer mask layer stacked from the side of the dielectric layer away from the substrate and arranged in a direction away from the substrate.
  • the uppermost mask layer is a photoresist layer.
  • the resist layer has a mask pattern composed of holes.
  • the mask pattern can be formed by exposure, etc.
  • the holes in the mask pattern can be circular holes, and the radius can be determined according to actual needs.
  • the mask pattern can also be set to other holes of any shape.
  • a through hole that penetrates the thickness of the mask layer can be formed in the uppermost mask layer whose thickness meets the requirements.
  • the uppermost mask layer is used as a mask to etch at least one mask layer located below the mask layer. It should be noted that, before performing the above-mentioned etching process, no pattern corresponding to the above-mentioned mask pattern is formed on any other film layer except the photoresist layer.
  • the thickness of each mask layer and the etching selection ratio between each layer below the mask layer meets the following requirements: the mask structure is used to form holes in the substrate and the dielectric layer corresponding to the etching selection ratio. During the etching process, in every two adjacent mask layers, the lower mask layer is etched to form through holes through its thickness, while the remaining thickness of the upper mask layer is greater than or equal to zero; in the dielectric layer At the same time, the remaining thickness of all mask layers located above the dielectric layer is greater than zero while being etched to form through holes through the thickness of the The remaining thickness of the mask layer is greater than or equal to zero.
  • each mask layer can be used as a mask for the formation of through holes by etching the underlying film layer adjacent to it, and when the substrate is etched, the remaining thickness of all mask layers located above the dielectric layer is less than The sum is large enough to enable the hole formed in the substrate to reach a set depth.
  • the pattern sheet provided in this embodiment includes a substrate 50 and a dielectric layer 40 and a mask structure sequentially disposed on the substrate 50 along a direction away from the substrate 50.
  • the mask layer is composed of two layers, which are respectively the second mask layer 20 and the first mask layer 10 stacked in a direction away from the substrate 50, wherein the first mask layer 10 is a light A resist layer, the photoresist layer has a mask pattern composed of holes 11.
  • the first mask layer 10 serves as a mask for etching through holes in the second mask layer 20, and the through holes 21 formed in the second mask layer 20 are shown in FIG. 2A.
  • the remaining thickness of the first mask layer 10 is greater than zero, that is, when the through hole 21 is formed, there is still a certain thickness of the first mask layer.
  • One mask layer 10 is not consumed, but the thickness of the second mask layer 20 remains unchanged. In this case, when the dielectric layer 40 is etched, the remaining first mask layer 10 and the second mask layer 20 Both serve as masks for etching the through holes in the dielectric layer 40.
  • the second mask layer 20 when the second mask layer 20 is etched to form the through holes 21 passing through the thickness, the first mask layer 10 is completely consumed, while the second mask layer The thickness of 20 remains unchanged.
  • the dielectric layer 40 when the dielectric layer 40 is etched, only the second mask layer 20 is used as a mask for etching the through holes in the dielectric layer 40.
  • the remaining thickness of the second mask layer 20 is greater than zero, that is, when the through hole 41 is formed, there is still a certain thickness of the second mask layer 20 that has not been consumed.
  • the remaining second mask layer 20 serves as a mask for etching holes in the substrate 50.
  • the remaining thickness of the first mask layer 10 may also be greater than zero.
  • the remaining first mask layer 10 and the second mask layer 20 are used as masks for etching holes in the substrate 50.
  • the remaining thickness of the second mask layer 20 is greater than zero, so that the hole with a set depth is formed in the substrate 50 at the same time.
  • the remaining thickness of the second mask layer 20 can also be equal to zero when the hole 51 with a set depth is formed by etching in the substrate 50, that is, the second mask layer 20 is completely It is consumed.
  • the hole 51 with a set depth formed by etching in the substrate 50 may be a blind hole with a depth less than the thickness of the substrate 50, or may also be a through hole penetrating the thickness of the substrate 50.
  • the second mask layer 20 includes a material containing silicon, which has good semiconductor properties, is easy to obtain materials, and has a low cost, thereby reducing the processing difficulty and processing cost; moreover, In the process of using the second mask layer 20 as a mask to etch the substrate, more materials can be etched at the same time, thereby helping to form a larger hole in the substrate.
  • the second mask layer 20 includes a silicon-containing material
  • the dielectric layer 40 and the substrate 50 can be etched in sequence by a fluorine-containing plasma, and both of them are etched using the second mask.
  • the layer 20 serves as a mask, which helps to form through holes through the respective thicknesses on the substrate 50 and the dielectric layer 40.
  • the second mask layer 20 is a silicon dioxide layer, which can further reduce the material cost and processing difficulty of the second mask layer 20, and improve product competitiveness.
  • the respective thicknesses of the first mask layer 10 and the second mask layer 20 and the etching selection ratios between the respective layers below each satisfy the following conditions:
  • d1 ⁇ S5 d2, and d2>(d1-d4/S3) ⁇ S2/S1+d4/S4;
  • d1 is the thickness of the first mask layer 10
  • d2 is the thickness of the second mask layer 20
  • d4 is the thickness of the dielectric layer 40
  • S1 is the etching selection ratio of the substrate 50 and the first mask layer 10
  • S2 is the etching selection ratio between the substrate 50 and the second mask layer 20
  • S3 is the etching selection ratio between the dielectric layer 40 and the first mask layer 10
  • S4 is the etching selection ratio between the dielectric layer 40 and the second mask layer 20 Etching selection ratio
  • S5 is the etching selection ratio of the second mask layer 20 to the first mask layer 10.
  • the etching selection ratio is used to indicate the relative etching rate of one material to another under the same etching conditions.
  • the etching selection ratio S1 of the substrate 50 and the first mask layer 10 means that under the same etching conditions, the first mask layer 10 is used as a mask and the substrate 50 is used as the material to be etched. During etching, the ratio of the etched rate of the substrate 50 to the etched rate of the first mask layer 10.
  • the second mask layer 20 can be used as a mask for etching the dielectric layer 40 (or etching the dielectric layer 40 and the substrate 50).
  • the mask structure of this composite film layer is compared to using photoresist alone as the dielectric layer and the liner.
  • the bottom mask structure can form holes with greater depth on the substrate to meet the needs of use.
  • d1 ⁇ S5 means that while the first mask layer 10 with a thickness of d1 is completely consumed, the second mask layer 20 is consumed with a thickness of dx.
  • the hole 21 is easy to understand.
  • the pattern containing the through hole 21 formed on the second mask layer 20 is consistent with the mask pattern containing the hole 11 on the first mask layer 10.
  • the positions of the through hole 21 and the hole 11 Corresponding.
  • the second mask layer 20 is formed through its thickness.
  • the first mask layer 10 with a thickness of d1 still remains, so that in the process of etching the dielectric layer 40 (or the dielectric layer 40 and the substrate 50), the second mask can be used
  • the layer 20 and the remaining part of the first mask layer 10 together serve as a mask.
  • d4/S4 represents: the process of etching the dielectric layer 40 with the second mask layer 20 as a mask In the dielectric layer 40 with a thickness of d4, the thickness of the second mask layer 20 that needs to be consumed when the through hole 41 is formed through the thickness of the dielectric layer 40; further, d2-d4/S4 represents: The remaining thickness of the second mask layer 20 when the through hole 41 is formed in the layer 40 just to penetrate its thickness; In the process of etching the substrate 50, the depth of the hole formed in the substrate 50 when the second mask layer 20 with a thickness of d2-d4/S4 is just completely consumed.
  • d1-d4/S3 indicate that during the process of etching the dielectric layer 40 by using the first mask layer 10 as a mask, a through hole 41 is formed in the dielectric layer 40 with a thickness of d4. , The remaining thickness of the first mask layer 10.
  • (d1-d4/S3)/S1 represents: in the process of etching the substrate 50 with the first mask layer 10 as a mask, the first mask layer with a thickness of d1-d4/S3 10 is the depth of the hole formed in the substrate 50 when it is just completely consumed.
  • the respective thicknesses of the first mask layer 10 and the second mask layer 20 and the etching selection ratios between the layers below each satisfy: d1 ⁇ S5>d2, and d2 ⁇ (d1- d4/S3) ⁇ S2/S1+d4/S4, in the process of etching the dielectric layer 40 (or the dielectric layer 40 and the substrate 50), the second mask layer 20 and the first The remaining part of the mask layer 10 is used as a mask to etch the dielectric layer 40.
  • the depth of the hole finally formed in the substrate 50 with only the second mask layer 20 as a mask will be greater than that with only the first mask layer 10 as a mask
  • the depth of the hole finally formed in the substrate 50 can meet the usage requirements.
  • the pattern sheet provided in this embodiment includes a substrate 500 and a dielectric layer 400 and a mask structure sequentially disposed on the substrate 500 along the direction of the substrate 500.
  • the mask layer has three layers, which are the third mask layer 300, the second mask layer 200, and the first mask layer 100 that are sequentially stacked in a direction away from the substrate 500.
  • the first mask layer 100 is a photoresist layer, and the photoresist layer has a mask pattern composed of holes 110.
  • the first mask layer 100 serves as a mask for etching through holes in the second mask layer 200.
  • the through holes 210 formed in the second mask layer 200 are shown in FIG. 4A.
  • the remaining thickness of the first mask layer 100 is greater than zero, that is, when the through hole 210 is formed, there is still a certain thickness of the first mask layer.
  • One mask layer 100 is not consumed, but the thickness of the second mask layer 200 remains unchanged.
  • the third mask layer 300 is etched, the remaining first mask layer 100 and the second mask layer
  • the film layer 200 serves as a mask for etching through holes in the third mask layer 300.
  • the second mask layer 200 when the second mask layer 200 is etched to form a through hole 210 penetrating its thickness, the first mask layer 100 is completely consumed, while the second mask layer The thickness of 200 remains unchanged.
  • the third mask layer 300 when the third mask layer 300 is etched, only the second mask layer 200 serves as a mask for etching the through holes in the third mask layer 300.
  • the third mask layer 300 is etched to form a through hole 310 extending through its thickness
  • the first mask layer 100 is completely consumed; the third mask layer 300 is etched to form While there is a through hole 310 running through its thickness, the remaining thickness of the second mask layer 200 is greater than zero, that is, when the through hole 310 is formed, there is still a certain thickness of the second mask layer 200 that is not consumed.
  • the remaining second mask layer 200 and the third mask layer 300 are used as masks for etching the through holes in the dielectric layer 400 together.
  • the remaining thickness of the second mask layer 200 can also be equal to zero.
  • the dielectric layer 400 is etched, only the third mask layer 300 is used as a mask for etching the through holes in the dielectric layer 400.
  • the second mask layer 200 is completely consumed; the dielectric layer 400 is etched to form a through hole 410 through its thickness.
  • the remaining thickness of the third mask layer 300 is greater than zero, that is, when the through hole 410 is formed, there is still a certain thickness of the third mask layer 300 that has not been consumed.
  • the remaining third mask layer 300 serves as a mask for etching holes in the substrate 500.
  • the remaining thickness of the second mask layer 200 may also be greater than zero.
  • the remaining second mask layer 200 and the third mask layer 300 are used as a mask for etching holes in the substrate 500.
  • the remaining thickness of the third mask layer 300 is greater than zero. In this way, the substrate 500 is formed with a hole with a predetermined depth. , There is still a third mask layer 300 with a certain thickness to prevent the dielectric layer 400 from being etched, so as to ensure that the dielectric layer is not damaged and has complete performance.
  • the remaining thickness of the third mask layer 300 may also be equal to zero, that is, the third mask layer 300 is completely It is consumed.
  • the hole 510 with a predetermined depth formed by etching in the substrate 500 may be a blind hole with a depth less than the thickness of the substrate 500, or may also be a through hole penetrating the thickness of the substrate 500.
  • the second mask layer 200 includes a material containing silicon, which has good semiconductor properties, is easy to obtain materials, and has a low cost, thereby reducing the processing difficulty and processing cost; moreover, the second mask layer 200 is used as a mask. In the process of etching the substrate by the film, more materials can be etched at the same time, which helps to form a larger hole in the substrate.
  • the second mask layer 200 includes a silicon-containing material
  • the dielectric layer 400 and the substrate 500 can be etched sequentially by a plasma containing fluorine, and both of the etchings are performed using the second mask.
  • the layer 200 serves as a mask, which helps to form through holes through the respective thicknesses on both the substrate 500 and the dielectric layer 400.
  • the second mask layer 200 is a silicon dioxide layer, which can further reduce the material cost and processing difficulty of the second mask layer 200, and improve product competitiveness.
  • the third mask layer 300 is an APF ⁇ -C layer.
  • the dielectric layer 400 and the substrate 500 can be etched sequentially by oxygen-containing plasma, and the third mask layer 300 is used for the etching of both.
  • the thickness of the first mask layer 100 is 1 ⁇ m-2 ⁇ m; the thickness of the second mask layer 200 is 400 nm-700 nm; and the thickness of the third mask layer 300 is 6 ⁇ m-7 ⁇ m.
  • a hole with a greater depth can be formed on the substrate to meet the requirements of use.
  • the respective thicknesses of the first mask layer 100, the second mask layer 200, and the third mask layer 300 and the etching selection ratios between the respective layers below each meet the following conditions:
  • the third mask can be guaranteed
  • the film layer 300 (or a part of the first mask layer 100, the second mask layer 200 and the third mask layer 300, or a part of the second mask layer 200 and the third mask layer 300) can be used as an etching medium
  • the mask of the layer 400 and the substrate 500 can form a larger hole in the substrate to meet the requirements of Usage requirements.
  • the pattern containing the through hole 210 formed on the second mask layer 200 is the same as the mask pattern containing the hole 110 on the first mask layer 100.
  • the position of the through hole 210 corresponds to the position of the hole 110.
  • the second mask layer 200 is formed While penetrating the thickness of the through hole 210, the first mask layer 100 with a thickness of d1' still remains, so that in the process of etching the dielectric layer 400 and the substrate 500, the second mask layer 200 can be used to etch the dielectric layer 400 and the substrate 500.
  • the remaining part of the first mask layer 100 serves as a mask together.
  • the thickness of the through hole 310 is easy to understand, and finally the pattern containing the through hole 310 formed on the third mask layer 300 is consistent with the mask pattern containing the hole 110 on the first mask layer 100.
  • the through hole 310, The positions of the through holes 210 and the holes 110 correspond to each other.
  • the third mask layer 300 is just When the through hole 310 is formed through its thickness, the second mask layer 200 with a thickness of d2' still remains, so that in the process of etching the dielectric layer 400 and the substrate 500, the third mask layer 300 can be used to etch the dielectric layer 400 and the substrate 500.
  • the remaining part of the second mask layer 200 serves as a mask together.
  • d4'/S4' means that the third mask layer 300 is used as a mask.
  • the thickness of the third mask layer 300 that needs to be consumed when a through hole 410 is formed in the dielectric layer 400 with a thickness of d4'.
  • -d4'/S4' means: the remaining thickness of the third mask layer 300 when the through hole 410 is formed in the dielectric layer 400 with a thickness of d4', and the remaining thickness of the third mask layer 300;
  • (d3'-d4'/ S4')/S2' means: in the process of etching the substrate 500 with the third mask layer 300 as a mask, the third mask layer 300 with a thickness of d3'-d4'/S4' is just completely The depth of the hole formed in the substrate 500 when it is consumed.
  • d1'-d4'/S3' means: in the process of etching the dielectric layer 400 by using the first mask layer 100 as a mask, the dielectric layer 400 with a thickness of d4' just forms through its thickness The through hole 410 is the remaining thickness of the first mask layer 100.
  • (d1'-d4'/S3')/S1' means: in the process of etching the substrate 500 with the first mask layer 100 as a mask, the thickness is d1'-d4'/S3 The depth of the hole formed in the substrate 500 when the first mask layer 100 is completely consumed.
  • the semiconductor intermediate product may include a substrate and a dielectric layer disposed on the substrate, wherein a through hole is formed in the dielectric layer through its thickness; and a through hole with a set depth is formed in the substrate. hole.
  • the substrate is etched to form a hole with a predetermined depth, while the remaining thickness of the mask layer above the dielectric layer is equal to zero, that is, completely It is consumed.
  • the hole with a set depth formed by etching in the substrate may be a blind hole with a depth less than the thickness of the substrate, or may also be a through hole penetrating the thickness of the substrate.
  • the semiconductor intermediate product may also include a substrate, a dielectric layer sequentially disposed on the substrate in a direction away from the substrate, and at least one mask layer remaining after etching, wherein at least one mask layer and the dielectric layer A through hole is formed in the middle corresponding to the thickness thereof; a hole having a set depth corresponding to the through hole is formed in the substrate.
  • the substrate is etched to form a hole with a predetermined depth, and the remaining thickness of the mask layer above the dielectric layer is greater than zero.
  • This embodiment provides a hole etching method, which utilizes the pattern sheet provided in the above embodiments of the present invention to etch a corresponding hole in a substrate and a dielectric layer disposed on the substrate.
  • the hole etching method includes:
  • At least one mask layer remaining above the dielectric layer is used to etch the dielectric layer to form a through hole penetrating its thickness, and a hole with a set depth is formed in the substrate.
  • the hole etching method provided in this embodiment is applied to a TSV (Through Silicon Via) etching process to further reduce processing difficulty and improve processing efficiency.
  • the technical solutions of the above-mentioned pattern sheet, semiconductor intermediate product, and hole etching method utilize the mask structure of the composite film layer, that is, from the side of the dielectric layer away from the substrate, And in the direction away from the substrate, the multiple mask layers are stacked in sequence, and the thickness of each mask layer and the etching selection ratio between each layer below the mask layer meet:
  • the etching process of forming holes in the substrate and the dielectric layer by using the mask structure in every two adjacent mask layers, the lower mask layer is etched to form a through hole through its thickness.
  • the remaining thickness of the upper mask layer is greater than or equal to zero, and the dielectric layer is etched to form a through hole through its thickness.
  • the sum of the remaining thickness of all mask layers above the dielectric layer is greater than or equal to The set depth of the hole formed in the substrate. Therefore, compared with the use of a photoresist mask alone in the prior art, a graphic sheet using the above-mentioned mask structure with a composite film layer can form a hole with a larger depth on the substrate, thereby meeting the requirements of use.

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Abstract

一种图形片、半导体中间产物及孔刻蚀方法，该图形片包括衬底（500）、介质层（400）和掩膜结构，该掩膜结构包括多层掩膜层，其中，最上层的掩膜层为光刻胶层；每层掩膜层的厚度和与位于该掩膜层以下的各层膜层之间的刻蚀选择比满足：每相邻的两层掩膜层中，在下层掩膜层中被刻蚀形成有贯穿其厚度的通孔的同时，上层掩膜层的剩余厚度大于或等于零；在介质层（400）中被刻蚀形成有贯穿其厚度的通孔的同时，位于介质层（400）以上的所有掩膜层的剩余厚度大于零；在衬底（500）中形成具有设定深度的孔的同时，位于介质层（400）以上的所有掩膜层的剩余厚度大于或等于零。采用上述技术方案可以在衬底（500）上形成深度较大的孔，以满足使用需求。

Description

图形片、半导体中间产物及孔刻蚀方法 技术领域
本发明涉及半导体制造技术领域，尤其涉及一种图形片、半导体中间产物及孔刻蚀方法。
背景技术
受用户需求的影响，IC制造业已经从二维(2D)平面集成制造技术转向三维(3D)立体集成制造技术。在3D立体集成制造技术中，可以采用刻蚀技术在衬底与衬底之间形成使二者垂直导通的通孔，该衬底可为硅衬底(晶圆)。具体地，衬底的表面一般设置有互补金属氧化物半导体(Complementary Metal-Oxide-Semiconductor，以下简称CMOS)介质层，在形成上述通孔的过程中，首先需要刻蚀CMOS介质层，形成贯穿该CMOS介质层的通孔，然后刻蚀衬底，形成贯穿衬底的通孔。
目前，刻蚀工艺采用的掩膜一般为光刻胶掩膜，由于该光刻胶掩膜通常形成在CMOS介质层背离衬底的一侧，这使得光刻胶掩膜要承担CMOS介质层和衬底两层刻蚀的掩膜作用，但是由于受光刻技术的曝光能量和精度等因素的限制，光刻胶掩膜的厚度需小于掩膜开口尺寸，导致光刻胶掩膜的厚度存在上限，可能无法满足直径较小(例如2～5μm)，且深度较大的孔对光刻胶掩膜的厚度要求。
发明内容
本发明公开一种图形片及孔刻蚀方法，可以在衬底上形成深度更大的孔，从而满足使用需求。
为了解决上述问题，本发明采用下述技术方案：
本发明实施例提供一种图形片，包括衬底和沿远离所述衬底的方向依次设置在所述衬底上的介质层和掩膜结构，所述掩膜结构包括自所述介质层的远离所述衬底的一侧，且沿远离所述衬底的方向依次层叠设置的多层掩膜层，其中，最上层的所述掩膜层为光刻胶层；并且，每层所述掩膜层的厚度和与位于该掩膜层以下的各层膜层之间的刻蚀选择比满足：在进行利用所述掩膜结构在所述衬底和所述介质层中对应形成孔的刻蚀工艺过程中，每相邻的两层所述掩膜层中，在下层掩膜层中被刻蚀形成有贯穿其厚度的通孔的同时，上层掩膜层的剩余厚度大于或等于零；在所述介质层中被刻蚀形成有贯穿其厚度的通孔的同时，位于所述介质层以上的所有掩膜层的剩余厚度大于零；在所述衬底中形成具有设定深度的孔的同时，位于所述介质层以上的所有掩膜层的剩余厚度大于或等于零。
可选的，所述掩膜层为两层，分别为沿远离所述衬底的方向依次层叠设置的第二掩膜层和第一掩膜层，其中，所述第一掩膜层为光刻胶层；并且，所述第一掩膜层和所述第二掩膜层各自的厚度和位于各自以下的各层膜层之间的刻蚀选择比满足以下条件：
d1×S5＞d2，且d2≥(d1－d4/S3)×S2/S1+d4/S4；或者，
d1×S5＝d2，且d2＞(d1－d4/S3)×S2/S1+d4/S4；
其中，d1为所述第一掩膜层的厚度；d2为所述第二掩膜层的厚度；d4为所述介质层的厚度；S1为所述衬底与所述第一掩膜层的刻蚀选择比；S2为所述衬底与所述第二掩膜层的刻蚀选择比；S3为所述介质层与所述第一掩膜层的刻蚀选择比；S4为所述介质层与所述第二掩膜层的刻蚀选择比；S5为所述第二掩膜层与所述第一掩膜层的刻蚀选择比。
可选的，所述第二掩膜层包括含硅元素的材料。
可选的，所述第二掩膜层为二氧化硅层。
可选的，所述掩膜层为三层，分别为沿远离所述衬底的方向依次层叠设 置的第三掩膜层、第二掩膜层和第一掩膜层，其中，所述第一掩膜层为光刻胶层；并且，所述第一掩膜层、所述第二掩膜层和所述第三掩膜层各自的厚度和位于各自以下的各层膜层之间的刻蚀选择比满足以下条件：
d1＇×S5＇＞d2＇，且d2＇×S6＇≥d3＇，且d3＇≥(d1＇－d4＇/S3＇)×S2＇/S1＇+d4＇/S4＇；或者，
d1＇×S5＇≥d2＇，且d2＇×S6＇＞d3＇，且d3＇≥(d1＇－d4＇/S3＇)×S2＇/S1＇+d4＇/S4＇；或者，
d1＇×S≥d2＇，且d2＇×S6＇≥d3＇，且d3＇＞(d1＇－d4＇/S3＇)×S2＇/S1＇+d4＇/S4＇；
其中，d1＇为所述第一掩膜层的厚度；d2＇为所述第二掩膜层的厚度；d3＇为所述第三掩膜层的厚度；d4＇为所述介质层的厚度；S1＇为所述衬底与所述第一掩膜层的刻蚀选择比，S2＇为所述衬底与所述第三掩膜层的刻蚀选择比；S3＇为所述介质层与所述第一掩膜层的刻蚀选择比；S4＇为所述介质层与所述第三掩膜层的选择比；S5＇为所述第二掩膜层与所述第一掩膜层的刻蚀选择比；S6＇为所述第三掩膜层与所述第二掩膜层的刻蚀选择比。
可选的，所述第二掩膜层为二氧化硅层。
可选的，所述第三掩膜层为APFα-C层。
可选的，所述第一掩膜层的厚度为1μm-2μm；所述第二掩膜层的厚度为400nm-700nm；所述第三掩膜层的厚度为6μm-7μm。
作为另一个技术方案，本发明实施例提供一种半导体中间产物，由本发明实施例提供的上述图形片采用刻蚀工艺形成，所述半导体中间产物包括衬底和设置在所述衬底上的介质层；或者，包括衬底和沿远离所述衬底的方向依次设置在所述衬底上的介质层和刻蚀后剩余的至少一层掩膜层，其中，所述至少一层掩膜层和介质层中对应形成有贯穿其厚度的通孔；所述衬底中形成具有设定深度的孔。
作为另一个技术方案，本发明实施例提供一种孔刻蚀方法，利用本发明实施例提供的上述图形片，在衬底和设置在所述衬底上的介质层中刻蚀形成对应的孔；所述孔刻蚀方法包括：
利用任意相邻的两层所述掩膜层中的上层掩膜层作为掩膜，在下层掩膜层中刻蚀形成贯穿其厚度的通孔；
利用位于所述介质层以上剩余的至少一层掩膜层，在所述介质层中刻蚀形成有贯穿其厚度的通孔，并在所述衬底中形成设定深度的孔。
可选的，所述孔刻蚀方法应用于硅通孔刻蚀工艺。
本发明采用的技术方案能够达到以下有益效果：
本发明公开一种图形片、半导体中间产物及孔刻蚀方法的技术方案，通过利用复合膜层的掩膜结构，即，自介质层的远离衬底的一侧，且沿远离衬底的方向依次层叠设置的多层掩膜层，并使每层掩膜层的厚度和与位于该掩膜层以下的各层膜层之间的刻蚀选择比满足：在进行利用掩膜结构在衬底和介质层中对应形成孔的刻蚀工艺过程中，每相邻的两层掩膜层中，在下层掩膜层中被刻蚀形成有贯穿其厚度的通孔的同时，上层掩膜层的剩余厚度大于或等于零；在介质层中被刻蚀形成有贯穿其厚度的通孔的同时，位于介质层以上的所有掩膜层的剩余厚度大于零；在衬底中形成具有设定深度的孔的同时，位于介质层以上的所有掩膜层的剩余厚度大于或等于零。由此，采用具有复合膜层的上述掩膜结构的图形片，与现有技术中单独使用光刻胶掩膜相比，可以在衬底上形成深度更大的孔，从而满足使用需求。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本发明的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1为本发明第一实施例公开的图形片的剖面示意图；
图2A为本发明第一实施例公开的图形片在第二掩膜层被刻蚀形成通孔之后的剖面示意图；
图2B为本发明第一实施例公开的图形片在介质层被刻蚀形成通孔之后的剖面示意图；
图2C为本发明第一实施例公开的半导体中间产物的剖面示意图；
图3为本发明第二实施例公开的图形片的剖面示意图；
图4A为本发明第二实施例公开的图形片在第二掩膜层被刻蚀形成通孔之后的剖面示意图；
图4B为本发明第二实施例公开的图形片在第三掩膜层被刻蚀形成通孔之后的剖面示意图；
图4C为本发明第二实施例公开的图形片在介质层被刻蚀形成通孔之后的剖面示意图；
图4D为本发明第二实施例公开的半导体中间产物的剖面示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合本发明具体实施例及相应的附图对本发明技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
以下结合附图，详细说明本发明各个实施例公开的技术方案。
本发明公开一种图形片，包括衬底和沿该衬底的方向依次设置在衬底上的介质层和掩膜结构，其中，利用该掩膜结构进行刻蚀工艺，可以在介质层和衬底上形成由孔组成的图形。该刻蚀工艺例如为硅通孔(Through Silicon  Via，TSV)工艺，其中，衬底为硅衬底；介质层例如为CMOS介质层，该介质层上设置有CMOS电路。
上述掩膜结构包括自介质层的远离衬底的一侧，且沿远离该衬底的方向依次层叠设置的多层掩膜层，其中，最上层的掩膜层为光刻胶层，该光刻胶层具有由孔组成的掩膜图形，该掩膜图形可以通过曝光等方式形成，掩膜图形中的孔可以为圆形孔，其半径可以根据实际需求确定，当然，掩膜图形中的孔还可以设置为其他任意形状的孔。此外，通过改变曝光能量等方式，可以在厚度满足要求的最上层的掩膜层中形成贯穿该掩膜层的厚度的通孔。在利用掩膜结构进行上述刻蚀工艺的过程中，利用最上层的掩膜层作为掩膜，对位于该掩膜层下方的至少一层掩膜层进行刻蚀。需要说明的是，在进行上述刻蚀工艺之前，除光刻胶层之外的其他膜层均未形成与上述掩膜图形对应的图形。
并且，每层掩膜层的厚度和与位于该掩膜层以下的各层膜层之间的刻蚀选择比满足：在进行利用上述掩膜结构在衬底和介质层中对应形成孔的刻蚀工艺过程中，每相邻的两层掩膜层中，在下层掩膜层中被刻蚀形成有贯穿其厚度的通孔的同时，上层掩膜层的剩余厚度大于或等于零；在介质层中被刻蚀形成有贯穿其厚度的通孔的同时，位于介质层以上的所有掩膜层的剩余厚度大于零；在衬底中形成具有设定深度的孔的同时，位于介质层以上的所有掩膜层的剩余厚度大于或等于零。也就是说，每层掩膜层可以用作与之相邻的下层膜层刻蚀形成通孔的掩膜，并且在刻蚀衬底时，位于介质层以上的所有掩膜层的剩余厚度之和足够大，以能够使形成在衬底中的孔达到设定深度。
由上可知，采用具有复合膜层的上述掩膜结构的图形片，与现有技术中单独使用光刻胶掩膜相比，可以在衬底上形成深度更大的孔，从而满足使用需求。
下面对上述图形片的具体实施方式进行详细描述。
第一实施例
请参阅图1，本实施例提供的图形片包括衬底50和沿远离衬底50的方向依次设置在该衬底50上的介质层40和掩膜结构。该掩膜结构中，掩膜层为两层，分别为沿远离衬底50的方向依次层叠设置的第二掩膜层20和第一掩膜层10，其中，第一掩膜层10为光刻胶层，该光刻胶层具有由孔11组成的掩膜图形。并且，第一掩膜层10作为在第二掩膜层20中刻蚀通孔的掩膜，该第二掩膜层20中形成的通孔21如图2A所示，在本实施例中，在第二掩膜层20中被刻蚀形成有贯穿其厚度的通孔21的同时，第一掩膜层10的剩余厚度大于零，即，在通孔21形成时，仍然有一定厚度的第一掩膜层10未被消耗，而第二掩膜层20的厚度不变，在这种情况下，在刻蚀介质层40时，剩余的第一掩膜层10和第二掩膜层20均作为在介质层40中刻蚀通孔的掩膜。
当然，在本发明的其他实施例中，在第二掩膜层20中被刻蚀形成有贯穿其厚度的通孔21的同时，第一掩膜层10完全被消耗，而第二掩膜层20的厚度仍然不变，在这种情况下，在刻蚀介质层40时，只有第二掩膜层20作为在介质层40中刻蚀通孔的掩膜。
如图2B所示，在介质层40中被刻蚀形成有贯穿其厚度的通孔41之前，第一掩膜层10完全被消耗；在介质层40中被刻蚀形成有贯穿其厚度的通孔41的同时，第二掩膜层20的剩余厚度大于零，即，在通孔41形成时，仍然有一定厚度的第二掩膜层20未被消耗，在这种情况下，在刻蚀衬底50时，剩余的第二掩膜层20作为在衬底50中刻蚀孔的掩膜。
当然，在本发明的其他实施例中，在介质层40中被刻蚀形成有贯穿其厚度的通孔41的同时，第一掩膜层10的剩余厚度也可以大于零，在这种情况下，在刻蚀衬底50时，剩余的第一掩膜层10和第二掩膜层20均作为在衬底50中刻蚀孔的掩膜。
如图2C所示，在衬底50中刻蚀形成设定深度的孔51的同时，第二掩膜层20的剩余厚度大于零，这样，在衬底50中形成设定深度的孔的同时，仍存留有一定厚度的第二掩膜层20，以防止出现介质层40被刻蚀的情况，从而保证介质层不会受损，具备完整性能。当然，在本发明的其他实施例中，在衬底50中刻蚀形成设定深度的孔51的同时，第二掩膜层20的剩余厚度也可以等于零，即，第二掩膜层20完全被消耗。另外，在衬底50中刻蚀形成设定深度的孔51可以是深度小于衬底50的厚度的盲孔，或者也可以是贯穿衬底50厚度的通孔。
基于上述实施例，可选地，第二掩膜层20包括含硅元素的材料，硅元素具有良好的半导体性能，且取材简便，成本较低，从而可以降低加工难度和加工成本；而且，在利用第二掩膜层20作为掩膜对衬底进行刻蚀的过程中，能够同时刻蚀二者的材料较多，从而有助于在衬底中形成深度较大的孔。另外，在第二掩膜层20包括含硅元素的材料的情况下，可以通过含氟的等离子体依次对介质层40和衬底50进行刻蚀，二者的刻蚀均利用第二掩膜层20作为掩膜，有助于在衬底50和介质层40上均形成贯穿各自厚度的通孔。
进一步可选地，第二掩膜层20为二氧化硅层，这可以进一步降低第二掩膜层20的材料成本和加工难度，提升产品竞争力。
并且，第一掩膜层10和第二掩膜层20各自的厚度和位于各自以下的各层膜层之间的刻蚀选择比满足以下条件：
d1×S5＞d2，且d2≥(d1－d4/S3)×S2/S1+d4/S4；或者，
d1×S5＝d2，且d2＞(d1－d4/S3)×S2/S1+d4/S4；
其中，d1为第一掩膜层10的厚度；d2为第二掩膜层20的厚度；d4为介质层40的厚度；S1为衬底50与第一掩膜层10的刻蚀选择比；S2为衬底50与第二掩膜层20的刻蚀选择比；S3为介质层40与第一掩膜层10的刻蚀选择比；S4为介质层40与第二掩膜层20的刻蚀选择比；S5为第二掩膜层 20与第一掩膜层10的刻蚀选择比。
需要说明的是，刻蚀选择比用于表示在同一刻蚀条件下，一种材料与另一种材料相对刻蚀速率的快慢。例如，衬底50与第一掩膜层10的刻蚀选择比S1指的是在同一刻蚀条件下，将第一掩膜层10作为掩膜，且将衬底50作为被刻蚀材料进行刻蚀时，衬底50的被刻蚀速率与第一掩膜层10的被刻蚀速率的比值。
通过使第一掩膜层10和第二掩膜层20各自的厚度和位于各自以下的各层膜层之间的刻蚀选择比满足上述条件，可以保证第一掩膜层10的一部分和第二掩膜层20能够作为刻蚀介质层40(或者刻蚀介质层40和衬底50)的掩膜，这种复合膜层的掩膜结构相比于单独使用光刻胶作为介质层和衬底的掩膜结构，可以在衬底上形成深度更大的孔，以满足使用需求。
详细地说，d1×S5所代表的含义为在厚度为d1的第一掩膜层10被完全消耗的同时，第二掩膜层20被消耗的厚度为dx，在dx＝d2的情况下，可以认为在厚度为d1的第一掩膜层10被完全消耗的同时，厚度为d2的第二掩膜层也刚好被完全消耗，基于此，通过使d1×S5＝d2，可以在借助第一掩膜层10作为掩膜刻蚀第二掩膜层20的过程中，当厚度为d1的第一掩膜层10被完全消耗时，使第二掩膜层20上正好形成贯穿其厚度的通孔21，容易理解，最终在使第二掩膜层20上形成的包含通孔21的图形与第一掩膜层10上的包含孔11的掩膜图形一致，通孔21和孔11的位置相对应。显然，在d1×S5＞d2的情况下，则可以认为，在借助第一掩膜层10作为掩膜刻蚀第二掩膜层20的过程中，第二掩膜层20上形成贯穿其厚度的通孔21的同时，厚度为d1的第一掩膜层10仍有存留，从而在对介质层40(或者介质层40和衬底50)进行刻蚀的过程中，可以以第二掩膜层20和第一掩膜层10的剩余部分一并作为掩膜。
d2＝(d1－d4/S3)×S2/S1+d4/S4，即可以推导为d2-d4/S4＝(d1－d4/S3) ×S2/S1，也可以进一步推导为(d2-d4/S4)/S2＝(d1－d4/S3)/S1。
在上述等式(d2-d4/S4)/S2＝(d1－d4/S3)/S1中，d4/S4表示：在借助第二掩膜层20作为掩膜对介质层40进行刻蚀的过程中，在厚度为d4的介质层40中刚好形成贯穿其厚度的通孔41时，需要消耗的第二掩膜层20的厚度；进一步的，d2-d4/S4表示：在厚度为d4的介质层40中刚好形成贯穿其厚度的通孔41时，第二掩膜层20的剩余厚度；再进一步的，(d2-d4/S4)/S2表示：在借助第二掩膜层20作为掩膜对衬底50进行刻蚀的过程中，在厚度为d2-d4/S4的第二掩膜层20刚好完全被消耗时，在衬底50中形成的孔的深度。
相似地，d1－d4/S3表示：在借助第一掩膜层10作为掩膜对介质层40进行刻蚀的过程中，在厚度为d4的介质层40中刚好形成贯穿其厚度的通孔41时，第一掩膜层10的剩余厚度。进一步的，(d1－d4/S3)/S1表示：在借助第一掩膜层10作为掩膜对衬底50进行刻蚀的过程中，在厚度为d1－d4/S3的第一掩膜层10刚好完全被消耗时，在衬底50中形成的孔的深度。
显然，在(d2-d4/S4)/S2＝(d1－d4/S3)/S1时，则可以认为：仅借助第二掩膜层20作为掩膜对介质层40和衬底50进行刻蚀，与仅借助第一掩膜层10作为掩膜对介质层40和衬底50进行刻蚀相比，二者在衬底50中形成的孔的深度相等。而在(d2-d4/S4)/S2＞(d1－d4/S3)/S1，即，d2＞(d1－d4/S3)×S2/S1+d4/S4的情况下，仅借助第二掩膜层20作为掩膜最终在衬底50中形成的孔的深度会大于仅借助第一掩膜层10作为掩膜最终在衬底50中形成的孔的深度。
由此，当第一掩膜层10和第二掩膜层20各自的厚度和位于各自以下的各层膜层之间的刻蚀选择比满足：d1×S5＞d2，且d2≥(d1－d4/S3)×S2/S1+d4/S4的条件时，在对介质层40(或者介质层40和衬底50)进行刻蚀的过程中，可以实现以第二掩膜层20和第一掩膜层10的剩余部分一并作为掩 膜刻蚀介质层40，这与仅借助第一掩膜层10作为掩膜对介质层40和衬底50进行刻蚀相比，必然能够在衬底50中形成的深度更大的孔，以满足使用需求。而当第一掩膜层10和第二掩膜层20各自的厚度和位于各自以下的各层膜层之间的刻蚀选择比满足：d1×S5＝d2，且d2＞(d1－d4/S3)×S2/S1+d4/S4时，如前述，仅借助第二掩膜层20作为掩膜最终在衬底50中形成的孔的深度会大于仅借助第一掩膜层10作为掩膜最终在衬底50中形成的孔的深度，从而可以满足使用需求。
第二实施例
请参阅图3，本实施例提供的图形片包括衬底500和沿该衬底500的方向依次设置在衬底500上的介质层400和掩膜结构。该掩膜结构中，掩膜层为三层，分别为沿远离衬底500的方向依次层叠设置的第三掩膜层300、第二掩膜层200和第一掩膜层100。其中，第一掩膜层100为光刻胶层，该光刻胶层具有由孔110组成的掩膜图形。并且，第一掩膜层100作为在第二掩膜层200中刻蚀通孔的掩膜，该第二掩膜层200中形成的通孔210如图4A所示，在本实施例中，在第二掩膜层200中被刻蚀形成有贯穿其厚度的通孔210的同时，第一掩膜层100的剩余厚度大于零，即，在通孔210形成时，仍然有一定厚度的第一掩膜层100未被消耗，而第二掩膜层200的厚度不变，在这种情况下，在刻蚀第三掩膜层300时，剩余的第一掩膜层100和第二掩膜层200均作为在第三掩膜层300中刻蚀通孔的掩膜。
当然，在本发明的其他实施例中，在第二掩膜层200中被刻蚀形成有贯穿其厚度的通孔210的同时，第一掩膜层100完全被消耗，而第二掩膜层200的厚度仍然不变，在这种情况下，在刻蚀第三掩膜层300时，只有第二掩膜层200作为在第三掩膜层300中刻蚀通孔的掩膜。
如图4B所示，在第三掩膜层300中被刻蚀形成有贯穿其厚度的通孔310之前，第一掩膜层100完全被消耗；在第三掩膜层300中被刻蚀形成有贯穿 其厚度的通孔310的同时，第二掩膜层200的剩余厚度大于零，即，在通孔310形成时，仍然有一定厚度的第二掩膜层200未被消耗，在这种情况下，在刻蚀介质层400时，剩余的第二掩膜层200和第三掩膜层300一并作为在介质层400中刻蚀通孔的掩膜。
当然，在本发明的其他实施例中，在第三掩膜层300中被刻蚀形成有贯穿其厚度的通孔310的同时，第二掩膜层200的剩余厚度也可以等于零，在这种情况下，在刻蚀介质层400时，只有第三掩膜层300作为在介质层400中刻蚀通孔的掩膜。
如图4C所示，在介质层400中被刻蚀形成有贯穿其厚度的通孔410之前，第二掩膜层200完全被消耗；在介质层400中被刻蚀形成有贯穿其厚度的通孔410的同时，第三掩膜层300的剩余厚度大于零，即，在通孔410形成时，仍然有一定厚度的第三掩膜层300未被消耗，在这种情况下，在刻蚀衬底500时，剩余的第三掩膜层300作为在衬底500中刻蚀孔的掩膜。
当然，在本发明的其他实施例中，在介质层400中被刻蚀形成有贯穿其厚度的通孔410的同时，第二掩膜层200的剩余厚度也可以大于零，在这种情况下，在刻蚀衬底500时，剩余的第二掩膜层200和第三掩膜层300一并作为在衬底500中刻蚀孔的掩膜。
如图4D所示，在衬底500中刻蚀形成设定深度的孔510的同时，第三掩膜层300的剩余厚度大于零，这样，在衬底500中形成设定深度的孔的同时，仍存留有一定厚度的第三掩膜层300，以防止出现介质层400被刻蚀的情况，从而保证介质层不会受损，具备完整性能。当然，在本发明的其他实施例中，在衬底500中刻蚀形成设定深度的孔510的同时，第三掩膜层300的剩余厚度也可以等于零，即，第三掩膜层300完全被消耗。另外，在衬底500中刻蚀形成设定深度的孔510可以是深度小于衬底500的厚度的盲孔，或者也可以是贯穿衬底500厚度的通孔。
第二掩膜层200包括含硅元素的材料，硅元素具有良好的半导体性能，且取材简便，成本较低，从而可以降低加工难度和加工成本；而且，在利用第二掩膜层200作为掩膜对衬底进行刻蚀的过程中，能够同时刻蚀二者的材料较多，从而有助于在衬底中形成深度较大的孔。另外，在第二掩膜层200包括含硅元素的材料的情况下，可以通过含氟的等离子体依次对介质层400和衬底500进行刻蚀，二者的刻蚀均利用第二掩膜层200作为掩膜，有助于在衬底500和介质层400上均形成贯穿各自厚度的通孔。
进一步可选地，第二掩膜层200为二氧化硅层，这可以进一步降低第二掩膜层200的材料成本和加工难度，提升产品竞争力。
可选地，第三掩膜层300为APFα-C层。在利用第三掩膜层300为APFα-C层的情况下，可以通过含氧的等离子体依次对介质层400和衬底500进行刻蚀，二者的刻蚀均利用第三掩膜层300作为掩膜，有助于在衬底500和介质层400上均形成贯穿各自厚度的通孔。
可选的，第一掩膜层100的厚度为1μm-2μm；第二掩膜层200的厚度为400nm-700nm；第三掩膜层300的厚度为6μm-7μm。在该厚度范围内，可以在衬底上形成深度更大的孔，从而满足使用需求。
并且，第一掩膜层100、第二掩膜层200和第三掩膜层300各自的厚度和位于各自以下的各层膜层之间的刻蚀选择比满足以下条件：
d1＇×S5＇＞d2＇，且d2＇×S6＇≥d3＇，且d3＇≥(d1＇－d4＇/S3＇)×S2＇/S1＇+d4＇/S4＇；或者，
d1＇×S5＇≥d2＇，且d2＇×S6＇＞d3＇，且d3＇≥(d1＇－d4＇/S3＇)×S2＇/S1＇+d4＇/S4＇；或者，
d1＇×S≥d2＇，且d2＇×S6＇≥d3＇，且d3＇＞(d1＇－d4＇/S3＇)×S2＇/S1＇+d4＇/S4＇；
其中，d1＇为第一掩膜层100的厚度；d2＇为第二掩膜层200的厚度； d3＇为第三掩膜层300的厚度；d4＇为介质层400的厚度；S1＇为衬底500与第一掩膜层100的刻蚀选择比，S2＇为衬底500与第三掩膜层300的刻蚀选择比；S3＇为介质层400与第一掩膜层100的刻蚀选择比；S4＇为介质层400与第三掩膜层300的选择比；S5＇为第二掩膜层200与第一掩膜层100的刻蚀选择比；S6＇为第三掩膜层300与第二掩膜层200的刻蚀选择比。
通过使第一掩膜层100、第二掩膜层200和第三掩膜层300各自的厚度和位于各自以下的各层膜层之间的刻蚀选择比满足上述条件，可以保证第三掩膜层300(或者第一掩膜层100的一部分、第二掩膜层200和第三掩膜层300，或者第二掩膜层200的一部分和第三掩膜层300)能够作为刻蚀介质层400和衬底500的掩膜，这种复合膜层的图形片相比于单独使用光刻胶作为介质层和衬底的图形片，可以在衬底上形成深度更大的孔，以满足使用需求。
详细地说，d1＇×S5＇所代表的含义为在厚度为d1＇的第一掩膜层100被完全消耗的同时，第二掩膜层200的厚度为dx，在dx＝d2＇的情况下，可以认为在厚度为d1＇的第一掩膜层100被完全消耗的同时，厚度为d2＇的第二掩膜层200也刚好被完全消耗，基于此，通过使d1＇×S5＇＝d2＇，可以在借助第一掩膜层100作为掩膜刻蚀第二掩膜层200的过程中，当厚度为d1＇的第一掩膜层100被完全消耗时，使第二掩膜层200上正好形成贯穿其厚度的通孔210，容易理解，最终在使第二掩膜层200上形成的包含通孔210的图形与第一掩膜层100上的包含孔110的掩膜图形一致，通孔210和孔110的位置相对应。显然，在d1＇×S5＇＞d2＇的情况下，则可以认为，在借助第一掩膜层100作为掩膜刻蚀第二掩膜层200的过程中，第二掩膜层200上形成贯穿其厚度的通孔210的同时，厚度为d1＇的第一掩膜层100仍有存留，从而在对介质层400和衬底500进行刻蚀的过程中，可以以第二掩膜层200和第一掩膜层100中存留的部分一并作为掩膜。
d2＇×S6＇所代表的含义为在厚度为d2＇的第二掩膜层200被完全消耗 的同时，第三掩膜层300的厚度为dy，在dy＝d3＇的情况下，可以在厚度为d3＇的第三掩膜层300被完全消耗的同时，厚度为d2＇的第二掩膜层200也刚好被完全消耗，基于此，通过使d2＇×S6＇＝d3＇，可以在借助第二掩膜层200作为掩膜刻蚀第三掩膜层300的过程中，当厚度为d2＇的第二掩膜层200被完全消耗时，使第三掩膜层300上正好形成贯穿其厚度的通孔310，容易理解，最终在使第三掩膜层300上形成的包含通孔310的图形与第一掩膜层100上的包含孔110的掩膜图形一致，通孔310、通孔210和孔110的位置相对应。显然，在d2＇×S6＇＞d3＇的情况下，则可以认为，在借助第二掩膜层200作为掩膜刻蚀第三掩膜层300的过程中，第三掩膜层300上正好形成贯穿其厚度的通孔310时，厚度为d2＇的第二掩膜层200仍有存留，从而在对介质层400和衬底500进行刻蚀的过程中，可以以第三掩膜层300和第二掩膜层200中存留的部分一并作为掩膜。
d3＇＝(d1＇－d4＇/S3＇)×S2＇/S1＇+d4＇/S4＇，即可以推导为d3＇-d4＇/S4＇＝(d1＇－d4＇/S3＇)×S2＇/S1＇，也可以进一步推导为(d3＇-d4＇/S4＇)/S2＇＝(d1＇－d4＇/S3＇)/S1＇。
在上述等式(d3＇-d4＇/S4＇)/S2＇＝(d1＇－d4＇/S3＇)/S1＇中，d4＇/S4＇表示：在借助第三掩膜层300作为掩膜对介质层400进行刻蚀的过程中，在厚度为d4＇的介质层400中刚好形成贯穿其厚度的通孔410时，需要消耗的第三掩膜层300的厚度；进一步的，d3＇-d4＇/S4＇表示：在厚度为d4＇的介质层400中刚好形成贯穿其厚度的通孔410时，第三掩膜层300的剩余厚度；再进一步的，(d3＇-d4＇/S4＇)/S2＇表示：在借助第三掩膜层300作为掩膜对衬底500进行刻蚀的过程中，在厚度为d3＇-d4＇/S4＇的第三掩膜层300刚好完全被消耗时，在衬底500中形成的孔的深度。
相似地，d1＇－d4＇/S3＇表示：在借助第一掩膜层100作为掩膜对介质层400进行刻蚀的过程中，在厚度为d4＇的介质层400中刚好形成贯穿其厚 度的通孔410时，第一掩膜层100的剩余厚度。进一步的，(d1＇－d4＇/S3＇)/S1＇表示：在借助第一掩膜层100作为掩膜对衬底500进行刻蚀的过程中，在厚度为d1＇－d4＇/S3＇的第一掩膜层100刚好完全被消耗时，在衬底500中形成的孔的深度。
显然，在(d3＇-d4＇/S4＇)/S2＇＝(d1＇－d4＇/S3＇)/S1＇时，则可以认为：仅借助第三掩膜层300作为掩膜对介质层400和衬底500进行刻蚀，与仅借助第一掩膜层100作为掩膜对介质层400和衬底500进行刻蚀相比，二者在衬底500中形成的孔的深度相等。而在(d3＇-d4＇/S4＇)/S2＇＞(d1＇－d4＇/S3＇)/S1＇，即，d3＇＞(d1＇－d4＇/S3＇)×S2＇/S1＇+d4＇/S4＇的情况下，仅借助第三掩膜层300作为掩膜最终在衬底500中形成的孔的深度会大于仅借助第一掩膜层100作为掩膜最终在衬底500中形成的孔的深度。
由上可知，与上述第一实施例相类似的，当第一掩膜层100、第二掩膜层200和第三掩膜层300各自的厚度和位于各自以下的各层膜层之间的刻蚀选择比满足上述条件时，与仅借助第一掩膜层100作为掩膜对介质层400和衬底500进行刻蚀相比，必然能够在衬底500中形成的深度更大的孔，以满足使用需求。
第三实施例
本实施例提供一种半导体中间产物，由本发明上述各个实施例提供的图形片采用刻蚀工艺形成。具体地，该半导体中间产物可以包括衬底和设置在衬底上的介质层，其中，介质层中形成有贯穿其厚度的通孔；衬底中形成与该通孔对应的具有设定深度的孔。在利用本发明实施例提供的上述图形片进行刻蚀工艺的过程中，在衬底中刻蚀形成设定深度的孔的同时，位于介质层以上的掩膜层的剩余厚度等于零，即，完全被消耗。另外，在衬底中刻蚀形成设定深度的孔可以是深度小于衬底的厚度的盲孔，或者也可以是贯穿衬底厚度的通孔。
或者，半导体中间产物还可以包括衬底和沿远离衬底的方向依次设置在衬底上的介质层和刻蚀后剩余的至少一层掩膜层，其中，至少一层掩膜层和介质层中对应形成有贯穿其厚度的通孔；衬底中形成具有与该通孔对应的设定深度的孔。在利用本发明实施例提供的上述图形片进行刻蚀工艺的过程中，在衬底中刻蚀形成设定深度的孔的同时，位于介质层以上的掩膜层的剩余厚度大于零，这样，在衬底中形成设定深度的孔的同时，仍存留有一定厚度的掩膜层，这样可以防止出现介质层被刻蚀，从而保证介质层不会受损，具备完整性能。例如，图2D和图4D中分别示出的两种半导体中间产物，二者在衬底中形成设定深度的孔的同时，仍存留有一定厚度的掩膜层。
第四实施例
本实施例提供一种孔刻蚀方法，其利用本发明上述各个实施例提供的图形片，在衬底和设置在该衬底上的介质层中刻蚀形成对应的孔。该孔刻蚀方法包括：
利用任意相邻的两层掩膜层中的上层掩膜层作为掩膜，在下层掩膜层中刻蚀形成贯穿其厚度的通孔；
利用位于介质层以上剩余的至少一层掩膜层，在介质层中刻蚀形成有贯穿其厚度的通孔，并在衬底中形成设定深度的孔。
可选地，本实施例提供的孔刻蚀方法应用于TSV(Through SiliconVias，硅通孔)刻蚀工艺，以进一步降低加工难度，提升加工效率。
综上所述，本发明实施例提供的上述图形片、半导体中间产物及孔刻蚀方法的技术方案，通过利用复合膜层的掩膜结构，即，自介质层的远离衬底的一侧，且沿远离衬底的方向依次层叠设置的多层掩膜层，并使每层掩膜层的厚度和与位于该掩膜层以下的各层膜层之间的刻蚀选择比满足：在进行利用掩膜结构在衬底和介质层中对应形成孔的刻蚀工艺过程中，每相邻的两层掩膜层中，在下层掩膜层中被刻蚀形成有贯穿其厚度的通孔的同时，上层掩 膜层的剩余厚度大于或等于零，以及在介质层中被刻蚀形成有贯穿其厚度的通孔的同时，位于介质层以上的所有掩膜层的剩余厚度之和大于或等于在衬底中形成孔的设定深度。由此，采用具有复合膜层的上述掩膜结构的图形片与现有技术中单独使用光刻胶掩膜相比，可以在衬底上形成深度更大的孔，从而满足使用需求。
本发明上文实施例中重点描述的是各个实施例之间的不同，各个实施例之间不同的优化特征只要不矛盾，均可以组合形成更优的实施例，考虑到行文简洁，在此则不再赘述。
以上所述仅为本发明的实施例而已，并不用于限制本发明。对于本领域技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本发明的权利要求范围之内。

Claims (11)

  1. 一种图形片，包括衬底和沿远离所述衬底的方向依次设置在所述衬底上的介质层和掩膜结构，其特征在于，所述掩膜结构包括自所述介质层的远离所述衬底的一侧，且沿远离所述衬底的方向依次层叠设置的多层掩膜层，其中，最上层的所述掩膜层为光刻胶层；并且，每层所述掩膜层的厚度和与位于该掩膜层以下的各层膜层之间的刻蚀选择比满足：在进行利用所述掩膜结构在所述衬底和所述介质层中对应形成孔的刻蚀工艺过程中，每相邻的两层所述掩膜层中，在下层掩膜层中被刻蚀形成有贯穿其厚度的通孔的同时，上层掩膜层的剩余厚度大于或等于零；在所述介质层中被刻蚀形成有贯穿其厚度的通孔的同时，位于所述介质层以上的所有掩膜层的剩余厚度大于零；在所述衬底中形成具有设定深度的孔的同时，位于所述介质层以上的所有掩膜层的剩余厚度大于或等于零。
  2. 根据权利要求1所述的图形片，其特征在于，所述掩膜层的数量为两层，分别为沿远离所述衬底的方向依次层叠设置的第二掩膜层和第一掩膜层，其中，所述第一掩膜层为光刻胶层；并且，所述第一掩膜层和所述第二掩膜层各自的厚度和位于各自以下的各层膜层之间的刻蚀选择比满足以下条件：
    d1×S5＞d2，且d2≥(d1－d4/S3)×S2/S1+d4/S4；或者，
    d1×S5＝d2，且d2＞(d1－d4/S3)×S2/S1+d4/S4；
    其中，d1为所述第一掩膜层的厚度；d2为所述第二掩膜层的厚度；d4为所述介质层的厚度；S1为所述衬底与所述第一掩膜层的刻蚀选择比；S2为所述衬底与所述第二掩膜层的刻蚀选择比；S3为所述介质层与所述第一掩膜层的刻蚀选择比；S4为所述介质层与所述第二掩膜层的刻蚀选择比；S5为所述第二掩膜层与所述第一掩膜层的刻蚀选择比。
  3. 根据权利要求2所述的图形片，其特征在于，所述第二掩膜层包括含硅元素的材料。
  4. 根据权利要求3所述的图形片，其特征在于，所述第二掩膜层为二氧化硅层。
  5. 根据权利要求1所述的图形片，其特征在于，所述掩膜层的数量为三层，分别为沿远离所述衬底的方向依次层叠设置的第三掩膜层、第二掩膜层和第一掩膜层，其中，所述第一掩膜层为光刻胶层；并且，所述第一掩膜层、所述第二掩膜层和所述第三掩膜层各自的厚度和位于各自以下的各层膜层之间的刻蚀选择比满足以下条件：
    d1＇×S5＇＞d2＇，且d2＇×S6＇≥d3＇，且d3＇≥(d1＇－d4＇/S3＇)×S2＇/S1＇+d4＇/S4＇；或者，
    d1＇×S5＇≥d2＇，且d2＇×S6＇＞d3＇，且d3＇≥(d1＇－d4＇/S3＇)×S2＇/S1＇+d4＇/S4＇；或者，
    d1＇×S≥d2＇，且d2＇×S6＇≥d3＇，且d3＇＞(d1＇－d4＇/S3＇)×S2＇/S1＇+d4＇/S4＇；
    其中，d1＇为所述第一掩膜层的厚度；d2＇为所述第二掩膜层的厚度；d3＇为所述第三掩膜层的厚度；d4＇为所述介质层的厚度；S1＇为所述衬底与所述第一掩膜层的刻蚀选择比，S2＇为所述衬底与所述第三掩膜层的刻蚀选择比；S3＇为所述介质层与所述第一掩膜层的刻蚀选择比；S4＇为所述介质层与所述第三掩膜层的选择比；S5＇为所述第二掩膜层与所述第一掩膜层的刻蚀选择比；S6＇为所述第三掩膜层与所述第二掩膜层的刻蚀选择比。
  6. 根据权利要求5所述的图形片，其特征在于，所述第二掩膜层为二氧化硅层。
  7. 根据权利要求5或6所述的图形片，其特征在于，所述第三掩膜层为APFα-C层。
  8. 根据权利要求5-7任意一项所述的图形片，其特征在于，所述第一掩膜层的厚度为1μm-2μm；所述第二掩膜层的厚度为400nm-700nm；所述第三掩膜层的厚度为6μm-7μm。
  9. 一种半导体中间产物，由权利要求1-8中任意一项所述的图形片采用刻蚀工艺形成，其特征在于，所述半导体中间产物包括衬底和设置在所述衬底上的介质层；或者，包括衬底和沿远离所述衬底的方向依次设置在所述衬底上的介质层和刻蚀后剩余的至少一层掩膜层，其中，所述至少一层掩膜层和介质层中对应形成有贯穿其厚度的通孔；所述衬底中形成具有设定深度的孔。
  10. 一种孔刻蚀方法，其特征在于，利用权利要求1-8任意一项所述的图形片，在衬底和设置在所述衬底上的介质层中刻蚀形成对应的孔；所述孔刻蚀方法包括：
    利用任意相邻的两层所述掩膜层中的上层掩膜层作为掩膜，在下层掩膜层中刻蚀形成贯穿其厚度的通孔；
    利用位于所述介质层以上剩余的至少一层掩膜层，在所述介质层中刻蚀形成有贯穿其厚度的通孔，并在所述衬底中形成设定深度的孔。
  11. 根据权利要求10所述的孔刻蚀方法，其特征在于，所述孔刻蚀方法应用于硅通孔刻蚀工艺。
PCT/CN2021/085171 2020-04-17 2021-04-02 图形片、半导体中间产物及孔刻蚀方法 WO2021208757A1 (zh)

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