WO2021196853A1 - 存储块以及存储器 - Google Patents

存储块以及存储器 Download PDF

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Publication number
WO2021196853A1
WO2021196853A1 PCT/CN2021/073981 CN2021073981W WO2021196853A1 WO 2021196853 A1 WO2021196853 A1 WO 2021196853A1 CN 2021073981 W CN2021073981 W CN 2021073981W WO 2021196853 A1 WO2021196853 A1 WO 2021196853A1
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Prior art keywords
unit
signal line
data signal
memory
order address
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PCT/CN2021/073981
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English (en)
French (fr)
Inventor
尚为兵
李红文
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长鑫存储技术有限公司
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Priority to EP21773437.5A priority Critical patent/EP3933839B1/en
Priority to US17/447,569 priority patent/US11869578B2/en
Publication of WO2021196853A1 publication Critical patent/WO2021196853A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
    • G11C11/4023—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh using field effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/10—Arrangements for interconnecting storage elements electrically, e.g. by wiring for interconnecting capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the embodiments of the present application relate to the field of semiconductor technology, and in particular, to a storage block and a memory.
  • Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory device commonly used in computers, which consists of many repeated memory cells. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage.
  • DRAM Dynamic Random Access Memory
  • DRAM is divided into double rate synchronous (Double Data Rate, DDR) dynamic random access memory, GDDR (Graphics Double Data Rate) dynamic random access memory, and low power double rate synchronous (Low Power Double Data Rate, LPDDR) dynamic random access memory.
  • DDR Double Data Rate
  • GDDR Graphics Double Data Rate
  • LPDDR Low Power Double Data Rate
  • the embodiments of the present application provide a storage block and a memory to solve the problem of high power consumption of the memory.
  • the embodiment of the present application provides a memory block, which includes at least one memory module, and each memory module includes: a read-write control circuit, a column decoding circuit, and a plurality of memories arranged along a first direction.
  • Array the plurality of memory arrays are divided into at least one first unit and at least one second unit; a first decoding selection signal line, the first decoding selection signal line is electrically connected to the column decoding circuit and the The storage array in the first unit; a second decoding selection signal line, the second decoding selection signal line is electrically connected to the column decoding circuit and the storage array in the second unit; first A data signal line, the first data signal line is used to electrically connect the read-write control circuit and the storage array in the first unit; a second data signal line, the second data signal line is used for electricity Connecting the read-write control circuit and the storage array in the second unit.
  • the number of the first unit and the second unit is one; and the first unit and the second unit are both high-order address units, or the first unit and the second unit They are all low-order address units.
  • first data signal line is electrically connected to all the storage arrays in the first unit; the second data signal line is electrically connected to all the storage arrays in the second unit.
  • the number of the storage arrays in the first unit is the same as the number of the storage arrays in the second unit.
  • both the first data signal line and the second data signal line are electrically connected to the read-write control circuit.
  • a switch module configured to switch one of the first data signal line or the second data signal line to be electrically connected to the read-write control circuit.
  • the switch module includes: a control unit and a switch unit; the control unit generates a control signal based on the received row decoding signal; the switch unit is used to communicate with the read-write control circuit based on the control signal To the first data signal line, or to communicate with the read/write control circuit and the second data signal line.
  • the switch unit includes a first switch and a second switch, the first switch is connected between the first data signal line and the read/write control circuit, and the second switch is connected to the second switch. Between the data signal line and the read-write control circuit.
  • the storage block includes two storage modules, one of the storage modules is a high-order address module, and the other storage module is a low-order address module.
  • a positioning control module for controlling the row decoding signal generated by the row decoding circuit, so that the row decoding signal simultaneously locates the first unit of the selected high-order address module and the low-order address module.
  • the second unit of the address module, or the second unit of the high-order address module and the first unit of the low-order address module are positioned and selected at the same time.
  • the first unit includes a first high-order address unit and a first low-order address unit;
  • the second unit includes a second high-order address unit and a second low-order address unit.
  • the first data signal line electrically connects the read/write control circuit and the storage array in the first high-order address unit;
  • the second data signal line electrically connects the read/write control circuit and the The storage array in the second low-order address unit;
  • the storage block further includes: a third data signal line, the third data signal line is electrically connected to the read-write control circuit and the second high-order address unit The storage array; a fourth data signal line, the fourth data signal line is electrically connected to the read-write control circuit and the storage array in the first low-order address unit.
  • first data signal line and the third data signal line are the same bus; the second data signal line and the fourth data signal line are the same bus.
  • first low-order address unit is adjacent to the second high-order address unit; or, the first low-order address unit and the second high-order address unit are separated by the second low-order address unit.
  • the storage block includes two storage modules.
  • the column decoding circuit includes: a first column decoding circuit and a second column decoding circuit, and the first decoding selection signal line is electrically connected to the first column decoding circuit and the first unit In the memory array, the second decoding selection signal line is electrically connected to the second column decoding circuit and the memory array in the second cell.
  • first column decoding circuit and the second column decoding circuit are respectively located on opposite sides of the plurality of memory arrays.
  • the first decoding selection signal line and the second decoding selection signal line are electrically connected to the same column decoding circuit.
  • a row decoding circuit for sending a row decoding signal to locate and select one of the first unit or the second unit.
  • an embodiment of the present application also provides a memory, including the storage block of the foregoing embodiment.
  • the embodiment of the present application provides a memory block with superior structural performance, which includes a column decoding circuit for positioning the memory array of the selected first cell and a first decoding selection signal line, which is used for positioning the memory array of the selected second cell.
  • the column decoding circuit and the second decoding selection signal line are used to implement the first data signal line for data transmission between the memory array in the first unit and the read-write control circuit, and are used to implement the memory array and the second unit in the second unit.
  • the second data signal line for data transmission between the read and write control circuits. In a single read and write operation, only the first decoding selection signal line or the second decoding selection signal line needs to be enabled. Since the first decoding selection signal line is only electrically connected to a part of the memory array, it has electricity.
  • the contact point, the second decoding selection signal line is only electrically connected to a part of the memory array, so the electrical contact points during a single read and write operation are reduced, so the parasitic resistance and parasitic capacitance of the memory block are also reduced, which is beneficial Reduce the power consumption of the storage block.
  • the first data signal line and the second data signal line used for data transmission are electrically connected to a part of the memory array, so that the electrical contact points during a single read and write operation are reduced, and the parasitic resistance of the memory block and The parasitic capacitance is also reduced, which helps to reduce the power consumption of the memory block.
  • the storage block further includes a switch module, which is used to switch one of the first data signal line or the second data signal line to be electrically connected to the read-write control circuit.
  • a switch module which is used to switch one of the first data signal line or the second data signal line to be electrically connected to the read-write control circuit.
  • the first unit includes a first high-order address unit and a first low-order address unit
  • the second unit includes a second high-order address unit and a second low-order address unit.
  • Figure 1 is a schematic diagram of the structure of a DARM
  • FIG. 2 is a schematic diagram of a structure of a storage block provided by an embodiment of this application.
  • FIG. 3 is a schematic diagram of another structure of a storage block provided by an embodiment of this application.
  • FIG. 4 is a schematic diagram of another structure of a storage block provided by an embodiment of this application.
  • FIG. 5 is a schematic structural diagram of a storage block provided by another embodiment of this application.
  • FIG. 6 is a schematic diagram of a partial structure of a storage block provided by another embodiment of the application.
  • FIG. 7 is a schematic structural diagram of a storage block provided by another embodiment of this application.
  • FIG. 8 is a schematic diagram of another structure of a storage block in another embodiment of the application.
  • FIG. 1 is a schematic diagram of the structure of a DARM.
  • a DRAM is composed of a plurality of memory blocks (banks, also called memory banks) 10, each memory block 10 includes a number of memory arrays, and each memory array includes a memory array (array) 11 and a sense amplifier array 12.
  • the memory block 10 is divided into a high-order group according to the output pin (DQ) and The lower group.
  • DQ output pin
  • each bank can also be divided into two half banks.
  • One half bank is used as the first module M1, the first module M1 provides low-level output pins, and the other half bank is used as the second module M2.
  • M2 provides high-order output pins.
  • the high and low bits refer to the high and low of the data bit, the low output pin transmits the data in the low bit, and the high output pin transmits the data in the high bit.
  • the decoding selection signal line CSL receives the column selection signal output by the column decoding circuit (YDEC) 13, and the data signal line YIO is used to transmit data between the selected memory array 11 and the read/write control circuit 14. Regardless of whether it is a low-level half bank or a high-level half bank, in order to successfully complete the read and write operations, the decoding selection signal line CSL and each memory array 11 in the half bank have electrical contact points. The contact point will generate parasitic capacitance accordingly; the decoding selection signal line CSL and the data signal line YIO line are very long, resulting in large parasitic resistance, which will cause the problem of large power consumption for each read and write, resulting in high DRAM power consumption .
  • parasitic resistance and parasitic capacitance are also one of the main reasons for the large power consumption of DARM.
  • the decoding selection signal line CSL during each reading operation or writing operation, there are parasitic capacitances and parasitic resistances at the electrical contact points between each group of decoding selection signal lines CSL and each memory array 11.
  • the data signal line YIO during each read operation or write operation, there are parasitic capacitances and parasitic resistances at the electrical contact points between each group of data signal lines YIO and each memory array 11. Due to the large number of electrical contacts, the corresponding parasitic resistance and parasitic resistance are large, resulting in high power consumption of the DRAM.
  • the embodiments of the present application provide a memory block with superior structural performance.
  • the parasitic resistance and parasitic capacitance of the memory block are reduced, thereby reducing the power consumption of the memory block.
  • FIG. 2 is a schematic diagram of a structure of a storage block provided by an embodiment of this application.
  • the memory block includes at least one memory module 100, and each memory module 100 includes: a read-write control circuit 101, a column decoding circuit 123, and a number of memory arrays 104 arranged along a first direction, so The several memory arrays 104 are divided into at least one first unit 110 and at least one second unit 120; the first decoding selection signal line CSL1, the first decoding selection signal line CSL1 is electrically connected to the column decoding circuit 123 and the first unit
  • the memory array 104 in the 110 enables the column decoding circuit 123 to position the memory array 104 in the first cell 110; the second decoding selection signal line CSL2, and the second decoding selection signal line CSL2 are electrically connected to the column decoding circuit 123
  • the memory array 104 in the second unit 120 enables the column decoding circuit 123 to position the memory array 104 in the second unit 120; the first data signal line YIO1 and the first data signal line YIO1 are used for electrical connection for reading and writing
  • the storage block includes two storage modules 100, where one storage module 100 is a high-order address module, and the other storage module 100 is a low-order address module.
  • one storage module 100 is a high-order address module
  • the other storage module 100 is a low-order address module.
  • the number of bits of the storage block is 16 bits
  • the number of bits of the low address module is the low 8 bits
  • the number of bits of the high address module is the high 8 bits.
  • the number of the first unit 110 and the second unit 120 is one, and the first unit 110 and the second unit 120 are both high-order address units, or the first unit 110 and the second unit 120 They are all low-order address units.
  • the first unit 110 and the second unit 120 in one of the storage modules 100 are high-order address units.
  • the storage module 100 is referred to as the high-order storage module; the first unit 110 and the second unit in the other storage module 100 are The two units 120 are both low-order address units.
  • the storage module 100 is referred to as a low-order storage module.
  • the upper storage module 100 is taken as an upper storage module
  • the lower storage module 100 is taken as an example of a lower storage module. It can be understood that in other embodiments, the number of the first unit and the number of the second unit can be designed according to actual storage requirements.
  • Each memory array 104 includes a memory array and a sense amplifier (SA).
  • the memory array includes a plurality of storage elements for storing data; the sensitive amplifier array is used for amplifying the output signal of the memory array.
  • the first unit 110 includes a first number of storage arrays 104, and the second unit 120 includes a second number of storage arrays 104. The first number and the second number may be the same or different.
  • the number of storage arrays 104 in the first unit 110 is the same as the number of storage arrays 104 in the second unit 120.
  • the column decoding circuit 123 includes: a first column decoding circuit 102 and a second column decoding circuit 103, and the first decoding selection signal line CSL1 is electrically connected to the first column decoding circuit 102 and the first unit 110
  • the memory array 104 in the first cell 110 is positioned and selected by the first column decoding circuit 102
  • the second decoding selection signal line CSL2 is electrically connected to the second column decoding circuit 103 and the second cell 120
  • the memory array 104 in the second cell 120 is positioned and selected by the second column decoding circuit 103.
  • the first column decoding circuit 102 outputs a first positioning signal, and locates and selects the memory array 104 located in the first cell 110 through the first decoding selection signal line CSL1, so as to perform a read operation or a write operation on the selected memory array 104 .
  • the second column decoding circuit 103 outputs a second positioning signal, and the memory array 104 located in the second cell 120 is selected through the second decoding selection signal line CSL2, so as to perform a read operation or a write operation on the selected memory array 104. More specifically, the first decoding selection signal line CSL1 is electrically connected to all the memory arrays 104 in the first cell 110, and the second decoding selection signal line CSL2 is electrically connected to all the memory arrays 104 in the second cell 120.
  • the first column decoding circuit 102 and The second column decoding circuits 103 are respectively located on opposite sides of the plurality of memory arrays 104.
  • FIG. 3 is a schematic diagram of another structure of a memory block provided by an embodiment of the application.
  • the column decoding circuit 123 The number can also be one.
  • the column decoding circuit 123 can locate and select the memory array 104 of the first cell 110, and can also locate the memory array 104 of the second cell 120, the first decoding selection signal line CSL1, and the second decoding circuit.
  • the code selection signal line CSL2 is electrically connected to the same column decoding circuit 123.
  • different memory modules 100 may have separate column decoding circuits 123, and different memory modules 100 may also share column decoding circuits 123.
  • the first decoding selection signal line CSL1 crosses the memory array 104 in the first cell 110
  • the second decoding selection signal line CSL2 crosses the memory array 104 in the second cell 120.
  • the first data signal line YIO1 traverses the plurality of storage arrays 104, that is, traverses the first unit 110 and the second unit 120, and is only electrically connected to the storage array 104 in the first unit 110;
  • the second data signal line YIO2 traverses The storage array 104 in the second unit 120. More specifically, the first data signal line YIO1 is electrically connected to all the storage arrays 104 in the first unit 110, and the second data signal line YIO2 is electrically connected to all the storage arrays 104 in the second unit 120.
  • each memory module 100 has two sets of first data signal lines YIO1 and two sets of second data signal lines YIO2 as an example.
  • the number of groups of the first data signal line and the second data signal line can be reasonably designed according to actual requirements.
  • both the first data signal line YIO1 and the second data signal line YIO2 are electrically connected to the read-write control circuit 101.
  • FIG. 4 is a schematic diagram of another structure of a memory block provided by an embodiment of this application.
  • the memory module 100 may also include a row decoding circuit 124 for issuing row decoding signals to locate and select the first One of the unit 110 or the second unit 120.
  • Different memory blocks 100 may have mutually independent row decoding circuits 124, and different memory blocks 100 may also share the same row decoding circuit 124.
  • the row decoding circuit 124 positions and selects the first cell 110, only the first decoding selection signal line CSL1 and the first column decoding circuit 102 are enabled; when the row decoding circuit 124 positions and selects the second cell 120, only The second decoding selection signal line CSL2 and the second column decoding circuit 103 are enabled.
  • the first decoding selection signal line CSL1 is in electrical contact with the memory array 104
  • the number of points is reduced, and the number of electrical contact points between the first data signal line YIO1 and the memory array 104 is also reduced.
  • the second data signal line YIO2 straddles the memory array 104 in the second unit 120, the length of the memory array 104 spanned by the second data signal line YIO2 is reduced. Therefore, the line length of the second data signal line YIO2 is shorter, which is beneficial to The resistance of the second data signal line YIO2 and the power consumption are further reduced, thereby further reducing the power consumption of the memory block.
  • the row decoding signal (row decode) output by the row decoding circuit 124 points to the first unit 110, only the first column decoding circuit 102 and the first decoding selection signal line CSL1 are enabled, and the row decoding signal line CSL1 is selected.
  • the power consumption of the memory block in this write operation is low. It can be understood that less load refers to less number of memory arrays 104 that are electrically connected, that is, less electrical contact points and less parasitic capacitance.
  • the memory block may further include: a positioning control module 125, which is used to control the row decoding signal generated by the row decoding circuit 124, so that the row decoding signal simultaneously locates the first selected high-order address module
  • a positioning control module 125 is electrically connected to the row decoding circuit 124, and is adapted to send a positioning control signal to the row decoding circuit 124, and the row decoding circuit 124 generates a row decoding signal based on the positioning control signal.
  • the total length of the first data signal line YIO1 and the second data signal line YIO2 that play the role of data transmission are equal, so that each read operation or write operation can be made.
  • the current consumption of the input operation is evenly distributed to avoid excessive current peaks, thereby further improving the performance of the memory block.
  • the first unit 110 in the upper address module and the second unit 120 in the lower address module are simultaneously selected.
  • the first data signal line YIO1 plays a role in data transmission;
  • the second data signal line YIO2 plays a role in data transmission;
  • the length of the data transmission bus is the first data signal line YIO1 and The total length of the second data signal line YIO2.
  • the second unit 120 in the upper address module and the first unit 110 in the lower address module are simultaneously selected.
  • the second data signal line YIO2 plays a role in data transmission;
  • the first data signal line YIO1 plays a role in data transmission;
  • the length of the data transmission bus is the first data signal line YIO1 and The total length of the second data signal line YIO2.
  • the length of the data transmission bus remains the same for each read operation, so the data transmission bus consumes the same amount of heat and the same number of loads, which helps to ensure the average current consumption during work and further improve storage The performance of the block.
  • the working mode of the memory block may also be: simultaneously selecting the first unit of the high-order address module and the first unit of the low-order address module, and simultaneously selecting the second unit of the high-order address module and the low-order address The second unit of the module.
  • the storage block provided in this embodiment consumes less power each time, and the corresponding storage block has the advantage of low power consumption.
  • Another embodiment of the present application further provides a storage block.
  • the storage block is substantially the same as the storage block provided in the previous embodiment. The difference is that it further includes a switch module for switching the first data signal line or the second data signal line. One of the two data signal lines is electrically connected to the read-write control circuit.
  • the storage block provided by this embodiment will be described below with reference to the accompanying drawings. It should be noted that, for the same or corresponding parts as the previous embodiment, please refer to the detailed description of the previous embodiment, which will not be described in detail below.
  • FIG. 5 is a schematic diagram of the structure of a storage block provided by another embodiment of this application
  • FIG. 6 is a schematic diagram of a partial structure of a storage block provided by another embodiment of this application.
  • the memory block includes: memory module 100, each memory module 100 includes: a read-write control circuit 101, a first column decoding circuit 102, a second column decoding circuit 103, and Several memory arrays 104 arranged along the first direction; first decoding selection signal line CSL1; second decoding selection signal line CSL2; first data signal line YIO1; second data signal line YIO2; switch module 126, switch The switch module 126 is used to switch one of the first data signal line YIO1 or the second data signal line YIO2 to be electrically connected to the read-write control circuit 101.
  • the column decoding circuit includes the first column decoding circuit 102 and the second column decoding circuit 103 as an example. In other embodiments, there may be only one column decoding circuit, and both the first decoding selection signal line and the second decoding selection signal line are electrically connected to the column decoding circuit.
  • the switch module 126 includes a switch unit 136 and a control unit 146; the control unit 146 is used to generate a control signal based on the received row decoding signal; the switch unit 136 is used to connect the read/write control circuit 101 and the first based on the control signal A data signal line YIO1 or, alternatively, connects the read-write control circuit 101 and the second data signal line YIO2.
  • the switch unit 136 includes a first switch S1 and a second switch S2.
  • the first switch S1 is connected between the first data signal line YIO1 and the reading and writing control circuit 101
  • the second switch S2 is connected to the second data signal line YIO2 and reading and writing. Between the control circuit 101.
  • the control unit 146 controls the first switch S1 to be closed or open, and controls the second switch S2 to be closed or open based on the row decoding signal.
  • the first switch S1 or the second switch S2 may be constituted by at least one MOS transistor.
  • the first switch S1 is closed, and the first data signal line YIO1 is electrically connected to the read/write control circuit 101; the first switch S1 is opened, and the first data signal line YIO1 is disconnected from the read/write control circuit 101; the second switch S2 is closed, and the second switch S2 is closed.
  • the second data signal line YIO2 is electrically connected to the read/write control circuit 101; the second switch S2 is turned off, and the second data signal line YIO2 is disconnected from the read/write control circuit 101.
  • the number of switch units 136 is the same as the number of groups of the first data signal line YIO1 and the number of groups of the second data signal line YIO2. In this embodiment, there are two switch units 136. In other embodiments, the number of switch units can be set reasonably according to the number of groups of the first data signal line and the second data signal line.
  • the storage module 100 at the top in FIG. 5 is a high-order address module, and the storage module 100 at the bottom is a low-order address module.
  • the storage block module may also include: a positioning control module 125.
  • the positioning control module 125 is connected to the switch module 126.
  • the switch module 126 is based on the information sent by the positioning control module 125.
  • the positioning control signal is switched on and off, so that the first data signal line YIO1 or the second data signal line YIO2 is electrically connected to the read-write control circuit 101.
  • the row decoding signal locates the first unit 110 of the high-order address module and the second unit 120 of the low-order address module
  • the first switch S1 in the high-order address module is closed and the second switch S2 is opened
  • the low-order address module The first switch S1 in the upper address module is opened and the second switch S2 is closed; when the row decoding signal position selects the second unit 120 of the upper address module and the first unit 110 of the lower address module, the first switch S1 in the upper address module is off
  • the second switch S2 is opened and the second switch S2 is closed, the first switch S1 in the lower address module is closed and the second switch S2 is opened.
  • the first unit 110 in the high-order address module and the second unit 120 in the low-order address module are selected; for the high-order address module, the first column decoding circuit 102 and the first translation The code selection signal line CSL1 is enabled, and the first switch S1 is closed and the second switch S2 is open, the first data signal line YIO1 is connected to the circuit, and the second data signal line YIO2 is disconnected from the circuit; for the lower address module, the second The column decoding circuit 103 and the second decoding selection signal line CSL2 are enabled, and the first switch S1 is opened and the second switch S2 is closed, the first data signal line YIO1 is disconnected from the circuit, and the second data signal line YIO2 is connected Circuit.
  • the second cell 120 in the upper address module and the first cell 110 in the lower address module are selected; for the upper address module, the second column decoding circuit 103 and the second decoding selection signal line CSL2 Enable, and the first switch S1 is open and the second switch S2 is closed, the first data signal line YIO1 is disconnected from the circuit, and the second data signal line YIO2 is connected to the circuit; for low-order address modules, the first column decoding circuit 102 And the first decoding selection signal line CSL1 is enabled, the first switch S1 is closed and the second switch S2 is open, the first data signal line YIO1 is connected to the circuit, and the second data signal line YIO2 is disconnected from the circuit.
  • the storage block can save 12mA of current at the 3733 baud rate.
  • Another embodiment of the present application also provides a storage block.
  • the first unit and the second unit in the previous embodiment are only one of the high-order address unit or the low-order address unit, and
  • the first unit includes a first high-order address unit and a first low-order address unit
  • the second unit includes a second high-order address unit and a second low-order address unit.
  • FIG. 7 is a schematic structural diagram of a storage block provided by another embodiment of this application.
  • the memory block includes at least one memory module 200, and each memory module 200 includes: a read-write control circuit 201, a column decoding circuit, and a number of memory arrays 204 arranged along a first direction.
  • the memory array 204 is divided into at least one first cell 210 and at least one second cell 220; a first decoding selection signal line csl1; a second decoding selection signal line csl2; a first data signal line yio1; a second data signal line yio2 .
  • the column decoding circuit includes a first column decoding circuit 202 and a second column decoding circuit 203.
  • the first decoding selection signal line csl1 is electrically connected to the first column decoding circuit 202 and the storage of the first unit 210.
  • the second decoding selection signal line csl2 is electrically connected to the second column decoding circuit 203 and the memory array 204 of the second unit 220.
  • the number of column decoding circuits can also be one.
  • the first unit 210 includes a first high-order address unit HDQ1 and a first low-order address unit LDQ1
  • the second unit 220 includes a second high-order address unit HDQ2 and a second low-order address unit LDQ2.
  • the first low-order address unit LDQ1 is adjacent to the second high-order address unit HDQ2, that is, according to the first high-order address unit HDQ1, the first low-order address unit LDQ1, the second high-order address unit HDQ2, and the second low-order address unit LDQ2 Arrange in the order of arrangement.
  • the first low-order address unit and the second high-order address unit are separated by the second low-order address unit, that is, the positions of the second low-order address unit and the second high-order address unit can be exchanged, correspondingly Yes, according to the arrangement order of the first high-order address unit, the first low-order address unit, the second low-order address unit, and the second high-order address unit.
  • the first decoding selection signal line csl1 is electrically connected to the first column decoding circuit 202 and all the memory arrays 204 in the first unit 210, so that the first decoding selection signal line csl1 is decoded based on the first column.
  • the circuit 202 locates and selects any memory array 204 located in the first unit 210;
  • the second decoding selection signal line csl2 is electrically connected to all the memory arrays 204 in the second unit 220, so that the second decoding selection signal line csl2 is based on the
  • the two-column decoding circuit 203 locates and selects any memory array 204 located in the second cell 220.
  • the memory block further includes a row decoding circuit, which is used to send a row decoding signal to locate and select the first unit 210 or the second unit 220.
  • the first data signal line yio1 is electrically connected to the read/write control circuit 201 and all storage arrays 204 of HDQ1 in the first high-order address unit; the second data signal line yio2 is electrically connected to the read/write control circuit and all the storage in the second low-order address unit LDQ2
  • the storage block also includes: a third data signal line yio3, the third data signal line yio3 is electrically connected to the read-write control circuit 201 and all storage arrays 204 in the second high-order address unit HDQ2; the fourth data signal line yio4, the fourth The data signal line yio4 is electrically connected to the read-write control circuit 201 and all the memory arrays 204 in the first lower address unit LDQ1.
  • Each memory module 200 in FIG. 7 shows two sets of first data signal lines yio1 and two sets of second data signal lines yio2. It can be understood that, in other embodiments, the first data signal lines and the second data signal lines The number of data signal lines can be any number.
  • the storage block includes two storage modules 200, and each storage module 200 has a high-order address unit and a low-order address unit.
  • the storage block may also include only one storage module, or may also include any other number of storage modules.
  • each storage module 200 includes a first unit 210 and a second unit 220, the storage block is divided into two first units 210 and two second units 220, and
  • the first unit 210 has a first high-order address unit HDQ1 and a first low-order address unit LDQ1
  • the second unit has a second high-order address unit HDQ2 and a second low-order address unit LDQ2, that is, each first unit 210 and each A second unit 220 has both high and low positions.
  • the first decoding selection signal line csl1 or the second decoding selection has a short line length and a significantly reduced load.
  • the first data signal line yio1, the second data signal line yio2, the third data signal line yio3, or the fourth data signal line yio4 has a short line length and a significant load.
  • the row decoding signal to select the first unit 210 of the upper memory module 200 is enabled, and the designation of the first high-order address unit HDQ1 is selected.
  • the first data signal line yio1 transmits data signals between the designated storage array 204 in the first high-order address unit HDQ1 and the read-write control circuit 201;
  • the fourth data The signal line yio4 transmits signals before the designated memory array 204 and the read/write control circuit 201 in the first low-order address unit LDQ1. In this way, the reading operation or the writing operation in the first unit 210 is completed.
  • the second column decoding circuit 203 and the second decoding selection signal line csl2 are enabled, and the designation of the second high-order address unit HDQ2 is selected.
  • the memory array 204 and the designated memory array 204 of the second lower address unit LDQ2; the second data signal line yio2 transmits data signals between the designated memory array 204 of the second lower address unit LDQ2 and the read-write control circuit 201; the third data signal The line yio3 transmits signals between the designated memory array 204 of the second high-order address unit HDQ2 and the read-write control circuit 201. In this way, the read operation or the write operation in the second unit 220 is completed.
  • the first data signal line yio1 and the third data signal line yio3 are on the same bus
  • the second data signal line yio2 and the fourth data signal line yio4 are on the same bus.
  • the root bus is marked with yio1 and yio3, and the same bus is marked with yio2 and yio4.
  • FIG. 8 is a schematic diagram of another structure of the memory block in this embodiment.
  • the third data signal line yio3 and the first data signal line yio1 are independent of each other, namely They are different buses; the fourth data signal line yio4 and the second data signal line yio2 are independent of each other, that is, they are different buses.
  • the number of memory arrays 204 in the first unit 210 is the same as the number of memory arrays 204 in the second unit 220, and the number of memory arrays 204 in the first high-order address unit HDQ1 is the same as that of the first low-order address unit LDQ1.
  • the number of storage arrays 204 in the second high-order address unit HDQ2 is the same as the number of storage arrays 204 in the second low-order address unit LDQ2. In this way, in each read operation or write operation, the number of storage arrays 204 involved is the same, which is beneficial to average the current consumption of the storage block, and is beneficial to avoid the occurrence of excessive current peaks, thereby further improving the performance of the storage block. performance.
  • the number of memory arrays in the first unit and the number of memory arrays in the second unit may also be different, and the number of memory arrays in the first high-order address unit is different from the first low-order address.
  • the number of storage arrays in the unit may also be different, and the number of storage arrays in the second high-order address unit and the number of storage arrays in the second low-order address unit may also be different.
  • the storage block provided in this embodiment can further reduce power consumption and power consumption.
  • an embodiment of the present application also provides a memory, including at least one storage block in any of the foregoing embodiments.
  • the column decoding circuits of different memory blocks can be shared or independent of each other; the read and write control circuits of different memory blocks can be shared or independent of each other.
  • the memory can be DRAM or SRAM.
  • the memory provided by this embodiment has the advantage of low power consumption, and the power consumption is significantly reduced.

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Abstract

本申请部分实施例涉及半导体技术领域，公开了一种存储块以及存储器。存储块包括至少一个存储模块(100)，每一存储模块(100)包括读写控制电路(101)、列译码电路(123)以及若干个存储阵列(104)，若干个存储阵列(104)划分为第一单元(110)以及第二单元(120)；第一译码选择信号线(CSL1)，电连接列译码电路(123)以及第一单元(110)内的存储阵列(104)；第二译码选择信号线(CSL2)，电连接列译码电路(123)以及第二单元(120)内的存储阵列(104)；第一数据信号线(YIO1)；第二数据信号线(YIO2)。

Description

存储块以及存储器
交叉引用
本申请引用于2020年3月30日递交的名称为“存储块以及存储器”的第202010237983.6号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及半导体技术领域，特别涉及一种存储块以及存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
DRAM分为双倍速率同步(Double Data Rate，DDR)动态随机存储器、GDDR(Graphics Double Data Rate)动态随机存储器、低功耗双倍速率同步(Low Power Double Data Rate，LPDDR)动态随机存储器。随着DRAM应用的领域越来越多，如DRAM越来越多地应用于移动领域，用户对于DRAM速度指标的要求越来越高。
然而，目前的DRAM功耗仍然较高，难以满足低功耗需求。
申请内容
本申请实施例提供一种存储块以及存储器，以解决存储器功耗大的问题。
为解决上述问题，本申请实施例提供一种存储块，包括：包括至少一个存储模块，每一所述存储模块包括：读写控制电路、列译码电路以及沿第一方向设置的若干个存储阵列，所述若干个存储阵列划分为至少一个第一单元以及至少一个第二单元；第一译码选择信号线，所述第一译码选择信号线电连接所述列译码电路以及所述第一单元内的所述存储阵列；第二译码选择信号线，所述第二译码选择信号线电连接所述列译码电路以及所述第二单元内的所述存储阵列；第一数据信号线，所述第一数据信号线用于电连接所述读写控制电路以及所述第一单元内的所述存储阵列；第二数据信号线，所述第二数据信号线用于电连接所述读写控制电路以及所述第二单元内的所述存储阵列。
另外，所述第一单元以及所述第二单元的数量均为一个；且所述第一单元以及所述第二单元均为高位地址单元，或者，所述第一单元以及所述第二单元均为低位地址单元。
另外，所述第一数据信号线电连接所述第一单元内的所有所述存储阵列；所述第二数据信号线电连接所述第二单元内的所有所述存储阵列。
另外，所述第一单元内的所述存储阵列的数量与所述第二单元内的所述存储阵列的数量相同。
另外，所述第一数据信号线以及所述第二数据信号线均与所述读写控制电路电连接。
另外，还包括：切换开关模块，所述切换开关模块用于切换所述第一数 据信号线或者所述第二数据信号线中的一者电连接至所述读写控制电路。
另外，所述切换开关模块包括：控制单元以及开关单元；所述控制单元基于接收到的行译码信号产生控制信号；所述开关单元用于，基于所述控制信号连通所述读写控制电路与所述第一数据信号线，或者，连通所述读写控制电路与所述第二数据信号线。
另外，所述开关单元包括第一开关和第二开关，所述第一开关连接于所述第一数据信号线与所述读写控制电路之间，所述第二开关连接于所述第二数据信号线与所述读写控制电路之间。
另外，所述存储块包括2个所述存储模块，其中一个所述存储模块为高位地址模块，另一个所述存储模块为低位地址模块。
另外，还包括：定位控制模块，所述定位控制模块用于控制行译码电路产生的行译码信号，以使行译码信号同时定位选中所述高位地址模块的第一单元以及所述低位地址模块的第二单元，或者，同时定位选中所述高位地址模块的第二单元以及所述低位地址模块的第一单元。
另外，所述第一单元包括第一高位地址单元以及第一低位地址单元；所述第二单元包括第二高位地址单元以及第二低位地址单元。
另外，所述第一数据信号线电连接所述读写控制电路与所述第一高位地址单元内的所述存储阵列；所述第二数据信号线电连接所述读写控制电路与所述第二低位地址单元内的所述存储阵列；所述存储块还包括：第三数据信号线，所述第三数据信号线电连接所述读写控制电路与所述第二高位地址单元内的所述存储阵列；第四数据信号线，所述第四数据信号线电连接所述读写控制电路与所述第一低位地址单元内的所述存储阵列。
另外，所述第一数据信号线与所述第三数据信号线为同一总线；所述第二数据信号线与所述第四数据信号线为同一总线。
另外，所述第一低位地址单元与所述第二高位地址单元相邻；或者，所述第一低位地址单元与所述第二高位地址单元由所述第二低位地址单元间隔开。
另外，所述存储块包括两个所述存储模块。
另外，所述列译码电路包括：第一列译码电路以及第二列译码电路，所述第一译码选择信号线电连接所述第一列译码电路以及所述第一单元内的所述存储阵列，所述第二译码选择信号线电连接所述第二列译码电路以及所述第二单元内的所述存储阵列。
另外，所述第一列译码电路以及所述第二列译码电路分别位于所述若干个存储阵列的相对两侧。
所述第一译码选择信号线以及所述第二译码选择信号线电连接同一所述列译码电路。
另外，还包括：行译码电路，用于发出行译码信号，以定位选中所述第一单元或者所述第二单元中的一者。
相应的，本申请实施例还提供一种存储器，包括上述实施例的存储块。
与现有技术相比，本申请提供的技术方案具有以下优点：
本申请实施例提供一种结构性能优越的存储块，包括用于定位选中第一单元的存储阵列的列译码电路以及第一译码选择信号线，用于定位选中第二单元的存储阵列的列译码电路以及第二译码选择信号线，用于实现第一单元内的存储阵列与读写控制电路之间数据传输的第一数据信号线，用于实现第二单元内的存储阵列与读写控制电路之间数据传输的第二数据信号线。在单次读写操 作时，仅需使能第一译码选择信号线或者第二译码选择信号线即可，由于第一译码选择信号线仅与部分数量的存储阵列电连接即具有电接触点，第二译码选择信号线仅与部分数量的存储阵列电连接，因此在单次读写操作过程中的电接触点减少，因此存储块的寄生电阻和寄生电容也减少，从而有利于降低存储块的功耗。此外，用于数据传输的第一数据信号线以及第二数据信号线均与部分数量的存储阵列电连接，使得在单次读写操作过程中的电接触点减少，此存储块的寄生电阻和寄生电容也减少，从而有利于降低存储块的功耗。
另外，存储块还包括切换开关模块，切换开关模块用于切换第一数据信号线或者第二数据信号线中的一者电连接至所述读写控制电路。如此，当第一数据信号线传输数据信号期间，第二数据信号线完全从电路中断开，从而避免第二数据信号线带来的热量损耗问题，进一步的降低存储块的功耗；同样的，当第二数据信号线传输数据信号期间，第一数据信号线完全从电路中断开，从而避免第一数据信号线带来的热量损耗问题，进一步的降低存储块的功耗。
另外，第一单元包括第一高位地址单元以及第一低位地址单元，第二单元包括第二高位地址单元以及第二低位地址单元，如此，在同一单元中能够获取高位数据和低位数据，每次行译码时只需选中一个单元，这样可以使存储块节省更多的电，进一步的降低存储块的功耗。
附图说明
图1为一种DARM的结构示意图；
图2为本申请一实施例提供的存储块的一种结构示意；
图3为本申请一实施例提供的存储块的另一种结构示意图；
图4为本申请一实施例提供的存储块的又一种结构示意图；
图5为本申请另一实施例提供的存储块的结构示意图；
图6为本申请另一实施例提供的存储块的局部结构示意图；
图7为本申请又一实施例提供的存储块的一种结构示意图；
图8为本申请又一实施例中存储块的另一种结构示意图。
具体实施方式
现结合一种DRAM的结构示意图进行分析，图1为一种DARM的结构示意图。参考图1，DRAM由多个存储块(bank，也称为存储体)10构成，每个存储块10包括若干存储阵列，每一存储阵列包括存储器阵列(array)11以及灵敏放大器阵列12。对于DRAM，无论是DDR(如DDR2/3/4，等)系列，还是LPDDR(如LPDDR2/3/4/5)系列，均按照输出管脚(DQ)将存储块10分为了高位一组和低位一组。也就是说，每个bank也可以对应分为2个half bank，其中一个half bank作为第一模块M1，第一模块M1提供低位输出管脚，另一个half bank作为第二模块M2，第二模块M2提供高位输出管脚。高位和低位指的是数据比特位(bit)的高低，低位输出管脚传输处于低比特位的数据，高位输出管脚传输处于高比特位的数据。
译码选择信号线CSL接收列译码电路(YDEC)13输出的列选择信号，数据信号线YIO用于在选中的存储器阵列11与读写控制电路14之间传输数据。无论是低位一组的half bank还是高位一组的half bank，为了顺利完成读取以及写入操作，译码选择信号线CSL与half bank中的每个存储器阵列11均具有电接触点，该电接触点相应会产生寄生电容；译码选择信号线CSL以及数据信号 线YIO线均很长，导致寄生电阻较大，这将带来每次读写消耗的电量大的问题，导致DRAM功耗大。
进一步分析发现，寄生电阻以及寄生电容也是导致DARM功耗大的主要原因之一。对于译码选择信号线CSL，在每一次读取操作或者写入操作期间，每一组译码选择信号线CSL与每一个存储器阵列11的电接触点均存在寄生电容以及寄生电阻。同样的，对于数据信号线YIO，在每一次读取操作或者写入操作期间，每一组数据信号线YIO与每一个存储器阵列11的电接触点均存在寄生电容以及寄生电阻。由于电接触点多，相应的寄生电阻以及寄生电阻大，导致DRAM功耗大。
为解决上述问题，本申请实施例提供一种结构性能优越的存储块，通过特殊结构的设计，减小存储块的寄生电阻以及寄生电容，从而降低存储块的功耗。
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图2为本申请一实施例提供的存储块的一种结构示意。
参考图2，本实施例中，存储块包括至少一个存储模块100，每一存储模块100包括：读写控制电路101、列译码电路123以及沿第一方向设置的若干个存储阵列104，所述若干个存储阵列104划分为至少一个第一单元110以及至少一个第二单元120；第一译码选择信号线CSL1，第一译码选择信号线CSL1 电连接列译码电路123以及第一单元110内的存储阵列104，使列译码电路123对位于第一单元110内的存储阵列104定位；第二译码选择信号线CSL2，第二译码选择信号线CSL2电连接列译码电路123以及第二单元120内的存储阵列104，使列译码电路123对位于第二单元120内的存储阵列104进行定位；第一数据信号线YIO1，第一数据信号线YIO1用于电连接读写控制电路101以及第一单元110内的存储阵列104；第二数据信号线YIO2，第二数据信号线YIO2用于电连接读写控制电路101以及第二单元120内的存储阵列104。
以下将结合附图对本实施例进行详细说明。需要说明的是，为了便于图示，图2和图3中标示的三角符号表示电连接即具有电接触点，未标示三角符号则表示未电连接不具有电接触点。
本实施例中，存储块包括2个存储模块100，其中一个存储模块100为高位地址模块，另一个存储模块100为低位地址模块。举例来说，存储块的位数为16位时，低位地址模块的位数为低8位，高位地址模块的位数为高8位。
相应的，本实施例中，第一单元110以及第二单元120的数量均为一个，且第一单元110以及第二单元120均为高位地址单元，或者，第一单元110以及第二单元120均为低位地址单元。其中一个存储模块100中的第一单元110以及第二单元120均为高位地址单元，为便于描述，将该存储模块100称为高位存储模块；另一存储模块100中的第一单元110以及第二单元120均为低位地址单元，为便于描述，将该存储模块100称为低位存储模块。图2中，以上方的存储模块100作为高位存储模块、下方的存储模块100作为低位存储模块作为示例。可以理解的是，在其他实施例中，第一单元以及第二单元的数量可以根据实际存储需求进行设计。
每一存储阵列104包括存储器阵列以及灵敏放大器阵列(Sense Amplifier，SA)。存储器阵列中包括多个存储元件，用于存储数据；灵敏放大器阵列用于放大存储器阵列的输出信号。第一单元110内包括第一数量的存储阵列104，第二单元120内包括第二数量的存储阵列104，第一数量与第二数量可以相同也可以不同。
本实施例中，第一单元110内的存储阵列104的数量与第二单元120内的存储阵列104的数量相同。
本实施例中，列译码电路123包括：第一列译码电路102以及第二列译码电路103，第一译码选择信号线CSL1电连接第一列译码电路102以及第一单元110内的存储阵列104，通过第一列译码电路102对第一单元110内的存储阵列104进行定位选中；第二译码选择信号线CSL2电连接第二列译码电路103以及第二单元120内的存储阵列104，通过第二列译码电路103对第二单元120内的存储阵列104进行定位选中。
第一列译码电路102输出第一定位信号，通过第一译码选择信号线CSL1定位选中位于第一单元110内的存储阵列104，以便对选中的存储阵列104进行读取操作或者写入操作。第二列译码电路103输出第二定位信号，通过第二译码选择信号线CSL2选中位于第二单元120内的存储阵列104，以便对选中的存储阵列104进行读取操作或者写入操作。更具体地，第一译码选择信号线CSL1电连接第一单元110内的所有存储阵列104，第二译码选择信号线CSL2电连接第二单元120内的所有存储阵列104。
本实施例中，为了进一步的减小第一译码选择信号线CSL1以及第二译码选择信号线CSL2的长度，以便于进一步的减小电阻，降低功耗，第一列译 码电路102以及第二列译码电路103分别位于该若干存储阵列104的相对两侧。
图3为本申请一实施例提供的存储块的另一种结构示意图，如图3所示，在其他实施例中，对于第一单元110或者第二单元120而言，列译码电路123的数量也可以为一个，该列译码电路123既可以定位选中第一单元110的存储阵列104，还可以定位选中第二单元120的存储阵列104，第一译码选择信号线CSL1以及第二译码选择信号线CSL2电连接同一列译码电路123。此外，不同存储模块100可具有单独的列译码电路123，且不同的存储模块100还可以共用列译码电路123。
第一译码选择信号线CSL1横跨第一单元110内的存储阵列104，第二译码选择信号线CSL2横跨第二单元120内的存储阵列104。第一数据信号线YIO1横跨该若干存储阵列104，即横跨第一单元110以及第二单元120，且仅与第一单元110内的存储阵列104电连接；第二数据信号线YIO2横跨第二单元120内的存储阵列104。更具体地，第一数据信号线YIO1电连接第一单元110内的所有存储阵列104，第二数据信号线YIO2电连接第二单元120内的所有存储阵列104。
本实施例中，以每一存储模块100具有2组第一数据信号线YIO1以及2组第二数据信号线YIO2作为示例。在其他实施例中，第一数据信号线以及第二数据信号线的组数可以根据实际需求进行合理设计。
本实施例中，第一数据信号线YIO1以及第二数据信号线YIO2均与读写控制电路101电连接。
如图4所示，图4为本申请一实施例提供的存储块的又一种结构示意图，存储模块100还可以包括行译码电路124，用于发出行译码信号，以定位选中 第一单元110或者第二单元120中的一者。不同的存储块100可以具有相互独立的行译码电路124，且不同的存储块100也可以共用同一行译码电路124。
具体地，行译码电路124定位选中第一单元110时，仅使能第一译码选择信号线CSL1以及第一列译码电路102；行译码电路124定位选中第二单元120时，仅使能第二译码选择信号线CSL2以及第二列译码电路103。
相较于采用同一根译码选择信号线电连接所有存储阵列的方案而言，本实施例中，在单次读取操作或者写入操作中，仅使能第一译码选择信号线CSL1或者第二译码选择信号线CSL2中的一者，以使能第一译码选择信号线CSL1以及第一列译码电路102为例，第一译码选择信号线CSL1与存储阵列104的电接触点的数量减少，第一数据信号线YIO1与存储阵列104的电接触点的数量也减少，如此，不仅能够减小存储块中的寄生电路以及寄生电容，且第一译码选择信号线CSL1以及第一数据信号线YIO1上挂的负载都明显减少，因而能够显著的降低存储块的功耗。可以理解的是，仅使能第二译码选择信号线CSL2以及第二列译码电路103时，同样的能够显著的降低存储块的功耗，从而节省更多的功耗。
此外，由于第二数据信号线YIO2横跨第二单元120内的存储阵列104，第二数据信号线YIO2跨越的存储阵列104的长度减少，因而第二数据信号线YIO2的线长短，从而有利于进一步的减小第二数据信号线YIO2的电阻以及消耗的功耗，从而进一步的降低存储块的功耗。
为了便于理解和说明，以下结合存储块进行写入操作的工作原理进行说明：
在一次写入操作中，行译码电路124输出的行译码信号(row decode) 指向第一单元110时，仅使能第一列译码电路102以及第一译码选择信号线CSL1，选中第一单元110中的存储阵列104；第一数据信号线YIO1将读写控制电路101输出的数据写入第一单元110中选中的存储阵列104中，第二译码选择信号线CSL2未使能，且第二数据信号线YIO2不传输数据信号。由于第一译码选择信号线CSL1的长度短且所挂的负载少，第一数据信号线YIO1所挂的负载少，因此在该次写入操作中存储块的功耗低。可以理解的是，负载少指的是电连接的存储阵列104的数量少，即电接触点少，寄生电容小。
在另一次写入操作中，行译码电路124输出的行译码信号指向第二单元120时，仅还能第二列译码电路103以及第二译码选择信号线YIO2，选择第二单元120中的存储阵列104；第二数据信号线YIO2将读写控制电路101输出的数据写入第二单元120中选中的存储阵列104中，第一译码选择信号线CSL1未使能，且第一数据信号线YIO1不传输数据信号。由于第二译码选择信号线CSL2的长度短且所挂的负载少，第二数据信号线YIO2的长度短且所挂的负载少，因此在该次写入操作中存储块的功耗低。
本实施例中，存储块还可以包括：定位控制模块125，定位控制模块125用于控制行译码电路124产生的行译码信号，以使行译码信号同时定位选中高位地址模块的第一单元110以及低位地址模块的第二单元120，或者，同时定位选中高位地址模块的第二单元120以及低位地址模块的第一单元110。具体地，定位控制模块125与行译码电路124电连接，适于向行译码电路124发出定位控制信号，行译码电路124基于该定位控制信号生成行译码信号。
如此，在每一次读取操作或者写入操作过程中，起到数据传输作用的第一数据信号线YIO1以及第二数据信号线YIO2的总长度均相等，因此能够使得 每一次读取操作或者写入操作的电流消耗分布平均，避免出现过大的电流峰值，从而进一步的改善存储块的性能。为便于理解，以存储块进行读取操作为例示例结合存储块的工作原理进行说明：
在前一次读取操作过程中，高位地址模块中的第一单元110以及低位地址模块中的第二单元120同时被选中。对于高位地址模块，起到数据传输作用的为第一数据信号线YIO1；对于低位地址模块，起到数据传输作用的为第二数据信号线YIO2；数据传输总线长度为第一数据信号线YIO1以及第二数据信号线YIO2的总长度。
在后一次读取操作过程中，高位地址模块中的第二单元120以及低位地址模块中的第一单元110同时被选中。对于高位地址模块，起到数据传输作用的为第二数据信号线YIO2；对于低位地址模块，起到数据传输作用的为第一数据信号线YIO1；数据传输总线长度为第一数据信号线YIO1以及第二数据信号线YIO2的总长度。
由上述分析可知，每次读取操作数据传输总线长度保持不变，因而数据传输总线消耗的热量相同且所挂的负载数量相同，从而有利于保证在工作过程中的电流消耗平均，进一步改善存储块的性能。
可以理解的是，在其他实施例中，存储块的工作模式也可以为：同时选中高位地址模块的第一单元以及低位地址模块的第一单元，同时选中高位地址模块的第二单元以及低位地址模块的第二单元。
综上所述，本实施例提供的存储块每次消耗的电量小，相应的存储块具有低功耗的优势。
本申请另一实施例还提供一种存储块，该存储块与上一实施例提供的存 储块大致相同，区别在于还包括切换开关模块，该切换开关模块用于切换第一数据信号线或者第二数据信号线中的一者电连接至读写控制电路。以下将结合附图对本实施提供的存储块进行说明，需要说明的是，与前一实施例相同或者相应的部分，请参考前一实施例的详细说明，以下将不做详细赘述。
图5为本申请另一实施例提供的存储块的结构示意图，图6为本申请另一实施例提供的存储块的局部结构示意图。
结合参考图5及图6，本实施例中，存储块包括：存储模块100，每一存储模块100包括：读写控制电路101、第一列译码电路102、第二列译码电路103以及沿第一方向设置的若干个存储阵列104；第一译码选择信号线CSL1；第二译码选择信号线CSL2；第一数据信号线YIO1；第二数据信号线YIO2；切换开关模块126，切换开关模块126用于切换第一数据信号线YIO1或者第二数据信号线YIO2中的一者电连接至读写控制电路101。
可以理解的是，本实施例中以列译码电路包括第一列译码电路102以及第二列译码电路103作为示例。在其他实施例中，列译码电路也可以仅有一个，第一译码选择信号线以及第二译码选择信号线均电连接至该列译码电路。
由于切换开关模块126的设置，使得在单次读取操作或者写入操作中，仅有第一数据信号线YIO1或者第二数据信号线YIO2中一者接入电路，从而有利于进一步的降低数据信号线消耗的热量，进而进一步的降低存储块的功能。
具体地，切换开关模块126包括开关单元136以及控制单元146；控制单元146用于基于接收到的行译码信号产生控制信号；开关单元136用于，基于控制信号连通读写控制电路101与第一数据信号线YIO1，或者，连通读写控制电路101与第二数据信号线YIO2。
开关单元136包括第一开关S1和第二开关S2，第一开关S1连接于第一数据信号线YIO1与读写控制电路101之间，第二开关S2连接于第二数据信号线YIO2与读写控制电路101之间。控制单元146基于行译码信号控制第一开关S1闭合或者断开，控制第二开关S2闭合或者断开。
可以理解的是，第一开关S1或者第二开关S2可以由至少一个MOS管构成。第一开关S1闭合，第一数据信号线YIO1与读写控制电路101电连接；第一开关S1断开，第一数据信号线YIO1与读写控制电路101断开；第二开关S2闭合，第二数据信号线YIO2与读写控制电路101电连接；第二开关S2断开，第二数据信号线YIO2与读写控制电路101断开。
对于同一存储模块100而言，开关单元136的数量与第一数据信号线YIO1的组数以及第二数据信号线YIO2的组数相同。本实施例中，开关单元136为两个，在其他实施例中，也可以根据第一数据信号线以及第二数据信号线的组数，合理设置开关单元的数量。
如前一实施例所述，图5中处于上方的存储模块100为高位地址模块，处于下方的存储模块100为低位地址模块。存储块模块还可以包括：定位控制模块125，有关定位控制模块125的详细说明可参考前一实施例，且定位控制模块125与切换开关模块126相连，切换开关模块126基于定位控制模块125发出的定位控制信号进行开关切换，以使第一数据信号线YIO1或者第二数据信号线YIO2电连接至读写控制电路101。
具体地，行译码信号定位选中高位地址模块的第一单元110以及低位地址模块的第二单元120时，高位地址模块中的第一开关S1闭合且第二开关S2断开时，低位地址模块中的第一开关S1断开且第二开关S2闭合；行译码信号 定位选中高位地址模块的第二单元120以及低位地址模块的第一单元110时，高位地址模块中的第一开关S1断开且第二开关S2闭合时，低位地址模块中的第一开关S1闭合且第二开关S2断开。
为了便于理解，以下将结合附图对本实施例提供的存储块的工作原理进行说明：
如图5，在前一次写入操作中，高位地址模块中的第一单元110和低位地址模块中的第二单元120被选中；对于高位地址模块，第一列译码电路102以及第一译码选择信号线CSL1使能，且第一开关S1闭合第二开关S2断开，第一数据信号线YIO1接入电路，第二数据信号线YIO2从电路中断开；对于低位地址模块，第二列译码电路103以及第二译码选择信号线CSL2使能，且第一开关S1断开第二开关S2闭合，第一数据信号线YIO1从电路中断开，第二数据信号线YIO2接入电路。
在下一次写入操作中，高位地址模块中的第二单元120和低位地址模块中的第一单元110被选中；对于高位地址模块，第二列译码电路103以及第二译码选择信号线CSL2使能，且第一开关S1断开第二开关S2闭合，第一数据信号线YIO1从电路中断开，第二数据信号线YIO2接入电路；对于低位地址模块，第一列译码电路102以及第一译码选择信号线CSL1使能，且第一开关S1闭合第二开关S2断开，第一数据信号线YIO1接入电路，第二数据信号线YIO2从电路中断开。
与前一实施例相比，本实施例中，当第一数据信号线YIO1或者第二数据信号线YIO2不起到电信号传输作用时，会彻底从电路中断开，从而有利于进一步的降低存储块的功耗。研究发现，若干存储阵列中存储阵列的数量为145 时，在3733波特率下该存储块能节省12mA的电流。
本申请又一实施例还提供一种存储块，与前述两个实施例不同的是，前述实施例中第一单元和第二单元均仅为高位地址单元或者低位地址单元中的一种，而本实施例中第一单元包括第一高位地址单元以及第一低位地址单元，第二单元包括第二高位地址单元以及第二低位地址单元。以下将结合附图对本实施提供的存储块进行说明，需要说明的是，与前一实施例相同或者相应的部分，请参考前一实施例的详细说明，以下将不做详细赘述。
图7为本申请又一实施例提供的存储块的一种结构示意图。
参考图7，本实施例中，存储块包括至少一个存储模块200，每一存储模块200包括：读写控制电路201、列译码电路以及沿第一方向设置的若干个存储阵列204，若干个存储阵列204划分为至少一个第一单元210以及至少一个第二单元220；第一译码选择信号线csl1；第二译码选择信号线csl2；第一数据信号线yio1；第二数据信号线yio2。
本实施例中，列译码电路包括第一列译码电路202以及第二列译码电路203，第一译码选择信号线csl1电连接第一列译码电路202以及第一单元210的存储阵列204，第二译码选择信号线csl2电连接第二列译码电路203以及第二单元220的存储阵列204。在其他实施例中，列译码电路的数量也可以为一个。
其中，第一单元210包括第一高位地址单元HDQ1以及第一低位地址单元LDQ1，第二单元220包括第二高位地址单元HDQ2以及第二低位地址单元LDQ2。本实施例中，第一低位地址单元LDQ1与第二高位地址单元HDQ2相邻，即按照第一高位地址单元HDQ1、第一低位地址单元LDQ1、第二高位地 址单元HDQ2、第二低位地址单元LDQ2的排列顺序进行排列。
可以理解的是，在其他实施例中，第一低位地址单元与第二高位地址单元由第二低位地址单元间隔开，即第二低位地址单元与第二高位地址单元的位置可以互换，相应的，按照第一高位地址单元、第一低位地址单元、第二低位地址单元、第二高位地址单元的排列顺序进行排列。
本实施例中，第一译码选择信号线csl1电连接第一列译码电路202以及第一单元210内的所有存储阵列204，以便使第一译码选择信号线csl1基于第一列译码电路202定位选中位于第一单元210内的任一存储阵列204；第二译码选择信号线csl2电连接第二单元220内的所有存储阵列204，以便使第二译码选择信号线csl2基于第二列译码电路203定位选中位于第二单元220内的任一存储阵列204。
本实施例中，存储块还包括行译码电路，用于发出行译码信号，定位选中第一单元210或者第二单元220。
第一数据信号线yio1电连接读写控制电路201与第一高位地址单元内HDQ1的所有存储阵列204；第二数据信号线yio2电连接读写控制电路与第二低位地址单元LDQ2内的所有存储阵列；存储块还包括：第三数据信号线yio3，第三数据信号线yio3电连接读写控制电路201与第二高位地址单元HDQ2内的所有存储阵列204；第四数据信号线yio4，第四数据信号线yio4电连接读写控制电路201与第一低位地址单元LDQ1内的所有存储阵列204。
图7中每一存储模块200中的示出了2组第一数据信号线yio1以及2组第二数据信号线yio2，可以理解的是，在其他实施例中，第一数据信号线以及第二数据信号线的组数可以为任意数量。
本实施例中，存储块包括2个存储模块200，且每一存储模块200中均具有高位地址单元以及低位地址单元。在其他实施例中，存储块也可以仅包括一个存储模块，或者，还可以包括其他任意数量个存储模块。
以存储块具有2个存储模块200为例，每个存储模块200包括一第一单元210以及一第二单元220，存储块被分为2个第一单元210以及2个第二单元220，且第一单元210中具有第一高位地址单元HDQ1以及第一低位地址单元LDQ1，第二单元中具有第二高位地址单元HDQ2以及第二低位地址单元LDQ2，也就是说每一第一单元210以及每一第二单元220均同时具有高位和低位。因此，在进行行译码时，仅需选中一个第一单元210或者一个第二单元220即可进行读取操作或者写入操作；如此，第一译码选择信号线csl1或者第二译码选择信号线csl2的线长短且所挂的负载明显减少，第一数据信号线yio1、第二数据信号线yio2、第三数据信号线yio3或者第四数据信号线yio4的线长短且所挂的负载明显减少；在单次读取操作或者写入操作中，信号线与存储阵列204的总电接触点减少，相应的存储块影响读取操作和写入操作的寄生电阻和寄生电容显著减少，这样可以节省更多的第一列译码电路202以及第二列译码电路203的电流，降低存储块的功耗。
为了便于理解，以下将结合存储块的工作原理对存储块进行说明：
以行译码信号选中位于上方的存储模块200的第一单元210为例，仅使能第一列译码电路202以及第一译码选择信号线csl1，定位选中第一高位地址单元HDQ1的指定存储阵列204以及第一低位地址单元LDQ1的指定存储阵列204；第一数据信号线yio1在第一高位地址单元HDQ1内的指定存储阵列204与读写控制电路201之间传输数据信号；第四数据信号线yio4在第一低位地址 单元LDQ1内的指定存储阵列204与读写控制电路201之前传输信号。如此，以完成在第一单元210内读取操作或者写入操作。
以行译码信号选中位于上方的存储模块200的第二单元220为例，仅使能第二列译码电路203以及第二译码选择信号线csl2，定位选中第二高位地址单元HDQ2的指定存储阵列204以及第二低位地址单元LDQ2的指定存储阵列204；第二数据信号线yio2在第二低位地址单元LDQ2的指定存储阵列204与读写控制电路201之间传输数据信号；第三数据信号线yio3在第二高位地址单元HDQ2的指定存储阵列204与读写控制电路201之间传输信号。如此，以完成在第二单元220内的读取操作或者写入操作。
本实施例中，第一数据信号线yio1与第三数据信号线yio3为同一总线，第二数据信号线yio2与第四数据信号线yio4同一总线，为了便于图示和说明，图7中在同一根总线上标示了yio1以及yio3，在同一根总线上标示了yio2以及yio4。如此，在简化结构复杂度的同时，有利于减小总线长度，进一步的降低总线电阻以及消耗的热量，从而有利于进一步的降低存储块的功耗。研究发现，若干存储阵列中存储阵列的数量为145时，在3733波特率下该存储块能节省10mA的电流。
需要说明的是，在其他实施例中，如图8所示，图8为本实施例中存储块的另一种结构示意图，第三数据信号线yio3与第一数据信号线yio1相互独立，即为不同的总线；第四数据信号线yio4与第二数据信号线yio2相互独立，即为不同的总线。
本实施例中，第一单元210内的存储阵列204的数量与第二单元220内的存储阵列204的数量相同，第一高位地址单元HDQ1内的存储阵列204的 数量与第一低位地址单元LDQ1内的存储阵列204的数量相同，第二高位地址单元HDQ2内的存储阵列204的数量与第二低位地址单元LDQ2内的存储阵列204的数量相同。如此，在每次读取操作或者写入操作中，涉及的存储阵列204的数量相同，因而有利于平均存储块的电流消耗，有利于避免出现过大的电流峰值，从而进一步的改善存储块的性能。
可以理解的是，在其他实施例中，第一单元内的存储阵列的数量与第二单元内的存储阵列的数量也可以不同，第一高位地址单元内的存储阵列的数量与第一低位地址单元内的存储阵列的数量也可以不同，第二高位地址单元内的存储阵列的数量与第二低位地址单元内的存储阵列的数量也可以不同。
综上所述，本实施例提供的存储块能够进一步的降低功耗，进一步的减少耗电量。
相应的，本申请实施例还提供一种存储器，包括上述任一实施例中的至少一个存储块。不同存储块的列译码电路可以共用，也可以为相互独立的；不同存储块的读写控制电路可以共用，也可以为相互独立的。
该存储器可以为DRAM或者SRAM。如前述分析可知，本实施例提供的存储器具有低功耗的优势，耗电量显著减小。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (20)

  1. 一种存储块，其中，包括至少一个存储模块，每一所述存储模块包括：
    读写控制电路、列译码电路以及沿第一方向设置的若干个存储阵列，所述若干个存储阵列划分为至少一个第一单元以及至少一个第二单元；
    第一译码选择信号线，所述第一译码选择信号线电连接所述列译码电路以及所述第一单元内的所述存储阵列；
    第二译码选择信号线，所述第二译码选择信号线电连接所述列译码电路以及所述第二单元内的所述存储阵列；
    第一数据信号线，所述第一数据信号线用于电连接所述读写控制电路以及所述第一单元内的所述存储阵列；
    第二数据信号线，所述第二数据信号线用于电连接所述读写控制电路以及所述第二单元内的所述存储阵列。
  2. 如权利要求1所述的存储块，其中，所述第一单元以及所述第二单元的数量均为一个；且所述第一单元以及所述第二单元均为高位地址单元，或者，所述第一单元以及所述第二单元均为低位地址单元。
  3. 如权利要求2所述的存储块，其中，所述第一数据信号线电连接所述第一单元内的所有所述存储阵列；所述第二数据信号线电连接所述第二单元内的所有所述存储阵列。
  4. 如权利要求2所述的存储块，其中，所述第一数据信号线以及所述第二数据信号线均与所述读写控制电路电连接。
  5. 如权利要求2所述的存储块，其中，所述存储块还包括：切换开关模块，所述切换开关模块用于切换所述第一数据信号线或者所述第二数据信号线中 的一者电连接至所述读写控制电路。
  6. 如权利要求5所述的存储块，其中，所述切换开关模块包括：控制单元以及开关单元；所述控制单元基于接收到的行译码信号产生控制信号；所述开关单元用于，基于所述控制信号连通所述读写控制电路与所述第一数据信号线，或者，连通所述读写控制电路与所述第二数据信号线。
  7. 如权利要求6所述的存储块，其中，所述开关单元包括第一开关和第二开关，所述第一开关连接于所述第一数据信号线与所述读写控制电路之间，所述第二开关连接于所述第二数据信号线与所述读写控制电路之间。
  8. 如权利要求2所述的存储块，其中，所述存储块包括2个所述存储模块，其中一个所述存储模块为高位地址模块，另一个所述存储模块为低位地址模块。
  9. 如权利要求8所述的存储块，其中，所述存储块还包括：定位控制模块，所述定位控制模块用于控制行译码电路产生的行译码信号，以使所述行译码信号同时定位选中所述高位地址模块的第一单元以及所述低位地址模块的第二单元，或者，同时定位选中所述高位地址模块的第二单元以及所述低位地址模块的第一单元。
  10. 如权利要求1所述的存储块，其中，所述第一单元包括第一高位地址单元以及第一低位地址单元；所述第二单元包括第二高位地址单元以及第二低位地址单元。
  11. 如权利要求10所述的存储块，其中，所述第一数据信号线电连接所述读写控制电路与所述第一高位地址单元内的所述存储阵列；所述第二数据信号线电连接所述读写控制电路与所述第二低位地址单元内的所述存储阵列。
  12. 如权利要求11所述的存储块，其中，所述存储块还包括：
    第三数据信号线，所述第三数据信号线电连接所述读写控制电路与所述第二高位地址单元内的所述存储阵列；
    第四数据信号线，所述第四数据信号线电连接所述读写控制电路与所述第一低位地址单元内的所述存储阵列。
  13. 如权利要求12所述的存储块，其中，所述第一数据信号线与所述第三数据信号线为同一总线；所述第二数据信号线与所述第四数据信号线为同一总线。
  14. 如权利要求13所述的存储块，其中，所述第一低位地址单元与所述第二高位地址单元相邻；或者，所述第一低位地址单元与所述第二高位地址单元由所述第二低位地址单元间隔开。
  15. 如权利要求10所述的存储块，其中，所述存储块包括两个所述存储模块。
  16. 如权利要求1所述的存储块，其中，所述列译码电路包括：第一列译码电路以及第二列译码电路，所述第一译码选择信号线电连接所述第一列译码电路以及所述第一单元内的所述存储阵列，所述第二译码选择信号线电连接所述第二列译码电路以及所述第二单元内的所述存储阵列。
  17. 如权利要求16所述的存储块，其中，所述第一列译码电路以及所述第二列译码电路分别位于所述若干个存储阵列的相对两侧。
  18. 如权利要求1所述的存储块，其中，所述第一译码选择信号线以及所述第二译码选择信号线电连接同一所述列译码电路。
  19. 如权利要求1所述的存储块，其中，所述存储块还包括：行译码电路，用于发出行译码信号，以定位选中所述第一单元或者所述第二单元中的一者。
  20. 一种存储器，其中，包括如权利要求1-19任一项所述的存储块。
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