WO2021092875A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2021092875A1
WO2021092875A1 PCT/CN2019/118675 CN2019118675W WO2021092875A1 WO 2021092875 A1 WO2021092875 A1 WO 2021092875A1 CN 2019118675 W CN2019118675 W CN 2019118675W WO 2021092875 A1 WO2021092875 A1 WO 2021092875A1
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WO
WIPO (PCT)
Prior art keywords
power supply
negative power
positive power
terminal
positive
Prior art date
Application number
PCT/CN2019/118675
Other languages
English (en)
French (fr)
Other versions
WO2021092875A9 (zh
Inventor
黄耀
黄炜赟
龙跃
曾超
李孟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority to EP22158338.8A priority Critical patent/EP4047662A1/en
Priority to BR112021012098A priority patent/BR112021012098A2/pt
Priority to JP2021538351A priority patent/JP7410152B2/ja
Priority to KR1020227021108A priority patent/KR20220093262A/ko
Priority to EP23206174.7A priority patent/EP4344387A1/en
Priority to RU2021119105A priority patent/RU2763690C1/ru
Priority to EP19945473.7A priority patent/EP4030482A4/en
Priority to KR1020217026560A priority patent/KR20220100786A/ko
Priority to AU2019474452A priority patent/AU2019474452B2/en
Priority to US17/256,197 priority patent/US11864435B2/en
Priority to KR1020237039417A priority patent/KR20230160961A/ko
Priority to MX2021010204A priority patent/MX2021010204A/es
Priority to CN202311113562.2A priority patent/CN117135970A/zh
Priority to PCT/CN2019/118675 priority patent/WO2021092875A1/zh
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202111645383.4A priority patent/CN114335114B/zh
Priority to CN201980002462.8A priority patent/CN113316851A/zh
Publication of WO2021092875A1 publication Critical patent/WO2021092875A1/zh
Publication of WO2021092875A9 publication Critical patent/WO2021092875A9/zh
Priority to US17/584,475 priority patent/US11963409B2/en
Priority to JP2022186013A priority patent/JP7420900B2/ja
Priority to AU2023200414A priority patent/AU2023200414B2/en
Priority to US18/369,930 priority patent/US20240008329A1/en
Priority to JP2023191045A priority patent/JP2024020328A/ja

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate and a display device.
  • the length and load of the signal transmission line outside the display area of the array substrate also increase.
  • the impedance of the signal transmission line for transmitting the positive voltage signal (VDD) or the signal transmission line for transmitting the negative voltage signal (VSS) is too large, the image displayed by the array substrate is prone to uneven brightness.
  • an array substrate including:
  • the base substrate includes a display area and a peripheral area surrounding the display area, and the display area includes a first boundary, a second boundary, a third boundary, and a fourth boundary;
  • a plurality of sub-pixels located in the display area at least one of the plurality of sub-pixels includes a light-emitting element, and the light-emitting element includes a first electrode, a light-emitting layer, and a second electrode stacked in sequence;
  • a plurality of positive power lines located in the display area and electrically connected to the first electrode
  • the first positive power supply terminal, the second positive power supply terminal, and the third positive power supply terminal are located on the side of the positive power bus away from the display area, and the second positive power supply terminal is located at the Between the first positive power supply access terminal and the third positive power supply access terminal, the first positive power supply access terminal, the second positive power supply access terminal, and the third positive power supply access terminal Are electrically connected to the positive power bus;
  • a negative power line located in the peripheral area and surrounding the second boundary, the third boundary, and the fourth boundary;
  • Auxiliary electrode located in the peripheral area and surrounding the first boundary, the second boundary, the third boundary, and the fourth boundary, and the auxiliary electrode is connected to the negative power line and the fourth boundary, respectively Two-electrode electrical connection;
  • the first negative power supply terminal, the second negative power supply terminal, and the third negative power supply terminal are located on the side of the positive power bus away from the display area, and the first negative power supply terminal is located at the The first positive power supply access terminal is far away from the second positive power supply access terminal, and the second negative power supply access terminal is located at the first positive power supply access terminal and the third positive power supply access terminal In between, the third negative power supply access terminal is located on the side of the third positive power supply access terminal away from the second positive power supply access terminal, and the first negative power supply access terminal and the third negative power supply access terminal are The power input terminals are respectively electrically connected to the negative power lines;
  • a negative power supply auxiliary line located in the peripheral area, between the first positive power supply connection terminal and the third positive power supply connection terminal, and between the positive power supply bus and the second negative power supply connection Between the terminals, the negative power auxiliary line is electrically connected to the second negative power input terminal and the auxiliary electrode, respectively.
  • the first positive power supply access terminal, the second positive power supply access terminal, and the third positive power supply access terminal are configured to pass through the positive power bus, the positive power line, and the The first electrode transmits a positive voltage signal to the light-emitting element;
  • the first negative power supply access terminal, the second negative power supply access terminal, and the third negative power supply access terminal are configured to pass through the negative power supply line, the negative power supply auxiliary line, and the auxiliary electrode And the second electrode transmits a negative voltage signal to the light-emitting element.
  • the array substrate further includes:
  • the fourth positive power input terminal is located on the side of the positive power bus away from the display area and between the first positive power input terminal and the third positive power input terminal.
  • the positive power input terminal is electrically connected to the positive power bus;
  • the fourth positive power input terminal is configured to transmit a positive voltage signal to the light-emitting element through the positive power bus, the positive power line and the first electrode.
  • the array substrate further includes:
  • the fourth negative power input terminal is located on the side of the positive power bus away from the display area and between the first positive power input terminal and the third positive power input terminal.
  • the negative power input terminal is electrically connected to the negative power auxiliary line;
  • the fourth negative power input terminal is configured to transmit a negative voltage signal to the light-emitting element through the negative power auxiliary line, the auxiliary electrode, and the second electrode.
  • the second negative power supply connection terminal is located between the second positive power supply connection terminal and the third positive power supply connection terminal, and the array substrate further includes:
  • the fourth positive power supply connection terminal and the fourth negative power supply connection terminal are located on the side of the positive power supply bus away from the display area, and the fourth positive power supply connection terminal is located at the second negative power supply connection terminal Between the third positive power supply terminal and the positive power supply bus, the fourth negative power supply terminal is located between the second negative power supply terminal and the fourth positive power supply terminal. Between the terminals and electrically connected to the negative power auxiliary line;
  • the fourth positive power access terminal is configured to transmit a positive voltage signal to the light-emitting element through the positive power bus, the positive power line, and the first electrode
  • the fourth negative power access terminal is It is configured to transmit a negative voltage signal to the light-emitting element through the negative power supply auxiliary line, the auxiliary electrode and the second electrode.
  • At least one of the plurality of sub-pixels includes a thin film transistor and a connection electrode
  • the thin film transistor includes an active layer on the base substrate, a gate located on the side of the active layer away from the base substrate, and a gate located on the side of the gate away from the base substrate. Source and drain.
  • the positive power bus includes a first sub-layer of a positive power bus and a second sub-layer of a positive power bus, and the first sub-layer of the positive power bus is electrically connected to the second sub-layer of the positive power bus;
  • the first sublayer of the positive power bus is located on the same layer as the source or the drain, and the second sublayer of the positive power bus is located on the same layer as the connection electrode.
  • the first sublayer of the positive power bus and the second sublayer of the positive power bus are electrically connected through a positive power bus via.
  • the negative power line includes a first sub-layer of a negative power line and a second sub-layer of a negative power line, and the first sub-layer of the negative power line is electrically connected to the second sub-layer of the negative power line;
  • the negative power auxiliary line includes a first sub-layer of a negative power auxiliary line and a second sub-layer of a negative power auxiliary line, and the first sub-layer of the negative power auxiliary line is electrically connected to the second sub-layer of the negative power auxiliary line;
  • the first sublayer of the negative power supply line and the first sublayer of the negative power supply auxiliary line are both located on the same layer as the source or the drain, and the second sublayer of the negative power supply line and the negative power supply auxiliary The second sub-layers of the wires are all located on the same layer as the connecting electrodes.
  • the first sub-layer of the negative power line and the second sub-layer of the negative power line are electrically connected through a negative power line via, and the first sub-layer of the negative power auxiliary line is connected to the second sub-layer of the negative power auxiliary line.
  • the two sub-layers are electrically connected through the negative power auxiliary line via.
  • At least one of the plurality of sub-pixels includes a thin film transistor
  • the thin film transistor includes an active layer on the base substrate, a gate located on the side of the active layer away from the base substrate, and a gate located on the side of the gate away from the base substrate. Source and drain;
  • the first positive power supply access terminal, the second positive power supply access terminal, the third positive power supply access terminal, and the fourth positive power supply access terminal are all connected to the source or the drain. Located on the same floor.
  • At least one of the plurality of sub-pixels includes a thin film transistor
  • the thin film transistor includes an active layer on the base substrate, a gate located on the side of the active layer away from the base substrate, and a gate located on the side of the gate away from the base substrate. Source and drain;
  • the first negative power supply access terminal, the second negative power supply access terminal, the third negative power supply access terminal, and the fourth negative power supply access terminal are all connected to the source or the drain. Located on the same floor.
  • the negative power auxiliary line includes a first sub-layer of a negative power auxiliary line and a second sub-layer of a negative power auxiliary line, the first sub-layer of the negative power auxiliary line and the second sub-layer of the negative power auxiliary line Electrical connection
  • the second negative power supply access terminal, the fourth negative power supply access terminal, and the first sub-layer of the negative power supply auxiliary line form an integrated structure.
  • the array substrate further includes:
  • the circuit board is located at the first positive power supply connection terminal, the second positive power supply connection terminal, the third positive power supply connection terminal, the fourth positive power supply connection terminal, and the first negative power supply terminal
  • the access terminal, the second negative power supply access terminal, the third negative power supply access terminal, and the fourth negative power supply access terminal are away from the side of the display area, and the first positive power supply access Terminal, the second positive power supply terminal, the third positive power supply terminal, the fourth positive power supply terminal, the first negative power supply terminal, and the second negative power supply terminal
  • the terminal, the third negative power supply access terminal and the fourth negative power supply access terminal are respectively electrically connected to the circuit board.
  • the auxiliary electrode is located on a side of the negative power supply line away from the base substrate, and the auxiliary electrode and the negative power supply auxiliary line are electrically connected through a negative power supply auxiliary via hole.
  • the light-emitting element is an organic light-emitting diode
  • the first electrode is an anode
  • the second electrode is a cathode
  • a display device including any one of the array substrates in the above aspect.
  • FIG. 1 is a front view of an array substrate provided by an embodiment of the present application
  • FIG. 2 is a front view of another array substrate provided by an embodiment of the present application.
  • FIG. 3 is a front view of still another array substrate provided by an embodiment of the present application.
  • FIG. 4 is a front view of another array substrate provided by an embodiment of the present application.
  • FIG. 5 is a cross-sectional view of a part a-a, a part b-b, a part c-c, and a part e-e of the array substrate shown in any one of FIGS. 1 to 4;
  • FIG. 6 is a cross-sectional view of a part a-a and a part f-f of the array substrate shown in FIG. 1;
  • FIG. 7 is a cross-sectional view of a part a-a and a part f-f of the array substrate shown in FIG. 2;
  • FIG. 8 is a cross-sectional view of a part a-a and a part f-f of the array substrate shown in FIG. 3;
  • FIG. 9 is a cross-sectional view of a part a-a and a part f-f of the array substrate shown in FIG. 4;
  • FIG. 10 is a cross-sectional view of a part a-a and a part g-g of the array substrate shown in FIG. 3 or FIG. 4.
  • the embodiment of the application provides an array substrate.
  • the impedance of the signal transmission line for transmitting positive voltage signals to the sub-pixels and the signal transmission line for transmitting negative voltage signals to the sub-pixels are both small, which helps The picture displayed by the array substrate is improved to be prone to uneven brightness, and the uniformity of the brightness of the picture displayed by the array substrate is ensured.
  • the detailed plan of this application is as follows:
  • the array substrate includes:
  • the base substrate includes a display area and a peripheral area surrounding the display area, and the display area includes a first boundary, a second boundary, a third boundary, and a fourth boundary;
  • a plurality of sub-pixels located in the display area at least one of the plurality of sub-pixels includes a light-emitting element, and the light-emitting element includes a first electrode, a light-emitting layer, and a second electrode stacked in sequence;
  • a plurality of positive power lines located in the display area and electrically connected to the first electrode
  • the first positive power supply terminal, the second positive power supply terminal, and the third positive power supply terminal are located on the side of the positive power bus away from the display area, and the second positive power supply terminal is located at the Between the first positive power supply access terminal and the third positive power supply access terminal, the first positive power supply access terminal, the second positive power supply access terminal, and the third positive power supply access terminal Are electrically connected to the positive power bus;
  • a negative power line located in the peripheral area and surrounding the second boundary, the third boundary, and the fourth boundary;
  • Auxiliary electrode located in the peripheral area and surrounding the first boundary, the second boundary, the third boundary, and the fourth boundary, and the auxiliary electrode is connected to the negative power line and the fourth boundary, respectively Two-electrode electrical connection;
  • the first negative power supply terminal, the second negative power supply terminal, and the third negative power supply terminal are located on the side of the positive power bus away from the display area, and the first negative power supply terminal is located at the The first positive power supply access terminal is far away from the second positive power supply access terminal, and the second negative power supply access terminal is located at the first positive power supply access terminal and the third positive power supply access terminal In between, the third negative power supply access terminal is located on the side of the third positive power supply access terminal away from the second positive power supply access terminal, and the first negative power supply access terminal and the third negative power supply access terminal are The power input terminals are respectively electrically connected to the negative power lines;
  • a negative power supply auxiliary line located in the peripheral area, between the first positive power supply connection terminal and the third positive power supply connection terminal, and between the positive power supply bus and the second negative power supply connection Between the terminals, the negative power auxiliary line is electrically connected to the second negative power input terminal and the auxiliary electrode, respectively.
  • the first positive power supply access terminal, the second positive power supply access terminal, and the third positive power supply access terminal are configured to pass through the positive power bus, the positive power line, and the The first electrode transmits a positive voltage signal to the light-emitting element; the first negative power supply terminal, the second negative power supply terminal, and the third negative power supply terminal are configured to pass through the negative power supply
  • the power supply line, the negative power supply auxiliary line, the auxiliary electrode and the second electrode transmit a negative voltage signal to the light-emitting element.
  • FIGS. 1 to 4 show front views of four array substrates provided by embodiments of the present application.
  • the array substrate includes:
  • the base substrate 10 includes a display area B1 and a peripheral area B2 surrounding the display area B1.
  • the display area B1 includes a first boundary (not shown in FIGS. 1 to 4) and a second boundary (all in FIGS. 1 to 4). Not marked), the third boundary (not marked in FIGS. 1 to 4), and the fourth boundary (not marked in FIGS. 1 to 4); the embodiment of the present application surrounds the display area B1 with the peripheral area B2 As an example to introduce;
  • a plurality of sub-pixels 11 are located in the display area B1. At least one of the plurality of sub-pixels 11 includes a light-emitting element (not shown in FIGS. 1 to 4), and the light-emitting element includes a first electrode (FIG. 1 to 4), a light-emitting layer (not shown in FIGS. 1 to 4), and a second electrode (not shown in FIGS. 1 to 4); the plurality of sub-pixels 11 can emit light to achieve Display function
  • a plurality of positive power lines 12 are located in the display area B1 and are electrically connected to the first electrode of the light-emitting element;
  • the positive power bus 13 is located in the peripheral area B2 and distributed along the first boundary of the display area B1, and the positive power bus 13 is electrically connected to the above-mentioned multiple positive power lines 12;
  • the first positive power supply terminal 14, the second positive power supply terminal 15 and the third positive power supply terminal 16 are located on the side of the positive power bus 13 away from the display area B1, and the second positive power supply terminal 15 is located at the first Between a positive power supply terminal 14 and a third positive power supply terminal 16, the first positive power supply terminal 14, the second positive power supply terminal 15 and the third positive power supply terminal 16 are respectively connected to the positive power supply bus 13 electrical connection;
  • the negative power line 17 is located in the peripheral area B2 and surrounds the second boundary, the third boundary, and the fourth boundary of the display area B1;
  • the auxiliary electrode 18 is located in the peripheral area B2 and surrounds the first boundary, the second boundary, the third boundary, and the fourth boundary of the display area B1.
  • the auxiliary electrode 18 is electrically connected to the negative power line 17 and the second electrode of the light-emitting element, respectively ;
  • the first negative power supply terminal 19, the second negative power supply terminal 20, and the third negative power supply terminal 21 are located on the side of the positive power bus 13 away from the display area B1, and the first negative power supply terminal 19 is located at the A positive power input terminal 14 is away from the side of the second positive power input terminal 15.
  • the second negative power input terminal 20 is located between the first positive power input terminal 14 and the third positive power input terminal 16.
  • the three-negative power supply terminal 21 is located on the side of the third positive power supply terminal 16 away from the second positive power supply terminal 15.
  • the first negative power supply terminal 19 and the third negative power supply terminal 21 are connected to the negative power supply terminal respectively.
  • the line 17 is electrically connected; the embodiment of the present application takes the second negative power supply connection terminal 20 located between the second positive power supply connection terminal 15 and the third positive power supply connection terminal 16 as an example for introduction;
  • the negative power supply auxiliary line 22 is located in the peripheral area B2, between the first positive power supply connection terminal 14 and the third positive power supply connection terminal 16, and between the positive power supply bus 13 and the second negative power supply connection terminal 20, The negative power auxiliary line 22 is electrically connected to the second negative power input terminal 20 and the auxiliary electrode 18 respectively.
  • the first positive power input terminal 14, the second positive power input terminal 15, and the third positive power input terminal 16 are configured to pass through the positive power bus 13, the positive power line 12 and the first electrode to the light-emitting element Transmit a positive voltage signal;
  • the first negative power access terminal 19, the second negative power access terminal 20, and the third negative power access terminal 21 are configured to pass through the negative power line 17, the negative power auxiliary line 22, the auxiliary electrode 18 and the The second electrode transmits a negative voltage signal to the light emitting element.
  • each positive power supply access terminal is configured as The positive voltage signal is transmitted to the light emitting element where the first electrode is located through the positive power bus 13, the positive power line 12, and the first electrode electrically connected to the positive power line 12, and the positive voltage signal on each positive power input terminal It can be transmitted through the positive power bus 13 to the positive power line 12 that is closer to the positive power input terminal, thereby transmitting to the light-emitting element electrically connected to the positive power line 12, for example, the first positive power input terminal 14 and the The positive voltage signal on the three-positive power input terminal 16 can be transmitted through the positive power bus 13 to the light-emitting device that is electrically connected to the positive power line 12 on the left and right sides (the left and right sides of the placement position shown in Figures 1 to 4).
  • the positive voltage signal on the second positive power input terminal 15 can be transmitted through the positive power bus 13 to the positive power line 12 in the central area (the central area of the placement position shown in Figures 1 to 4).
  • the light-emitting element as a result, the path of the positive voltage signal transmitted from the positive power input terminal to the light-emitting element is shorter, so that the signal transmission line used to transmit the positive voltage signal to the light-emitting element is shorter and has a smaller impedance, which helps Ensure the uniformity of the brightness of the screen displayed by the array substrate.
  • the first positive power input terminal 14, the second positive power input terminal 15, and the third positive power input terminal 16 simultaneously transmit positive voltage signals to the light-emitting elements of all sub-pixels in the array substrate.
  • the first positive power access terminal 14 and the third positive power access terminal 16 are closer to the light-emitting elements on the left and right sides, and they are transmitted from the first positive power access terminal 14 and the third positive power access terminal 16 to
  • the positive voltage signals of the light-emitting elements on the left and right sides have a shorter path and smaller impedance.
  • the second positive power input terminal 15 is closer to the light-emitting elements in the central area, and is transmitted from the second positive power input terminal 15 to the central area.
  • the path of the positive voltage signal of the light-emitting element is shorter and the impedance is smaller.
  • each of the first negative power supply access terminal 19 and the third negative power supply access terminal 21 is configured to pass through the negative power supply line 17, the auxiliary electrode 18 and The second electrode transmits a negative voltage signal to the light-emitting element
  • the second negative power access terminal 20 is configured to transmit a negative voltage signal to the light-emitting element through the negative power auxiliary line 22, the auxiliary electrode 18, and the second electrode.
  • the negative voltage signals on the first negative power input terminal 19 and the third negative power input terminal 21 can be transmitted to the left and right sides through the negative power line 17 and the auxiliary electrode 18 (the placement positions shown in Figures 1 to 4)
  • the light-emitting elements on the left and right sides), the negative voltage signal on the second negative power input terminal 20 can be transmitted to the central area (the center of the placement position shown in Figures 1 to 4 through the negative power auxiliary line 22 and the auxiliary electrode 18). Area) of the light-emitting element, in this way, the negative voltage signal transmitted from the negative power input terminal to the light-emitting element has a shorter path, so that the signal transmission line used to transmit the negative voltage signal to the light-emitting element is shorter and has a smaller impedance. It helps to ensure the uniformity of the brightness of the picture displayed by the array substrate.
  • the first negative power supply terminal 19, the second negative power supply terminal 20 and the third negative power supply terminal 21 simultaneously transmit negative voltage signals to the light-emitting elements of all sub-pixels in the array substrate.
  • the first negative power input terminal 19 and the third negative power input terminal 21 are closer to the light-emitting elements on the left and right sides, which are transmitted from the first negative power input terminal 19 and the third negative power input terminal 21 to
  • the negative voltage signal of the light-emitting elements on the left and right sides has a shorter path and smaller impedance.
  • the second negative power input terminal 20 is closer to the light-emitting elements in the central area, and is transmitted from the second negative power input terminal 20 to the central area.
  • the negative voltage signal of the light-emitting element has a shorter path and a smaller impedance.
  • the array substrate provided by the embodiments of the present application includes a first positive power supply terminal, a second positive power supply terminal, a third positive power supply terminal, a first negative power supply terminal,
  • the second negative power supply terminal and the third negative power supply terminal, the second positive power supply terminal and the second negative power supply terminal are both located between the first positive power supply terminal and the third positive power supply terminal ,
  • Each positive power input terminal can transmit a positive voltage signal to the light-emitting element of the sub-pixel near it through the positive power bus and the positive power line
  • each negative power input terminal can transmit the positive voltage signal through the negative power line, the negative power auxiliary line and the auxiliary power line.
  • the electrode transmits a negative voltage signal to the light-emitting element of the sub-pixel close to it, so that the length of the signal transmission line that transmits the positive voltage signal to the light-emitting element and the signal transmission line that transmits the negative voltage signal to the light-emitting element are shorter and have lower impedance, which helps To ensure the uniformity of the brightness of the screen displayed by the array substrate.
  • the array substrate further includes:
  • the fourth positive power input terminal is located on the side of the positive power bus away from the display area and between the first positive power input terminal and the third positive power input terminal.
  • the positive power input terminal is electrically connected to the positive power bus;
  • the fourth positive power input terminal is configured to transmit a positive voltage signal to the light-emitting element through the positive power bus, the positive power line and the first electrode.
  • the array substrate further includes:
  • the fourth positive power input terminal 23 is located on the side of the positive power bus 13 away from the display area B1 and between the first positive power input terminal 14 and the third positive power input terminal 16.
  • the fourth positive power input The terminal 23 is electrically connected to the positive power bus 13; the fourth positive power access terminal 23 is configured to transmit a positive voltage signal to the light-emitting element through the positive power bus 13, the positive power line 12 and the first electrode.
  • the fourth positive power supply access terminal 23 is located between the second negative power supply access terminal 20 and the third positive power supply access terminal 16, and the fourth positive power supply access terminal 23 is connected to the second positive power supply access terminal 16.
  • the access terminal 15 may be symmetrical.
  • the positive voltage signals on the fourth positive power input terminal 23 and the second positive power input terminal 15 can be transmitted to the positive power line with the central area (the central area of the placement position shown in FIG. 2) through the positive power bus 13 12 Electrically connected light-emitting elements.
  • the path of the positive voltage signal transmitted from the positive power input terminal to the light-emitting element is shorter, so that the signal transmission line used to transmit the positive voltage signal to the light-emitting element is shorter and has a smaller impedance , which helps to ensure the uniformity of the brightness of the image displayed by the array substrate.
  • the first positive power access terminal 14, the second positive power access terminal 15, the third positive power access terminal 16, and the fourth positive power access terminal 23 are simultaneously connected to all sub-modules in the array substrate.
  • the light-emitting element of the pixel transmits a positive voltage signal, but the second positive power supply terminal 15 and the fourth positive power supply terminal 23 are closer to the light-emitting element in the central area, and the second positive power supply terminal 15 and the fourth positive power supply terminal 23 are closer to the light-emitting element in the central area.
  • the positive voltage signal transmitted from the positive power input terminal 23 to the light-emitting element in the central area passes through a short path and has a small impedance.
  • the array substrate further includes:
  • the fourth negative power input terminal is located on the side of the positive power bus away from the display area and between the first positive power input terminal and the third positive power input terminal.
  • the negative power input terminal is electrically connected to the negative power auxiliary line;
  • the fourth negative power input terminal is configured to transmit a negative voltage signal to the light-emitting element through the negative power auxiliary line, the auxiliary electrode, and the second electrode.
  • the array substrate further includes:
  • the fourth negative power supply connection terminal 24 is located on the side of the positive power supply bus 13 away from the display area B1 and between the first positive power supply connection terminal 14 and the third positive power supply connection terminal 16.
  • the fourth negative power supply connection The terminal 24 is electrically connected to the negative power auxiliary line 22; the fourth negative power access terminal 24 is configured to transmit a negative voltage signal to the light-emitting element through the negative power auxiliary line 22, the auxiliary electrode 18 and the second electrode.
  • the fourth negative power supply terminal 24 is located between the second negative power supply terminal 20 and the third positive power supply terminal 16, and the fourth negative power supply terminal 24 is connected to the second negative power supply terminal.
  • the access terminal 20 may be symmetrical.
  • the negative voltage signal on the fourth negative power input terminal 24 and the second negative power input terminal 20 can be transmitted to the central area through the negative power auxiliary line 22 and the auxiliary electrode 18 (the central area of the placement position shown in FIG. 3) In this way, the negative voltage signal transmitted from the negative power input terminal to the light-emitting element has a shorter path, so that the signal transmission line used to transmit the negative voltage signal to the light-emitting element is shorter and has a smaller impedance. To ensure the uniformity of the brightness of the screen displayed by the array substrate.
  • the first negative power supply access terminal 19, the second negative power supply access terminal 20, the third negative power supply access terminal 21 and the fourth negative power supply access terminal 24 are simultaneously connected to all the elements in the array substrate.
  • the light-emitting element of the pixel transmits a negative voltage signal, but the second negative power supply terminal 20 and the fourth negative power supply terminal 24 are closer to the light-emitting element in the central area, and the second negative power supply terminal 20 and the fourth negative power supply terminal 24
  • the negative voltage signal transmitted from the negative power input terminal 24 to the light-emitting element in the central area passes through a short path and has a small impedance.
  • the second negative power supply connection terminal is located between the second positive power supply connection terminal and the third positive power supply connection terminal, and the array substrate further includes:
  • the fourth positive power supply connection terminal and the fourth negative power supply connection terminal are located on the side of the positive power supply bus away from the display area, and the fourth positive power supply connection terminal is located at the second negative power supply connection terminal Between the third positive power supply terminal and the positive power supply bus, the fourth negative power supply terminal is located between the second negative power supply terminal and the fourth positive power supply terminal. Between the terminals and electrically connected to the negative power auxiliary line;
  • the fourth positive power access terminal is configured to transmit a positive voltage signal to the light-emitting element through the positive power bus, the positive power line, and the first electrode
  • the fourth negative power access terminal is It is configured to transmit a negative voltage signal to the light-emitting element through the negative power supply auxiliary line, the auxiliary electrode and the second electrode.
  • the array substrate further includes:
  • the fourth positive power access terminal 23 and the fourth negative power access terminal 24 are located on the side of the positive power bus 13 away from the display area B1, and the fourth positive power access terminal 23 is located at the second negative power access terminal 20 and The third positive power supply terminal 16 is electrically connected to the positive power supply bus 13.
  • the fourth negative power supply terminal 24 is located between the second negative power supply terminal 20 and the fourth positive power supply terminal 23 and is connected to the The negative power auxiliary line 22 is electrically connected; the fourth positive power input terminal 23 is configured to transmit a positive voltage signal to the light-emitting element through the positive power bus 13, the positive power line 12 and the first electrode, and the fourth negative power input terminal 24 is It is configured to transmit a negative voltage signal to the light-emitting element through the negative power supply auxiliary line 22, the auxiliary electrode 18, and the second electrode.
  • the fourth positive power input terminal 23 and the second positive power input terminal 15 may be symmetrical, and the fourth negative power input terminal 24 and the second negative power input terminal 20 may be symmetrical.
  • the positive voltage signals on the fourth positive power input terminal 23 and the second positive power input terminal 15 can be transmitted to the central area (the central area of the placement position shown in FIG. 4) through the positive power bus 13 and the positive power line 12
  • the negative voltage signals on the fourth negative power supply connection terminal 24 and the second negative power supply connection terminal 20 can be transmitted to the central area through the negative power supply auxiliary line 22 and the auxiliary electrode 18.
  • the path of the positive voltage signal transmitted from the positive power input terminal to the light-emitting element is shorter, and the path of the negative voltage signal transmitted from the negative power input terminal to the light-emitting element is relatively short. Short, so that the signal transmission line used to transmit positive voltage signals to the light-emitting element and the signal transmission line used to transmit negative voltage signals to the light-emitting element are shorter, and the impedance is small, which helps to ensure the uniformity of the brightness of the image displayed by the array substrate .
  • the first positive power access terminal 14, the second positive power access terminal 15, the third positive power access terminal 16, and the fourth positive power access terminal 23 are simultaneously connected to all the sub-modules in the array substrate.
  • the light-emitting element of the pixel transmits a positive voltage signal, and the first negative power supply terminal 19, the second negative power supply terminal 20, the third negative power supply terminal 21, and the fourth negative power supply terminal 24 are simultaneously transmitted to the array substrate.
  • the light-emitting elements of all sub-pixels transmit negative voltage signals, except that the second positive power supply terminal 15 and the fourth positive power supply terminal 23 are closer to the light-emitting elements in the central area, and the second positive power supply terminal 15
  • the positive voltage signal transmitted from the fourth positive power input terminal 23 to the light-emitting element in the central area has a shorter path and has a smaller impedance.
  • the second negative power input terminal 20 and the fourth negative power input terminal 24 are away from the central area.
  • the light-emitting element is closer, and the negative voltage signal transmitted from the second negative power input terminal 20 and the fourth negative power input terminal 24 to the light-emitting element in the central area passes through a shorter path and has a smaller impedance.
  • the light-emitting element is an organic light-emitting diode
  • the first electrode is an anode
  • the second electrode is a cathode
  • At least one of the plurality of sub-pixels includes a thin film transistor and a connecting electrode; the thin film transistor includes an active layer on the base substrate, and is located on the active layer.
  • the gate on the side away from the base substrate, and the source and drain on the side of the gate away from the base substrate.
  • the positive power bus includes a first sub-layer of a positive power bus and a second sub-layer of a positive power bus, and the first sub-layer of the positive power bus is electrically connected to the second sub-layer of the positive power bus;
  • the first sublayer of the positive power bus is located on the same layer as the source or the drain, and the second sublayer of the positive power bus is located on the same layer as the connection electrode.
  • the first sublayer of the positive power bus and the second sublayer of the positive power bus are electrically connected through a positive power bus via.
  • the negative power line includes a first sub-layer of a negative power line and a second sub-layer of a negative power line, and the first sub-layer of the negative power line is electrically connected to the second sub-layer of the negative power line;
  • the negative power auxiliary line includes a first sub-layer of a negative power auxiliary line and a second sub-layer of a negative power auxiliary line, and the first sub-layer of the negative power auxiliary line is electrically connected to the second sub-layer of the negative power auxiliary line;
  • the first sublayer of the negative power supply line and the first sublayer of the negative power supply auxiliary line are both located on the same layer as the source or the drain, and the second sublayer of the negative power supply line and the negative power supply auxiliary The second sub-layers of the wires are all located on the same layer as the connecting electrodes.
  • the first sub-layer of the negative power line and the second sub-layer of the negative power line are electrically connected through a negative power line via, and the first sub-layer of the negative power auxiliary line is connected to the second sub-layer of the negative power auxiliary line.
  • the two sub-layers are electrically connected through the negative power auxiliary line via.
  • FIG. 5 shows a cross-sectional view of the aa part, bb part, cc part, and ee part of the array substrate shown in any one of FIGS.
  • At least one includes a thin film transistor 110 and a connection electrode 111;
  • the thin film transistor 110 includes an active layer 1101 located on the base substrate 10, a gate 1102 located on the side of the active layer 1101 away from the base substrate 10, and a gate 1102 located far away from the base substrate 10.
  • the source electrode 1103 and the drain electrode 1104 on the side of the base substrate 10, and the source electrode 1103 and the drain electrode 1104 may be located in the same layer.
  • the positive power bus 13 includes a positive power bus first sublayer 131 and a positive power bus second sublayer 132.
  • the positive power bus first sublayer 131 and the positive power bus second sublayer 132 pass through the positive power bus vias (not shown in FIG. 5). Mark) electrical connection; the positive power bus first sub-layer 131 and the source electrode 1103 or the drain electrode 1104 are located on the same layer, and the positive power bus second sub-layer 132 and the connection electrode 111 are located on the same layer.
  • the number of positive power bus vias may be multiple, and the first sublayer 131 of the positive power bus and the second sublayer 132 of the positive power bus are electrically connected through multiple positive power bus vias to ensure the reliability of the connection.
  • the negative power line 17 includes a negative power line first sub-layer 171 and a negative power line second sub-layer 172.
  • the negative power line first sub-layer 171 and the negative power line second sub-layer 172 pass through the negative power line via ( Figure 5) Not shown) electrical connection;
  • the negative power auxiliary line 22 includes a negative power auxiliary line first sub-layer 221 and a negative power auxiliary line second sub-layer 222, the negative power auxiliary line first sub-layer 221 and the negative power auxiliary line second sub-layer
  • the layer 222 is electrically connected through the negative power auxiliary line via;
  • the first sub-layer 171 of the negative power line and the first sub-layer 221 of the negative power line are located on the same layer as the source electrode 1103 or the drain electrode 1104, and the second sub-layer of the negative power line
  • Both the 172 and the second sub-layer 222 of the negative power supply auxiliary line are located on the same layer as the connection electrode 111.
  • the number of negative power line vias and the number of negative power auxiliary line vias may both be multiple.
  • the first sub-layer 171 of the negative power line and the second sub-layer 172 of the negative power line pass through multiple negative power line vias.
  • the first sub-layer 221 of the negative power auxiliary line and the second sub-layer 222 of the negative power auxiliary line are electrically connected through a plurality of negative power auxiliary line vias to ensure the reliability of the connection.
  • the auxiliary electrode is located on a side of the negative power supply line away from the base substrate, and the auxiliary electrode and the negative power supply auxiliary line are electrically connected through a negative power supply auxiliary via hole .
  • the auxiliary electrode 18 is located on the side of the negative power supply line 17 away from the base substrate 10, and the auxiliary electrode 18 and the negative power supply auxiliary line 22 are electrically connected through a negative power supply auxiliary via.
  • the auxiliary electrode 18 and the second sub-layer 222 of the negative power supply auxiliary line are electrically connected through a negative power supply auxiliary via.
  • the number of negative power auxiliary vias may be multiple, and the auxiliary electrode 18 and the second sub-layer 222 of the negative power auxiliary line are electrically connected through multiple negative power auxiliary vias to ensure the reliability of the connection.
  • the auxiliary electrode is located on a side of the negative power supply line away from the base substrate, and the auxiliary electrode and the negative power supply line are electrically connected through a negative power supply auxiliary via.
  • the auxiliary electrode 18 is located on the side of the negative power supply line 17 away from the base substrate 10, and the auxiliary electrode 18 and the negative power supply line 17 are electrically connected through the negative power supply auxiliary via.
  • the auxiliary electrode 18 and the second sub-layer 172 of the negative power supply line are electrically connected through a negative power supply auxiliary via.
  • the number of negative power auxiliary vias may be multiple, and the auxiliary electrode 18 and the second sub-layer 172 of the negative power line are electrically connected through multiple negative power auxiliary vias to ensure the reliability of the connection.
  • the negative power auxiliary via that connects the auxiliary electrode 18 and the second sub-layer 222 of the negative power auxiliary line is an overpass located on the insulating layer between the auxiliary electrode 18 and the second sub-layer 222 of the negative power auxiliary line.
  • the negative power auxiliary via connecting the auxiliary electrode 18 and the second sub-layer 172 of the negative power line is a via on the insulating layer between the auxiliary electrode 18 and the second sub-layer 172 of the negative power line, connecting the auxiliary electrode 18 and
  • the negative power auxiliary via hole of the second sub-layer 222 of the negative power auxiliary line and the negative power auxiliary via connecting the auxiliary electrode 18 and the second sub-layer 172 of the negative power line are different via holes.
  • At least one of the plurality of sub-pixels includes a thin film transistor;
  • the thin film transistor includes an active layer located on the base substrate, and the active layer is located far away from the The gate on one side of the base substrate, and the source and drain on the side of the gate far away from the base substrate;
  • the first positive power supply access terminal, the second positive power supply access terminal, and The third positive power supply access terminal is located on the same layer as the source or the drain;
  • the access terminals are located on the same layer as the source electrode or the drain electrode.
  • FIG. 6 shows a cross-sectional view of the aa portion and the ff portion of the array substrate shown in FIG. 1.
  • the thin film transistor 110 includes The active layer 1101 on the base substrate 10, the gate 1102 on the side of the active layer 1101 away from the base substrate 10, and the source 1103 and the drain 1104 on the side of the gate 1102 away from the base substrate 10,
  • the first positive power supply terminal 14, the second positive power supply terminal 15 and the third positive power supply terminal 16 are all located on the same layer as the source 1103 or the drain 1104.
  • the first negative power supply terminal 19, the second The negative power access terminal 20 and the third negative power access terminal 21 are both located on the same layer as the source electrode 1103 or the drain electrode 1104.
  • the array substrate further includes a fourth positive power supply connection terminal and/or a fourth negative power supply connection terminal
  • the fourth positive power supply connection terminal and/or the fourth negative power supply connection terminal are located on the same layer as the source electrode or the drain electrode.
  • FIG. 7 shows a cross-sectional view of the aa part and the ff part of the array substrate shown in FIG. 2.
  • the first positive power supply terminal 14 and the second positive power supply terminal 15 The third positive power access terminal 16 and the fourth positive power access terminal 23 are located on the same layer with the source 1103 or the drain 1104, the first negative power access terminal 19, the second negative power access terminal 20 and the first The three negative power input terminals 21 are all located on the same layer as the source electrode 1103 or the drain electrode 1104.
  • FIG. 8 shows a cross-sectional view of the aa part and the ff part of the array substrate shown in FIG. 3.
  • the first positive power input terminal 14 and the second positive power input terminal 15 And the third positive power access terminal 16 are located on the same layer as the source 1103 or the drain 1104, the first negative power access terminal 19, the second negative power access terminal 20, the third negative power access terminal 21 and the second
  • the four negative power input terminals 24 are all located on the same layer as the source electrode 1103 or the drain electrode 1104.
  • FIG. 9 shows a cross-sectional view of the aa part and the ff part of the array substrate shown in FIG. 4.
  • the first positive power input terminal 14 and the second positive power input terminal 15 The third positive power access terminal 16 and the fourth positive power access terminal 23 are located on the same layer as the source 1103 or the drain 1104, the first negative power access terminal 19, the second negative power access terminal 20, and the The three negative power access terminals 21 and the fourth negative power access terminal 24 are both located on the same layer as the source electrode 1103 or the drain electrode 1104.
  • the negative power auxiliary line includes a first sub-layer of a negative power auxiliary line and a second sub-layer of a negative power auxiliary line, and the first sub-layer of the negative power auxiliary line is connected to the negative power auxiliary line.
  • the second sub-layer of the auxiliary power line is electrically connected; the second negative power access terminal, the fourth negative power access terminal, and the first sub-layer of the negative power auxiliary line form an integrated structure.
  • the negative power supply auxiliary line 22 includes a negative power supply auxiliary line.
  • the sub-layer 221 and the second sub-layer 222 of the negative power auxiliary line, the first sub-layer 221 of the negative power auxiliary line and the second sub-layer 222 of the negative power auxiliary line are electrically connected through the negative power auxiliary line via (not shown in FIG. 10) ;
  • the second negative power access terminal 20, the fourth negative power access terminal 24 and the first sub-layer 221 of the negative power auxiliary line are integrated.
  • FIG. 10 is taken as an example to illustrate that the array substrate includes both the second negative power input terminal 20 and the fourth negative power input terminal 24.
  • the array substrate only includes the second negative power input terminal 20 or the fourth negative power input terminal 24, In the case of four negative power supply terminals 24, the second negative power supply terminal 20 or the fourth negative power supply terminal 24 and the first sub-layer 221 of the negative power supply auxiliary line are integrated.
  • the array substrate includes the second negative power supply When the access terminal 20 does not include the fourth negative power access terminal 24, the second negative power access terminal 20 and the first sub-layer 221 of the negative power auxiliary line are integrated, and when the array substrate includes the fourth negative power access terminal When 24 does not include the second negative power access terminal 20, the fourth negative power access terminal 24 and the first sub-layer 221 of the negative power auxiliary line are integrated.
  • the array substrate further includes: a circuit board, which is located at the first positive power supply terminal, the second positive power supply terminal, and the third positive power supply terminal. Terminal, the fourth positive power supply terminal, the first negative power supply terminal, the second negative power supply terminal, the third negative power supply terminal, and the fourth negative power supply terminal The side far away from the display area, the first positive power access terminal, the second positive power access terminal, the third positive power access terminal, the fourth positive power access terminal, The first negative power supply access terminal, the second negative power supply access terminal, the third negative power supply access terminal, and the fourth negative power supply access terminal are respectively electrically connected to the circuit board.
  • the array substrate further includes: a circuit board 25, which is located at the first positive power supply terminal 14, the second positive power supply terminal 15, the third positive power supply terminal 16, and the first negative power supply terminal.
  • the power access terminal 19, the second negative power access terminal 20, and the third negative power access terminal 21 are away from the side of the display area B1, the first positive power access terminal 14, the second positive power access terminal 15, and the The three positive power supply terminals 16, the first negative power supply terminals 19, the second negative power supply terminals 20, and the third negative power supply terminals 21 are electrically connected to the circuit board 25, respectively.
  • the array substrate further includes: a circuit board 25, which is located at the first positive power supply terminal 14, the second positive power supply terminal 15, the third positive power supply terminal 16, and the fourth positive power supply terminal.
  • the power supply terminal 23, the first negative power supply terminal 19, the second negative power supply terminal 20, and the third negative power supply terminal 21 are far away from the display area B1.
  • the first positive power supply terminal 14 and the third negative power supply terminal 21 Two positive power supply terminals 15, a third positive power supply terminal 16, a fourth positive power supply terminal 23, a first negative power supply terminal 19, a second negative power supply terminal 20, and a third negative power supply terminal
  • the terminals 21 are electrically connected to the circuit board 25 respectively.
  • the array substrate further includes: a circuit board 25, which is located at the first positive power supply terminal 14, the second positive power supply terminal 15, the third positive power supply terminal 16, and the first negative power supply terminal.
  • the power supply terminal 19, the second negative power supply terminal 20, the third negative power supply terminal 21, and the fourth negative power supply terminal 24 are away from the side of the display area B1.
  • the first positive power supply terminal 14, the first positive power supply terminal 14 and the fourth negative power supply terminal 24 are far away from the display area B1.
  • the terminals 24 are electrically connected to the circuit board 25 respectively.
  • the array substrate further includes: a circuit board 25, which is located at the first positive power supply terminal 14, the second positive power supply terminal 15, the third positive power supply terminal 16, and the fourth positive power supply terminal.
  • the power input terminal 23, the first negative power input terminal 19, the second negative power input terminal 20, the third negative power input terminal 21 and the fourth negative power input terminal 24 are far away from the side of the display area B1.
  • the terminal 20, the third negative power input terminal 21, and the fourth negative power input terminal 24 are electrically connected to the circuit board 25, respectively.
  • circuit board 25 described in the embodiment of the present application may be a flexible circuit board (English: Flexible Printed Circuit; abbreviated as FPC).
  • At least one of the plurality of sub-pixels 11 includes a thin film transistor 110, a connection electrode 111, a light emitting element 112 and a storage capacitor 113.
  • the thin film transistor 110 includes an active layer 1101 located on a base substrate 10, a first insulating layer 1105 located on the side of the active layer 1101 away from the base substrate 10, and a gate located on the side of the first insulating layer 1105 away from the base substrate 10.
  • Pole 1102 the second insulating layer 1106 on the side of the gate 1102 away from the base substrate 10, the third insulating layer 1107 on the side of the second insulating layer 1106 away from the base substrate 10, and the third insulating layer 1107 away from the substrate
  • the source electrode 1103 and the drain electrode 1104 on the side of the substrate 10.
  • the connecting electrode 111 is located on the side of the thin film transistor 110 away from the base substrate 10, and the connecting electrode 111 is electrically connected to the drain electrode 1104.
  • the light emitting element 112 is located on the side of the connecting electrode 111 away from the base substrate.
  • the first electrode 1121, the light emitting layer 1122, and the second electrode 1123 are sequentially stacked in the direction of the substrate 10, and the first electrode 1121 is electrically connected to the connection electrode 111.
  • the storage capacitor 113 includes a first electrode plate 1131 and a second electrode plate 1132.
  • the first electrode plate 1131 and the gate electrode 1101 are located on the same layer, and the second electrode plate 1132 is located between the second insulating layer 1106 and the third insulating layer 1107.
  • At least one of the plurality of sub-pixels 11 further includes a buffer layer 114 located between the active layer 1101 and the base substrate 10, and is located at the source in a direction away from the base substrate 10.
  • the passivation layer 115 and the first flat layer 116 between 1103 and the connection electrode 111, and the second flat layer 117 between the connection electrode 111 and the first electrode 1121.
  • the passivation layer 115 and the first flat layer 116 have via holes
  • the connection electrode 111 is electrically connected to the drain 1104 through the via holes on the passivation layer 115 and the first flat layer 116
  • the second flat layer 117 has a via hole.
  • An electrode 1121 is electrically connected to the connection electrode 111 through a via hole on the second flat layer 117.
  • the array substrate further includes: a pixel defining layer 26 located on the side of the second flat layer 117 away from the base substrate 10, and the pixel defining layer 26 includes a structure defined by a barrier wall.
  • the light-emitting element 112 is located in the opening area of the pixel defining layer 26; the packaging structure 27 located on the side of the light-emitting element 112 away from the base substrate is used to package the light-emitting element 112.
  • the flat layer 115, the passivation layer 115, the first flat layer 116, and the second flat layer 117 may be the first insulating layer 1105, the second insulating layer 1106, the third insulating layer 1107, the buffer layer 114, and the flat layer at the aa portion 115, the passivation layer 115, the first flat layer 116, and the second flat layer 117 respectively extend to a portion of the peripheral region B2.
  • the array substrate may also include other structures.
  • the array substrate further includes a plurality of gate lines with the same extending direction, a plurality of data lines with the same extending direction, the plurality of gate lines and the plurality of data lines intersect to define a plurality of pixel regions, and the plurality of sub-pixels are located in a one-to-one correspondence.
  • the array substrate may also include a flip-chip film (English: Chip On Film; abbreviation: COF) and an integrated circuit (English: Integrated Circuit; abbreviation: IC), etc. The embodiments of the present application will not Repeat it again.
  • the array substrate provided by the embodiments of the present application includes a first positive power supply terminal, a second positive power supply terminal, a third positive power supply terminal, a first negative power supply terminal,
  • the second negative power supply terminal and the third negative power supply terminal, the second positive power supply terminal and the second negative power supply terminal are both located between the first positive power supply terminal and the third positive power supply terminal ,
  • Each positive power input terminal can transmit a positive voltage signal to the light-emitting element of the sub-pixel near it through the positive power bus and the positive power line
  • each negative power input terminal can transmit the positive voltage signal through the negative power line, the negative power auxiliary line and the auxiliary power line.
  • the electrode transmits a negative voltage signal to the light-emitting element of the sub-pixel close to it, so that the length of the signal transmission line that transmits the positive voltage signal to the light-emitting element and the signal transmission line that transmits the negative voltage signal to the light-emitting element are shorter and have lower impedance, which helps To ensure the uniformity of the brightness of the screen displayed by the array substrate.
  • an embodiment of the present application further provides a display device, which includes any of the above-mentioned array substrates.
  • the display device in the embodiment of the present application may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • the term "same layer” refers to the relationship between layers simultaneously formed in the same step.
  • the second sub-layer 222 of the negative power supply auxiliary line and the connection electrode 111 are formed as a result of one or more steps of the same patterning performed in the same layer of material, they are located in the same layer; in another example The second sub-layer 222 of the negative power auxiliary line and the connection electrode 111 can be formed in the same layer by simultaneously performing the steps of forming the second sub-layer 222 of the negative power auxiliary line and forming the connection electrode 111; “the same layer” does not always mean The layer thickness or layer height in the cross-sectional view is the same.
  • the terms “first”, “second”, “third”, “fourth” and similar words in the embodiments of the present application do not denote any order, quantity or importance, but are only used to distinguish different components.
  • the “electrical connection” of two conductors refers to the direct or indirect electrical connection between the two conductors, and the two conductors can transmit electrical signals.
  • the term “at least one” refers to one or more, and “multiple” refers to two or more.

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Abstract

一种阵列基板及显示装置。阵列基板包括：子像素（11），位于显示区域（B1）且包括发光元件，发光元件包括第一电极、发光层和第二电极；正电源线（12），位于显示区域（B1）且与第一电极电连接；正电源总线（13），位于周边区域（B2）且与正电源线（12）电连接；三个正电源接入端（14，15，16），位于正电源总线（13）远离显示区域（B1）的一侧且分别与正电源总线（13）电连接；负电源线（17），位于周边区域（B2）；辅助电极（18），位于周边区域（B2）且分别与负电源线（17）和第二电极电连接；三个负电源接入端（19，20，21），位于正电源总线（13）远离显示区域（B1）的一侧且分别与负电源线（17）电连接；负电源辅助线（22），位于周边区域（B2）且分别与负电源接入端（20）和辅助电极（18）电连接。有助于保证阵列基板所显示的画面亮度的均匀性。

Description

阵列基板及显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种阵列基板及显示装置。
背景技术
随着阵列基板尺寸的增大，在阵列基板的显示区域之外的信号传输线的长度和负载也随之增大。在用于传输正电压信号(VDD)的信号传输线或用于传输负电压信号(VSS)的信号传输线的阻抗过大时，阵列基板所显示的画面容易出现亮度不均的情况。
发明内容
本申请实施例提供一种阵列基板及显示装置，本申请的技术方案如下：
一方面，提供一种阵列基板，包括：
衬底基板，包括显示区域和围绕所述显示区域的周边区域，所述显示区域包括第一边界、第二边界、第三边界和第四边界；
多个子像素，位于所述显示区域中，所述多个子像素中的至少一个包括发光元件，所述发光元件包括依次层叠的第一电极、发光层和第二电极；
多条正电源线，位于所述显示区域中且与所述第一电极电连接；
正电源总线，位于所述周边区域中且沿所述第一边界分布，所述正电源总线与所述多条正电源线电连接；
第一正电源接入端、第二正电源接入端和第三正电源接入端，位于所述正电源总线远离所述显示区域的一侧，所述第二正电源接入端位于所述第一正电源接入端与所述第三正电源接入端之间，所述第一正电源接入端、所述第二正电源接入端和所述第三正电源接入端分别与所述正电源总线电连接；
负电源线，位于所述周边区域中且围绕所述第二边界、所述第三边界和所述第四边界；
辅助电极，位于所述周边区域中且围绕所述第一边界、所述第二边界、所述第三边界和所述第四边界，所述辅助电极分别与所述负电源线和所述第二电 极电连接；
第一负电源接入端、第二负电源接入端和第三负电源接入端，位于所述正电源总线远离所述显示区域的一侧，所述第一负电源接入端位于所述第一正电源接入端远离所述第二正电源接入端的一侧，所述第二负电源接入端位于所述第一正电源接入端与所述第三正电源接入端之间，所述第三负电源接入端位于所述第三正电源接入端远离所述第二正电源接入端的一侧，所述第一负电源接入端和所述第三负电源接入端分别与所述负电源线电连接；
负电源辅助线，位于所述周边区域中，位于所述第一正电源接入端与所述第三正电源接入端之间且位于所述正电源总线与所述第二负电源接入端之间，所述负电源辅助线分别与所述第二负电源接入端和所述辅助电极电连接。
可选地，所述第一正电源接入端、所述第二正电源接入端和所述第三正电源接入端被配置为通过所述正电源总线、所述正电源线和所述第一电极向所述发光元件传输正电压信号；
所述第一负电源接入端、所述第二负电源接入端和所述第三负电源接入端被配置为通过所述负电源线、所述负电源辅助线、所述辅助电极和所述第二电极向所述发光元件传输负电压信号。
可选地，所述阵列基板还包括：
第四正电源接入端，位于所述正电源总线远离所述显示区域的一侧且位于所述第一正电源接入端与所述第三正电源接入端之间，所述第四正电源接入端与所述正电源总线电连接；
所述第四正电源接入端被配置为通过所述正电源总线、所述正电源线和所述第一电极向所述发光元件传输正电压信号。
可选地，所述阵列基板还包括：
第四负电源接入端，位于所述正电源总线远离所述显示区域的一侧且位于所述第一正电源接入端与所述第三正电源接入端之间，所述第四负电源接入端与所述负电源辅助线电连接；
所述第四负电源接入端被配置为通过所述负电源辅助线、所述辅助电极和所述第二电极向所述发光元件传输负电压信号。
可选地，所述第二负电源接入端位于所述第二正电源接入端与所述第三正电源接入端之间，所述阵列基板还包括：
第四正电源接入端和第四负电源接入端，位于所述正电源总线远离所述显 示区域的一侧，所述第四正电源接入端位于所述第二负电源接入端与所述第三正电源接入端之间且与所述正电源总线电连接，所述第四负电源接入端位于所述第二负电源接入端与所述第四正电源接入端之间且与所述负电源辅助线电连接；
所述第四正电源接入端被配置为通过所述正电源总线、所述正电源线和所述第一电极向所述发光元件传输正电压信号，所述第四负电源接入端被配置为通过所述负电源辅助线、所述辅助电极和所述第二电极向所述发光元件传输负电压信号。
可选地，所述多个子像素中的至少一个包括薄膜晶体管和连接电极；
所述薄膜晶体管包括位于所述衬底基板上的有源层，位于所述有源层远离所述衬底基板一侧的栅极，以及位于所述栅极远离所述衬底基板一侧的源极和漏极。
可选地，所述正电源总线包括正电源总线第一子层和正电源总线第二子层，所述正电源总线第一子层与所述正电源总线第二子层电连接；
所述正电源总线第一子层与所述源极或所述漏极位于同一层，所述正电源总线第二子层与所述连接电极位于同一层。
可选地，所述正电源总线第一子层与所述正电源总线第二子层通过正电源总线过孔电连接。
可选地，所述负电源线包括负电源线第一子层和负电源线第二子层，所述负电源线第一子层与所述负电源线第二子层电连接；
所述负电源辅助线包括负电源辅助线第一子层和负电源辅助线第二子层，所述负电源辅助线第一子层与所述负电源辅助线第二子层电连接；
所述负电源线第一子层和所述负电源辅助线第一子层均与所述源极或所述漏极位于同一层，所述负电源线第二子层和所述负电源辅助线第二子层均与所述连接电极位于同一层。
可选地，所述负电源线第一子层与所述负电源线第二子层通过负电源线过孔电连接，所述负电源辅助线第一子层与所述负电源辅助线第二子层通过负电源辅助线过孔电连接。
可选地，所述多个子像素中的至少一个包括薄膜晶体管；
所述薄膜晶体管包括位于所述衬底基板上的有源层，位于所述有源层远离所述衬底基板一侧的栅极，以及位于所述栅极远离所述衬底基板一侧的源极和 漏极；
所述第一正电源接入端、所述第二正电源接入端、所述第三正电源接入端和所述第四正电源接入端均与所述源极或所述漏极位于同一层。
可选地，所述多个子像素中的至少一个包括薄膜晶体管；
所述薄膜晶体管包括位于所述衬底基板上的有源层，位于所述有源层远离所述衬底基板一侧的栅极，以及位于所述栅极远离所述衬底基板一侧的源极和漏极；
所述第一负电源接入端、所述第二负电源接入端、所述第三负电源接入端和所述第四负电源接入端均与所述源极或所述漏极位于同一层。
可选地，所述负电源辅助线包括负电源辅助线第一子层和负电源辅助线第二子层，所述负电源辅助线第一子层与所述负电源辅助线第二子层电连接；
所述第二负电源接入端、所述第四负电源接入端和所述负电源辅助线第一子层为一体结构。
可选地，所述阵列基板还包括：
电路板，位于所述第一正电源接入端、所述第二正电源接入端、所述第三正电源接入端、所述第四正电源接入端、所述第一负电源接入端、所述第二负电源接入端、所述第三负电源接入端和所述第四负电源接入端远离所述显示区域的一侧，所述第一正电源接入端、所述第二正电源接入端、所述第三正电源接入端、所述第四正电源接入端、所述第一负电源接入端、所述第二负电源接入端、所述第三负电源接入端和所述第四负电源接入端分别与所述电路板电连接。
可选地，所述辅助电极位于所述负电源线远离所述衬底基板的一侧，所述辅助电极与所述负电源辅助线通过负电源辅助过孔电连接。
可选地，所述发光元件为有机发光二极管，所述第一电极为阳极，所述第二电极为阴极。
另一方面，提供一种显示装置包括上述一方面中的任意一种阵列基板。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下， 还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种阵列基板的正视图；
图2是本申请实施例提供的另一种阵列基板的正视图；
图3是本申请实施例提供的再一种阵列基板的正视图；
图4是本申请实施例提供的又一种阵列基板的正视图；
图5是图1至图4任一所示的阵列基板的a-a部位、b-b部位、c-c部位和e-e部位的截面图；
图6是图1所示的阵列基板的a-a部位和f-f部位的截面图；
图7是图2所示的阵列基板的a-a部位和f-f部位的截面图；
图8是图3所示的阵列基板的a-a部位和f-f部位的截面图；
图9是图4所示的阵列基板的a-a部位和f-f部位的截面图；
图10是图3或图4所示的阵列基板的a-a部位和g-g部位的截面图。
具体实施方式
为使本申请的原理、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
本申请实施例提供了一种阵列基板，该阵列基板中，用于向子像素传输正电压信号的信号传输线和用于向子像素传输负电压信号的信号传输线的阻抗均较小，有助于改善阵列基板所显示的画面容易出现亮度不均的情况，保证阵列基板所显示的画面亮度的均匀性。本申请的详细方案如下：
在本申请实施例中，所述阵列基板，包括：
衬底基板，包括显示区域和围绕所述显示区域的周边区域，所述显示区域包括第一边界、第二边界、第三边界和第四边界；
多个子像素，位于所述显示区域中，所述多个子像素中的至少一个包括发光元件，所述发光元件包括依次层叠的第一电极、发光层和第二电极；
多条正电源线，位于所述显示区域中且与所述第一电极电连接；
正电源总线，位于所述周边区域中且沿所述第一边界分布，所述正电源总线与所述多条正电源线电连接；
第一正电源接入端、第二正电源接入端和第三正电源接入端，位于所述正电源总线远离所述显示区域的一侧，所述第二正电源接入端位于所述第一正电源接入端与所述第三正电源接入端之间，所述第一正电源接入端、所述第二正 电源接入端和所述第三正电源接入端分别与所述正电源总线电连接；
负电源线，位于所述周边区域中且围绕所述第二边界、所述第三边界和所述第四边界；
辅助电极，位于所述周边区域中且围绕所述第一边界、所述第二边界、所述第三边界和所述第四边界，所述辅助电极分别与所述负电源线和所述第二电极电连接；
第一负电源接入端、第二负电源接入端和第三负电源接入端，位于所述正电源总线远离所述显示区域的一侧，所述第一负电源接入端位于所述第一正电源接入端远离所述第二正电源接入端的一侧，所述第二负电源接入端位于所述第一正电源接入端与所述第三正电源接入端之间，所述第三负电源接入端位于所述第三正电源接入端远离所述第二正电源接入端的一侧，所述第一负电源接入端和所述第三负电源接入端分别与所述负电源线电连接；
负电源辅助线，位于所述周边区域中，位于所述第一正电源接入端与所述第三正电源接入端之间且位于所述正电源总线与所述第二负电源接入端之间，所述负电源辅助线分别与所述第二负电源接入端和所述辅助电极电连接。
可选地，所述第一正电源接入端、所述第二正电源接入端和所述第三正电源接入端被配置为通过所述正电源总线、所述正电源线和所述第一电极向所述发光元件传输正电压信号；所述第一负电源接入端、所述第二负电源接入端和所述第三负电源接入端被配置为通过所述负电源线、所述负电源辅助线、所述辅助电极和所述第二电极向所述发光元件传输负电压信号。
示例地，请参考图1至图4，图1至图4示出了本申请实施例提供的四种阵列基板的正视图，参见图1至图4，该阵列基板包括：
衬底基板10，包括显示区域B1和围绕显示区域B1的周边区域B2，显示区域B1包括第一边界(图1至图4中均未标出)、第二边界(图1至图4中均未标出)、第三边界(图1至图4中均未标出)和第四边界(图1至图4中均未标出)；本申请实施例以周边区域B2围绕在显示区域B1的四周为例进行介绍；
多个子像素11，位于显示区域B1中，该多个子像素11中的至少一个包括发光元件(图1至图4中均未示出)，该发光元件包括依次层叠的第一电极(图1至图4中均未示出)、发光层(图1至图4中均未示出)和第二电极(图1至图4中均未示出)；该多个子像素11可以发光，从而实现显示功能；
多条正电源线12，位于显示区域B1中且与发光元件的第一电极电连接；
正电源总线13，位于周边区域B2中且沿显示区域B1的第一边界分布，该正电源总线13与上述多条正电源线电12电连接；
第一正电源接入端14、第二正电源接入端15和第三正电源接入端16，位于正电源总线13远离显示区域B1的一侧，第二正电源接入端15位于第一正电源接入端14与第三正电源接入端16之间，第一正电源接入端14、第二正电源接入端15和第三正电源接入端16分别与正电源总线13电连接；
负电源线17，位于周边区域B2中且围绕显示区域B1的第二边界、第三边界和第四边界；
辅助电极18，位于周边区域B2中且围绕显示区域B1的第一边界、第二边界、第三边界和第四边界，该辅助电极18分别与负电源线17和发光元件的第二电极电连接；
第一负电源接入端19、第二负电源接入端20和第三负电源接入端21，位于正电源总线13远离显示区域B1的一侧，第一负电源接入端19位于第一正电源接入端14远离第二正电源接入端15的一侧，第二负电源接入端20位于第一正电源接入端14与第三正电源接入端16之间，第三负电源接入端21位于第三正电源接入端16远离第二正电源接入端15的一侧，第一负电源接入端19和第三负电源接入端21分别与负电源线17电连接；本申请实施例以第二负电源接入端20位于第二正电源接入端15与第三正电源接入端16之间为例进行介绍；
负电源辅助线22，位于周边区域B2中，位于第一正电源接入端14与第三正电源接入端16之间且位于正电源总线13与第二负电源接入端20之间，该负电源辅助线22分别与第二负电源接入端20和辅助电极18电连接。
可选地，第一正电源接入端14、第二正电源接入端15和第三正电源接入端16被配置为通过正电源总线13、正电源线12和第一电极向发光元件传输正电压信号；第一负电源接入端19、第二负电源接入端20和第三负电源接入端21被配置为通过负电源线17、负电源辅助线22、辅助电极18和第二电极向发光元件传输负电压信号。
例如，如图1至图4所示，在第一正电源接入端14、第二正电源接入端15和第三正电源接入端16中，每个正电源接入端被配置为通过正电源总线13、正电源线12以及与该正电源线12电连接的第一电极，向该第一电极所在的发光元件传输正电压信号，每个正电源接入端上的正电压信号可以通过正电源总线 13传输至距离该正电源接入端较近的正电源线12，从而传输至与该正电源线12电连接的发光元件，例如，第一正电源接入端14和第三正电源接入端16上的正电压信号可以通过正电源总线13传输至与左右两侧(图1至图4所示的摆放位置的左右两侧)的正电源线12电连接的发光元件，第二正电源接入端15上的正电压信号可以通过正电源总线13传输至与中央区域(图1至图4所示的摆放位置的中央区域)的正电源线12电连接的发光元件，这样一来，由正电源接入端传输至发光元件的正电压信号经过的路径较短，从而用于向发光元件传输正电压信号的信号传输线较短，阻抗较小，有助于保证阵列基板所显示的画面亮度的均匀性。
本领域技术人员容易理解，第一正电源接入端14、第二正电源接入端15和第三正电源接入端16是同时向阵列基板中所有子像素的发光元件传输正电压信号的，只不过第一正电源接入端14和第三正电源接入端16距离左右两侧的发光元件较近，由第一正电源接入端14和第三正电源接入端16传输至左右两侧的发光元件的正电压信号经过的路径较短，阻抗较小，第二正电源接入端15距离中央区域的发光元件较近，由第二正电源接入端15传输至中央区域的发光元件的正电压信号经过的路径较短，阻抗较小。
例如，如图1至图4所示，第一负电源接入端19和第三负电源接入端21中的每个负电源接入端被配置为通过负电源线17、辅助电极18和第二电极向发光元件传输负电压信号，第二负电源接入端20被配置为通过负电源辅助线22、辅助电极18和第二电极向发光元件传输负电压信号。第一负电源接入端19和第三负电源接入端21上的负电压信号可以通过负电源线17和辅助电极18传输至左右两侧(图1至图4所示的摆放位置的左右两侧)的发光元件，第二负电源接入端20上的负电压信号可以通过负电源辅助线22和辅助电极18传输至中央区域(图1至图4所示的摆放位置的中央区域)的发光元件，这样一来，由负电源接入端传输至发光元件的负电压信号经过的路径较短，从而用于向发光元件传输负电压信号的信号传输线较短，阻抗较小，有助于保证阵列基板所显示的画面亮度的均匀性。
本领域技术人员容易理解，第一负电源接入端19、第二负电源接入端20和第三负电源接入端21是同时向阵列基板中所有子像素的发光元件传输负电压信号的，只不过第一负电源接入端19和第三负电源接入端21距离左右两侧的发光元件较近，由第一负电源接入端19和第三负电源接入端21传输至左右两侧 的发光元件的负电压信号经过的路径较短，阻抗较小，第二负电源接入端20距离中央区域的发光元件较近，由第二负电源接入端20传输至中央区域的发光元件的负电压信号经过的路径较短，阻抗较小。
综上所述，本申请实施例提供的阵列基板，该阵列基板包括第一正电源接入端、第二正电源接入端、第三正电源接入端、第一负电源接入端、第二负电源接入端和第三负电源接入端，第二正电源接入端和第二负电源接入端均位于第一正电源接入端与第三正电源接入端之间，每个正电源接入端可以通过正电源总线和正电源线向与其较近的子像素的发光元件传输正电压信号，每个负电源接入端可以通过负电源线、负电源辅助线和辅助电极向与其较近的子像素的发光元件传输负电压信号，从而向发光元件传输正电压信号的信号传输线的长度以及向发光元件传输负电压信号的信号传输线均较短，阻抗较小，有助于保证阵列基板所显示的画面亮度的均匀性。
可选地，在本申请实施例中，所述阵列基板还包括：
第四正电源接入端，位于所述正电源总线远离所述显示区域的一侧且位于所述第一正电源接入端与所述第三正电源接入端之间，所述第四正电源接入端与所述正电源总线电连接；
所述第四正电源接入端被配置为通过所述正电源总线、所述正电源线和所述第一电极向所述发光元件传输正电压信号。
示例地，如图2所示，在图1的基础上，该阵列基板还包括：
第四正电源接入端23，位于正电源总线13远离显示区域B1的一侧且位于第一正电源接入端14与第三正电源接入端16之间，该第四正电源接入端23与正电源总线13电连接；该第四正电源接入端23被配置为通过正电源总线13、正电源线12和第一电极向发光元件传输正电压信号。
例如，如图2所示，第四正电源接入端23位于第二负电源接入端20与第三正电源接入端16之间，第四正电源接入端23与第二正电源接入端15可以对称。第四正电源接入端23和第二正电源接入端15上的正电压信号可以通过正电源总线13传输至与中央区域(图2所示的摆放位置的中央区域)的正电源线12电连接的发光元件，这样一来，由正电源接入端传输至发光元件的正电压信号经过的路径较短，从而用于向发光元件传输正电压信号的信号传输线较短，阻抗较小，有助于保证阵列基板所显示的画面亮度的均匀性。
本领域技术人员容易理解，第一正电源接入端14、第二正电源接入端15、 第三正电源接入端16和第四正电源接入端23是同时向阵列基板中所有子像素的发光元件传输正电压信号的，只不过第二正电源接入端15和第四正电源接入端23距离中央区域的发光元件较近，由第二正电源接入端15和第四正电源接入端23传输至中央区域的发光元件的正电压信号经过的路径较短，阻抗较小。
可选地，在本申请实施例中，所述阵列基板还包括：
第四负电源接入端，位于所述正电源总线远离所述显示区域的一侧且位于所述第一正电源接入端与所述第三正电源接入端之间，所述第四负电源接入端与所述负电源辅助线电连接；
所述第四负电源接入端被配置为通过所述负电源辅助线、所述辅助电极和所述第二电极向所述发光元件传输负电压信号。
示例地，如图3所示，在图1的基础上，该阵列基板还包括：
第四负电源接入端24，位于正电源总线13远离显示区域B1的一侧且位于第一正电源接入端14与第三正电源接入端16之间，该第四负电源接入端24与负电源辅助线22电连接；该第四负电源接入端24被配置为通过负电源辅助线22、辅助电极18和第二电极向发光元件传输负电压信号。
例如，如图3所示，第四负电源接入端24位于第二负电源接入端20与第三正电源接入端16之间，第四负电源接入端24与第二负电源接入端20可以对称。第四负电源接入端24和第二负电源接入端20上的负电压信号可以通过负电源辅助线22和辅助电极18传输至中央区域(图3所示的摆放位置的中央区域)的发光元件，这样一来，由负电源接入端传输至发光元件的负电压信号经过的路径较短，从而用于向发光元件传输负电压信号的信号传输线较短，阻抗较小，有助于保证阵列基板所显示的画面亮度的均匀性。
本领域技术人员容易理解，第一负电源接入端19、第二负电源接入端20、第三负电源接入端21和第四负电源接入端24是同时向阵列基板中所有子像素的发光元件传输负电压信号的，只不过第二负电源接入端20和第四负电源接入端24距离中央区域的发光元件较近，由第二负电源接入端20和第四负电源接入端24传输至中央区域的发光元件的负电压信号经过的路径较短，阻抗较小。
可选地，在本申请实施例中，所述第二负电源接入端位于所述第二正电源接入端与所述第三正电源接入端之间，所述阵列基板还包括：
第四正电源接入端和第四负电源接入端，位于所述正电源总线远离所述显示区域的一侧，所述第四正电源接入端位于所述第二负电源接入端与所述第三 正电源接入端之间且与所述正电源总线电连接，所述第四负电源接入端位于所述第二负电源接入端与所述第四正电源接入端之间且与所述负电源辅助线电连接；
所述第四正电源接入端被配置为通过所述正电源总线、所述正电源线和所述第一电极向所述发光元件传输正电压信号，所述第四负电源接入端被配置为通过所述负电源辅助线、所述辅助电极和所述第二电极向所述发光元件传输负电压信号。
示例地，如图4所示，在图1的基础上，该阵列基板还包括：
第四正电源接入端23和第四负电源接入端24，位于正电源总线13远离显示区域B1的一侧，该第四正电源接入端23位于第二负电源接入端20与第三正电源接入端16之间且与正电源总线13电连接，该第四负电源接入端24位于第二负电源接入端20与第四正电源接入端23之间且与负电源辅助线22电连接；第四正电源接入端23被配置为通过正电源总线13、正电源线12和第一电极向发光元件传输正电压信号，第四负电源接入端24被配置为通过负电源辅助线22、辅助电极18和第二电极向发光元件传输负电压信号。
例如，如图4所示，第四正电源接入端23与第二正电源接入端15可以对称，第四负电源接入端24与第二负电源接入端20可以对称。第四正电源接入端23和第二正电源接入端15上的正电压信号可以通过正电源总线13和正电源线12传输至中央区域(图4所示的摆放位置的中央区域)的发光元件，第四负电源接入端24和第二负电源接入端20上的负电压信号可以通过负电源辅助线22和辅助电极18传输至中央区域(图4所示的摆放位置的中央区域)的发光元件，这样一来，由正电源接入端传输至发光元件的正电压信号经过的路径较短，且由负电源接入端传输至发光元件的负电压信号经过的路径较短，从而用于向发光元件传输正电压信号的信号传输线以及用于向发光元件传输负电压信号的信号传输线均较短，阻抗较小，有助于保证阵列基板所显示的画面亮度的均匀性。
本领域技术人员容易理解，第一正电源接入端14、第二正电源接入端15、第三正电源接入端16和第四正电源接入端23是同时向阵列基板中所有子像素的发光元件传输正电压信号的，第一负电源接入端19、第二负电源接入端20、第三负电源接入端21和第四负电源接入端24是同时向阵列基板中所有子像素的发光元件传输负电压信号的，只不过第二正电源接入端15和第四正电源接入 端23距离中央区域的发光元件较近，由第二正电源接入端15和第四正电源接入端23传输至中央区域的发光元件的正电压信号经过的路径较短，阻抗较小，第二负电源接入端20和第四负电源接入端24距离中央区域的发光元件较近，由第二负电源接入端20和第四负电源接入端24传输至中央区域的发光元件的负电压信号经过的路径较短，阻抗较小。
可选地，在本申请实施例中，所述发光元件为有机发光二极管，所述第一电极为阳极，所述第二电极为阴极。
可选地，在本申请实施例中，所述多个子像素中的至少一个包括薄膜晶体管和连接电极；所述薄膜晶体管包括位于所述衬底基板上的有源层，位于所述有源层远离所述衬底基板一侧的栅极，以及位于所述栅极远离所述衬底基板一侧的源极和漏极。
可选地，所述正电源总线包括正电源总线第一子层和正电源总线第二子层，所述正电源总线第一子层与所述正电源总线第二子层电连接；
所述正电源总线第一子层与所述源极或所述漏极位于同一层，所述正电源总线第二子层与所述连接电极位于同一层。
可选地，所述正电源总线第一子层与所述正电源总线第二子层通过正电源总线过孔电连接。
可选地，所述负电源线包括负电源线第一子层和负电源线第二子层，所述负电源线第一子层与所述负电源线第二子层电连接；
所述负电源辅助线包括负电源辅助线第一子层和负电源辅助线第二子层，所述负电源辅助线第一子层与所述负电源辅助线第二子层电连接；
所述负电源线第一子层和所述负电源辅助线第一子层均与所述源极或所述漏极位于同一层，所述负电源线第二子层和所述负电源辅助线第二子层均与所述连接电极位于同一层。
可选地，所述负电源线第一子层与所述负电源线第二子层通过负电源线过孔电连接，所述负电源辅助线第一子层与所述负电源辅助线第二子层通过负电源辅助线过孔电连接。
示例地，请参考图5，其示出了图1至图4任一所示的阵列基板的a-a部位、b-b部位、c-c部位和e-e部位的截面图，参见图5，多个子像素11中的至少一个包括薄膜晶体管110和连接电极111；薄膜晶体管110包括位于衬底基板10上的有源层1101，位于有源层1101远离衬底基板10一侧的栅极1102，以及位 于栅极1102远离衬底基板10一侧的源极1103和漏极1104，源极1103和漏极1104可以位于同一层。
正电源总线13包括正电源总线第一子层131和正电源总线第二子层132，正电源总线第一子层131与正电源总线第二子层132通过正电源总线过孔(图5中未标出)电连接；该正电源总线第一子层131与源极1103或漏极1104位于同一层，该正电源总线第二子层132与连接电极111位于同一层。其中，正电源总线过孔的数量可以是多个，正电源总线第一子层131与正电源总线第二子层132通过多个正电源总线过孔电连接，以保证连接的可靠性。
负电源线17包括负电源线第一子层171和负电源线第二子层172，负电源线第一子层171与负电源线第二子层172通过负电源线过孔(图5中未标出)电连接；负电源辅助线22包括负电源辅助线第一子层221和负电源辅助线第二子层222，负电源辅助线第一子层221与负电源辅助线第二子层222通过负电源辅助线过孔电连接；负电源线第一子层171和负电源辅助线第一子层221均与源极1103或漏极1104位于同一层，负电源线第二子层172和负电源辅助线第二子层222均与连接电极111位于同一层。其中，负电源线过孔的数量和负电源辅助线过孔的数量均可以是多个，负电源线第一子层171与负电源线第二子层172通过多个负电源线过孔电连接，以保证连接的可靠性，负电源辅助线第一子层221与负电源辅助线第二子层222通过多个负电源辅助线过孔电连接，以保证连接的可靠性。
可选地，在本申请实施例中，所述辅助电极位于所述负电源线远离所述衬底基板的一侧，所述辅助电极与所述负电源辅助线通过负电源辅助过孔电连接。
示例地，如图5所示，辅助电极18位于负电源线17远离衬底基板10的一侧，辅助电极18与负电源辅助线22通过负电源辅助过孔电连接。例如，辅助电极18与负电源辅助线第二子层222通过负电源辅助过孔电连接。其中，负电源辅助过孔的数量可以是多个，辅助电极18与负电源辅助线第二子层222通过多个负电源辅助过孔电连接，以保证连接的可靠性。
可选地，在本申请实施例中，所述辅助电极位于所述负电源线远离所述衬底基板的一侧，所述辅助电极与所述负电源线通过负电源辅助过孔电连接。
示例地，如图5所示，辅助电极18位于负电源线17远离衬底基板10的一侧，辅助电极18与负电源线17通过负电源辅助过孔电连接。例如，辅助电极18与负电源线第二子层172通过负电源辅助过孔电连接。其中，负电源辅助过 孔的数量可以是多个，辅助电极18与负电源线第二子层172通过多个负电源辅助过孔电连接，以保证连接的可靠性。
本领域技术人员容易理解，连接辅助电极18与负电源辅助线第二子层222的负电源辅助过孔是位于辅助电极18与负电源辅助线第二子层222之间的绝缘层上的过孔，连接辅助电极18与负电源线第二子层172的负电源辅助过孔是位于辅助电极18与负电源线第二子层172之间的绝缘层上的过孔，连接辅助电极18与负电源辅助线第二子层222的负电源辅助过孔与连接辅助电极18与负电源线第二子层172的负电源辅助过孔是不同的过孔。
可选地，在本申请实施例中，所述多个子像素中的至少一个包括薄膜晶体管；所述薄膜晶体管包括位于所述衬底基板上的有源层，位于所述有源层远离所述衬底基板一侧的栅极，以及位于所述栅极远离所述衬底基板一侧的源极和漏极；所述第一正电源接入端、所述第二正电源接入端和所述第三正电源接入端均与所述源极或所述漏极位于同一层；所述第一负电源接入端、所述第二负电源接入端和所述第三负电源接入端均与所述源极或所述漏极位于同一层。
示例地，请参考图6，其示出了图1所示的阵列基板的a-a部位和f-f部位的截面图，参见图6，多个子像素11中的至少一个包括薄膜晶体管110；薄膜晶体管110包括位于衬底基板10上的有源层1101，位于有源层1101远离衬底基板10一侧的栅极1102，以及位于栅极1102远离衬底基板10一侧的源极1103和漏极1104，第一正电源接入端14、第二正电源接入端15和第三正电源接入端16均与源极1103或漏极1104位于同一层，第一负电源接入端19、第二负电源接入端20和第三负电源接入端21均与源极1103或漏极1104位于同一层。
可选地，在本申请实施例中，当阵列基板还包括第四正电源接入端和/或第四负电源接入端，该第四正电源接入端和/或第四负电源接入端均与所述源极或所述漏极位于同一层。
示例地，请参考图7，其示出了图2所示的阵列基板的a-a部位和f-f部位的截面图，参见图7，第一正电源接入端14、第二正电源接入端15、第三正电源接入端16和第四正电源接入端23均与源极1103或漏极1104位于同一层，第一负电源接入端19、第二负电源接入端20和第三负电源接入端21均与源极1103或漏极1104位于同一层。
示例地，请参考图8，其示出了图3所示的阵列基板的a-a部位和f-f部位的截面图，参见图8，第一正电源接入端14、第二正电源接入端15和第三正电 源接入端16均与源极1103或漏极1104位于同一层，第一负电源接入端19、第二负电源接入端20、第三负电源接入端21和第四负电源接入端24均与源极1103或漏极1104位于同一层。
示例地，请参考图9，其示出了图4所示的阵列基板的a-a部位和f-f部位的截面图，参见图9，第一正电源接入端14、第二正电源接入端15、第三正电源接入端16和第四正电源接入端23均与源极1103或漏极1104位于同一层，第一负电源接入端19、第二负电源接入端20、第三负电源接入端21和第四负电源接入端24均与源极1103或漏极1104位于同一层。
可选地，在本申请实施例中，所述负电源辅助线包括负电源辅助线第一子层和负电源辅助线第二子层，所述负电源辅助线第一子层与所述负电源辅助线第二子层电连接；所述第二负电源接入端、所述第四负电源接入端和所述负电源辅助线第一子层为一体结构。
示例地，请参考图10，其示出了图3或图4所示的阵列基板的a-a部位和g-g部位的截面图，如图10所示，负电源辅助线22包括负电源辅助线第一子层221和负电源辅助线第二子层222，负电源辅助线第一子层221与负电源辅助线第二子层222通过负电源辅助线过孔(图10中未标出)电连接；第二负电源接入端20、第四负电源接入端24和负电源辅助线第一子层221为一体结构。
需要说明的是，图10是以阵列基板同时包括第二负电源接入端20和第四负电源接入端24为例说明的，当阵列基板仅包括第二负电源接入端20或第四负电源接入端24时，第二负电源接入端20或第四负电源接入端24和负电源辅助线第一子层221为一体结构，例如，当阵列基板包括第二负电源接入端20而不包括第四负电源接入端24时，第二负电源接入端20和负电源辅助线第一子层221为一体结构，当阵列基板包括第四负电源接入端24而不包括第二负电源接入端20时，第四负电源接入端24和负电源辅助线第一子层221为一体结构，
可选地，在本申请实施例中，所述阵列基板还包括：电路板，位于所述第一正电源接入端、所述第二正电源接入端、所述第三正电源接入端、所述第四正电源接入端、所述第一负电源接入端、所述第二负电源接入端、所述第三负电源接入端和所述第四负电源接入端远离所述显示区域的一侧，所述第一正电源接入端、所述第二正电源接入端、所述第三正电源接入端、所述第四正电源接入端、所述第一负电源接入端、所述第二负电源接入端、所述第三负电源接入端和所述第四负电源接入端分别与所述电路板电连接。
示例地，如图1所示，该阵列基板还包括：电路板25，位于第一正电源接入端14、第二正电源接入端15、第三正电源接入端16、第一负电源接入端19、第二负电源接入端20和第三负电源接入端21远离显示区域B1的一侧，第一正电源接入端14、第二正电源接入端15、第三正电源接入端16、第一负电源接入端19、第二负电源接入端20和第三负电源接入端21分别与电路板25电连接。
示例地，如图2所示，该阵列基板还包括：电路板25，位于第一正电源接入端14、第二正电源接入端15、第三正电源接入端16、第四正电源接入端23、第一负电源接入端19、第二负电源接入端20和第三负电源接入端21远离显示区域B1的一侧，第一正电源接入端14、第二正电源接入端15、第三正电源接入端16、第四正电源接入端23、第一负电源接入端19、第二负电源接入端20和第三负电源接入端21分别与电路板25电连接。
示例地，如图3所示，该阵列基板还包括：电路板25，位于第一正电源接入端14、第二正电源接入端15、第三正电源接入端16、第一负电源接入端19、第二负电源接入端20、第三负电源接入端21和第四负电源接入端24远离显示区域B1的一侧，第一正电源接入端14、第二正电源接入端15、第三正电源接入端16、第一负电源接入端19、第二负电源接入端20、第三负电源接入端21和第四负电源接入端24分别与电路板25电连接。
示例地，如图4所示，该阵列基板还包括：电路板25，位于第一正电源接入端14、第二正电源接入端15、第三正电源接入端16、第四正电源接入端23、第一负电源接入端19、第二负电源接入端20、第三负电源接入端21和第四负电源接入端24远离显示区域B1的一侧，第一正电源接入端14、第二正电源接入端15、第三正电源接入端16、第四正电源接入端23、第一负电源接入端19、第二负电源接入端20、第三负电源接入端21和第四负电源接入端24分别与电路板25电连接。
需要说明的是，本申请实施例中所述的电路板25可以是柔性电路板(英文：Flexible Printed Circuit；简称：FPC)。
示例地，如图5至图10所示，多个子像素11中的至少一个包括薄膜晶体管110、连接电极111、发光元件112和存储电容113。薄膜晶体管110包括位于衬底基板10上的有源层1101，位于有源层1101远离衬底基板10一侧的第一绝缘层1105，位于第一绝缘层1105远离衬底基板10一侧的栅极1102，位于栅极1102远离衬底基板10一侧的第二绝缘层1106，位于第二绝缘层1106远离衬 底基板10一侧的第三绝缘层1107，位于第三绝缘层1107远离衬底基板10一侧的源极1103和漏极1104。连接电极111位于薄膜晶体管110远离衬底基板10的一侧，连接电极111与漏极1104电连接，发光元件112位于连接电极111远离衬底基板的一侧，该发光元件112包括沿远离衬底基板10的方向依次层叠的第一电极1121、发光层1122和第二电极1123，第一电极1121与连接电极111电连接。存储电容113包括第一极板1131和第二极板1132，第一极板1131和栅极1101位于同一层，第二极板1132位于第二绝缘层1106和第三绝缘层1107之间。
示例地，如图5至图10所示，多个子像素11中的至少一个还包括位于有源层1101与衬底基板10之间的缓冲层114，沿远离衬底基板10的方向位于源极1103与连接电极111之间的钝化层115和第一平坦层116，以及位于连接电极111与第一电极1121之间的第二平坦层117。钝化层115和第一平坦层116上具有过孔，连接电极111通过钝化层115和第一平坦层116上的过孔与漏极1104电连接，第二平坦层117上具有过孔第一电极1121通过第二平坦层117上的过孔与连接电极111电连接。
可选地，如图5至图10所示，该阵列基板还包括：位于第二平坦层117远离衬底基板10一侧的像素界定层26，该像素界定层26包括由挡墙结构限定的开口区域，发光元件112位于像素界定层26的开口区域中；位于发光元件112远离衬底基板一侧的封装结构27，该封装结构27用于对发光元件112进行封装。
需要说明的是，在图5至图10的b-b部位、c-c部位、e-e部位、f-f部位和g-g部位中，第一绝缘层1105、第二绝缘层1106、第三绝缘层1107、缓冲层114、平坦层115、钝化层115、第一平坦层116和第二平坦层117，可以是a-a部位的第一绝缘层1105、第二绝缘层1106、第三绝缘层1107、缓冲层114、平坦层115、钝化层115、第一平坦层116和第二平坦层117分别延伸至周边区域B2的部分。本领域技术人员容易理解，在图5至图10的b-b部位、c-c部位、e-e部位、f-f部位和g-g部位中，仅仅示出了正电源总线13、第一正电源接入端14、第二正电源接入端15和第三正电源接入端16、负电源线17、辅助电极18、第一负电源接入端19、第二负电源接入端20、第三负电源接入端21、负电源辅助线22、第四正电源接入端23和第四负电源接入端24，阵列基板的周边区域还可以包括其他电路结构，该其他电路结构在图5至图10中并未示出。
还需要说明的是，该阵列基板中除本申请中所描述的结构外，还可以包括 其他结构。例如，该阵列基板还包括延伸方向相同的多条栅线，延伸方向相同的多条数据线，多条栅线与多条数据线交叉限定出多个像素区，多个子像素一一对应位于多个像素区中；再例如，该阵列基板还可以包括覆晶薄膜(英文：Chip On Film；简称：COF)和集成电路(英文：Integrated Circuit；简称：IC)等，本申请实施例在此不再赘述。
综上所述，本申请实施例提供的阵列基板，该阵列基板包括第一正电源接入端、第二正电源接入端、第三正电源接入端、第一负电源接入端、第二负电源接入端和第三负电源接入端，第二正电源接入端和第二负电源接入端均位于第一正电源接入端与第三正电源接入端之间，每个正电源接入端可以通过正电源总线和正电源线向与其较近的子像素的发光元件传输正电压信号，每个负电源接入端可以通过负电源线、负电源辅助线和辅助电极向与其较近的子像素的发光元件传输负电压信号，从而向发光元件传输正电压信号的信号传输线的长度以及向发光元件传输负电压信号的信号传输线均较短，阻抗较小，有助于保证阵列基板所显示的画面亮度的均匀性。
基于同样的发明构思，本申请实施例还提供一种显示装置，该显示装置包括上述任意一种阵列基板。本申请实施例中的显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本申请实施例中，术语“同一层”是指在同一步骤中同时形成的层之间的关系。例如，当负电源辅助线第二子层222与连接电极111是在同一层材料中执行的同一图案处理的一个或多个步骤的结果而形成时，它们位于同一层中；在另一示例中，负电源辅助线第二子层222与连接电极111可以通过同时执行形成负电源辅助线第二子层222和形成连接电极111的步骤在同一层中形成；“同一层”并不总是指横截面图中的层厚度或层高度相同。
本申请实施例中术语“第一”、“第二”、“第三”、“第四”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。两个导体“电连接”所指的是这两个导体直接的或间接的电连接，并且，这两个导体能够传输电信号。术语，“至少一个”指的是一个或多个，“多个”指的是两个或两个以上。
本申请实施例中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
需要指出的是，在附图中，为了图示的清晰可能夸大了部分或全部的层的尺寸，或者部分或全部区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
以上所述仅为本申请的示例性实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (17)

  1. 一种阵列基板，包括：
    衬底基板，包括显示区域和围绕所述显示区域的周边区域，所述显示区域包括第一边界、第二边界、第三边界和第四边界；
    多个子像素，位于所述显示区域中，所述多个子像素中的至少一个包括发光元件，所述发光元件包括依次层叠的第一电极、发光层和第二电极；
    多条正电源线，位于所述显示区域中且与所述第一电极电连接；
    正电源总线，位于所述周边区域中且沿所述第一边界分布，所述正电源总线与所述多条正电源线电连接；
    第一正电源接入端、第二正电源接入端和第三正电源接入端，位于所述正电源总线远离所述显示区域的一侧，所述第二正电源接入端位于所述第一正电源接入端与所述第三正电源接入端之间，所述第一正电源接入端、所述第二正电源接入端和所述第三正电源接入端分别与所述正电源总线电连接；
    负电源线，位于所述周边区域中且围绕所述第二边界、所述第三边界和所述第四边界；
    辅助电极，位于所述周边区域中且围绕所述第一边界、所述第二边界、所述第三边界和所述第四边界，所述辅助电极分别与所述负电源线和所述第二电极电连接；
    第一负电源接入端、第二负电源接入端和第三负电源接入端，位于所述正电源总线远离所述显示区域的一侧，所述第一负电源接入端位于所述第一正电源接入端远离所述第二正电源接入端的一侧，所述第二负电源接入端位于所述第一正电源接入端与所述第三正电源接入端之间，所述第三负电源接入端位于所述第三正电源接入端远离所述第二正电源接入端的一侧，所述第一负电源接入端和所述第三负电源接入端分别与所述负电源线电连接；
    负电源辅助线，位于所述周边区域中，位于所述第一正电源接入端与所述第三正电源接入端之间且位于所述正电源总线与所述第二负电源接入端之间，所述负电源辅助线分别与所述第二负电源接入端和所述辅助电极电连接。
  2. 根据权利要求1所述的阵列基板，其中，
    所述第一正电源接入端、所述第二正电源接入端和所述第三正电源接入端 被配置为通过所述正电源总线、所述正电源线和所述第一电极向所述发光元件传输正电压信号；
    所述第一负电源接入端、所述第二负电源接入端和所述第三负电源接入端被配置为通过所述负电源线、所述负电源辅助线、所述辅助电极和所述第二电极向所述发光元件传输负电压信号。
  3. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：
    第四正电源接入端，位于所述正电源总线远离所述显示区域的一侧且位于所述第一正电源接入端与所述第三正电源接入端之间，所述第四正电源接入端与所述正电源总线电连接；
    所述第四正电源接入端被配置为通过所述正电源总线、所述正电源线和所述第一电极向所述发光元件传输正电压信号。
  4. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：
    第四负电源接入端，位于所述正电源总线远离所述显示区域的一侧且位于所述第一正电源接入端与所述第三正电源接入端之间，所述第四负电源接入端与所述负电源辅助线电连接；
    所述第四负电源接入端被配置为通过所述负电源辅助线、所述辅助电极和所述第二电极向所述发光元件传输负电压信号。
  5. 根据权利要求1所述的阵列基板，其中，所述第二负电源接入端位于所述第二正电源接入端与所述第三正电源接入端之间，所述阵列基板还包括：
    第四正电源接入端和第四负电源接入端，位于所述正电源总线远离所述显示区域的一侧，所述第四正电源接入端位于所述第二负电源接入端与所述第三正电源接入端之间且与所述正电源总线电连接，所述第四负电源接入端位于所述第二负电源接入端与所述第四正电源接入端之间且与所述负电源辅助线电连接；
    所述第四正电源接入端被配置为通过所述正电源总线、所述正电源线和所述第一电极向所述发光元件传输正电压信号，所述第四负电源接入端被配置为通过所述负电源辅助线、所述辅助电极和所述第二电极向所述发光元件传输负 电压信号。
  6. 根据权利要求1至5任一所述的阵列基板，其中，
    所述多个子像素中的至少一个包括薄膜晶体管和连接电极；
    所述薄膜晶体管包括位于所述衬底基板上的有源层，位于所述有源层远离所述衬底基板一侧的栅极，以及位于所述栅极远离所述衬底基板一侧的源极和漏极。
  7. 根据权利要求6所述的阵列基板，其中，
    所述正电源总线包括正电源总线第一子层和正电源总线第二子层，所述正电源总线第一子层与所述正电源总线第二子层电连接；
    所述正电源总线第一子层与所述源极或所述漏极位于同一层，所述正电源总线第二子层与所述连接电极位于同一层。
  8. 根据权利要求7所述的阵列基板，其中，
    所述正电源总线第一子层与所述正电源总线第二子层通过正电源总线过孔电连接。
  9. 根据权利要求6所述的阵列基板，其中，
    所述负电源线包括负电源线第一子层和负电源线第二子层，所述负电源线第一子层与所述负电源线第二子层电连接；
    所述负电源辅助线包括负电源辅助线第一子层和负电源辅助线第二子层，所述负电源辅助线第一子层与所述负电源辅助线第二子层电连接；
    所述负电源线第一子层和所述负电源辅助线第一子层均与所述源极或所述漏极位于同一层，所述负电源线第二子层和所述负电源辅助线第二子层均与所述连接电极位于同一层。
  10. 根据权利要求9所述的阵列基板，其中，
    所述负电源线第一子层与所述负电源线第二子层通过负电源线过孔电连接，所述负电源辅助线第一子层与所述负电源辅助线第二子层通过负电源辅助 线过孔电连接。
  11. 根据权利要求3或5所述的阵列基板，其中，
    所述多个子像素中的至少一个包括薄膜晶体管；
    所述薄膜晶体管包括位于所述衬底基板上的有源层，位于所述有源层远离所述衬底基板一侧的栅极，以及位于所述栅极远离所述衬底基板一侧的源极和漏极；
    所述第一正电源接入端、所述第二正电源接入端、所述第三正电源接入端和所述第四正电源接入端均与所述源极或所述漏极位于同一层。
  12. 根据权利要求4或5所述的阵列基板，其中，
    所述多个子像素中的至少一个包括薄膜晶体管；
    所述薄膜晶体管包括位于所述衬底基板上的有源层，位于所述有源层远离所述衬底基板一侧的栅极，以及位于所述栅极远离所述衬底基板一侧的源极和漏极；
    所述第一负电源接入端、所述第二负电源接入端、所述第三负电源接入端和所述第四负电源接入端均与所述源极或所述漏极位于同一层。
  13. 根据权利要求4或5所述的阵列基板，其中，
    所述负电源辅助线包括负电源辅助线第一子层和负电源辅助线第二子层，所述负电源辅助线第一子层与所述负电源辅助线第二子层电连接；
    所述第二负电源接入端、所述第四负电源接入端和所述负电源辅助线第一子层为一体结构。
  14. 根据权利要求5所述的阵列基板，其中，所述阵列基板还包括：
    电路板，位于所述第一正电源接入端、所述第二正电源接入端、所述第三正电源接入端、所述第四正电源接入端、所述第一负电源接入端、所述第二负电源接入端、所述第三负电源接入端和所述第四负电源接入端远离所述显示区域的一侧，所述第一正电源接入端、所述第二正电源接入端、所述第三正电源接入端、所述第四正电源接入端、所述第一负电源接入端、所述第二负电源接 入端、所述第三负电源接入端和所述第四负电源接入端分别与所述电路板电连接。
  15. 根据权利要求1至14任一所述的阵列基板，其中，
    所述辅助电极位于所述负电源线远离所述衬底基板的一侧，所述辅助电极与所述负电源辅助线通过负电源辅助过孔电连接。
  16. 根据权利要求1至15任一所述的阵列基板，其中，
    所述发光元件为有机发光二极管，所述第一电极为阳极，所述第二电极为阴极。
  17. 一种显示装置，包括权利要求1至16任一所述的阵列基板。
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