WO2021016800A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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WO2021016800A1
WO2021016800A1 PCT/CN2019/098165 CN2019098165W WO2021016800A1 WO 2021016800 A1 WO2021016800 A1 WO 2021016800A1 CN 2019098165 W CN2019098165 W CN 2019098165W WO 2021016800 A1 WO2021016800 A1 WO 2021016800A1
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layer
type semiconductor
semiconductor layer
groove
semiconductor structure
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PCT/CN2019/098165
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English (en)
French (fr)
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程凯
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苏州晶湛半导体有限公司
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Priority to US17/613,575 priority Critical patent/US20220246752A1/en
Priority to PCT/CN2019/098165 priority patent/WO2021016800A1/zh
Priority to CN201980098556.XA priority patent/CN114175274B/zh
Priority to TW109124905A priority patent/TWI768410B/zh
Publication of WO2021016800A1 publication Critical patent/WO2021016800A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7788—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H01L29/8122—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Definitions

  • This application relates to the field of semiconductors, and in particular to a semiconductor structure and a preparation method thereof.
  • the depth of the gate will affect the performance of the overall device.
  • the specific etching depth of the groove cannot be accurately controlled, resulting in the specific depth of the gate cannot be accurately controlled.
  • the layer structure under the groove is generally GaN material, and the GaN material will decompose and volatilize due to the temperature rise, making the groove deeper and causing the groove The final depth cannot be controlled and affects the performance of the entire semiconductor device.
  • the invention provides a semiconductor structure and a preparation method thereof, which solves the problem that the final depth of the groove is uncontrollable.
  • the semiconductor structure includes:
  • a first n-type semiconductor layer, a p-type semiconductor layer, and a second n-type semiconductor layer are stacked, wherein the first n-type semiconductor layer is provided with a buried layer, and the buried layer is AlGaN;
  • a groove at least penetrates the second n-type semiconductor layer and the p-type semiconductor layer, and at least part of the buried layer is left under the groove;
  • the Al composition in the buried layer increases from bottom to top along the growth direction of the buried layer.
  • the Al composition in the buried layer increases linearly from bottom to top along the growth direction of the buried layer, or increases in steps, or increases in arc.
  • the thickness of the buried layer is not less than 0.05 microns.
  • the first n-type semiconductor layer includes a first sub-n-type semiconductor layer, the buried layer, and a second sub-n-type semiconductor layer that are stacked.
  • the first n-type semiconductor layer, the second n-type semiconductor layer, and the p-type semiconductor layer all include a GaN-based material.
  • the semiconductor structure further includes a riser layer and a dielectric layer, the riser layer is located in the groove and on the second n-type semiconductor layer; the dielectric layer is located on the riser layer, so The gate is located on the dielectric layer.
  • the material of the dummy layer includes a GaN-based material.
  • the first n-type semiconductor layer is a lightly doped n-type semiconductor layer.
  • the semiconductor structure further includes a heavily doped n-type semiconductor layer provided under the first n-type semiconductor layer.
  • the semiconductor structure further includes a source electrode and a drain electrode, the source electrode is provided on both sides of the gate electrode and is in contact with the second n-type semiconductor layer; the drain electrode is provided on the first The bottom of the n-type semiconductor layer is in contact with the first n-type semiconductor layer.
  • the semiconductor structure further includes a source electrode and a drain electrode, the source electrode is provided on one side of the gate electrode and is in contact with the second n-type semiconductor layer; the drain electrode is provided on the gate electrode And contact with the first n-type semiconductor layer.
  • a manufacturing method of a semiconductor structure includes:
  • the groove at least penetrates the second n-type semiconductor layer and the p-type semiconductor layer, and at least a part of the buried layer is left under the groove;
  • a gate is formed in the groove.
  • the preparation method further includes:
  • a dielectric layer is formed, and the dielectric layer is formed on the dummy layer.
  • the groove does not penetrate the buried layer, and thus the recess
  • the depth of the groove will not be lower than the buried layer with AlGaN, and the depth of the groove can be precisely controlled.
  • FIG. 1 is a schematic cross-sectional structure diagram of a semiconductor structure according to an exemplary embodiment of the present invention.
  • FIG. 2 is a flowchart of a manufacturing method of a semiconductor structure according to an exemplary embodiment of the present invention.
  • Figures 3(a) to 3(f) are process flow diagrams of a semiconductor packaging method according to an exemplary embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional structure diagram of a semiconductor structure according to an exemplary embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional structure diagram of a semiconductor structure according to another exemplary embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional structure diagram of a semiconductor structure according to another exemplary embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional structure diagram of a semiconductor structure according to another exemplary embodiment of the present invention.
  • FIG. 8 is a schematic cross-sectional structure diagram of a semiconductor structure according to another embodiment of an exemplary embodiment of the present invention.
  • the semiconductor structure includes a first n-type semiconductor layer 21, a p-type semiconductor layer 22, a second n-type semiconductor layer 23, a dummy layer 28, a dielectric layer 29, a gate 25, a source 26 and a drain. ⁇ 27.
  • the first n-type semiconductor layer 21, the second n-type semiconductor layer 23, the p-type semiconductor layer 22, and the dummy layer 28 all comprise GaN-based materials.
  • the GaN-based material is a material that includes at least Ga atoms and N atoms. In this embodiment, the GaN-based material includes GaN, AlGaN, and AlInGaN.
  • the first n-type semiconductor layer 21 is a lightly doped n-type semiconductor layer.
  • the so-called lightly doped means that the doping concentration of n-type impurities in the first n-type semiconductor layer 21 does not exceed 2e17 cm ⁇ 3 .
  • the p-type semiconductor layer 22 and the second n-type semiconductor layer 23 are stacked on the first n-type semiconductor layer 21 along the growth direction F.
  • a groove 24 is opened from the side of the second n-type semiconductor layer 23 away from the p-type semiconductor layer 22, and the groove 24 penetrates at least the second n-type semiconductor layer 23 and the p-type semiconductor layer 22.
  • the groove 24 may be formed by etching. In other embodiments, the groove 24 may also be formed by selective growth. Regarding the method of forming the groove 24, this case does not Do restrictions.
  • the specific method of etching to form the groove 24 may be dry etching.
  • the dummy layer 28 is located in the groove 24 and on the second n-type semiconductor layer 23; the dielectric layer 29 is located on the dummy layer 28, and the gate 25 is located On the dielectric layer 29. Furthermore, the gate 25 can also be exposed to form the T-shaped gate 25. But it is not limited to this. Another implementation of this embodiment is shown in FIG. 8.
  • the semiconductor structure may not include the dummy layer 28 and the dielectric layer 29, and the gate 26 may be directly formed on the In the groove 24.
  • the source electrode 26 is provided on both sides of the gate electrode 25 and is in contact with the second n-type semiconductor layer 23.
  • the drain 27 is disposed at the bottom of the first n-type semiconductor layer 21 and is in contact with the first n-type semiconductor layer 21 to form a vertical semiconductor structure.
  • the source electrode 26 is provided on one side of the gate 25 and is in contact with the second n-type semiconductor layer 23.
  • the drain 27 is arranged on the other side of the gate 25 and is in contact with the first n-type semiconductor layer 21 to form a semi-vertical semiconductor structure.
  • the first n-type semiconductor layer 21 includes a first sub-n-type semiconductor layer 211, the buried layer 212, and a second sub-n-type semiconductor layer 213 stacked in a growth direction F, and the buried layer 212 is AlGaN.
  • the groove 24 penetrates at least the second n-type semiconductor layer 23 and the p-type semiconductor layer 22, and at least a part of the buried layer 212 is left under the groove 24.
  • the bottom 241 of the groove may stop at the upper surface 2131 of the second sub-n-type semiconductor layer 213; or, the bottom 241 of the groove may partially penetrate the second sub-n-type semiconductor layer 213.
  • Sub-n-type semiconductor layer 213; or, the bottom 241 of the groove may stop at the upper surface 2121 of the buried layer 212; or, the bottom 241 of the groove may partially penetrate the buried layer 212.
  • the bottom 241 of the groove does not penetrate the buried layer 212, that is, a part of the buried layer 212 is always left under the groove 24.
  • the recess 24 will not penetrate the buried layer 212 because AlGaN is not easily decomposed at high temperature. Therefore, the depth of the groove 24 will not be lower than the buried layer 212, and the depth of the groove 24 can be accurately controlled.
  • the precise depth of the groove 24 can be controlled by setting the buried layer 212 at a specific position of the first n-type semiconductor layer 21. Meet the design requirements.
  • the AlGaN composition remains unchanged; in other embodiments, preferably, the Al composition in the buried layer 212 increases from bottom to top along the growth direction F of the buried layer 212 Big. Specifically, the Al composition in the buried layer 212 increases linearly from bottom to top along the growth direction F of the buried layer 212, or increases in steps, or increases in arc. In this way, the Al composition in the buried layer 212 is the largest at the position closest to the second sub-n-type semiconductor layer 213, and is the least likely to be decomposed at high temperatures, so as to better prevent the buried layer 212 from being at high temperatures. Decompose downward, so that the depth of the groove 24 can be accurately controlled.
  • the thickness of the buried layer 212 is not less than 0.05 microns.
  • n-type semiconductor layer 30 may be provided on the lower side of the first n-type semiconductor layer 21 to reduce voltage drop.
  • the doping concentration of n-type impurities is not less than 5e17cm -3 .
  • the semiconductor structure may further include a substrate 20, which is provided on the lower side of the first n-type semiconductor layer 21 for forming a first n-type semiconductor layer on the upper side thereof. Layer 21.
  • this embodiment also provides a method for manufacturing a semiconductor structure, and the manufacturing method includes:
  • Step 100 sequentially forming a first n-type semiconductor layer, a p-type semiconductor layer, and a second n-type semiconductor layer, the first n-type semiconductor layer is provided with a buried layer, and the buried layer is AlGaN;
  • Step 200 forming a groove, the groove penetrating at least the second n-type semiconductor layer and the p-type semiconductor layer, and at least part of the buried layer is left under the groove;
  • Step 300 forming a dummy layer formed in the groove and on the second n-type semiconductor layer
  • Step 400 forming a dielectric layer, the dielectric layer being formed on the dummy layer;
  • Step 500 forming an electrode, forming a gate in the groove, and forming the gate on the dielectric layer.
  • a first n-type semiconductor layer 21, a p-type semiconductor layer 22, and a second n-type semiconductor layer 23 are sequentially formed along the growth direction F.
  • the first n-type semiconductor layer 21 includes a first sub-n-type semiconductor layer 211, a buried layer 212, and a second sub-n-type semiconductor layer 213 stacked along the growth direction F, and the buried layer 212 is AlGaN.
  • the groove 24 is formed from a side of the second n-type semiconductor layer 23 away from the p-type semiconductor layer 22.
  • the groove 24 may be formed by etching, but it is not limited to this.
  • the groove 24 may also be formed by selective growth.
  • the method of forming the groove 24 is not limited in this case.
  • the specific method of etching to form the groove 24 may be dry etching.
  • the groove 24 penetrates at least the second n-type semiconductor layer 23 and the p-type semiconductor layer 22, and at least a part of the buried layer 212 is left under the groove 24. Specifically, there are the following situations: the bottom 241 of the groove may stop at the upper surface 2131 of the second sub-n-type semiconductor layer; or, the bottom 241 of the groove may partially penetrate the second sub-layer
  • the n-type semiconductor layer 213 is shown in FIG. 3(b); alternatively, the bottom 241 of the groove may stop at the upper surface 2121 of the buried layer, as shown in 3(c); or, the bottom of the groove 241 may partially penetrate the buried layer 212.
  • the bottom 241 of the groove does not penetrate the buried layer 212, that is, a part of the buried layer 212 is always left under the groove 24.
  • the groove 24 will not penetrate the buried layer 212, so that the The depth of the groove 24 will not be lower than the buried layer 212, and the depth of the groove 24 can be accurately controlled.
  • the precise depth of the groove 24 can be controlled by setting the buried layer 212 at a specific position of the first n-type semiconductor layer 21. Meet the design requirements.
  • step 300 as shown in FIG. 3(d), a dummy layer 28 is formed, and the dummy layer 28 is formed in the groove 24 and on the second n-type semiconductor layer 23.
  • high temperature growth may be used to form the dummy layer 28.
  • step 400 as shown in FIG. 3(e), a dielectric layer 29 is formed, and the dielectric layer 29 is formed on the dummy layer 28. Similarly, the dielectric layer 29 is also partially located in the groove 24.
  • step 500 as shown in FIG. 3(f), an electrode is formed, a gate 25 is formed in the groove 24, and the gate 25 is formed on the dielectric layer 29.
  • the formation of the electrode includes: as shown in FIG. 4, the source electrode 26 is formed on the second n-type semiconductor layer 23, and the source electrode 26 is provided on both sides of the gate electrode 25 and is in contact with the The second n-type semiconductor layer 23 is in contact; the drain 27 is formed at the bottom of the first n-type semiconductor layer 21, and the drain 27 is in contact with the first n-type semiconductor layer 21 to form a vertical semiconductor structure. It can be understood that when the heavily doped n-type semiconductor layer 30 is provided under the first n-type semiconductor layer 21, the drain 27 may also contact the heavily doped n-type semiconductor layer 30 to form a vertical semiconductor layer.
  • the structure is shown in Figure 6.
  • the electrode may also be shown in FIG. 5, and the source electrode 26 is provided on one side of the gate 25 and is in contact with the second n-type semiconductor layer 23.
  • the drain 27 is provided on the other side of the gate 25, and is in contact with the first n-type semiconductor layer 21 to form a semi-vertical semiconductor structure. Specifically, the front side of the gate 25 can be engraved first.
  • the etching method is used to etch until the second n-type semiconductor layer 23 is exposed to form a source electrode 26 so that the source electrode 26 is in contact with the second n-type semiconductor layer 23; then the other side of the gate electrode 25 is etched by a front etching method Until the first n-type semiconductor layer 21 is exposed, the drain 27 is formed so that the drain 27 is in contact with the first n-type semiconductor layer 21.
  • a heavily doped n-type semiconductor layer 30 may be further provided on the lower side of the first n-type semiconductor layer 21, which can reduce the voltage drop, wherein the heavily doped n-type semiconductor layer
  • the doping concentration of n-type impurities in 30 is not less than 5e17cm -3 .
  • the preparation method further includes: sequentially forming the first n-type semiconductor layer 21, the p-type semiconductor layer 22, and the second n-type semiconductor layer 23 on the substrate 20, as shown in FIG. As shown in FIG. 7, and before forming the drain 27, the substrate 20 is removed to form the vertical semiconductor structure as shown in FIG. It can be understood that a semi-vertical semiconductor structure as shown in FIG. 5 can also be formed.
  • the method for preparing the semiconductor structure may not include step 300 and step 400, that is, after step 200 is completed, the preparation of step 500 can be directly performed: forming an electrode, in the groove The gate is formed.
  • the semiconductor structure obtained by this preparation method is shown in Fig. 8.
  • the groove does not penetrate the buried layer, thus the recess
  • the depth of the groove will not be lower than the buried layer with AlGaN, and the depth of the groove can be precisely controlled.

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Abstract

本申请提供一种半导体结构及其制备方法。所述半导体结构包括：层叠设置的第一n型半导体层、p型半导体层以及第二n型半导体层，所述第一n型半导体层中设有掩埋层，所述掩埋层为AlGaN；凹槽，所述凹槽至少贯穿所述第二n型半导体层以及所述p型半导体层，且所述凹槽的下方至少留有部分所述掩埋层；设于凹槽内的栅极。所述制备方法用于制备所述半导体结构。本申请通过设置具有AlGaN的掩埋层，在接续高温生长其他半导体层的过程中，由于AlGaN在高温下不易分解，因此凹槽不会贯穿掩埋层，从而凹槽的深度不会低于具有AlGaN的掩埋层，而能够精确控制凹槽的深度。

Description

半导体结构及其制备方法 技术领域
本申请涉及半导体领域，尤其涉及一种半导体结构及其制备方法。
背景技术
现有技术中，在制备半导体结构的过程中，需要刻蚀凹槽来沉积金属，从而形成栅极。对于半导体结构而言，栅极的深度会影响整体器件的性能，但是在传统的制备过程中，凹槽的具体刻蚀深度不可精确控制，从而导致栅极的具体深度不可精确控制。比如说在已经刻蚀凹槽之后，升温再生长其它半导体层时，凹槽下方的层结构一般为GaN材料，而GaN材料会因为升温而分解挥发，使得凹槽变得更深，从而造成凹槽的最终深度不可控制，而影响了整个半导体器件的性能。
发明内容
本发明提供一种半导体结构及其制备方法，解决了凹槽的最终深度不可控制的问题。
为实现上述目的，根据本发明实施例的第一方面，提供一种半导体结构。所述半导体结构包括：
层叠设置的第一n型半导体层、p型半导体层以及第二n型半导体层，所述第一n型半导体层中设有掩埋层，所述掩埋层为AlGaN；
凹槽，所述凹槽至少贯穿所述第二n型半导体层以及所述p型半导体层，且所述凹槽的下方至少留有部分所述掩埋层；
设于凹槽内的栅极。
可选的，所述掩埋层中的Al组分沿着所述掩埋层的生长方向由下至上增大。
可选的，所述掩埋层中的Al组分沿着所述掩埋层的生长方向由下至上线性增大、或阶梯增大、或弧形增大。
可选的，所述掩埋层的厚度不小于0.05微米。
可选的，所述第一n型半导体层包括层叠设置的第一子n型半导体层、所述掩埋层以及第二子n型半导体层。
可选的，所述第一n型半导体层、所述第二n型半导体层、以及所述p型半导体层均包括GaN基材料。
可选的，所述半导体结构还包括冒层和介质层，所述冒层位于所述凹槽内、以及所述第二n型半导体层上；所述介质层位于所述冒层上，所述栅极位于所述介质层上。
可选的，所述冒层的材料包括GaN基材料。
可选的，所述第一n型半导体层为轻掺杂的n型半导体层。
可选的，所述半导体结构还包括设于第一n型半导体层下侧的重掺杂n型半导体层。
可选的，所述半导体结构还包括源极和漏极，所述源极设于所述栅极的两侧，且与第二n型半导体层接触；所述漏极设于所述第一n型半导体层的底部，与所述第一n型半导体层接触。
可选的，所述半导体结构还包括源极和漏极，所述源极设于所述栅极的一侧，且与第二n型半导体层接触；所述漏极设于所述栅极的另一侧，且与所述第一n型半导体层接触。
根据本发明实施例的第二方面，提供一种半导体结构的制备方法，所 述制备方法包括：
依次形成第一n型半导体层、p型半导体层和第二n型半导体层，所述第一n型半导体层中设有掩埋层，所述掩埋层为AlGaN；
形成凹槽，所述凹槽至少贯穿所述第二n型半导体层以及所述p型半导体层，且所述凹槽的下方至少留有部分所述掩埋层；
在所述凹槽内形成栅极。
可选的，在形成栅极之前，所述制备方法还包括：
形成冒层，所述冒层形成于所述凹槽内、以及所述第二n型半导体层上；
形成介质层，所述介质层形成于所述冒层上。
上述实施例的半导体结构及其制备方法中，通过设置具有AlGaN的掩埋层，在接续高温生长其它半导体层的过程中，由于AlGaN在高温下不易分解，因此凹槽不会贯穿掩埋层，从而凹槽的深度不会低于具有AlGaN的掩埋层，而能够精确控制凹槽的深度。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本发明一示例性实施例的半导体结构的剖面结构示意图。
图2是本发明一示例性实施例的半导体结构的制备方法的流程图。
图3(a)-图3(f)是是本发明一示例性实施例的半导体封装方法的 工艺流程图。
图4是本发明一示例性实施例的半导体结构的剖面结构示意图。
图5是本发明其他示例性实施例的半导体结构的剖面结构示意图。
图6是本发明其他示例性实施例的半导体结构的剖面结构示意图。
图7是本发明其他示例性实施例的半导体结构的剖面结构示意图。
图8是本发明一示例性实施例的另一实施方式的半导体结构的剖面结构示意图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。除非另作定义，本申请使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本申请说明书以及权利要求书中使用的“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接，不管是直接的还是间接的。“多个”包括两个，相当于至少两个。在本申请说明书和所附权利要求书中所使用的单数形式的 “一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
本发明实施例提供一种半导体结构。如图1所示，所述半导体结构包括第一n型半导体层21、p型半导体层22、第二n型半导体层23、冒层28、介质层29、栅极25、源极26和漏极27。其中，所述第一n型半导体层21、所述第二n型半导体层23、所述p型半导体层22以及冒层28均包括GaN基材料。所述GaN基材料为至少包括Ga原子、N原子的材料，本实施例中，所述GaN基材料包括GaN、AlGaN、AlInGaN。
所述第一n型半导体层21是轻掺杂的n型半导体层，所谓轻掺杂即所述第一n型半导体层21中的n型杂质的掺杂浓度不超过2e17cm -3。
所述p型半导体层22以及所述第二n型半导体层23沿生长方向F层叠设置于所述第一n型半导体层21上。从所述第二n型半导体层23远离所述p型半导体层22的一侧开设有凹槽24，所述凹槽24至少贯穿所述第二n型半导体层23以及所述p型半导体层22，具体地，可以通过刻蚀的方式形成所述凹槽24，其它实施例中，也可以通过选择性生长形成所述凹槽24，对于所述凹槽24的形成方式，本案对此不做限制。刻蚀形成所述凹槽24的具体方式可为干法刻蚀。
在本实施例中，所述冒层28位于所述凹槽24内、以及所述第二n型半导体层23上；所述介质层29位于所述冒层28上，所述栅极25位于所述介质层29上。进一步的，所述栅极25还可以暴露在外形成所述T型栅极25。但不限于此，本实施例的另一种实施方式如图8所示，所述半导体结构可以不包括所述冒层28以及所述介质层29，所述栅极26可直接形成于所述凹槽24之中。
在本实施例中，所述源极26设于所述栅极25的两侧，且与所述第 二n型半导体层23接触。所述漏极27设于所述第一n型半导体层21的底部，与所述第一n型半导体层21接触，形成垂直型半导体结构。其它实施例中，如图5所示，所述源极26设于所述栅极25的一侧，且与所述第二n型半导体层23接触。所述漏极27设于所述栅极25的另一侧，且与所述第一n型半导体层21接触，形成半垂直型半导体结构。
所述第一n型半导体层21包括沿生长方向F层叠设置的第一子n型半导体层211、所述掩埋层212以及第二子n型半导体层213，所述掩埋层212为AlGaN。
所述凹槽24至少贯穿所述第二n型半导体层23以及所述p型半导体层22，且所述凹槽24的下方至少留有部分所述掩埋层212。具体来说有以下几种情况：所述凹槽的底部241可以停止于所述第二子n型半导体层213的上表面2131；或者，所述凹槽的底部241可以部分贯穿所述第二子n型半导体层213；或者，所述凹槽的底部241可以停止于所述掩埋层212的上表面2121；或者，所述凹槽的底部241可以部分贯穿所述掩埋层212。综上几种情况中，所述凹槽的底部241均未贯穿所述掩埋层212，也就是说，所述凹槽24的下方始终留有部分所述掩埋层212。这样，通过设置具有AlGaN的所述掩埋层212，在接续高温生长冒层28或者其它半导体层的过程中，由于AlGaN在高温下不易分解，因此所述凹槽24不会贯穿所述掩埋层212，从而所述凹槽24的深度不会低于所述掩埋层212，而能够精确控制所述凹槽24的深度。进一步，当对所述凹槽24的深度有具体设计要求时，可以通过设置所述掩埋层212在所述第一n型半导体层21的具体位置，而控制所述凹槽24的精确深度而满足设计要求。
本实施例中，所述AlGaN的组分保持不变；在其它实施例中，较佳地，所述掩埋层212中的Al组分沿着所述掩埋层212的生长方向F由下至上增大。具体地，所述掩埋层212中的Al组分沿着所述掩埋层212的生长方向F由下至上线性增大、或阶梯增大、或弧形增大。这样，所述掩埋 层212中的Al组分在最靠近所述第二子n型半导体层213的位置最大，而最不易在高温下分解，从而能够更好地防止所述掩埋层212在高温下分解，从而能够精确控制所述凹槽24的深度。
在本实施例中，所述掩埋层212的厚度不小于0.05微米。
进一步的，如图6所示，所述第一n型半导体层21下侧还可以设置重掺杂n型半导体层30，用于减少压降，所述重掺杂n型半导体层30中的n型杂质的掺杂浓度不小于5e17cm -3。
进一步的，如图7所示，所述半导体结构还可以包括衬底20，所述衬底20设于第一n型半导体层21的下侧，用于在其上侧形成第一n型半导体层21。
如图2所示，本实施例还提供一种半导体结构的制备方法，所述制备方法包括：
步骤100：依次形成第一n型半导体层、p型半导体层和第二n型半导体层，所述第一n型半导体层中设有掩埋层，所述掩埋层为AlGaN；
步骤200：形成凹槽，所述凹槽至少贯穿所述第二n型半导体层以及所述p型半导体层，且所述凹槽的下方至少留有部分所述掩埋层；
步骤300：形成冒层，所述冒层形成于所述凹槽内、以及所述第二n型半导体层上；
步骤400：形成介质层，所述介质层形成于所述冒层上；
步骤500：形成电极，在所述凹槽内形成栅极，所述栅极形成于所述介质层上。
在步骤100中，如图3(a)所示，沿生长方向F依次形成第一n型半导体层21、p型半导体层22和第二n型半导体层23。其中，所述第一n型半导体层21包括沿生长方向F层叠设置的第一子n型半导体层211、掩 埋层212以及第二子n型半导体层213，所述掩埋层212为AlGaN。
在步骤200中，如图3(b)和图3(c)所示，从所述第二n型半导体层23远离所述p型半导体层22的一侧形成所述凹槽24。可以通过刻蚀的方式形成所述凹槽24，但不限于此，选择性生长也可以形成所述凹槽24，对于所述凹槽24的形成方式，本案对此不做限制。刻蚀形成所述凹槽24的具体方式可为干法刻蚀。
所述凹槽24至少贯穿所述第二n型半导体层23以及所述p型半导体层22，且所述凹槽24的下方至少留有部分所述掩埋层212。具体来说有以下几种情况：所述凹槽的底部241可以停止于所述第二子n型半导体层的上表面2131；或者，所述凹槽的底部241可以部分贯穿所述第二子n型半导体层213，如图3(b)所示；或者，所述凹槽的底部241可以停止于所述掩埋层的上表面2121，如3(c)；或者，所述凹槽的底部241可以部分贯穿所述掩埋层212。综上几种情况中，所述凹槽的底部241均未贯穿所述掩埋层212，也就是说，所述凹槽24的下方始终留有部分所述掩埋层212。这样，通过设置具有AlGaN的所述掩埋层212，在接续高温生长冒层28的过程中，由于AlGaN在高温下不易分解，因此所述凹槽24不会贯穿所述掩埋层212，从而所述凹槽24的深度不会低于所述掩埋层212，而能够精确控制所述凹槽24的深度。进一步，当对所述凹槽24的深度有具体设计要求时，可以通过设置所述掩埋层212在所述第一n型半导体层21的具体位置，而控制所述凹槽24的精确深度而满足设计要求。
在步骤300中，如图3(d)所示，形成冒层28，所述冒层28形成于所述凹槽24内、以及所述第二n型半导体层23上。在形成所述冒层28中，可以采用高温生长形成所述冒层28。
在步骤400中，如图3(e)所示，形成介质层29，所述介质层29形成于所述冒层28上，同样所述介质层29也有部分位于所述凹槽24内。
在步骤500中，如图3(f)所示，形成电极，在所述凹槽24内形成栅极25，所述栅极25形成于所述介质层29上。
在形成电极中包括：如图4所示，在所述第二n型半导体层23上形成所述源极26，所述源极26设于所述栅极25的两侧，且与所述第二n型半导体层23接触；在所述第一n型半导体层21底部形成所述漏极27，所述漏极27与所述第一n型半导体层21接触，形成垂直型半导体结构。可以理解的是，当在第一n型半导体层21下侧设置重掺杂n型半导体层30时，所述漏极27还可与所述重掺杂n型半导体层30接触形成垂直型半导体结构，如图6所示。
在其它实施例中，所述电极还可以如图5所示，所述源极26设于所述栅极25的一侧，与所述第二n型半导体层23接触。所述漏极27设于所述栅极25的另一侧，与所述第一n型半导体层21接触，形成半垂直型半导体结构，具体的，可以先在栅极25一侧采用正面刻蚀方法刻蚀至露出第二n型半导体层23，形成源极26，使得源极26与所述第二n型半导体层23接触；再在栅极25另一侧采用正面刻蚀方法刻蚀至露出第一n型半导体层21，形成漏极27，使得漏极27与所述第一n型半导体层21接触。
在其它实施例中，如图6所示，所述第一n型半导体层21下侧还可以设置重掺杂n型半导体层30，可以减少压降，其中所述重掺杂n型半导体层30中的n型杂质的掺杂浓度不小于5e17cm -3。
在其他实施例中，所述制备方法还包括：在衬底20上依次形成所述第一n型半导体层21、所述p型半导体层22和所述第二n型半导体层23，如图7所示，以及，在形成所述漏极27之前，去除所述衬底20，形成如图4所述的垂直型半导体结构。可以理解的是，也可以形成如图5所示的半垂直半导体结构。在本实施例的另一实施方式中，该半导体结构的制备方法可以不包括步骤300和步骤400，即，在完成步骤200后可以直接进行步骤500的制备：形成电极，在所述凹槽内形成栅极。而通过该制备方 法而得到的半导体结构如图8所示。
上述实施例的半导体结构及其制备方法中，通过设置具有AlGaN的掩埋层，在接续高温生长其他半导体层的过程中，由于AlGaN在高温下不易分解，因此凹槽不会贯穿掩埋层，从而凹槽的深度不会低于具有AlGaN的掩埋层，而能够精确控制凹槽的深度。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。

Claims (14)

  1. 一种半导体结构，其特征在于，所述半导体结构包括：
    层叠设置的第一n型半导体层、p型半导体层以及第二n型半导体层，所述第一n型半导体层中设有掩埋层，所述掩埋层为AlGaN；
    凹槽，所述凹槽至少贯穿所述第二n型半导体层以及所述p型半导体层，且所述凹槽的下方至少留有部分所述掩埋层；
    设于凹槽内的栅极。
  2. 如权利要求1所述的半导体结构，其特征在于，所述掩埋层中的Al组分沿着所述掩埋层的生长方向由下至上增大。
  3. 如权利要求2所述的半导体结构，其特征在于，所述掩埋层中的Al组分沿着所述掩埋层的生长方向由下至上线性增大、或阶梯增大、或弧形增大。
  4. 如权利要求1所述的半导体结构，其特征在于，所述掩埋层的厚度不小于0.05微米。
  5. 如权利要求1所述的半导体结构，其特征在于，所述第一n型半导体层包括层叠设置的第一子n型半导体层、所述掩埋层以及第二子n型半导体层。
  6. 如权利要求1所述的半导体结构，其特征在于，所述第一n型半导体层、所述第二n型半导体层、以及所述p型半导体层均包括GaN基材料。
  7. 如权利要求1所述的半导体结构，其特征在于，所述半导体结构还包括冒层和介质层，所述冒层位于所述凹槽内、以及所述第二n型半导体层上；所述介质层位于所述冒层上，所述栅极位于所述介质层上。
  8. 如权利要求7所述的半导体结构，其特征在于，所述冒层的材料包括GaN基材料。
  9. 如权利要求1所述的半导体结构，其特征在于，所述第一n型半导体层为轻掺杂的n型半导体层。
  10. 如权利要求1所述的半导体结构，其特征在于，所述半导体结构还包括设于第一n型半导体层下侧的重掺杂n型半导体层。
  11. 如权利要求1所述的半导体结构，其特征在于，所述半导体结构还包括源极和漏极，所述源极设于所述栅极的两侧，且与第二n型半导体层接触；所述漏极设于所述第一n型半导体层的底部，与所述第一n型半导体层接触。
  12. 如权利要求1所述的半导体结构，其特征在于，所述半导体结构还包括源极和漏极，所述源极设于所述栅极的一侧，且与第二n型半导体层接触；所述漏极设于所述栅极的另一侧，且与所述第一n型半导体层接触。
  13. 一种半导体结构的制备方法，所述制备方法包括：
    依次形成第一n型半导体层、p型半导体层和第二n型半导体层，所述第一n型半导体层中设有掩埋层，所述掩埋层为AlGaN；
    形成凹槽，所述凹槽至少贯穿所述第二n型半导体层以及所述p型半导体层，且所述凹槽的下方至少留有部分所述掩埋层；
    在所述凹槽内形成栅极。
  14. 如权利要求13所述的半导体结构的制备方法，其特征在于，在形成栅极之前，所述制备方法还包括：
    形成冒层，所述冒层形成于所述凹槽内、以及所述第二n型半导体层上；
    形成介质层，所述介质层形成于所述冒层上。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7807531B2 (en) * 2006-05-18 2010-10-05 Nec Electronics Corporation Semiconductor device having trench-type gate and its manufacturing method capable of simplifying manufacturing steps
CN101930974A (zh) * 2009-06-17 2010-12-29 万国半导体股份有限公司 用于配置超低电压瞬态电压抑制器的底部源极n型金属氧化物半导体触发的齐纳箝位
CN106170832A (zh) * 2014-09-25 2016-11-30 克劳帕斯科技有限公司 交叉耦合晶闸管sram半导体结构及制造方法
CN108493242A (zh) * 2018-05-31 2018-09-04 电子科技大学 一种优化体内电场的载流子增强型igbt器件
CN109728084A (zh) * 2018-12-04 2019-05-07 电子科技大学 一种具有深槽电场屏蔽结构的平面栅igbt器件
CN110034176A (zh) * 2019-04-22 2019-07-19 东南大学 解决反向恢复失效的逆导型横向绝缘栅双极型晶体管

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1593151B1 (en) * 2003-01-31 2012-09-26 Nxp B.V. Trench isolation structure, semiconductor assembly comprising such a trench isolation, and method for forming such a trench isolation
JP2007311684A (ja) * 2006-05-22 2007-11-29 Mitsubishi Electric Corp 電界効果型トランジスタ
US7678654B2 (en) * 2006-06-30 2010-03-16 Qimonda Ag Buried bitline with reduced resistance
JP2009212386A (ja) * 2008-03-05 2009-09-17 Mitsubishi Electric Corp 半導体光素子の製造方法
JP2010232610A (ja) * 2009-03-30 2010-10-14 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
CN102208506B (zh) * 2010-03-30 2013-06-12 厦门乾照光电股份有限公司 掩埋式高亮度发光二极管结构
US8614478B2 (en) * 2010-07-26 2013-12-24 Infineon Technologies Austria Ag Method for protecting a semiconductor device against degradation, a semiconductor device protected against hot charge carriers and a manufacturing method therefor
DE112011104322T5 (de) * 2010-12-10 2013-10-02 Mitsubishi Electric Corporation Halbleitervorrichtung und Verfahren zur Herstellung einer Halbleitervorrichtung
US8912570B2 (en) * 2012-08-09 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. High electron mobility transistor and method of forming the same
US9412744B1 (en) * 2015-01-30 2016-08-09 International Business Machines Corporation III-V CMOS integration on silicon substrate via embedded germanium-containing layer
DE102017210711A1 (de) * 2016-06-27 2017-12-28 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Halbleiterbauelement
CN106206711B (zh) * 2016-08-22 2019-04-30 东南大学 一种P型埋层AlGaN-GaN高电子迁移率晶体管
TWI722166B (zh) * 2017-04-10 2021-03-21 聯穎光電股份有限公司 高電子遷移率電晶體
CN107623032A (zh) * 2017-10-24 2018-01-23 电子科技大学 一种新型的GaN异质结场效应晶体管

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7807531B2 (en) * 2006-05-18 2010-10-05 Nec Electronics Corporation Semiconductor device having trench-type gate and its manufacturing method capable of simplifying manufacturing steps
CN101930974A (zh) * 2009-06-17 2010-12-29 万国半导体股份有限公司 用于配置超低电压瞬态电压抑制器的底部源极n型金属氧化物半导体触发的齐纳箝位
CN106170832A (zh) * 2014-09-25 2016-11-30 克劳帕斯科技有限公司 交叉耦合晶闸管sram半导体结构及制造方法
CN108493242A (zh) * 2018-05-31 2018-09-04 电子科技大学 一种优化体内电场的载流子增强型igbt器件
CN109728084A (zh) * 2018-12-04 2019-05-07 电子科技大学 一种具有深槽电场屏蔽结构的平面栅igbt器件
CN110034176A (zh) * 2019-04-22 2019-07-19 东南大学 解决反向恢复失效的逆导型横向绝缘栅双极型晶体管

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