WO2021012359A1 - Tft驱动背板及micro-led显示器 - Google Patents

Tft驱动背板及micro-led显示器 Download PDF

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Publication number
WO2021012359A1
WO2021012359A1 PCT/CN2019/104902 CN2019104902W WO2021012359A1 WO 2021012359 A1 WO2021012359 A1 WO 2021012359A1 CN 2019104902 W CN2019104902 W CN 2019104902W WO 2021012359 A1 WO2021012359 A1 WO 2021012359A1
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Prior art keywords
layer
metal
thin film
source
base substrate
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PCT/CN2019/104902
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English (en)
French (fr)
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李恭檀
徐铉植
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/615,158 priority Critical patent/US11587955B2/en
Publication of WO2021012359A1 publication Critical patent/WO2021012359A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield

Definitions

  • This application relates to the field of display technology, and in particular to a TFT drive backplane and a Micro-LED display for large-size Micro-LED display.
  • Micro-LED technology that is, LED miniaturization and matrix technology, refers to a high-density and small-size LED array integrated on a chip. For example, each pixel of an LED display can be addressed and individually driven to light up. The millimeter level is reduced to the micron level. An important application area of Micro-LED is the display of super large size.
  • the driving backplane used by Micro-LED is a top-gate low-temperature polysilicon thin film transistor (Top Gate LTPS TFT).
  • Top Gate LTPS TFT top-gate low-temperature polysilicon thin film transistor
  • LTPS low-temperature polycrystalline silicon thin-film transistors
  • the mother glass size is small, and the production capacity is likely to encounter bottlenecks in the application of ultra-large size.
  • splicing technology is often used in large-size Micro-LED applications.
  • the edge area of the conventional panel is the area where the traces and the driver chip are connected, usually 3-50mm. Therefore, the borders during splicing will form black lines, which will affect the display effect.
  • the purpose of this application is to provide a TFT drive backplane and a Micro-LED display in view of the problems existing in the prior art, which can meet the needs of large-size Micro-LED display, reduce the frame during splicing and reduce the preparation of thin film transistor drive backplanes. The process steps of the board.
  • a TFT drive backplane which includes: a base substrate; at least one thin film transistor arranged above the base substrate, the thin film transistor including an active layer;
  • the metal light blocking layer is arranged on the lower surface of the base substrate and is positioned relative to the active layer, and the metal wiring layer is made of transparent conductive material for shielding and protecting the active layer , Wherein the length of the metal light blocking layer is greater than the length of the channel region of the active layer, the width of the metal light blocking layer is greater than the width of the channel region of the active layer, and the active
  • the channel region of the layer is aligned with the center of the metal light blocking layer;
  • a back insulating layer is provided on the lower surface of the metal light blocking layer and covers the metal light blocking layer and the lower surface of the base substrate; and
  • a metal wiring layer is provided on the side surface of the base substrate and the lower surface of the back insulating layer, and is in contact with the metal light blocking layer through a through hole formed on the back insulating layer for Connect
  • the present application also provides a TFT drive backplane, which includes: a base substrate; at least one thin film transistor disposed above the base substrate, the thin film transistor including an active layer; A metal light blocking layer is provided on the lower surface of the base substrate and is positioned opposite to the active layer for light shielding and protection of the active layer; and a metal wiring layer is provided on the The side surface of the base substrate and the bottom of the metal light blocking layer are used to connect an external driving chip.
  • the present application also provides a Micro-LED display
  • the Micro-LED display includes a TFT drive backplane
  • the TFT drive backplane includes: a base substrate; at least one thin film transistor, located in Above the base substrate, the thin film transistor includes an active layer; at least one metal light blocking layer is provided on the lower surface of the base substrate and is opposite to the active layer.
  • the line layer is made of a transparent conductive material and used to shield and protect the active layer, wherein the length of the metal light blocking layer is greater than the length of the channel region of the active layer, and the metal light blocking layer
  • the width of the active layer is greater than the width of the channel region of the active layer, and the channel region of the active layer is aligned with the center of the metal light blocking layer;
  • a back insulating layer is provided under the metal light blocking layer The surface and cover the metal light blocking layer and the lower surface of the base substrate; and a metal wiring layer, which is provided on the side surface of the base substrate and the lower surface of the back insulating layer, and is formed by The through hole on the back insulating layer is in contact with the metal light blocking layer, and is used to connect an external driving chip.
  • the present application reduces the frame of panel splicing in large-size Micro-LED applications by preparing the metal wiring layer used to connect the driver chip on the side and under the base substrate; while preparing the metal wiring layer, A metal light barrier layer for blocking ambient light is prepared on the lower surface of the base substrate relative to the position of the active layer, which can save the original metal light shielding layer deposition and patterning steps when preparing thin film transistors, and reduce The process steps for preparing the TFT driving backplane are eliminated, and the manufacturing cost is saved.
  • FIG. 1A is a schematic diagram of the layered structure of the first embodiment of the TFT driving backplane of the present application
  • FIG. 1B is a schematic diagram of the layered structure of the first embodiment of the existing TFT array substrate
  • 2A is a schematic diagram of the layered structure of the second embodiment of the TFT driving backplane of the present application.
  • 2B is a schematic diagram of the layered structure of the second embodiment of the existing TFT array substrate
  • Figure 3 is a schematic diagram of the influence of light of different wavelengths on the electrical properties of the thin film transistor.
  • the "on” or “under” of the first feature of the second feature may include the first and second features in direct contact, or may include the first and second features Not in direct contact but through other features between them.
  • “above”, “above” and “above” the second feature of the first feature include the first feature being directly above and obliquely above the second feature, or it simply means that the level of the first feature is higher than the second feature.
  • the “below”, “below” and “below” the first feature of the second feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • the TFT drive backplane includes: a base substrate; at least one thin film transistor arranged above the base substrate, The thin film transistor includes an active layer; at least one metal light blocking layer (Metal Light Shield Layer), located on the lower surface of the base substrate and relative to the active layer, for shielding and protecting the active layer; and a metal wiring layer located on the substrate
  • the side surface of the base substrate and the bottom of the metal light blocking layer are used to connect an external driving chip.
  • the thin film transistor may be a top gate oxide thin film transistor, or a top gate low temperature polysilicon thin film transistor made by using top gate low temperature polysilicon technology.
  • the thin film transistor includes a single-layer source/drain metal layer or multiple source/drain metal layers.
  • the TFT driving backplane further includes: a gate insulating layer and a gate metal layer sequentially arranged on the surface of the channel region of the active layer, the gate metal layer constituting the thin film transistor A gate; a dielectric insulating layer covering the base substrate, the active layer, the gate insulating layer and the gate metal layer; and a source/drain metal layer disposed on the dielectric On the electrically insulating layer, the source/drain metal layer constitutes the source/drain of the thin film transistor, and the source/drain is in contact with the source/drain contact area of the active layer through a through hole.
  • the driver chip can be placed on the back of the driver backplane to compress the panel frame, which can reduce the frame when panel splicing in large-size Micro-LED applications, and meet the needs of large-size Micro-LED displays.
  • the metal light blocking layer can play a role as the metal light shielding layer (Shield Metal Layer) has the same function, therefore, the metal light-shielding layer is no longer needed in the thin film transistor of the driving backplane of the present application, so that the original metal light-shielding layer deposition and patterning steps can be saved when the thin film transistor is prepared, thereby reducing the number of TFTs.
  • the process steps when driving the backplane saves the preparation cost.
  • FIGS. 1A-1B Please refer to FIGS. 1A-1B, in which FIG. 1A is a schematic diagram of the layered structure of the first embodiment of the TFT driving backplane of this application, and FIG. 1B is a schematic diagram of the layered structure of the first embodiment of the existing TFT array substrate for comparison.
  • the TFT driver backplane of the present application includes: a base substrate 100; at least one thin film transistor (the structure of which will be described in detail later) provided on the base substrate 100,
  • the thin film transistor includes an active layer (Act) 102, and the active layer 102 includes a channel region 1022; at least one metal light shield layer (Metal Light Shield Layer) 121 is disposed under the base substrate 100 The surface and the position relative to the active layer 102 are used to shield and protect the active layer 102;
  • a back insulating layer 122 is provided on the lower surface of the metal light blocking layer 121 and covers the metal light blocking layer Layer 121 and the lower surface of the base substrate 100; and a metal wiring layer 123, which is provided on the side surface of the base substrate and the lower surface of the back insulating layer 122, and is formed on the back insulating layer 122
  • the upper through hole is in contact with the metal light blocking layer 121 and is used to connect an external driving chip.
  • the metal light-blocking layer 121 is prepared at the same time as the metal wiring layer 123 is prepared on the back of the base substrate 100.
  • the metal light-blocking layer 121 can play the same role as the metal light-shielding layer in the existing thin film transistors, thereby preparing thin film transistors. At this time, the original metal shading layer deposition and patterning steps can be saved.
  • the material of the metal light blocking layer 121 is a metal having a light blocking effect, such as a composite layer composed of IZO and CuCa, or other metal materials having a light blocking effect.
  • the length and width of the metal light blocking layer 121 are both greater than the length and width of the channel region 1022 of the active layer 102, and the centers of the two are aligned, so as to effectively block ambient light to prevent the active The layer 102 performs light shielding protection.
  • the back insulating layer 122 may be a silicon oxide (SiOx) layer, or a silicon nitride (SiNx) layer, or a silicon oxynitride (SiOxNy) layer.
  • the metal wiring layer 123 is used to connect an external driving chip to transmit the driving IC signal of the external driving chip to the display area. Therefore, the driver chip can be placed on the back of the driver backplane to compress the panel frame.
  • the metal wiring layer 123 is made of transparent conductive material (ITO).
  • the present application prepares a metal light barrier layer for blocking ambient light on the lower surface of the base substrate relative to the position of the active layer while preparing the metal wiring layer, which can save costs when preparing thin film transistors.
  • the deposition and patterning steps of some metal shading layers reduce the process steps when preparing the TFT driving backplane, and save the preparation cost.
  • the thin film transistor is made using top-gate low temperature poly-silicon (LTPS) technology.
  • LTPS top-gate low temperature poly-silicon
  • the LTPS technology is to form a low-temperature polysilicon driving circuit by forming, exposing, and etching layers of different patterns and different materials to form a low-temperature polysilicon driving circuit, which provides a light-emitting device with a lighting signal and a stable power input.
  • a buffer layer (Buffer) 101 is further provided between the base substrate 100 and the active layer 102.
  • the TFT driving backplane includes: an active layer (Act) 102 disposed on the base substrate 100 (or on the buffer layer 101), and A first gate insulating layer (GI1) 103 on the active layer 102 and covering the active layer 102 and the base substrate 100 (or the buffer layer 101) is disposed on the first gate
  • a first gate metal layer (GE1) 104 on the insulating layer 103 is disposed on the first gate metal layer 104 and covers the first gate metal layer 104 and the first gate insulating layer 103
  • the first gate metal layer 104 includes a patterned gate 1041 and a first plate 1042 of the capacitor of the TFT driving backplane, and the second gate metal layer 106 includes a second plate of the capacitor.
  • Plate 1061; the active layer 102 includes a channel region 1022 corresponding to the gate 1041, and source/drain contact regions 1021 located on both sides of the channel region 1022; the first source/drain
  • the electrode metal layer 108 includes a patterned source/drain 1081, and the source/drain 1081 is in contact with the source/drain contact region 1021 through a through hole.
  • the active layer 102, the gate 1041, the source/drain 1081 constitute a thin film transistor of the TFT driving backplane.
  • the TFT driving backplane further includes: a second source/drain metal layer (S/D2) 110 disposed on the first passivation layer 109, and disposed on the A second passivation layer (VIA2) 111 on the second source/drain metal layer 110 and covering the second source/drain metal layer 110, and a third passivation layer (VIA2) provided on the second passivation layer 111
  • the source/drain metal layer (S/D3) 112, and a first transparent conductive layer (ITO1) 113 disposed on the third source/drain metal layer 112.
  • the second source/drain metal layer 110 includes an electrode connection line 1101 and a first driving power line 1102.
  • the electrode connection line 1101 and the first driving power line 1102 are connected to the source/drain electrode through corresponding through holes, respectively.
  • the drain 1081 is electrically connected.
  • the third source/drain metal layer 112 includes a patterned anode (Anode) 1121 and a second driving power line 1122, and the anode 1121 is connected to the electrode connection line 1101 through a through hole.
  • the first transparent conductive layer 112 serves as a pixel electrode.
  • the first driving power line 1102 is used to provide a voltage driving signal (VDD)
  • the second driving power line 112 is used to provide a power switch signal (VSS).
  • a third passivation layer (VIA3) 114 is provided on the second passivation layer 111, and the third passivation layer 115 is etched to expose the anode 1121 and the second passivation layer. Drive the preparation area of the power cord 1122.
  • the TFT driving backplane adopts three source/drain metal layers. It should be noted that, as the mainstream technology of LTPS, a single-layer source/drain metal layer or two or more multi-layer source/drain metal layers can adopt the improved structure of the TFT drive backplane described in this application. That is, a metal light blocking layer is provided on the back of the backplane relative to the active layer.
  • the base substrate 100 may be a glass substrate or a flexible substrate made of a high molecular polymer, and the high molecular polymer may be polyimide (PI).
  • PI polyimide
  • the buffer layer 213 may be a silicon oxide (SiOx) layer or a silicon nitride (SiNx) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the first passivation layer (VIA1) 107, the second passivation layer (VIA2) 109, and the third passivation layer (VIA3) 113 can be made of the same material.
  • the TFT array substrate in the prior art includes a base substrate 100b and a metal light-shielding layer (Shield Metal Layer) 121b, a buffer layer 101b, an active layer 102b, a first gate insulating layer (GI1) 103b, a first gate metal layer (GE1) 104b, a second gate insulating layer (GI2) 105b, a second gate metal layer (GE2) 106b, a dielectric insulating layer (ILD) 107b, a first source/drain metal layer (S/D1) 108b, and a first passivation layer (VIA1) 109b .
  • a metal light-shielding layer shield Metal Layer
  • the driving backplane using the TFT array substrate in the prior art further includes: a second source/drain metal layer (S/D2) 110b and a second passivation layer 109b stacked in sequence on the first passivation layer 109b.
  • FIGS. 2A-2B are schematic diagram of the layered structure of the second embodiment of the TFT driving backplane of this application, and FIG. 2B is a schematic diagram of the layered structure of the second embodiment of the existing TFT array substrate for comparison.
  • the thin film transistor in this embodiment is a top gate oxide thin film transistor.
  • the TFT driving backplane includes: a base substrate 200 disposed on the base substrate 200 (or a buffer layer 201 prepared on the base substrate 200) Above) an active layer (Act) 202, a gate insulating layer (GI) 203 disposed on the active layer 202, a gate metal layer (GE) disposed on the gate insulating layer 203 ) 204, disposed on the gate metal layer 204 and covering the gate metal layer 204, the gate insulating layer 203, the active layer 202 and the base substrate 200 (or buffer layer 201)
  • the layer 206 is on and covers the first source/drain metal layer 206 and a first passivation layer (VIA1) 207 of the dielectric insulating layer 205.
  • the gate metal layer 204 includes a patterned gate 2041; the active layer 202 includes a channel region 2022 corresponding to the gate 2041, and source/drain electrodes located on both sides of the channel region 2022 Contact area 2021; the first source/drain metal layer 206 includes a patterned source/drain 2061, and the source/drain 2061 is in contact with the source/drain contact area 2021 through a through hole.
  • the active layer 202, the gate 2041, the source/drain 2061 constitute a thin film transistor of the TFT driving backplane.
  • the TFT driving backplane further includes: a second source/drain metal layer (S/D2) 208 disposed on the first passivation layer 207, which is disposed on the A second passivation layer (VIA2) 209 on the second source/drain metal layer 208 and covering the second source/drain metal layer 208, and a third passivation layer (VIA2) 209 disposed on the second passivation layer 209
  • the second source/drain metal layer 208 includes an electrode connection line 2081 and a first driving power line 2082.
  • the electrode connection line 2081 and the first driving power line 2082 are connected to the source/drain electrode through corresponding through holes respectively.
  • the drain 2061 is electrically connected.
  • the third source/drain metal layer 210 includes a patterned anode (Anode) 2101 and a second driving power line 2102, and the anode 2101 is connected to the electrode connection line 2081 through a through hole.
  • the first transparent conductive layer 211 serves as a pixel electrode.
  • the first drive power line 2082 is used to provide a voltage drive signal (VDD)
  • the second drive power line 2102 is used to provide a power switch signal (VSS).
  • the third source/drain metal layer 111 may also include a cathode.
  • a third passivation layer (VIA3) 212 is provided on the second passivation layer 209, and the third passivation layer 212 is etched to expose the anode 2101 and the second passivation layer. Drive the preparation area of the power cord 2102.
  • the TFT driving backplane adopts three source/drain metal layers. It should be noted that a single-layer source/drain metal layer or two or more multi-layer source/drain metal layers can adopt the improved structure of the TFT drive backplane described in this application, that is, the backplane is opposite to the backplane.
  • a metal light blocking layer is arranged at the position of the active layer.
  • a metal light shield layer (Metal Light Shield Layer) 221 is provided on the lower surface of the base substrate 200 relative to the active layer 202 to shield and protect the active layer 102; a back surface An insulating layer 222 is disposed on the lower surface of the metal light blocking layer 221 and covers the metal light blocking layer 221 and the lower surface of the base substrate 200; and a metal wiring layer 223 is disposed on the base substrate 200 And the bottom surface of the back insulating layer 222, and contact the metal light blocking layer 221 through the through holes formed on the back insulating layer 222 for connecting to an external driving chip. That is, the metal light-blocking layer 221 is prepared at the same time as the metal wiring layer 223 is prepared on the back surface of the base substrate 200.
  • the metal light-blocking layer 221 can play the same role as the metal light-shielding layer in the existing thin film transistors, thereby preparing thin film transistors. At this time, the original metal shading layer deposition and patterning steps can be saved.
  • the TFT array substrate in the prior art includes a base substrate 200b and a metal light-shielding layer (Shield Metal Layer) 221b, a buffer layer 201b, an active layer 202b, a gate insulating layer (GI) 203b, a gate metal layer (GE) 204b, a dielectric insulating layer (ILD) 205b, a first source /Drain metal layer (S/D1) 206b and a first passivation layer (VIA1) 207b.
  • a metal light-shielding layer shield Metal Layer
  • GI gate insulating layer
  • GE gate metal layer
  • ILD dielectric insulating layer
  • S/D1 first source /Drain metal layer
  • VIPA1 first passivation layer
  • the driving backplane using the TFT array substrate in the prior art further includes: a second source/drain metal layer (S/D2) 208b and a second passivation layer 207b stacked in sequence on the first passivation layer 207b Layer (VIA2) 209b, a third source/drain metal layer (S/D3) 210b, a first transparent conductive layer (ITO1) 211b, and a third passivation layer (VIA3) 212b. That is, in the prior art, when the thin film transistor is prepared, the deposition and patterning steps of the metal light-shielding layer are required.
  • FIG. 3 a schematic diagram of the influence of light of different wavelengths on the electrical properties of the thin film transistor.
  • the abscissa is the gate voltage V GS (unit is volt (V))
  • the ordinate is the source/drain current I DS (unit is ampere (A))
  • the curve in the figure is used to indicate the wavelength ( ⁇ ) is the influence of light from 365 nm to 700 nm on the electrical properties of thin film transistors. It can be seen from the figure that light from 365 nm to 700 nm has a significant impact on the electrical characteristics of thin film transistor devices.
  • the TFT driver backplane of the present application is prepared by preparing the metal wiring layer while on the substrate
  • the metal light barrier layer for blocking ambient light is prepared on the lower surface and relative to the position of the active layer, which can improve the resistance of the thin film transistor device to ambient light, thereby saving the original metal shading when preparing the thin film transistor
  • the layer deposition and patterning steps reduce the process steps when preparing the TFT driving backplane and save the preparation cost.
  • the present application also provides a Micro-LED display.
  • the Micro-LED display includes a TFT drive backplane, and the TFT drive backplane adopts the TFT drive backplane described in the present application.
  • the Micro-LED display of the present application adopts a metal light barrier layer for blocking ambient light on the lower surface of the base substrate and at a position relative to the active layer while preparing the metal wiring layer, which can achieve large size Micro-LED display requirements reduce the frame of panel splicing in large-size Micro-LED applications, and save the original metal shading layer deposition and patterning steps when preparing thin film transistors, reducing the preparation of TFT driver back The process steps of the board save the preparation cost.
  • the subject of this application can be manufactured and used in industry and has industrial applicability.

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Abstract

一种TFT驱动背板及Micro-LED显示器，通过在衬底基板（100，200）的侧面以及下方制备用于连接驱动芯片的金属走线层（123，223），减少了大尺寸的Micro-LED应用中面板拼接时边框；通过在制备金属走线层（123，223）的同时，在衬底基板（100，200）的下表面并相对于有源层（102，202）的位置制备用于阻挡环境光的金属光阻挡层（121，221），可以在制备薄膜晶体管的时候节省原有金属遮光层的沉积和图形化步骤。

Description

TFT驱动背板及Micro-LED显示器 技术领域
本申请涉及显示技术领域，尤其涉及一种用于大尺寸的Micro-LED显示的TFT驱动背板及Micro-LED显示器。
 背景技术
Micro-LED技术，即LED微缩化和矩阵化技术，是指在一个芯片上集成的高密度微小尺寸的LED阵列，如LED显示屏每一个像素可定址、单独驱动点亮，将像素点距离从毫米级降低至微米级。Micro-LED的一个重要应用领域是超大尺寸的显示。
 技术问题
目前，Micro-LED所用的驱动背板为顶栅低温多晶硅薄膜晶体管(Top Gate LTPS TFT)。目前低温多晶体硅薄膜晶体管(LTPS)仅能在6代线(玻璃尺寸1.5米×1.85米)进行生产，母板玻璃尺寸较小，在针对超大尺寸的应用方面产能容易遇到瓶颈。
另外，在大尺寸的Micro-LED应用中多采用拼接技术。常规面板的边缘区域为走线和与驱动芯片连接的区域，通常为3-50mm。因此在拼接时的边框会形成黑线，影响显示效果。
因此，如何减少拼接时的边框并减少制备薄膜晶体管驱动背板时的工艺步骤，是目前面向Micro-LED显示应用技术发展急需解决的技术问题。
 技术解决方案
本申请的目的在于，针对现有技术存在的问题，提供一种TFT驱动背板及Micro-LED显示器，可以实现满足大尺寸Micro-LED显示需求，减少拼接时的边框并减少制备薄膜晶体管驱动背板时的工艺步骤。
为实现上述目的，本申请提供了一种TFT驱动背板，包括：一衬底基板；至少一薄膜晶体管，设于所述衬底基板的上方，所述薄膜晶体管包括一有源层；至少一金属光阻挡层，设于所述衬底基板的下表面并相对于所述有源层的位置，所述金属走线层采用透明导电材料制成，用于对所述有源层进行遮光保护，其中，所述金属光阻挡层的长度大于所述有源层的沟道区的长度，所述金属光阻挡层的宽度大于所述有源层的沟道区的宽度，且所述有源层的沟道区与所述金属光阻挡层中心对齐；一背面绝缘层，设于所述金属光阻挡层的下表面并覆盖所述金属光阻挡层及所述衬底基板的下表面；以及一金属走线层，设于所述衬底基板的侧面以及所述背面绝缘层的下表面，并通过形成在所述背面绝缘层上的通孔与所述金属光阻挡层相接触，用于连接外部驱动芯片。
为实现上述目的，本申请还提供了一种TFT驱动背板，包括：一衬底基板；至少一薄膜晶体管，设于所述衬底基板的上方，所述薄膜晶体管包括一有源层；至少一金属光阻挡层，设于所述衬底基板的下表面并相对于所述有源层的位置，用于对所述有源层进行遮光保护；以及一金属走线层，设于所述衬底基板的侧面以及所述金属光阻挡层的下方，用于连接外部驱动芯片。
为实现上述目的，本申请还提供了一种Micro-LED显示器，所述Micro-LED显示器包括一TFT驱动背板，所述TFT驱动背板包括：一衬底基板；至少一薄膜晶体管，设于所述衬底基板的上方，所述薄膜晶体管包括一有源层；至少一金属光阻挡层，设于所述衬底基板的下表面并相对于所述有源层的位置，所述金属走线层采用透明导电材料制成，用于对所述有源层进行遮光保护，其中，所述金属光阻挡层的长度大于所述有源层的沟道区的长度，所述金属光阻挡层的宽度大于所述有源层的沟道区的宽度，且所述有源层的沟道区与所述金属光阻挡层中心对齐；一背面绝缘层，设于所述金属光阻挡层的下表面并覆盖所述金属光阻挡层及所述衬底基板的下表面；以及一金属走线层，设于所述衬底基板的侧面以及所述背面绝缘层的下表面，并通过形成在所述背面绝缘层上的通孔与所述金属光阻挡层相接触，用于连接外部驱动芯片。
 有益效果
本申请通过在衬底基板的侧面以及下方制备用于连接驱动芯片的金属走线层，减少了大尺寸的Micro-LED应用中面板拼接时的边框；通过在制备金属走线层的同时，在衬底基板的下表面并相对于所述有源层的位置制备用于阻挡环境光的金属光阻挡层，可以在制备薄膜晶体管的时候节省原有的金属遮光层的沉积和图形化步骤，减少了制备TFT驱动背板时的工艺步骤，节约制备成本。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1A，本申请TFT驱动背板第一实施例的层状结构示意图；
图1B，现有TFT阵列基板第一实施例的层状结构示意图；
图2A，本申请TFT驱动背板第二实施例的层状结构示意图；
图2B，现有TFT阵列基板第二实施例的层状结构示意图；
图3，不同波长的光对薄膜晶体管电性的影响示意图。
 本发明的实施方式
下面详细描述本申请的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。
本申请的说明书和权利要求书以及附图中的术语“第一”、“第二”、“第三”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序，应当理解，这样描述的对象在适当情况下可以互换。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
本申请提出了一种新型的适用于大尺寸Micro-LED应用的TFT驱动背板，所述TFT驱动背板包括：一衬底基板；至少一薄膜晶体管，设于所述衬底基板的上方，所述薄膜晶体管包括一有源层；至少一金属光阻挡层(Metal Light Shield Layer)，设于所述衬底基板的下表面并相对于所述有源层的位置，用于对所述有源层进行遮光保护；以及一金属走线层，设于所述衬底基板的侧面以及所述金属光阻挡层的下方，用于连接外部驱动芯片。
可选地，所述薄膜晶体管可以为顶栅氧化物薄膜晶体管，或采用顶栅低温多晶硅技术制成的顶栅低温多晶硅薄膜晶体管。
可选地，所述薄膜晶体管包括单层源/漏金属层或多层源/漏金属层。
具体的，所述TFT驱动背板进一步包括：依次设于所述有源层的沟道区表面的一栅极绝缘层及一栅极金属层，所述栅极金属层构成所述薄膜晶体管的栅极；一介电绝缘层，覆盖所述衬底基板、所述有源层、所述栅极绝缘层及所述栅极金属层；以及一源/漏极金属层，设于所述介电绝缘层上，所述源/漏极金属层构成所述薄膜晶体管的源/漏极，所述源/漏极通过通孔与所述有源层的源/漏极接触区相接触。
采用本申请TFT驱动背板，可以将驱动芯片放置在驱动背板的背面，以压缩面板边框，可以减少大尺寸的Micro-LED应用中面板拼接时的边框，满足大尺寸Micro-LED显示需求。同时，金属光阻挡层能够起到与现有薄膜晶体管中金属遮光层(Shield Metal Layer)相同的作用，因此本申请驱动背板的薄膜晶体管中不再需要金属遮光层，从而在制备薄膜晶体管的时候可以节省原有的金属遮光层的沉积和图形化步骤，进而减少制备TFT驱动背板时的工艺步骤，节约制备成本。
请参阅图1A-1B，其中图1A为本申请TFT驱动背板第一实施例的层状结构示意图，图1B现有TFT阵列基板第一实施例的层状结构示意图作为对比。
如图1A所示，在本实施例中，本申请TFT驱动背板包括：一衬底基板100；至少一设于所述衬底基板100上方的薄膜晶体管（其结构在后文详述），所述薄膜晶体管包括一有源层(Act)102，所述有源层102包括沟道区1022；至少一金属光阻挡层(Metal Light Shield Layer)121，设于所述衬底基板100的下表面并相对于所述有源层102的位置，用于对所述有源层102进行遮光保护；一背面绝缘层122，设于所述金属光阻挡层121下表面并覆盖所述金属光阻挡层121及所述衬底基板100下表面；以及一金属走线层123，设于所述衬底基板的侧面以及所述背面绝缘层122的下表面，并通过形成在所述背面绝缘层122上的通孔与所述金属光阻挡层121相接触，用于连接外部驱动芯片。即，在衬底基板100的背面制备金属走线层123的同时制备金属光阻挡层121，金属光阻挡层121能够起到与现有薄膜晶体管中金属遮光层相同的作用，从而在制备薄膜晶体管的时候可以节省原有的金属遮光层的沉积和图形化步骤。
具体的，所述金属光阻挡层121的材料为具有光阻挡作用的金属，例如IZO、CuCa叠加构成的复合层，也可以为其它具有光阻挡作用的金属材料。优选的，所述金属光阻挡层121的长度和宽度均大于所述有源层102的沟道区1022的长度和宽度，且两者中心对齐，从而有效阻挡环境光，以对所述有源层102进行遮光保护。
具体的，所述背面绝缘层122可以为氧化硅(SiOx)层，或氮化硅(SiNx)层，或氮氧化硅(SiOxNy)层。
具体的，所述金属走线层123用于连接外部驱动芯片，以传输外部驱动芯片的驱动IC信号到显示区域。从而可以将驱动芯片放置在驱动背板的背面，以压缩面板边框。优选地，金属走线层123采用透明导电材料(ITO)制成。
本申请通过在制备金属走线层的同时，在衬底基板的下表面并相对于所述有源层的位置制备用于阻挡环境光的金属光阻挡层，可以在制备薄膜晶体管的时候节省原有的金属遮光层的沉积和图形化步骤，减少了制备TFT驱动背板时的工艺步骤，节约制备成本。
在本实施例中，所述薄膜晶体管采用顶栅低温多晶硅(Low Temperature Poly-silicon，简称LTPS)技术制成。LTPS技术是通过成膜、曝光、蚀刻叠加不同图形不同材质的膜层以形成低温多晶硅驱动电路，其为发光器件提供点亮信号以及稳定的电源输入。
优选地，在本实施例中，衬底基板100与有源层102之间还设有缓冲层(Buffer)101。
具体的，在本实施例中，所述TFT驱动背板包括：设于所述衬底基板100上（或设于所述缓冲层101上）的一有源层(Act)102，设于所述有源层102上并覆盖所述有源层102及所述衬底基板100（或所述缓冲层101）的一第一栅极绝缘层(GI1)103，设于所述第一栅极绝缘层103上的一第一栅极金属层(GE1)104，设于所述第一栅极金属层104上并覆盖所述第一栅极金属层104及所述第一栅极绝缘层103的一第二栅极绝缘层(GI2)105，设于所述第二栅极绝缘层105上的一第二栅极金属层(GE2)106，设于所述第二栅极金属层106上并覆盖所述第二栅极金属层106及所述第二栅极绝缘层105的一介电绝缘层107，设于所述介电绝缘层107上的一第一源/漏极金属层(S/D1)108，以及设于所述第一源/漏极金属层108上并覆盖所述第一源/漏极金属层108及所述介电绝缘层107的一第一钝化层(VIA1)109。
所述第一栅极金属层104包括图案化的栅极1041以及所述TFT驱动背板的电容的一第一极板1042，所述第二栅极金属层106包括所述电容的一第二极板1061；所述有源层102包括对应于所述栅极1041的沟道区1022，及位于所述沟道区1022两侧的源/漏极接触区1021；所述第一源/漏极金属层108包括图案化的源/漏极1081，所述源/漏极1081通过通孔与所述源/漏极接触区1021相接触。所述有源层102、所述栅极1041、所述源/漏极1081构成所述TFT驱动背板的薄膜晶体管。
优选地，在本实施例中，所述TFT驱动背板还包括：设于所述第一钝化层109上的一第二源/漏极金属层(S/D2)110，设于所述第二源/漏极金属层110上并覆盖所述第二源/漏极金属层110的一第二钝化层(VIA2)111，设于所述第二钝化层111上的一第三源/漏极金属层(S/D3)112，以及设于所述第三源/漏极金属层112上的一第一透明导电层(ITO1)113。所述第二源/漏极金属层110包括电极连接线1101及第一驱动电源线1102，所述电极连接线1101及所述第一驱动电源线1102分别通过相应的通孔与所述源/漏极1081电连接。所述第三源/漏极金属层112包括图案化的阳极(Anode)1121及第二驱动电源线1122，所述阳极1121通过通孔与所述电极连接线1101相连接。所述第一透明导电层112作为像素电极。本实施例中，所述第一驱动电源线1102用于提供电压驱动信号(VDD)，所述第二驱动电源线112用于提供电源开关信号(VSS)。
本实施例中，所述第二钝化层111上设有一第三钝化层(VIA3)114，通过对所述第三钝化层115蚀刻，以暴露出所述阳极1121及所述第二驱动电源线1122的制备区域。
在本实施例中，所述TFT驱动背板采用三层源/漏金属层。需要说明的是，作为LTPS的主流技术，采用单层源/漏金属层或两层及以上的多层源/漏金属层都是可以采用改进后的本申请所述TFT驱动背板的结构，即在背板背面相对于有源层位置设置一层金属光阻挡层。
具体的，所述衬底基板100可以玻璃基板或采用高分子聚合物制备的柔性基板，高分子聚合物可以为聚酰亚胺(PI)。
具体的，所述缓冲层213可以为氧化硅(SiOx)层或氮化硅(SiNx)层，或者由氧化硅层与氮化硅层叠加构成的复合层。
具体的，所述第一钝化层(VIA1)107、第二钝化层(VIA2)109、第三钝化层(VIA3)113可以采用相同材料制成。
作为对比，如图1B所示，现有技术中TFT阵列基板包括依次层叠设置的一衬底基板100b、一金属遮光层(Shield Metal Layer)121b、一缓冲层101b、一有源层102b、一第一栅极绝缘层(GI1)103b、一第一栅极金属层(GE1)104b、一第二栅极绝缘层(GI2)105b、一第二栅极金属层(GE2)106b、一介电绝缘层(ILD)107b、一第一源/漏极金属层(S/D1)108b以及一第一钝化层(VIA1)109b。采用现有技术中TFT阵列基板的驱动背板还包括：在所述第一钝化层109b上依次层叠设置的一第二源/漏极金属层(S/D2)110b、一第二钝化层(VIA2)111b、一第三源/漏极金属层(S/D3)112b、一第一透明导电层(ITO1)113b、以及一第三钝化层(VIA3)114b。也即，现有技术中，在制备薄膜晶体管的时候，需要金属遮光层的沉积和图形化步骤。
请参阅图2A-2B，其中图2A为本申请TFT驱动背板第二实施例的层状结构示意图，图2B现有TFT阵列基板第二实施例的层状结构示意图作为对比。与图1A所示实施例的不同之处在于，在本实施例中所述薄膜晶体管为顶栅氧化物薄膜晶体管。
具体的，如图2A所示，所述TFT驱动背板包括：一衬底基板200，设于所述衬底基板200上（或设于制备在所述衬底基板200上的一缓冲层201上）的一有源层(Act)202，设于所述有源层202上的一栅极绝缘层(GI)203，设于所述栅极绝缘层203上的一栅极金属层(GE)204，设于所述栅极金属层204上并覆盖所述栅极金属层204、所述栅极绝缘层203、所述有源层202及所述衬底基板200（或缓冲层201）的一介电绝缘层(ILD)205，设于所述介电绝缘层205上的一第一源/漏极金属层(S/D1)206，以及设于所述第一源/漏极金属层206上并覆盖所述第一源/漏极金属层206及所述介电绝缘层205的一第一钝化层(VIA1)207。
所述栅极金属层204包括图案化的栅极2041；所述有源层202包括对应于所述栅极2041的沟道区2022，及位于所述沟道区2022两侧的源/漏极接触区2021；所述第一源/漏极金属层206包括图案化的源/漏极2061，所述源/漏极2061通过通孔与所述源/漏极接触区2021相接触。所述有源层202、所述栅极2041、所述源/漏极2061构成所述TFT驱动背板的薄膜晶体管。
优选地，在本实施例中，所述TFT驱动背板还包括：设于所述第一钝化层207上的一第二源/漏极金属层(S/D2)208，设于所述第二源/漏极金属层208上并覆盖所述第二源/漏极金属层208的一第二钝化层(VIA2)209，设于所述第二钝化层209上的一第三源/漏极金属层(S/D3)210，以及设于所述第三源/漏极金属层210上的一第一透明导电层(ITO1)211。
所述第二源/漏极金属层208包括电极连接线2081及第一驱动电源线2082，所述电极连接线2081及所述第一驱动电源线2082分别通过相应的通孔与所述源/漏极2061电连接。所述第三源/漏极金属层210包括图案化的阳极(Anode)2101及第二驱动电源线2102，所述阳极2101通过通孔与所述电极连接线2081相连接。所述第一透明导电层211作为像素电极。本实施例中，所述第一驱动电源线2082用于提供电压驱动信号(VDD)，所述第二驱动电源线2102用于提供电源开关信号(VSS)。在其它实施例中，所述第三源/漏极金属层111也可以包括阴极。
本实施例中，所述第二钝化层209上设有一第三钝化层(VIA3)212，通过对所述第三钝化层212蚀刻，以暴露出所述阳极2101及所述第二驱动电源线2102的制备区域。
在本实施例中，所述TFT驱动背板采用三层源/漏金属层。需要说明的是，采用单层源/漏金属层或两层及以上的多层源/漏金属层都是可以采用改进后的本申请所述TFT驱动背板的结构，即在背板背面相对于有源层位置设置一层金属光阻挡层。
所述衬底基板200的下表面并相对于所述有源层202的位置，设有一金属光阻挡层(Metal Light Shield Layer)221，用于对所述有源层102进行遮光保护；一背面绝缘层222，设于所述金属光阻挡层221下表面并覆盖所述金属光阻挡层221及所述衬底基板200下表面；以及一金属走线层223，设于所述衬底基板200的侧面以及所述背面绝缘层222的下表面，并通过形成在所述背面绝缘层222上的通孔与所述金属光阻挡层221相接触，用于连接外部驱动芯片。即，在衬底基板200的背面制备金属走线层223的同时制备金属光阻挡层221，金属光阻挡层221能够起到与现有薄膜晶体管中金属遮光层相同的作用，从而在制备薄膜晶体管的时候可以节省原有的金属遮光层的沉积和图形化步骤。
作为对比，如图2B所示，现有技术中TFT阵列基板包括依次层叠设置的一衬底基板200b、一金属遮光层(Shield Metal Layer)221b、一缓冲层201b、一有源层202b、一栅极绝缘层(GI)203b、一栅极金属层(GE)204b、一介电绝缘层(ILD)205b、一第一源/漏极金属层(S/D1)206b以及一第一钝化层(VIA1)207b。采用现有技术中TFT阵列基板的驱动背板还包括：在所述第一钝化层207b上依次层叠设置的一第二源/漏极金属层(S/D2)208b、一第二钝化层(VIA2)209b、一第三源/漏极金属层(S/D3)210b、一第一透明导电层(ITO1)211b、以及一第三钝化层(VIA3)212b。也即，现有技术中，在制备薄膜晶体管的时候，需要金属遮光层的沉积和图形化步骤。
请参阅图3，不同波长的光对薄膜晶体管电性的影响示意图。如图2所示，横坐标为栅极电压V GS(单位为伏特(V))，纵坐标为源/漏极电流I DS(单位为安培(A))，图中曲线用于示意波长（λ）为365 nm到700 nm的光对薄膜晶体管电性的影响。由图示可以看出，365 nm到700 nm的光对薄膜晶体管器件的电性特性具有明显的影响，而本申请TFT驱动背板，通过在制备金属走线层的同时，在衬底基板的下表面并相对于所述有源层的位置制备用于阻挡环境光的金属光阻挡层，可以提升薄膜晶体管器件对环境光的抵抗能力，从而可以在制备薄膜晶体管的时候节省原有的金属遮光层的沉积和图形化步骤，减少了制备TFT驱动背板时的工艺步骤，节约制备成本。
基于同一发明构思，本申请还提供了一种Micro-LED显示器，所述Micro-LED显示器包括一TFT驱动背板，所述TFT驱动背板采用本申请上述的TFT驱动背板。本申请Micro-LED显示器采用在制备金属走线层的同时，在衬底基板的下表面并相对于所述有源层的位置制备用于阻挡环境光的金属光阻挡层，可以实现满足大尺寸Micro-LED显示需求，减少了大尺寸的Micro-LED应用中面板拼接时的边框，且在制备薄膜晶体管的时候可以节省原有的金属遮光层的沉积和图形化步骤，减少了制备TFT驱动背板时的工艺步骤，节约制备成本。
 工业实用性
本申请的主题可以在工业中制造和使用，具备工业实用性。

Claims (20)

  1. 一种TFT驱动背板，其中，包括：一衬底基板；至少一薄膜晶体管，设于所述衬底基板的上方，所述薄膜晶体管包括一有源层；至少一金属光阻挡层，设于所述衬底基板的下表面并相对于所述有源层的位置，所述金属走线层采用透明导电材料制成，用于对所述有源层进行遮光保护，并且其中，所述金属光阻挡层的长度大于所述有源层的沟道区的长度，所述金属光阻挡层的宽度大于所述有源层的沟道区的宽度，且所述有源层的沟道区与所述金属光阻挡层中心对齐；一背面绝缘层，设于所述金属光阻挡层的下表面并覆盖所述金属光阻挡层及所述衬底基板的下表面；以及一金属走线层，设于所述衬底基板的侧面以及所述背面绝缘层的下表面，并通过形成在所述背面绝缘层上的通孔与所述金属光阻挡层相接触，用于连接外部驱动芯片。
  2. 如权利要求1所述的TFT驱动背板，其中，所述薄膜晶体管为顶栅氧化物薄膜晶体管。
  3. 如权利要求1所述的TFT驱动背板，其中，所述薄膜晶体管采用顶栅低温多晶硅技术制成。
  4. 如权利要求1所述的TFT驱动背板，其中，所述薄膜晶体管包括单层源/漏金属层或多层源/漏金属层。
  5. 如权利要求1所述的TFT驱动背板，其中，所述TFT驱动背板进一步包括：依次设于所述有源层的沟道区表面的一栅极绝缘层及一栅极金属层，所述栅极金属层构成所述薄膜晶体管的栅极；一介电绝缘层，覆盖所述衬底基板、所述有源层、所述栅极绝缘层及所述栅极金属层；以及一源/漏极金属层，设于所述介电绝缘层上，所述源/漏极金属层构成所述薄膜晶体管的源/漏极，所述源/漏极通过通孔与所述有源层的源/漏极接触区相接触。
  6. 如权利要求1所述的TFT驱动背板，其中，所述TFT驱动背板进一步包括：设于所述有源层及所述衬底基板之间的一缓冲层。
  7. 一种TFT驱动背板，其中，包括：一衬底基板；至少一薄膜晶体管，设于所述衬底基板的上方，所述薄膜晶体管包括一有源层；至少一金属光阻挡层，设于所述衬底基板的下表面并相对于所述有源层的位置，用于对所述有源层进行遮光保护；以及一金属走线层，设于所述衬底基板的侧面以及所述金属光阻挡层的下方，用于连接外部驱动芯片。
  8. 如权利要求7所述的TFT驱动背板，其中，所述金属光阻挡层的长度大于所述有源层的沟道区的长度，所述金属光阻挡层的宽度大于所述有源层的沟道区的宽度，且所述有源层的沟道区与所述金属光阻挡层中心对齐。
  9. 如权利要求7所述的TFT驱动背板，其中，所述TFT驱动背板进一步包括：一背面绝缘层，设于所述金属光阻挡层的下表面并覆盖所述金属光阻挡层及所述衬底基板的下表面；所述金属走线层设于所述衬底基板的侧面以及所述背面绝缘层的下表面，并通过形成在所述背面绝缘层上的通孔与所述金属光阻挡层相接触。
  10. 如权利要求7所述的TFT驱动背板，其中，所述金属走线层采用透明导电材料制成。
  11. 如权利要求7所述的TFT驱动背板，其中，所述薄膜晶体管为顶栅氧化物薄膜晶体管。
  12. 如权利要求7所述的TFT驱动背板，其中，所述薄膜晶体管采用顶栅低温多晶硅技术制成。
  13. 如权利要求7所述的TFT驱动背板，其中，所述薄膜晶体管包括单层源/漏金属层或多层源/漏金属层。
  14. 如权利要求7所述的TFT驱动背板，其中，所述TFT驱动背板进一步包括：依次设于所述有源层的沟道区表面的一栅极绝缘层及一栅极金属层，所述栅极金属层构成所述薄膜晶体管的栅极；一介电绝缘层，覆盖所述衬底基板、所述有源层、所述栅极绝缘层及所述栅极金属层；以及一源/漏极金属层，设于所述介电绝缘层上，所述源/漏极金属层构成所述薄膜晶体管的源/漏极，所述源/漏极通过通孔与所述有源层的源/漏极接触区相接触。
  15. 如权利要求7所述的TFT驱动背板，其中，所述TFT驱动背板进一步包括：设于所述有源层及所述衬底基板之间的一缓冲层。
  16. 一种Micro-LED显示器，其中，所述Micro-LED显示器包括一起TFT驱动背板，所述TFT驱动背板包括：一衬底基板；至少一薄膜晶体管，设于所述衬底基板的上方，所述薄膜晶体管包括一有源层；至少一金属光阻挡层，设于所述衬底基板的下表面并相对于所述有源层的位置，所述金属走线层采用透明导电材料制成，用于对所述有源层进行遮光保护，并且其中，所述金属光阻挡层的长度大于所述有源层的沟道区的长度，所述金属光阻挡层的宽度大于所述有源层的沟道区的宽度，且所述有源层的沟道区与所述金属光阻挡层中心对齐；一背面绝缘层，设于所述金属光阻挡层的下表面并覆盖所述金属光阻挡层及所述衬底基板的下表面；以及一金属走线层，设于所述衬底基板的侧面以及所述背面绝缘层的下表面，并通过形成在所述背面绝缘层上的通孔与所述金属光阻挡层相接触，用于连接外部驱动芯片。
  17. 如权利要求16所述的显示器，其中，所述薄膜晶体管采用顶栅低温多晶硅技术制成。
  18. 如权利要求16所述的显示器，其中，所述薄膜晶体管包括单层源/漏金属层或多层源/漏金属层。
  19. 如权利要求16所述的显示器，其中，所述TFT驱动背板进一步包括：依次设于所述有源层的沟道区表面的一栅极绝缘层及一栅极金属层，所述栅极金属层构成所述薄膜晶体管的栅极；一介电绝缘层，覆盖所述衬底基板、所述有源层、所述栅极绝缘层及所述栅极金属层；以及一源/漏极金属层，设于所述介电绝缘层上，所述源/漏极金属层构成所述薄膜晶体管的源/漏极，所述源/漏极通过通孔与所述有源层的源/漏极接触区相接触。
  20. 如权利要求16所述的显示器，其中，所述TFT驱动背板进一步包括：设于所述有源层及所述衬底基板之间的一缓冲层。
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