CN110047899B - 显示面板、显示装置及制造方法 - Google Patents
显示面板、显示装置及制造方法 Download PDFInfo
- Publication number
- CN110047899B CN110047899B CN201910345749.2A CN201910345749A CN110047899B CN 110047899 B CN110047899 B CN 110047899B CN 201910345749 A CN201910345749 A CN 201910345749A CN 110047899 B CN110047899 B CN 110047899B
- Authority
- CN
- China
- Prior art keywords
- hole
- display
- conductive structure
- layer
- base plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 149
- 238000000034 method Methods 0.000 claims description 33
- 230000008569 process Effects 0.000 claims description 17
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 15
- 230000004888 barrier function Effects 0.000 claims description 11
- 239000004642 Polyimide Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 229920001721 polyimide Polymers 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 115
- 238000010586 diagram Methods 0.000 description 13
- 230000005611 electricity Effects 0.000 description 12
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- 238000005538 encapsulation Methods 0.000 description 6
- 238000000059 patterning Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- 238000005553 drilling Methods 0.000 description 4
- 238000005224 laser annealing Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004568 cement Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133305—Flexible substrates, e.g. plastics, organic film
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/13338—Input devices, e.g. touch panels
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
- G06V40/13—Sensors therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
- G06V40/13—Sensors therefor
- G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/126—Shielding, e.g. light-blocking means over the TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
- H10K59/65—OLEDs integrated with inorganic image sensors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/32237—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45139—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Manufacturing & Machinery (AREA)
- Inorganic Chemistry (AREA)
- Theoretical Computer Science (AREA)
- Multimedia (AREA)
- Human Computer Interaction (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Development (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
本发明公开了一种显示面板、显示装置及制造方法,属于显示技术领域。所述显示面板包括:衬底基板,衬底基板具有第一通孔;导电结构,导电结构设置在衬底基板上,导电结构在第一通孔处露出;显示结构,显示结构位于设置有导电结构的衬底基板上,显示结构包括下方显示结构、控制线路以及上方显示结构,下方显示结构具有第二通孔,控制线路通过第二通孔与导电结构电连接。本发明通过在显示结构和衬底基板之间设置导电结构,并在该导电结构一侧的下方显示结构以及另一侧的衬底基板分别设置通孔,通过衬底基板上的通孔可以将导电结构与显示面板背部的控制集成电路电连接。由于无需弯折衬底基板,因而能够达到缩小显示面板的边框的效果。
Description
技术领域
本申请涉及显示技术领域,特别涉及一种显示面板、显示装置及制造方法。
背景技术
目前,为了缩小显示面板的边框的宽度,通常会将控制集成电路(英文:integrated circuit;简称:IC)设置在显示面板的背部,再将显示面板内部的控制线路绕到该背部与控制IC相连接。
一种显示面板,选用了具有柔性的衬底基板,并将该柔性的衬底基板弯折到显示面板的背部,显示面板的控制线路经过该弯折部分与背部的控制IC相连。
但是,弯折的衬底基板仍在一定程度上增加了显示面板的边框的宽度。
发明内容
本申请实施例提供了一种显示面板、显示装置及制造方法,能够解决相关技术中显示面板的边框的宽度较宽问题。所述技术方案如下:
根据本申请的第一方面,提供了一种显示面板,所述显示面板包括:
衬底基板,所述衬底基板具有第一通孔;
导电结构,所述导电结构设置在所述衬底基板上,所述导电结构在所述第一通孔处露出;
显示结构,所述显示结构位于设置有所述导电结构的衬底基板上,所述显示结构包括依次设置在设置有导电结构的衬底基板上的下方显示结构、控制线路以及上方显示结构,所述下方显示结构上具有第二通孔,所述控制线路通过所述第二通孔与所述导电结构电连接。
可选地,所述显示面板包括指纹识别组件,所述指纹识别组件包括带孔遮光层和指纹识别传感器,所述带孔遮光层用于将所述显示结构发出并经触摸主体反射后的光进行通过,以被所述指纹识别传感器感测;
所述导电结构与所述带孔遮光层为通过同一次构图工艺形成的同层结构。
可选地,所述导电结构和所述带孔遮光层的材料包括金属。
可选地,所述显示面板包括衬底层,所述衬底层位于所述导电结构和所述下方显示结构之间。
所述衬底层上具有与所述下方显示结构的第二通孔连通的第三通孔,所述控制线路通过所述第二通孔以及所述第三通孔与所述导电结构电连接。
可选地,所述衬底层和所述衬底基板均包括沿靠近所述显示结构的方向层叠着的聚酰亚胺结构层和屏障层。
可选地,所述屏障层的材料包括氧化硅。
可选地,所述导电结构位于所述显示面板的显示区域中。
可选地,所述下方显示结构包括缓冲层和有源层。
可选地,所述缓冲层的材料包括氮化硅或氧化硅。
可选地,所述上方显示结构包括:
沿远离所述下方显示结构方向依次设置的驱动电路层、有机发光层和封装层。
根据本申请的第二方面,提供一种显示面板的制造方法,所述方法包括:
提供衬底基板;
在所述衬底基板上形成导电结构;
在形成有所述导电结构的衬底基板上形成显示结构,所述显示结构包括依次设置在设置有导电结构的衬底基板上的下方显示结构、控制线路以及上方显示结构,所述下方显示结构上具有第二通孔,所述控制线路通过所述第二通孔与所述导电结构电连接;
在所述衬底基板上形成第一通孔,所述导电结构在所述第一通孔处露出。
可选地,所述在所述衬底基板上形成导电结构,包括;
通过一次构图工艺在所述衬底基板上形成所述导电结构和带孔遮光层,所述显示面板包括指纹识别组件,所述指纹识别组件包括所述带孔遮光层和指纹识别传感器,所述带孔遮光层用于将所述显示结构发出并经触摸主体反射后的光进行通过,以被所述指纹识别传感器感测。
可选地,所述在所述衬底基板上形成第一通孔,包括:
通过激光打孔工艺在所述衬底基板上形成所述第一通孔。
根据本申请的第三方面,提供一种显示装置的制造方法,所述方法包括:
提供显示面板,所述显示面板包括衬底基板,所述衬底基板具有第一通孔;导电结构,所述导电结构设置在所述衬底基板上,所述导电结构在所述第一通孔处露出;显示结构,所述显示结构位于设置有所述导电结构的衬底基板上,所述显示结构包括依次设置在设置有导电结构的衬底基板上的下方显示结构、控制线路以及上方显示结构,所述下方显示结构上具有第二通孔,所述控制线路通过所述第二通孔与所述导电结构电连接;
提供控制集成电路;
通过所述第一通孔将所述控制集成电路与所述导电结构电连接。
可选地,所述通过所述第一通孔将所述控制集成电路与所述导电结构电连接,包括:
在所述第一通孔中设置导电银胶;
将所述控制集成电路与所述导电银胶电连接。
根据本申请的第四方面,提供一种显示装置,所述显示装置包括控制集成电路和显示面板,所述显示面板包括衬底基板,所述衬底基板具有第一通孔;导电结构,所述导电结构设置在所述衬底基板上,所述导电结构在所述第一通孔处露出;显示结构,所述显示结构位于设置有所述导电结构的衬底基板上,所述显示结构包括依次设置在设置有导电结构的衬底基板上的下方显示结构、控制线路以及上方显示结构,所述下方显示结构上具有第二通孔,所述控制线路通过所述第二通孔与所述导电结构电连接;
所述控制集成电路通过所述第一通孔与所述导电结构电连接。
可选地,所述显示装置包括柔性电路板,所述柔性电路板与所述导电结构电连接,所述控制集成电路位于所述柔性电路板上。
可选地,所述第一通孔中设置有导电银胶,所述控制集成电路与所述导电银胶电连接。
本申请实施例提供的技术方案带来的有益效果至少包括:
通过在显示结构和衬底基板之间设置导电结构,并在该导电结构一侧的下方显示结构以及另一侧的衬底基板分别设置通孔,通过导电结构与控制线路之间的通孔将导电结构与控制线路电连接,通过衬底基板上的通孔可以将导电结构与显示面板背部的控制集成电路电连接,如此便可以将显示面板背部的控制集成电路与显示面板内部的控制线路电连接。由于无需弯折衬底基板,因而能够减小弯折部分所增加的边框的宽度。解决了相关技术中显示面板的边框的宽度较宽的问题。达到了缩小显示面板的边框的效果。
附图说明
为了更清楚地说明本申请实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是相关技术中的一种显示装置的结构示意图;
图2是本申请实施例提供的一种显示面板的结构示意图;
图3是本申请实施例提供的另一种显示面板的结构示意图;
图4是图3所示的显示面板中带孔遮光层和导电结构等结构的俯视;
图5是本申请实施例提供的一种显示面板的制造方法的流程图;
图6是图5所示实施例中一种衬底基板的结构示意图;
图7是图5所示实施例中另一种衬底基板的结构示意图;
图8是图5所示实施例中另一种衬底基板的结构示意图;
图9是本申请实施例提供的一种显示装置的制造方法的流程图;
图10是图9所示实施例中一种控制集成电路与导电结构电连接的流程图;
图11是图9所示实施例中一种显示装置的结构示意图。
通过上述附图,已示出本申请明确的实施例,后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本申请构思的范围,而是通过参考特定实施例为本领域技术人员说明本申请的概念。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚,下面将结合附图对本申请实施方式作进一步地详细描述。
图1是相关技术中的一种显示装置的结构示意图,该显示装置包括显示面板以及控制IC-13,显示面板包括衬底基板11以及设置在衬底基板11上的控制线路12,控制IC-13位于衬底基板11远离控制线路12一侧的柔性基底14上,柔性基底14以及设置在其上的IC-13可以共同称为覆晶薄膜(英文:Chip On Film;简称:COF)。其中,柔性基底可以包括柔性层(可以由聚酰亚胺构成)以及设置在柔性层上的导电线路等。
为了缩小显示面板的边框,该显示面板的衬底基板11由柔性材料构成,使其能够弯曲至显示面板的背部(显示面板的背部即显示面板不进行图像显示的一面)。控制线路12通过该弯曲部以及覆晶薄膜14与控制IC-13电连接。
图1所示的方式虽然能够在一定程度上缩小显示面板的边框(显示面板除显示区域外的部分均可以称为显示面板的边框),但是其弯曲部分仍会增大显示面板的边框。
另外,直接在显示面板的背部打孔,以使背部的控制IC能够与显示面板内部的控制线路电连接的方式,也由于所需打孔的深度过深(直接从显示面板背部形成一个贯穿至控制线路所在层的孔的深度较深,而打孔过深的技术难度较大,可能引起显示面板的损坏等严重问题)的原因,而难以实施。
本申请实施例提供了一种显示面板、显示装置及制造方法,可以解决上述相关技术中的问题。
图2是本申请实施例提供的一种显示面板的结构示意图。该显示面板20可以包括:
衬底基板21。
导电结构22,导电结构22设置在衬底基板21上,衬底基板21具有第一通孔21a,导电结构22在第一通孔21a处露出。
显示结构23,显示结构23位于设置有导电结构22的衬底基板21上,显示结构23包括依次设置在设置有导电结构22的衬底基板21上的下方显示结构231、控制线路232以及上方显示结构233,下方显示结构231上具有第二通孔(图2中未标出),控制线路232通过第二通孔与导电结构22电连接。
综上所述,本申请实施例提供的一种显示面板,通过在显示结构和衬底基板之间设置导电结构,并在该导电结构一侧的下方显示结构以及另一侧的衬底基板分别设置通孔,通过导电结构与控制线路之间的通孔将导电结构与控制线路电连接,通过衬底基板上的通孔可以将导电结构与显示面板背部的控制集成电路电连接,如此便可以将显示面板背部的控制集成电路与显示面板内部的控制线路电连接。由于无需弯折衬底基板,因而能够减小弯折部分所增加的边框的宽度。解决了相关技术中显示面板的边框的宽度较宽的问题。达到了缩小显示面板的边框的效果。
请参考图3,其示出了本申请实施例提供的另一种显示面板的结构示意图,该显示面板在图2所示的显示面板的基础上进行了一些调整。
可选地,显示面板20包括指纹识别组件24,指纹识别组件24包括带孔遮光层241和指纹识别传感器242,带孔遮光层241用于将显示结构发出并经触摸主体反射后的光进行通过,以被指纹识别传感器感测。导电结构22与带孔遮光层241为通过同一次构图工艺形成的同层结构。也即是通过同一张掩膜(英文:MASK)在一次构图工艺中即可形成导电结构22与带孔遮光层241,方便快捷,节省制造成本。
图3示出的是指纹识别传感器242位于衬底基板21远离显示结构23的一侧的情况,但指纹识别传感器242还可以位于其他位置,本申请实施例不进行限制。
如图4所示,其为图3所示的显示面板中,带孔遮光层241和导电结构22等结构的俯视图。带孔遮光层241上具有多个开孔,导电结构22包括多个块状结构,以便于与控制IC上的多个接点进行连接(或称为邦定(英文:bonding))。
该指纹识别组件以及其中的带孔遮光层241可以用于通过小孔成像原理实现屏下指纹识别的功能,带孔遮光层241可以通过等离子化学气相沉积(英文:Plasma EnhancedChemical Vapor Deposition;简称:PECVD)工艺(或其它气相沉积工艺)来形成。
可选地,导电结构22和带孔遮光层241的材料包括金属。金属材料的导电性能和遮光性能通常较强,可以满足导电结构22对于导电性能的要求,并满足带孔遮光层241对于遮光性能的要求。
如图3所示,显示面板20包括衬底层25,衬底层25位于导电结构22和下方显示结构231之间。衬底层25上具有与下方显示结构231的第二通孔(图3中未标出)连通的第三通孔(图3中未标出),控制线路232(控制线路可以包括VSS(公共连接线)和VDD(工作电压连接线)等线路)通过第二通孔以及第三通孔与导电结构22电连接。也即是显示面板20的衬底结构可以由衬底层25以及衬底基板21共同构成,而导电结构22以及带孔遮光层241可以位于衬底层25和衬底基板21之间。其中,第二通孔和第三通孔均可以通过构图工艺来形成。
在本申请实施例中,涉及的构图工艺可以包括形成光刻胶,对光刻胶进行曝光和显影,以显影后的光刻胶为掩膜对其下方膜层进行刻蚀以及剥离光刻胶等。
相关技术中,带孔遮光层通常位于整个衬底结构的上方,由于后续会在带孔遮光层241上方形成有源层等结构,相关技术中为了避免形成有源层的过程中对带孔遮光层241造成损坏(例如激光退火等工艺会严重影响带孔遮光层241),会先在带孔遮光层241上方形成保护层(比如以较低功率的化学气相沉积工艺形成氧化硅层来作为保护层)。但这样不但使显示面板的结构较为复杂,而且增加了制造成本和制造时长。此外,带孔遮光层上的孔洞还会影响上方有源层的平整度,对激光退火造成影响,导致有源层中晶粒结晶不均匀,进而影响显示面板的显示效果。
而本申请实施例中,将带孔遮光层241和导电结构22设置在衬底层25和衬底基板21之间,由衬底层25来保护衬底层25和衬底基板21,无需再形成保护层,简化了显示面板的结构和制造工艺,降低了制造成本。另外,衬底层可以作为平坦层,且带孔遮光层距离有源层较远,不会对有源层的平整度造成影响,进而使得激光退火后的有源层中晶粒结晶较为均匀,提高了显示面板的显示效果。
可选地,衬底层25和衬底基板21均包括沿靠近显示结构23的方向层叠着的聚酰亚胺(英文:Polyimide;简称:PI)结构层211和屏障(英文:BARRIER)层212。屏障层的212的材料可以包括氧化硅。层叠着的PI结构层和屏障层可以构成一种性能较好的衬底结构,通常PI结构层可以位于屏障层远离导电结构的一侧。
可选地,导电结构22位于显示面板的显示区域中。由于导电结构22位于衬底结构中,不会对显示面板的正常显示造成影响,因而导电结构22可以位于显示面板的显示区域中,如此能够进一步的缩小显示面板的边框的宽度。但是,导电结构22也可以位于显示面板显示区域外的周边区域,本申请实施例对此不进行限制。
可选地,下方显示结构231包括缓冲(英文:Buffer)层231a和有源层231b。缓冲层的材料可以包括氮化硅或氧化硅。有源层231b可以由多晶硅构成,其可以由非晶硅经退火工艺(如准分子激光退火(英文:Excimer Laser Anneal;简称:ELA)工艺)后得到。
可选地,根据显示面板的显示原理的不同,上方显示结构233可以包括不同的器件。示例性的,当显示面板为有机发光二级光显示面板时,上方显示结构233可以包括沿远离下方显示结构231方向依次设置的驱动电路层233a、有机发光层233b和封装层233c等。其中,驱动电路层233a可以包括驱动有机发光层的像素电路和控制线路等结构,有机发光层233b可以包括依次层叠的阳极、电致发光(英文:electroluminescent;简称:EL)层和阴极等。封装层233c可以是由薄膜封装技术或其它相关技术形成的封装层,例如,封装层233c可以是玻璃胶封装层。
另外,当显示面板为液晶显示面板时,上方显示结构233可以包括液晶层以及彩膜基板等结构。
可选地,第一通孔21a可以由激光打孔工艺形成。可以在显示面板的其它结构制造完成后,通过激光打孔工艺从显示面板的背部打孔,直至导电结构22露出。该第一通孔21a可以用于导电结构22能够与显示面板背部的控制IC电连接。
综上所述,本申请实施例提供的一种显示面板,通过在显示结构和衬底基板之间设置导电结构,并在该导电结构一侧的下方显示结构以及另一侧的衬底基板分别设置通孔,通过导电结构与控制线路之间的通孔将导电结构与控制线路电连接,通过衬底基板上的通孔可以将导电结构与显示面板背部的控制集成电路电连接,如此便可以将显示面板背部的控制集成电路与显示面板内部的控制线路电连接。由于无需弯折衬底基板,因而能够减小弯折部分所增加的边框的宽度。解决了相关技术中显示面板的边框的宽度较宽的问题。达到了缩小显示面板的边框的效果。
图5是本申请实施例提供的一种显示面板的制造方法的流程图,该方法包括:
步骤501、提供衬底基板。
该衬底基板可以为包括聚酰亚胺结构层和屏障层的多层结构。
步骤502、在衬底基板上形成导电结构。
在形成导电结构时,还可以在同一次构图工艺中形成带孔遮光层。该带孔遮光层为指纹识别组件中的结构,指纹识别组件还包括指纹识别传感器,带孔遮光层用于将所述显示结构发出并经触摸主体反射后的光进行通过,以被所述指纹识别传感器感测。
如图6所示,其为步骤502结束时,衬底基板的结构示意图。带孔遮光层241和导电结构22形成于衬底基板21上。衬底基板21包括沿靠近显示结构23的方向层叠着的聚酰亚胺结构层211和屏障层212。
步骤503、在形成有导电结构的衬底基板上形成衬底层。
该衬底层的结构可以与衬底基板类似,也为包括聚酰亚胺结构层和屏障层的多层结构。
步骤504、在形成有衬底层的衬底基板上形成显示结构。
其中,显示结构包括依次设置在设置有导电结构的衬底基板上的下方显示结构、控制线路以及上方显示结构,下方显示结构上具有第二通孔,控制线路通过第二通孔与导电结构电连接。
如图7所示,其为步骤503结束时,衬底基板的结构示意图。控制线路232通过下方显示结构231以及衬底层25上的过孔与导电结构22电连接。图7中其他标记的含义可以参考图3,在此不再赘述。
步骤503为可选的步骤,也即是可以在步骤502结束后,直接执行步骤504,相应的在形成有导电结构的衬底基板上形成显示结构。
步骤505、在衬底基板上形成第一通孔,导电结构在第一通孔处露出。
可以通过激光打孔工艺在衬底基板上形成第一通孔。由于仅需要打穿衬底基板,因而第一通孔的深度较浅,打孔难度较低。
如图8所示,其为步骤505结束时,衬底基板的结构示意图。导电结构22在第一通孔21a处露出,后续可以通过该通孔将导电结构22与控制IC电连接。图8中其他标记的含义可以参考图3,在此不再赘述。
综上所述,本申请实施例提供的一种显示面板的制造方法,通过在显示结构和衬底基板之间形成导电结构,并在该导电结构一侧的下方显示结构以及另一侧的衬底基板分别设置通孔,通过导电结构与控制线路之间的通孔将导电结构与控制线路电连接,通过衬底基板上的通孔可以将导电结构与显示面板背部的控制集成电路电连接,如此便可以将显示面板背部的控制集成电路与显示面板内部的控制线路电连接。由于无需弯折衬底基板,因而能够减小弯折部分所增加的边框的宽度。解决了相关技术中显示面板的边框的宽度较宽的问题。达到了缩小显示面板的边框的效果。
图9是本申请实施例提供的一种显示装置的制造方法的流程图,该方法包括:
步骤901、提供显示面板。
该显示面板可以为图3所示的显示面板。
步骤902、提供控制集成电路。
该控制集成电路可以为用于对显示面板的显示功能进行控制的器件。
步骤903、通过第一通孔将控制集成电路与导电结构电连接。
为了缩小显示面板的边框宽度,控制集成电路通常设置在衬底基板远离导电结构的一侧,也即是显示面板的背部。可以将显示面板的背部的控制集成电路通过第一通孔与导电结构电连接。
如图10所示,步骤903可以包括下面两个子步骤:
子步骤9031、在第一通孔中设置导电银胶。
导电银胶(英文:Conductive Adhesive)是一种具有导电性能的胶黏剂,可以在第一中设置导电银胶,该导电银胶可以与第一通孔中露出的导电结构电连接。
子步骤9032、将控制集成电路与导电银胶电连接。
将控制集成电路与导电银胶电连接后,控制集成电路即可通过导电银胶与导电结构电连接,进而与显示面板内部的控制线路电连接。
另外,还可以通过其他方式来将控制集成电路与导电结构电连接,如通过纳米银线等,本发明实施例不进行限制。
如图11所示,其为步骤903结束时,显示装置的结构示意图。控制集成电路32可以设置在柔性基底31上,导电银胶33可以通过柔性基底31与控制集成电路32电连接。图11中其他标记的含义可以参考图3,在此不再赘述。
综上所述,本申请实施例提供的一种显示装置,通过在显示结构和衬底基板之间形成导电结构,并在该导电结构一侧的下方显示结构以及另一侧的衬底基板分别设置通孔,通过导电结构与控制线路之间的通孔将导电结构与控制线路电连接,通过衬底基板上的通孔可以将导电结构与显示面板背部的控制集成电路电连接,如此便可以将显示面板背部的控制集成电路与显示面板内部的控制线路电连接。由于无需弯折衬底基板,因而能够减小弯折部分所增加的边框的宽度。解决了相关技术中显示面板的边框的宽度较宽的问题。达到了缩小显示面板的边框的效果。
如图11所示,本申请还提供一种显示装置,显示装置包括控制集成电路32和显示面板,显示面板包括衬底基板21,衬底基板21具有第一通孔(图11未标出);导电结构22,导电结构22设置在衬底基板21上,导电结构22在第一通孔处露出;显示结构23,显示结构23位于设置有导电结构22的衬底基板21上,显示结构23包括依次设置在设置有导电结构22的衬底基板21上的下方显示结构231、控制线路232以及上方显示结构233,下方显示结构231上具有第二通孔(图11未标出),控制线路232通过第二通孔与导电结构22电连接。
控制集成电路32通过第一通孔与导电结构22电连接。
可选地,显示装置包括柔性基底31,柔性基底31与导电结构22电连接,控制集成电路32位于柔性基底31上。
可选地,第一通孔中设置有导电银胶33,控制集成电路32与导电银胶33电连接。
需要指出的是,在附图中,为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解,当元件或层被称为在另一元件或层“上”时,它可以直接在其他元件上,或者可以存在中间的层。另外,可以理解,当元件或层被称为在另一元件或层“下”时,它可以直接在其他元件下,或者可以存在一个以上的中间的层或元件。另外,还可以理解,当层或元件被称为在两层或两个元件“之间”时,它可以为两层或两个元件之间唯一的层,或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
在本发明中,术语“第一”、“第二”、“第三”和“第四”仅用于描述目的,而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上,除非另有明确的限定。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成,也可以通过程序来指令相关的硬件完成,所述的程序可以存储于一种计算机可读存储介质中,上述提到的存储介质可以是只读存储器,磁盘或光盘等。
以上所述仅为本发明的可选实施例,并不用以限制本发明,凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (12)
1.一种显示面板,其特征在于,所述显示面板包括:
衬底基板,所述衬底基板具有第一通孔;
导电结构,所述导电结构设置在所述衬底基板上,所述导电结构在所述第一通孔处露出;
显示结构,所述显示结构位于设置有所述导电结构的衬底基板上,所述显示结构包括依次设置在设置有导电结构的衬底基板上的下方显示结构、控制线路以及上方显示结构,所述下方显示结构上具有第二通孔,所述控制线路通过所述第二通孔与所述导电结构电连接;
指纹识别组件,所述指纹识别组件包括带孔遮光层和指纹识别传感器,所述带孔遮光层用于将所述显示结构发出并经触摸主体反射后的光进行通过,以被所述指纹识别传感器感测;
衬底层,所述衬底层位于所述导电结构和所述下方显示结构之间,所述衬底层上具有与所述下方显示结构的第二通孔连通的第三通孔,所述控制线路通过所述第二通孔以及所述第三通孔与所述导电结构电连接;
其中,所述导电结构与所述带孔遮光层为通过同一次构图工艺形成的同层结构。
2.根据权利要求1所述的显示面板,其特征在于,所述导电结构和所述带孔遮光层的材料包括金属。
3.根据权利要求1所述的显示面板,其特征在于,所述衬底层和所述衬底基板均包括沿靠近所述显示结构的方向层叠着的聚酰亚胺结构层和屏障层。
4.根据权利要求3所述的显示面板,其特征在于,所述屏障层的材料包括氧化硅。
5.根据权利要求1所述的显示面板,其特征在于,所述导电结构位于所述显示面板的显示区域中。
6.根据权利要求1所述的显示面板,其特征在于,所述下方显示结构包括缓冲层和有源层。
7.根据权利要求6所述的显示面板,其特征在于,所述缓冲层的材料包括氮化硅或氧化硅。
8.根据权利要求1所述的显示面板,其特征在于,所述上方显示结构包括:
沿远离所述下方显示结构方向依次设置的驱动电路层、有机发光层和封装层。
9.一种显示面板的制造方法,其特征在于,所述方法包括:
提供衬底基板;
在所述衬底基板上形成导电结构;
在形成有所述导电结构的衬底基板上形成显示结构,所述显示结构包括依次设置在设置有导电结构的衬底基板上的下方显示结构、控制线路以及上方显示结构,所述下方显示结构上具有第二通孔,所述控制线路通过所述第二通孔与所述导电结构电连接;
在所述衬底基板上形成第一通孔,所述导电结构在所述第一通孔处露出;
在所述导电结构和所述下方显示结构之间形成衬底层,所述衬底层上具有与所述下方显示结构的第二通孔连通的第三通孔,所述控制线路通过所述第二通孔以及所述第三通孔与所述导电结构电连接;
其中,所述在所述衬底基板上形成导电结构,包括:
通过一次构图工艺在所述衬底基板上形成所述导电结构和带孔遮光层,所述显示面板包括指纹识别组件,所述指纹识别组件包括所述带孔遮光层和指纹识别传感器,所述带孔遮光层用于将所述显示结构发出并经触摸主体反射后的光进行通过,以被所述指纹识别传感器感测。
10.一种显示装置,其特征在于,所述显示装置包括控制集成电路和显示面板,所述显示面板包括衬底基板;导电结构,所述导电结构设置在所述衬底基板上,所述衬底基板具有第一通孔,所述导电结构在所述第一通孔处露出;显示结构,所述显示结构位于设置有所述导电结构的衬底基板上,所述显示结构包括依次设置在设置有导电结构的衬底基板上的下方显示结构、控制线路以及上方显示结构,所述下方显示结构上具有第二通孔,所述控制线路通过所述第二通孔与所述导电结构电连接;指纹识别组件,所述指纹识别组件包括带孔遮光层和指纹识别传感器,所述带孔遮光层用于将所述显示结构发出并经触摸主体反射后的光进行通过,以被所述指纹识别传感器感测;衬底层,所述衬底层位于所述导电结构和所述下方显示结构之间,所述衬底层上具有与所述下方显示结构的第二通孔连通的第三通孔,所述控制线路通过所述第二通孔以及所述第三通孔与所述导电结构电连接;
所述控制集成电路通过所述第一通孔与所述导电结构电连接;
其中,所述导电结构与所述带孔遮光层为通过同一次构图工艺形成的同层结构。
11.根据权利要求10所述的显示装置,其特征在于,所述显示装置包括柔性基底,所述柔性基底与所述导电结构电连接,所述控制集成电路位于所述柔性基底上。
12.根据权利要求11所述的显示装置,其特征在于,所述第一通孔中设置有导电银胶,所述控制集成电路与所述导电银胶电连接。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910345749.2A CN110047899B (zh) | 2019-04-26 | 2019-04-26 | 显示面板、显示装置及制造方法 |
PCT/CN2020/086199 WO2020216259A1 (zh) | 2019-04-26 | 2020-04-22 | 显示面板、显示装置及制造方法 |
US17/256,192 US11960180B2 (en) | 2019-04-26 | 2020-04-22 | Display device with conductive structure and perforated light-shielding layer in same layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910345749.2A CN110047899B (zh) | 2019-04-26 | 2019-04-26 | 显示面板、显示装置及制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110047899A CN110047899A (zh) | 2019-07-23 |
CN110047899B true CN110047899B (zh) | 2021-10-22 |
Family
ID=67279649
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910345749.2A Active CN110047899B (zh) | 2019-04-26 | 2019-04-26 | 显示面板、显示装置及制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US11960180B2 (zh) |
CN (1) | CN110047899B (zh) |
WO (1) | WO2020216259A1 (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110047899B (zh) | 2019-04-26 | 2021-10-22 | 京东方科技集团股份有限公司 | 显示面板、显示装置及制造方法 |
CN110400809A (zh) * | 2019-07-24 | 2019-11-01 | 深圳市华星光电半导体显示技术有限公司 | TFT驱动背板及Micro-LED显示器 |
CN111052136B (zh) * | 2019-07-30 | 2023-01-24 | 深圳市汇顶科技股份有限公司 | 一种屏下指纹系统、光学指纹显示模组及电子装置 |
KR20210016237A (ko) * | 2019-08-02 | 2021-02-15 | 삼성디스플레이 주식회사 | 표시 장치, 그것의 제조 방법, 및 멀티 표시 장치 |
CN111415587B (zh) * | 2020-03-31 | 2022-04-19 | 京东方科技集团股份有限公司 | 一种显示基板及其制备方法和显示面板 |
US11244996B2 (en) * | 2020-04-27 | 2022-02-08 | Facebook Technologies, Llc | Micro OLEDs having narrow bezel |
CN111613607B (zh) * | 2020-05-27 | 2021-08-03 | 武汉华星光电半导体显示技术有限公司 | 柔性有机发光二极管显示面板 |
KR20220021062A (ko) * | 2020-08-12 | 2022-02-22 | 삼성디스플레이 주식회사 | 표시 장치 및 이를 포함하는 타일형 표시 장치 |
TWI764449B (zh) * | 2020-12-18 | 2022-05-11 | 友達光電股份有限公司 | 顯示裝置 |
CN113411939B (zh) * | 2021-06-09 | 2022-12-06 | 武汉华星光电技术有限公司 | 一种显示模组 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10529745B2 (en) * | 2016-07-05 | 2020-01-07 | Innolux Corporation | Display device |
CN106384740A (zh) * | 2016-09-20 | 2017-02-08 | 昆山工研院新型平板显示技术中心有限公司 | 无边框显示装置及其制备方法 |
CN106896599A (zh) * | 2017-03-10 | 2017-06-27 | 惠科股份有限公司 | 显示面板及其显示装置 |
CN106973520A (zh) | 2017-05-27 | 2017-07-21 | 京东方科技集团股份有限公司 | 一种显示面板、显示装置及显示面板的制作方法 |
CN107039377B (zh) * | 2017-06-16 | 2019-10-25 | 京东方科技集团股份有限公司 | 一种显示面板、其制作方法及显示装置 |
US20180373913A1 (en) * | 2017-06-26 | 2018-12-27 | Qualcomm Incorporated | Ultrasonic fingerprint sensor for under-display applications |
US10571758B2 (en) * | 2018-01-05 | 2020-02-25 | Innolux Corporation | Display device |
US10690973B2 (en) * | 2018-01-19 | 2020-06-23 | Innolux Corporation | Electronic device |
CN109065756B (zh) * | 2018-08-03 | 2020-06-02 | 京东方科技集团股份有限公司 | 一种显示器件及其制备方法、显示装置 |
CN109103231B (zh) | 2018-08-27 | 2021-08-24 | 京东方科技集团股份有限公司 | 显示基板及其制造方法、显示装置 |
KR102578350B1 (ko) * | 2018-11-27 | 2023-09-13 | 엘지디스플레이 주식회사 | 표시 장치 |
CN109524421B (zh) * | 2019-01-04 | 2024-06-18 | 京东方科技集团股份有限公司 | 转接基板及其制造方法、阵列基板及显示装置 |
CN109585462A (zh) * | 2019-01-23 | 2019-04-05 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法、柔性显示面板、拼接屏 |
CN109858434B (zh) * | 2019-01-29 | 2021-04-30 | 上海天马微电子有限公司 | 显示面板及其指纹识别方法和显示装置 |
CN110047899B (zh) | 2019-04-26 | 2021-10-22 | 京东方科技集团股份有限公司 | 显示面板、显示装置及制造方法 |
TWI702579B (zh) * | 2019-05-07 | 2020-08-21 | 友達光電股份有限公司 | 軟性顯示器 |
CN110164937A (zh) * | 2019-05-30 | 2019-08-23 | 武汉华星光电半导体显示技术有限公司 | Oled显示面板 |
-
2019
- 2019-04-26 CN CN201910345749.2A patent/CN110047899B/zh active Active
-
2020
- 2020-04-22 US US17/256,192 patent/US11960180B2/en active Active
- 2020-04-22 WO PCT/CN2020/086199 patent/WO2020216259A1/zh active Application Filing
Also Published As
Publication number | Publication date |
---|---|
CN110047899A (zh) | 2019-07-23 |
WO2020216259A1 (zh) | 2020-10-29 |
US11960180B2 (en) | 2024-04-16 |
US20210265453A1 (en) | 2021-08-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN110047899B (zh) | 显示面板、显示装置及制造方法 | |
CN109103231B (zh) | 显示基板及其制造方法、显示装置 | |
US11215893B2 (en) | Array substrate, method for manufacturing the same, and display apparatus | |
CN113078199B (zh) | 显示基板、显示基板的制备方法及显示模组 | |
CN108461530B (zh) | 一种阵列基板和显示装置 | |
WO2020207013A1 (en) | Array substrate, manufacturing method thereof, and display apparatus | |
US11853519B2 (en) | Touch substrate and manufacturing method therefor, touch display substrate, and touch display device | |
CN113053309B (zh) | 显示面板和显示装置 | |
US11737310B2 (en) | Flexible display module, method for manufacturing the same, and flexible display device | |
EP4145515A1 (en) | Organic light emitting display and manufacturing method therefor | |
US11637166B2 (en) | Array substrate, manufacturing method thereof, and display apparatus | |
US11043545B2 (en) | Display substrate, fabricating method thereof, and display device | |
WO2020143024A1 (zh) | 阵列基板及其制作方法、显示面板 | |
US12096675B2 (en) | Display panel | |
CN113835557B (zh) | 显示面板及其制造方法 | |
CN112366218A (zh) | 一种显示面板的制作方法及显示面板 | |
US12089480B2 (en) | Display panel including redundant driving circuits that form alignment marks in a peripheral region thereof, method for manufacturing the same, display device and method for manufacturing the same | |
CN110047896B (zh) | 显示基板及其制造方法、显示装置 | |
CN110634935A (zh) | 一种阵列基板及显示装置 | |
WO2022126314A1 (zh) | 显示基板及其制造方法、显示装置 | |
CN110224010B (zh) | Oled显示基板、显示面板、oled显示基板的制备方法 | |
JP7466701B2 (ja) | 表示装置および表示装置の製造方法 | |
TWI802471B (zh) | 顯示面板 | |
US20240032339A1 (en) | Display device and method for fabricating the same | |
US20240260329A1 (en) | Display device and display panel |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |