WO2020253420A1 - 氧化镓sbd终端结构及制备方法 - Google Patents
氧化镓sbd终端结构及制备方法 Download PDFInfo
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- WO2020253420A1 WO2020253420A1 PCT/CN2020/089764 CN2020089764W WO2020253420A1 WO 2020253420 A1 WO2020253420 A1 WO 2020253420A1 CN 2020089764 W CN2020089764 W CN 2020089764W WO 2020253420 A1 WO2020253420 A1 WO 2020253420A1
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- Prior art keywords
- gallium oxide
- metal layer
- concentration
- layer
- terminal structure
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- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 48
- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 48
- 238000002360 preparation method Methods 0.000 title description 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 55
- 239000002184 metal Substances 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 claims description 34
- 238000000137 annealing Methods 0.000 claims description 28
- 238000011282 treatment Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 11
- 230000008859 change Effects 0.000 claims description 8
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 229910004541 SiN Inorganic materials 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 230000004888 barrier function Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 241001354791 Baliga Species 0.000 description 1
- 208000033999 Device damage Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L29/861—Diodes
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- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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Definitions
- This application belongs to the technical field of semiconductor device manufacturing, and in particular relates to a gallium oxide SBD terminal structure and a preparation method.
- Power electronic devices also known as power semiconductor devices, are mainly used for power changes and circuit control of power equipment. They are the core devices for power control and conversion of industrial facilities, household appliances and other equipment. They can perform typical power processing, including frequency conversion, voltage transformation, Converter, power management, etc. Silicon-based semiconductor power devices are currently the most commonly used power devices in power systems, but their performance is close to the theoretical limit determined by their materials, making the growth of their power density appear to be saturated.
- ultra-wide bandgap gallium oxide As a new semiconductor material, ultra-wide bandgap gallium oxide has outstanding advantages in breakdown field strength, Barriga merit and cost. At present, five types of gallium oxide crystals have been discovered: ⁇ , ⁇ , ⁇ , ⁇ , and ⁇ Among them, the ⁇ -structure gallium oxide is the most stable. So far, the research on gallium oxide in the semiconductor field has been carried out on the ⁇ -structure gallium oxide; the Baliga figure of merit is usually used to characterize the material suitable for power devices.
- the Balijia figure of merit of the ⁇ -Ga 2 O 3 material is 3444 times that of the first-generation semiconductor Si material, 4 times that of the third-generation wide-gap semiconductor GaN material, and 10 times that of the SiC material.
- ⁇ -Ga 2 When the O 3 power device has the same withstand voltage as the GaN and SiC devices, the on-resistance is lower and the power consumption is smaller, which can greatly reduce the power loss when the device is working.
- the image force-induced barrier reduction effect is a bottleneck problem that limits the characteristics of gallium oxide SBD (Schottky Barrier Diode).
- the use of plasma treatment to reduce the concentration of the drift region can alleviate the image force-induced barrier reduction effect and improve device damage.
- Ar ion implantation Through the introduction of Ar ion implantation, the area outside the anode junction becomes a high resistance area, the anode electric field is adjusted, and the breakdown voltage is increased.
- Ar ion implantation damages the material greatly and affects the further increase of the breakdown voltage. How to further increase the breakdown voltage while ensuring low on-resistance has become an urgent problem to be solved.
- the embodiments of the present application provide a gallium oxide SBD terminal structure and a manufacturing method to solve the problem of further increasing the breakdown voltage while ensuring low on-resistance in the prior art.
- the embodiments of the present application provide a gallium oxide SBD terminal structure and a manufacturing method to solve the problem of further increasing the breakdown voltage while ensuring low on-resistance in the prior art.
- the first aspect of the embodiments of the present application provides a gallium oxide SBD terminal structure and a preparation method to solve the problem of further increasing the breakdown voltage while ensuring low on-resistance in the prior art.
- the first aspect of the embodiments of the present invention provides a gallium oxide SBD terminal structure: from bottom to top, it includes a cathode metal layer, an N+ high-concentration substrate layer, an N-low-concentration Ga 2 O 3 epitaxial layer, and an anode metal.
- the N-low concentration Ga 2 O 3 epitaxial layer is within a certain thickness range close to the anode metal layer, and the doping concentration under the anode metal layer is greater than the doping concentration on both sides of the anode metal layer.
- the doping concentration of the N-low concentration Ga 2 O 3 epitaxial layer is gradually reduced from bottom to top within a certain thickness range close to the anode metal layer.
- the electron concentration of the N-low concentration Ga 2 O 3 epitaxial layer is 1.0 ⁇ 1015 cm -3 to 1.0 ⁇ 1020 cm -3 .
- the thickness of the N-low concentration Ga 2 O 3 epitaxial layer is 100 nm to 50 ⁇ m.
- the material of the N+ high concentration substrate layer is Ga 2 O 3 or SiC.
- the anode metal layer is Ni/Au
- the cathode metal layer is Ti/Au
- the second aspect of the embodiments of the present application provides a method for preparing a gallium oxide SBD terminal structure, including:
- gallium oxide SBD terminal sample Subjecting the gallium oxide SBD terminal sample to a high temperature annealing treatment containing at least two temperatures;
- the mask layer on the gallium oxide SBD terminal sample after the high temperature annealing treatment is removed, and an anode metal layer and a cathode metal layer are formed on both sides of the gallium oxide SBD terminal sample.
- the material of the mask layer is SiO 2 , SiN or Al 2 O 3 realized by PECVD or sputtering.
- the high temperature annealing treatment is performed in an oxygen atmosphere.
- the temperature change mode of the high-temperature annealing treatment is linear or step change.
- the annealing temperature is any value from 200° C. to 900° C.
- the annealing time is 10 seconds to 100 minutes.
- the annealing temperature is 400°C and 450°C, and the annealing time at each temperature is 10 minutes.
- a mask layer is deposited on the N-low concentration Ga 2 O 3 epitaxial layer, and parts of the mask layer other than the area corresponding to the anode metal layer are removed to obtain a mask with only the area corresponding to the anode metal layer covered by the mask.
- the gallium oxide SBD terminal sample of the film layer this sample is annealed, only the mask layer and the anode metal layer outside the corresponding area can form a gradually decreasing doping concentration from bottom to top, without changing the anode metal
- the doping concentration of the corresponding region of the layer can improve the breakdown voltage of the gallium oxide SBD terminal structure under the condition of low on-resistance.
- FIG. 1 is a schematic diagram of the structure of a gallium oxide SBD terminal provided by an embodiment of the present application
- FIG. 2 is a flowchart of a method for preparing a gallium oxide SBD terminal structure provided by an embodiment of the present application
- FIG. 3 is a schematic diagram of the structure of a deposition mask layer of a gallium oxide SBD terminal structure provided by an embodiment of the present application;
- FIG. 4 is a schematic structural diagram of a gallium oxide SBD terminal sample provided by an embodiment of the present application after annealing treatment.
- the gallium oxide SBD terminal structure includes a cathode metal layer 1, an N+ high-concentration substrate layer 2, an N-low-concentration Ga 2 O 3 epitaxial layer 3, and an anode metal layer 4, where N-low-concentration Ga 2 O 3
- the epitaxial layer 3 is within a certain thickness range close to the anode metal layer 4, and the doping concentration under the anode metal layer is greater than the doping concentration on both sides of the anode metal layer.
- the second N-low-concentration Ga 2 O 3 epitaxial layer 31 belongs to the N-low-concentration Ga 2 O 3 epitaxial layer 3, and is within a certain thickness range close to the anode metal layer, except for the area corresponding to the anode metal layer.
- the doping concentration of the two N-low concentration Ga 2 O 3 epitaxial layer 31 is less than the doping concentration of the corresponding area of the anode metal layer.
- the electron concentration of the N-low concentration Ga 2 O 3 epitaxial layer is 1.0 ⁇ 1015 cm -3 to 1.0 ⁇ 1020 cm -3 .
- the doping concentration of the N-low-concentration Ga 2 O 3 epitaxial layer 3 can be a fixed value or a value that changes in a gradient.
- the thickness of the N-low concentration Ga 2 O 3 epitaxial layer 3 is 100 nm to 50 ⁇ m.
- the material of the N+ high concentration substrate layer 2 is Ga 2 O 3 or SiC.
- the anode metal layer is Ni/Au
- the cathode metal layer is Ti/Au
- the present invention discloses a method for preparing a gallium oxide SBD terminal structure, including
- Step S101 growing an N-low concentration Ga 2 O 3 epitaxial layer on the N+ high concentration substrate layer;
- Step S102 as shown in FIG. 3, a mask layer 3'is deposited on the N-low concentration Ga 2 O 3 epitaxial layer;
- the material of the mask layer is SiO 2 , SiN or Al 2 O 3 realized by PECVD or sputtering.
- the thickness of the mask layer is 50 nm to 3000 nm.
- Step S103 removing parts other than the region corresponding to the mask layer and the anode metal layer to obtain a gallium oxide SBD terminal sample
- a layer of photoresist may be coated on the area corresponding to the anode metal layer, and then the mask layer outside the area corresponding to the anode metal layer may be removed by dry or wet etching.
- Step S104 as shown in FIG. 4, subject the gallium oxide SBD terminal sample to a high temperature annealing treatment containing at least two temperatures;
- the annealing treatment will make the doping concentration of the part other than the area corresponding to the anode metal layer be Within a certain thickness range close to the anode metal layer, it gradually decreases from bottom to top; while the annealing treatment does not change the doping concentration of the area corresponding to the anode metal layer, that is, the area under the anode metal layer is not annealed, so it is close to A lateral concentration change is introduced into the N-low concentration Ga 2 O 3 epitaxial layer within a certain thickness range of the anode metal layer, so that the on-resistance of the overall gallium oxide SBD terminal structure is lower.
- Step S105 removing the mask layer on the gallium oxide SBD terminal sample after the high temperature annealing treatment, and forming an anode metal layer and a cathode metal layer on both sides of the gallium oxide SBD terminal sample.
- the high temperature annealing treatment is performed in an oxygen atmosphere.
- the temperature change mode of the high-temperature annealing treatment is linear or step change.
- the temperature change may be high temperature first and then low temperature, or low temperature first and then high temperature.
- the annealing temperature is any value from 200°C to 900°C, and the annealing time is 10 seconds to 100 minutes.
- the annealing temperature is 400°C and 450°C, and the annealing time at each temperature is 10 minutes.
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Abstract
本申请适用于半导体器件制造技术领域,提供了一种氧化镓SBD终端结构,自下至上包括阴极金属层、N+高浓度衬底层、N-低浓度Ga 2O 3外延层和阳极金属层,其中,N-低浓度Ga 2O 3外延层在靠近阳极金属层的一定厚度范围内,阳极金属层下方的掺杂浓度大于阳极金属层两侧的掺杂浓度。即只改变阳极金属层对应区域以外部分的掺杂浓度,从而保证在低导通电阻的情况下,提高氧化镓SBD终端结构的击穿电压。
Description
本申请属于半导体器件制造技术领域,尤其涉及一种氧化镓SBD终端结构及制备方法。
电力电子器件又称为功率半导体器件主要用于电力设备的电能变化和电路控制,是工业设施、家用电器等设备电能控制与转换的核心器件,可以进行典型的功率处理,包括变频、变压、变流、功率管理等。硅基半导体功率器件是目前电力系统使用最普遍的功率器件,但其性能已接近由其材料决定的理论极限,使得其功率密度的增长呈饱和趋势。
超宽禁带氧化镓作为一种新的半导体材料,在击穿场强、巴利加优值和成本等方面优势突出,目前共发现α、β、γ、δ、ε五种氧化镓的结晶形态,其中,以β结构的氧化镓最为稳定,目前为止在半导体领域围绕氧化镓的研究都是在β结构的氧化镓上展开的;国际上通常采用巴利加优值来表征材料适合功率器件的程度,β-Ga
2O
3材料的巴利加优值是第一代半导体Si材料的3444倍,第三代宽禁带半导体GaN材料的4倍、SiC材料的10倍,β-Ga
2O
3功率器件与GaN和SiC器件相同耐压情况下,导通电阻更低,功耗更小,能够极大地降低器件工作时的电能损耗。
镜像力致势垒降低效应是限制氧化镓SBD(Schottky Barrier Diode,肖特基势垒二极管)特性的瓶颈问题,利用等离子处理工艺降低漂移区浓度可以缓解镜像力致势垒降低效应和提高器件击穿电压,通过引入Ar离子注入,使阳极结以外区域变成高阻区,调节阳极电场,提高击穿电压。然而,Ar离子注入对材料损伤大且影响击穿电压的进一步提升,如何在保证低导通电阻的情况下进一步提高击穿电压成为亟待解决的问题。
有鉴于此,本申请实施例提供了一种氧化镓SBD终端结构及制备方法,以解决现有技术中在保证低导通电阻的情况下进一步提高击穿电压的问题。
有鉴于此,本申请实施例提供了一种氧化镓SBD终端结构及制备方法,以解决现有技术中在保证低导通电阻的情况下进一步提高击穿电压的问题。
本申请实施例的第一方面提供了一种氧化镓SBD终端结构及制备方法,以解决现有技术中在保证低导通电阻的情况下进一步提高击穿电压的问题。
为了实现上述目的,本发明实施例的第一方面提供了一种氧化镓SBD终端结构:自下至上包括阴极金属层、N+高浓度衬底层、N-低浓度Ga
2O
3外延层和阳极金属层,其中,N-低浓度Ga
2O
3外延层在靠近阳极金属层的一定厚度范围内,阳极金属层下方的掺杂浓度大于阳极金属层两侧的掺杂浓度。
进一步地,所述N-低浓度Ga
2O
3外延层在靠近阳极金属层的一定厚度范围内,掺杂浓度自下至上逐渐减小。
进一步地,所述N-低浓度Ga
2O
3外延层的电子浓度为1.0×1015 cm
-3至1.0×1020 cm
-3。
进一步地,所述N-低浓度Ga
2O
3外延层的厚度为100nm至50μm。
进一步地,所述N+高浓度衬底层的材料为Ga
2O
3或SiC。
进一步地,所述阳极金属层为Ni/Au,所述阴极金属层为Ti/Au。
本申请实施例的第二方面提供了一种氧化镓SBD终端结构的制备方法,包括:
在N+高浓度衬底层上生长N-低浓度Ga
2O
3外延层;
在所述N-低浓度Ga
2O
3外延层上淀积掩膜层;
去除掩膜层与阳极金属层对应的区域以外的部分,得到氧化镓SBD终端样品;
对所述氧化镓SBD终端样品进行含至少两种温度的高温退火处理;
去除经过高温退火处理后的氧化镓SBD终端样品上的掩膜层,并在氧化镓SBD终端样品的两侧分别形成阳极金属层和阴极金属层。
进一步地,所述掩膜层材料为采用PECVD或者溅射方式实现的SiO
2、SiN或者Al
2O
3。
进一步地,所述高温退火处理在氧气氛围中进行。
进一步地,所述高温退火处理的温度变化方式为线性或者阶梯状变化。
进一步地,所述退火温度为200℃至900℃中的任意值,退火时间为10秒至100分钟。
进一步地,所述退火温度为400℃和450℃,每种温度下的退火时间均为10分钟。
本申请实施例通过在N-低浓度Ga
2O
3外延层上淀积掩膜层,并去除掩膜层与阳极金属层对应的区域以外的部分,得到一个只有阳极金属层对应区域覆盖有掩膜层的氧化镓SBD终端样品,对此样品进行退火处理,可以只使掩膜层与阳极金属层对应区域以外的部分形成掺杂浓度由下至上的逐渐减小的变化,而不改变阳极金属层对应区域的掺杂浓度,从而实现在低导通电阻的情况下,提高氧化镓SBD终端结构的击穿电压。
为了更清楚地说明本申请实施例中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的氧化镓SBD终端结构示意图;
图2是本申请实施例提供的氧化镓SBD终端结构制备方法的流程图;
图3是本申请实施例提供的氧化镓SBD终端结构淀积掩膜层的结构示意图;
图4是本申请实施例提供的氧化镓SBD终端样品进行退火处理后的结构示意图。
图中:1、阴极金属层;2、N+高浓度衬底层;3、N-低浓度Ga
2O
3外延层;31、第二N-低浓度Ga
2O
3外延层;3’、掩膜层;4、阳极金属层。
以下描述中,为了说明而不是为了限定,提出了诸如特定系统结构、技术之类的具体细节,以便透彻理解本申请实施例。然而,本领域的技术人员应当清楚,在没有这些具体细节的其它实施例中也可以实现本申请。在其它情况中,省略对众所周知的系统、装置、电路以及方法的详细说明,以免不必要的细节妨碍本申请的描述。
为了说明本申请所述的技术方案,下面通过具体实施例来进行说明。
如图1所示,氧化镓SBD终端结构包括阴极金属层1、N+高浓度衬底层2、N-低浓度Ga
2O
3外延层3和阳极金属层4,其中N-低浓度Ga
2O
3外延层3在靠近阳极金属层4的一定厚度范围内,阳极金属层下方的掺杂浓度大于阳极金属层两侧的掺杂浓度。
具体地,第二N-低浓度Ga
2O
3外延层31属于N-低浓度Ga
2O
3外延层3,为靠近阳极金属层的一定厚度范围内,阳极金属层对应区域以外的部分,第二N-低浓度Ga
2O
3外延层31的掺杂浓度小于阳极金属层对应区域的掺杂浓度。
在上述实施例的基础上:
作为一种优选的实施例,N-低浓度Ga
2O
3外延层的电子浓度为1.0×1015 cm
-3至1.0×1020 cm
-3。
具体的,N-低浓度Ga
2O
3外延层3的掺杂浓度可以为一个固定值,也可以是一个梯度变化的值。
作为一种优选的实施例,N-低浓度Ga
2O
3外延层3的厚度为100nm至50μm。
作为一种优选的实施例,N+高浓度衬底层2的材料为Ga
2O
3或SiC。
作为一种优选的实施例,阳极金属层为Ni/Au,所述阴极金属层为Ti/Au。
如图2所示,本发明中公开了一种氧化镓SBD终端结构的制备方法,包括
步骤S101,在N+高浓度衬底层上生长N-低浓度Ga
2O
3外延层;
步骤S102,如图3所示,在所述N-低浓度Ga
2O
3外延层上淀积掩膜层3’;
作为一种优选的实施例,所述掩膜层材料为采用PECVD或者溅射方式实现的SiO
2、SiN或者Al
2O
3。
具体的,所述掩膜层的厚度为50nm至3000nm。
步骤S103,去除掩膜层与阳极金属层对应的区域以外的部分,得到氧化镓SBD终端样品;
具体的,可以在阳极金属层对应的区域涂覆上一层光刻胶,然后再采用干法或湿法刻蚀的方式去除阳极金属层对应的区域以外的部分的掩膜层。
步骤S104,如图4所示,对所述氧化镓SBD终端样品进行含至少两种温度的高温退火处理;
具体的,由于阳极金属层对应的N-低浓度Ga
2O
3外延层上表面淀积有掩膜层3’,因此退火处理会使与阳极金属层对应的区域以外的部分的掺杂浓度在靠近阳极金属层的一定厚度范围内,由下至上逐渐减小;而退火处理并没有改变阳极金属层对应的区域的掺杂浓度,即阳极金属层下方为未进行退火处理区域,这样就在靠近阳极金属层的一定厚度范围内的N-低浓度Ga
2O
3外延层中引入了横向浓度变化,从而使整体氧化镓SBD终端结构的导通电阻更低。
其中,两个不同温度的退火处理会导致N-低浓度Ga
2O
3外延层的表面区域掺杂浓度降低,从而实现掺杂浓度自下至上,从内部到表面逐渐减小。
步骤S105,去除经过高温退火处理后的氧化镓SBD终端样品上的掩膜层,并在氧化镓SBD终端样品的两侧分别形成阳极金属层和阴极金属层。
作为一种优选的实施例,高温退火处理在氧气氛围中进行。
作为一种优选的实施例,高温退火处理的温度变化方式为线性或者阶梯状变化。
其中,温度变化可以是先高温后低温,也可以是先低温后高温。
作为一种优选的实施例,退火温度为200℃至900℃中的任意值,退火时间为10秒至100分钟。
作为一种优选的实施例,所述退火温度为400℃和450℃,每种温度下的退火时间均为10分钟。
以上所述实施例仅用以说明本申请的技术方案,而非对其限制;尽管参照前述实施例对本申请进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围,均应包含在本申请的保护范围之内。
Claims (12)
- 一种氧化镓SBD终端结构,其特征在于,自下至上包括阴极金属层、N+高浓度衬底层、N-低浓度Ga 2O 3外延层和阳极金属层,其中,N-低浓度Ga 2O 3外延层在靠近阳极金属层的一定厚度范围内,阳极金属层下方的掺杂浓度大于阳极金属层两侧的掺杂浓度。
- 如权利要求1所述的氧化镓SBD终端结构,其特征在于,所述N-低浓度Ga 2O 3外延层在靠近阳极金属层的一定厚度范围内,掺杂浓度自下至上逐渐减小。
- 如权利要求1所述的氧化镓SBD终端结构,其特征在于,所述N-低浓度Ga 2O 3外延层的电子浓度为1.0×1015 cm -3至1.0×1020 cm -3。
- 如权利要求1所述的氧化镓SBD终端结构,其特征在于,所述N-低浓度Ga 2O 3外延层的厚度为100nm至50μm。
- 如权利要求1所述的氧化镓SBD终端结构,其特征在于,所述N+高浓度衬底层的材料为Ga 2O 3或SiC。
- 如权利要求1至5任一项所述的氧化镓SBD终端结构,其特征在于,所述阳极金属层为Ni/Au,所述阴极金属层为Ti/Au。
- 一种氧化镓SBD终端结构的制备方法,其特征在于,包括以下步骤:在N+高浓度衬底层上生长N-低浓度Ga 2O 3外延层;在所述N-低浓度Ga 2O 3外延层上淀积掩膜层;去除掩膜层与阳极金属层对应的区域以外的部分,得到氧化镓SBD终端样品;对所述氧化镓SBD终端样品进行含至少两种温度的高温退火处理;去除经过高温退火处理后的氧化镓SBD终端样品上的掩膜层,并在氧化镓SBD终端样品的两侧分别形成阳极金属层和阴极金属层。
- 如权利要求7所述的氧化镓SBD终端结构的制备方法,其特征在于,所述掩膜层材料为采用PECVD或者溅射方式实现的SiO 2、SiN或者Al 2O 3。
- 如权利要求7所述的氧化镓SBD终端结构的制备方法,其特征在于,所述高温退火处理在氧气氛围中进行。
- 如权利要求7所述的氧化镓SBD终端结构的制备方法,其特征在于,所述高温退火处理的温度变化方式为线性或者阶梯状变化。
- 如权利要求7至10任一项所述的氧化镓SBD终端结构的制备方法,其特征在于,所述退火温度为200℃至900℃中的任意值,退火时间为10秒至100分钟。
- 如权利要求11所述的氧化镓SBD终端结构的制备方法,其特征在于,所述退火温度为400℃和450℃,每种温度下的退火时间均为10分钟。
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