WO2024050865A1 - 一种垂直型氧化镓晶体管及其制备方法 - Google Patents

一种垂直型氧化镓晶体管及其制备方法 Download PDF

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WO2024050865A1
WO2024050865A1 PCT/CN2022/119566 CN2022119566W WO2024050865A1 WO 2024050865 A1 WO2024050865 A1 WO 2024050865A1 CN 2022119566 W CN2022119566 W CN 2022119566W WO 2024050865 A1 WO2024050865 A1 WO 2024050865A1
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layer
gallium oxide
prepare
preparing
annealing
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周选择
徐光伟
龙世兵
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中国科学技术大学
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Priority to US18/216,425 priority Critical patent/US20240079477A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/42—Bombardment with radiation
    • H01L21/423—Bombardment with radiation with high-energy radiation
    • H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a vertical gallium oxide transistor and a preparation method thereof.
  • Gallium oxide is an emerging ultra-wide band gap semiconductor material. Transistors based on gallium oxide materials have the characteristics of potential breakdown resistance and low loss, and are expected to be used in the field of power electronics. Gallium oxide transistors are divided into two types: horizontal and vertical. As shown in Figure 1(a), it is a horizontal structure transistor. In the existing technology, the gallium oxide transistor structure is mainly horizontal type (conventional accumulation type horizontal MOSFET). The horizontal structure gallium oxide field effect transistor cannot withstand high voltage due to its thin channel thickness. High current density makes it difficult to meet actual application requirements.
  • FIG. 1(b) it is a vertical structure transistor.
  • Vertical transistors can withstand higher currents and therefore have greater potential than horizontal devices.
  • P-type gallium oxide it is impossible to design conventional vertical MOSFET structures like traditional semiconductor Si or SiC, such as VDMOSFET, UMOSFET, etc.
  • junction devices that is, between the source and drain electrodes.
  • the existing technology usually adopts structures such as current aperture vertical transistor (CAVET) or vertical fin structure transistor (FinFET).
  • CAVET current aperture vertical transistor
  • FinFET vertical fin structure transistor
  • the CAVET structure is realized by implanting N ions and Si ions.
  • the N ion implanted area serves as the current blocking layer
  • the Si ion implanted area serves as the electron channel layer.
  • the FinFET structure uses fine fin channels, each fin channel is about a few hundred nanometers wide.
  • Both CAVET and FinFET structures work in accumulation mode (no junction type), unlike conventional VDMOSFET and UMOSFET which work in inversion mode (junction type).
  • junctionless devices A huge problem with junctionless devices is that the device is unstable and generally tends to be depletion mode (meaning that the threshold voltage is less than zero, corresponding to the enhancement mode).
  • the threshold voltage of the device is prone to offset, and the threshold voltage of multiple devices The uniformity is poor, so it is difficult to achieve mass production according to standards.
  • a junction device If a junction device operates in inversion mode, it must be an enhancement device. Enhancement devices are more acceptable to the industry and have better threshold voltage stability. Therefore, it is necessary to develop a gallium oxide transistor structure that operates in the inversion mode.
  • the present invention mainly solves the problems in the prior art that the current of the gallium oxide field effect transistor is not large enough, the enhancement mode is difficult to realize, and the threshold voltage is easy to shift. It designs a vertical structure gallium oxide field effect transistor that works in the quasi-inversion mode.
  • the invention discloses a vertical gallium oxide transistor, which is a quasi-P-type doped vertical gallium oxide transistor.
  • the quasi-p-type is doped with compensation electrons and does not generate holes.
  • the specific preparation method is as follows:
  • a method for preparing a vertical gallium oxide transistor including the following steps:
  • the annealing atmosphere in step 1) also includes: the air pressure is not less than a standard atmospheric pressure, and the oxygen atmosphere is a pure oxygen atmosphere or a mixed atmosphere of oxygen, nitrogen and argon.
  • step 3) includes the following preparation process:
  • etching depth is determined based on the depth of the oxide layer during the high-temperature annealing treatment in step 1);
  • the annealing activation includes: annealing in a nitrogen or argon environment at a temperature of 100 to 1100°C and within 1 hour.
  • the rapid thermal annealing includes: annealing in a nitrogen or argon atmosphere at a temperature of 400-550°C and a time of 1 minute.
  • the doping element is a donor impurity, including Si, Sn or Ge.
  • the method for preparing the gate electrode, drain electrode and source electrode includes: evaporating Ti/Au using electron beam evaporation, magnetron sputtering or thermal evaporation.
  • a method for preparing a vertical gallium oxide transistor 1) using N ion implantation to prepare a high-resistance layer on the gallium oxide material, forming an initial sample with a single crystal layer and a high-resistance layer;
  • N ion implantation has an energy range of 100-680keV, a dose range of 10 12 -10 15 cm -3 , and is annealed at 900-1200°C for 10 to 120 minutes in a nitrogen or argon environment.
  • the present invention provides a gallium oxide transistor with a vertical structure, and the entire material can conduct electricity, so it can solve the problem of insufficient current in the existing technology;
  • the alternative is to use oxygen environment annealing to form an oxidized layer or N ion implantation to form a similar layer as a quasi-inversion layer.
  • the difference from p-type doping is that quasi-p-type doping cannot generate holes and can only compensate electrons. It can realize gallium oxide field effect transistors with a quasi-inversion structure, so it can solve the difficulty of enhancement-type
  • the problem is that the threshold voltage is easy to shift.
  • High-temperature annealing in oxygen atmosphere affects the change of carrier concentration.
  • the concentration is reduced to close to zero, so it can be used as a high-resistance layer.
  • after forming a high-resistance layer it can be used as a "quasi-inversion" layer. Breaking through the common preparation logic.
  • This solution uses high-temperature annealing, that is, oxygen atmosphere annealing in the range of 1000 to 1400°C, and annealing time of 1-24 hours.
  • This technology can form a high-resistance layer (quasi-inversion layer); currently, it is not There are no published technical documents indicating that annealing temperatures above 600°C can form a high-resistance layer for single crystal gallium oxide, so this technology is original.
  • the existing Si ion implantation is usually used to improve functions such as ohmic contact, while the purpose of N ion implantation in this solution is to compensate for doping and form a high-resistance layer (quasi-inversion layer).
  • This solution The idea of preparing a high-resistance layer (quasi-inversion layer) was proposed, and the idea was realized through ion implantation, which is original.
  • Figure 1(a) is a gallium oxide horizontal structure transistor
  • Figure 1(b) is a gallium oxide vertical structure transistor
  • Figure 2 is a flow chart of a method for preparing a vertical gallium oxide transistor
  • Figure 3 Vertical gallium oxide transistor with gate electrode on the outside
  • This embodiment discloses a vertical gallium oxide transistor that uses oxygen atmosphere high-temperature annealing technology to prepare a quasi-P-type doping, which is used to replace p-type doping to achieve device functions. As shown in Figure 1(b) and Figure 2.
  • the annealing atmosphere also includes: the air pressure is a standard atmospheric pressure or higher, and the atmosphere is a pure oxygen atmosphere or a mixed atmosphere of oxygen and nitrogen or argon.
  • step 2) uses BCl 3 and Ar or Cl 2 as etching gases to perform inductively coupled plasma etching to remove the defective layer and oxidized layer on the back and the defective layer on the front. ) carved out.
  • a heavily doped contact layer is formed using epitaxial growth or ion implantation.
  • the doping elements can be donor impurities such as Si, Sn, Ge, etc., and are activated by annealing at a temperature of 100 to 1100°C in a nitrogen or argon atmosphere within 1 hour.
  • the purpose is to improve the source ohmic contact quality.
  • the preparation process of the contact layer is not limited to these two. If the technology can be realized, other solutions are not excluded. The preparation of other layers is the same as below.
  • Photolithography is used for patterning, and Ti/Au or Cr/Au metal electrodes are evaporated using electron beam evaporation, magnetron sputtering, or thermal evaporation to form the ohmic contact of the source electrode. And adopt rapid thermal annealing method, annealing in nitrogen or argon gas environment, annealing at 400-550°C for about 1 minute to improve the contact quality of ohmic contact.
  • etching depth is determined based on the depth of the oxide layer during the high-temperature annealing treatment in step 1):
  • etching depth needs to be determined based on the effect of oxygen atmosphere annealing or ion implantation, and is generally within the range of 100 nanometers to 5 microns.
  • gate dielectrics such as aluminum oxide, hafnium oxide, zirconium oxide, silicon oxide, or stacked layers of the above dielectrics.
  • Total dielectric thickness ranges from 10nm to 200nm.
  • Photolithography is used for patterning, and etching is used to open holes 10 in the gate dielectric to expose the electrode area.
  • the etching method can be either dry etching or wet etching.
  • Photolithography is used for patterning, and Ni/Au or other metals or polycrystalline Si are evaporated using electron beam evaporation, magnetron sputtering or thermal evaporation to form the gate electrode.
  • Steps 3-7 can be switched to any step between steps 3-1 to 3-6 without affecting the final result. The order of other steps cannot be reversed.
  • this embodiment provides a more limited method for preparing a preferred vertical gallium oxide transistor and a vertical gallium oxide transistor prepared by this method, including the following steps:
  • BCl3 and Ar or Cl2 as etching gases to perform inductively coupled plasma etching to etch away the defective layer and oxidized layer on the back and the defective layer on the front.
  • Step 9 can be switched to any step between steps 3-8 without affecting the final result. The order of other steps cannot be reversed.
  • Example 2 Based on the solutions of Example 1 and Example 2, another method for preparing a vertical gallium oxide transistor is provided. The difference is that in the first step, N ion implantation is used to prepare a high-resistance layer of the gallium oxide material to form a single crystal layer. and the initial sample of the high-resistance layer; and delete the second step, the remaining steps remain unchanged, refer to the above.
  • N ion implantation has an energy range of 100-680keV, a dose range of 10 12 -10 15 cm -3 , and is annealed at 900-1200°C for 10 to 120 minutes in a nitrogen or argon environment.
  • N ions are implanted with an energy of 480keV, a dose of 10 14 cm -3 , and annealing at 1100°C for 1 hour in a nitrogen environment.
  • Figure 4 shows the structure of two devices connected in parallel.
  • the present invention uses oxygen atmosphere annealing or N ion implantation to form a high-resistance layer, and uses Si, Sn, and Ge ion implantation to form a heavily doped layer, so that the channel between the source and drain in the transistor structure forms an "n-type conductive layer.”
  • the composition of "layer-high-resistance layer-n-type conductive layer” causes the device to be in a state where current cannot be conducted under normal conditions.
  • the high-resistance layer accumulates electrons, and the original channel forms a composition of "n-type conductive layer-electron accumulation layer-n-type conductive layer", and the device state changes to a state where current can be conducted. The switching characteristics of the transistor are thus achieved.

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Abstract

本发明公开了半导体技术领域的一种垂直型氧化镓晶体管及其制备方法，方法包括以下步骤：对氧化镓材料在1000～1400℃范围内的氧气氛围退火，退火时间1-24h，形成单晶层、缺陷层和氧化层；将氧化镓材料背面的缺陷层和氧化层，以及氧化镓材料正面的缺陷层去除，得到初始样品；在氧化层上制备重掺杂的接触层，在接触层上制备源电极层，以及制备垂直于样品平面的沟槽，在沟槽制备栅介质层，制备栅电极和漏电极。针对现有技术氧化镓场效应晶体管电流不够大，增强型难以实现，且阈值电压容易偏移的问题，设计了垂直型结构的工作于准反型模式的氧化镓场效应晶体管及其制备方法。

Description

一种垂直型氧化镓晶体管及其制备方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种垂直型氧化镓晶体管及其制备方法。
背景技术
氧化镓作为新兴的超宽禁带半导体材料，基于氧化镓材料的晶体管具有潜在耐击穿低损耗的特点，有望用于电力电子领域。氧化镓晶体管按结构类型划分，可分为水平型和垂直型两种类型。如图1(a)是水平结构晶体管，现有技术中氧化镓晶体管结构以水平型(常规的积累型水平MOSFET)为主，水平结构的氧化镓场效应晶体管由于沟道厚度较薄难以承受较高的电流密度，因此难以满足实际的应用需求。
如图1(b)是垂直结构晶体管，垂直型晶体管则能够承受更高的电流，因此比水平器件更有潜力。然而目前氧化镓P型掺杂困难，无法像传统半导体Si或SiC那样设计常规的垂直MOSFET结构，如VDMOSFET，UMOSFET等，该两种常规结构都是有结型器件，即源、漏电极之间存在PN结实现电学隔离，有结型器件工作于反型模式。
为实现氧化镓垂直MOSFET结构，现有技术通常采用如电流孔径型垂直晶体管(CAVET)或垂直鳍式结构晶体管(FinFET)等结构。CAVET结构采用N离子和Si离子注入来实现，N离子注入区域作为电流阻挡层，Si离子注入区作为电子沟道层。FinFET结构采用精细的鳍式沟道，每个鳍沟道宽约几百纳米。无论是CAVET还是FinFET结构都是工作于积累模式(无结型)，不同于常规VDMOSFET与UMOSFET工作于反型模式(有结型)。无结型器件存在巨大的问题是器件不稳定，一般情况下趋于耗尽型(指阈值电压小于零，与增强型相对应)，器件的阈值电压容易发生偏移，多个器件的阈值电压均一性较差，因此难以按标准实现量产化。有结型器件工作于反型模式，则必然为增强型器件，增强型器件更能够被业界所接受，且阈值电压稳定性较好。因此有必要发展有结型工作于反型模式的氧化镓晶体管结构。
发明内容
本发明主要解决现有技术下氧化镓场效应晶体管电流不够大，增强型难以实现，且阈值电压容易偏移的问题，设计了垂直型结构的工作于准反型模式的氧化镓场效应晶体管。
本发明公开一种垂直型氧化镓晶体管，其是一种准P型掺杂的垂直型氧化镓晶体管，准p型掺杂有补偿电子，不产生空穴。具体制备方式如下：
一种垂直型氧化镓晶体管的制备方法，包括以下步骤：
1)对氧化镓材料在1000～1400℃范围内的氧气氛围退火，退火时间1-24h，形成单晶层、缺陷层和氧化层；
2)将氧化镓材料背面的缺陷层和氧化层，以及氧化镓材料正面的缺陷层去除，得到初始样品；
3)在氧化层上制备重掺杂的接触层，在接触层上制备源电极层，以及制备垂直于样品平面的沟槽，在沟槽制备栅介质层，制备栅电极和漏电极。
作为一种优选的方案，步骤1)退火氛围还包括：气压不小于一个标准大气压，氧气氛围是纯氧氛围或者氧气与氮气和氩气的混合氛围。
作为一种优选的方案，步骤3)包括以下制备工艺：
3-1，在样品正面氧化层上制备重掺杂的接触层，退火激活；
3-2，采用图形化工艺，制备欧姆接触的金属电极形成源电极的欧姆接触，快速热退火；
3-3，进行电感耦合等离子刻蚀，形成垂直于样品平面的沟槽，刻蚀深度根据1)步骤中高温退火处理的氧化层深度确定；
3-4，在沟槽和样品表面生长栅介质；
3-5，采用图形化工艺，对栅介质进行开孔，露出电极区域；
3-6，采用图形化工艺，制备栅电极；
3-7，制备能够形成欧姆接触的金属电极形成漏电极的欧姆接触，快速热退火。
作为一种优选的方案，步骤3-1，所述退火激活包括：在氮气或氩气环境氛围退火，温度100至1100℃，时间1小时之内。
作为一种优选的方案，所述快速热退火包括：在氮气或氩气环境氛围退火，温度400-550℃，时间1分钟。
作为一种优选的方案，制备重掺杂的接触层中，掺杂元素为施主杂质，包括Si、Sn或Ge。
作为一种优选的方案，制备栅电极、漏电极和源电极的方法包括：利用电子束蒸发、磁控溅射或热蒸发方式蒸镀Ti/Au。
还公开另一种制备方案：
一种垂直型氧化镓晶体管的制备方法，1)对氧化镓材料采用N离子注入的方式制备高阻层，形成有单晶层和高阻层的初始样品；
2)在氧化层上制备重掺杂的接触层，在接触层上制备源电极层，以及制备垂直于样品平面的沟槽，在沟槽制备栅介质层，制备栅电极和漏电极。
其中，N离子注入，能量范围100-680keV，剂量范围10 12-10 15cm -3，并在氮气或氩气环境下900-1200℃退火10～120min。
本发明具有如下有益效果：
首先，本发明提供氧化镓晶体管为垂直结构，整个体材料都能导电，因此可以解决现有技术电流不够大的问题；
其次，鉴于氧化镓材料没有P型掺杂，做不了反型的缺陷，采用了用氧气环境退火形成oxidized layer或N离子注入形成类似的layer作为准反型层的思路实现替代方案。
作为准p型掺杂，与p型掺杂的区别在于准p型掺杂无法产生空穴，只能补偿电子，其可以实现准反型结构的氧化镓场效应晶体管，因此可以解决增强型难以实现且阈值电压容易偏移的问题。氧氛围下高温退火影响载流子浓度的变化，在defective layer和oxidized layer中，由于氧氛围高温退火或者N离子注入的产生补偿掺杂作用，使浓度降低至接近零，因此可以作为高阻层，形成了高阻层后就可以当作“准反型”层使用。突破了常见的制备逻辑。
具体地说明：本方案中采用高温退火，即在1000～1400℃范围内的氧气氛围退火，退火时间1-24h的技术，该技术能够形成高阻层(准反型层)；而目前，并没有公开的技术文献指出600℃以上的退火温度对单晶氧化镓能够形成高阻层，所以该技术具备独创性。
关于离子注入技术，例如现有的采用如Si离子注入，通常是为了提升欧姆接触等功能，而本方案N离子注入的目的是补偿掺杂，形成高阻层(准反型层)，本方案提出了一种高阻层(准反型层)的制备思想，从而通过离子注入实现了该思想，具备了独创性。
进一步的，本方案中无需覆盖SiO2作为遮挡层，具有制备工艺优势。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1(a)是氧化镓水平结构晶体管；
图1(b)是氧化镓垂直结构晶体管；
图2是一种垂直型氧化镓晶体管制备方法的流程图；
图3栅电极在外侧的垂直型氧化镓晶体管；
图4双极并联的垂直型氧化镓晶体管。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领 域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的权利要求书和说明书的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序，应该理解这样使用的术语在适当情况下可以互换，这仅仅是描述本申请的实施例中对相同属性的对象在描述时所采用的区分方式，此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，以便包含一系列单元的过程、方法、系统、产品或设备不必限于那些单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其他单元。
实施例1：
本实施例公开一种垂直型氧化镓晶体管，采用氧氛围高温退火技术，制备一种准P型掺杂，用于代替p型掺杂实现器件功能。如图1(b)和图2所示。
1)对氧化镓材料在1000～1400℃范围内的氧气氛围退火，退火时间1-24h，形成单晶层1、缺陷层2和氧化层3；
2)将氧化镓材料背面的缺陷层2和氧化层3，以及氧化镓材料正面的缺陷层3去除，得到初始样品；
3)在氧化层上制备重掺杂的接触层4，在接触层上制备源电极层5，以及制备垂直于样品平面的沟槽6，在沟槽制备栅介质层7，制备栅电极8和漏电极9。
其中，退火氛围还包括：气压为一个标准大气压或者更高的气压，氛围是纯氧氛围或者氧气与氮气或氩气的混合氛围。
其中，步骤2)用BCl 3和Ar或Cl 2作为刻蚀气体，进行电感耦合等离子体刻蚀，将背面的缺陷层(defective layer)和氧化层(oxidized layer)以及正面的缺陷层(defective layer)刻掉。
其中，关于3)在氧化层上制备重掺杂的接触层，在接触层上制备源电极层，以及制备垂直于样品平面的沟槽，在沟槽制备栅介质层，制备栅电极和漏电极。详细的描述如下：
3-1，在样品正面氧化层上制备重掺杂的接触层，退火激活：
采用外延生长的方式或者离子注入的方式，形成一层重掺杂的接触层(implanted layer)。掺杂元素可以是Si、Sn、Ge等施主杂质，并退火激活，温度为100至1100℃，氮气或氩气氛围，时间1小时之内。目的是提升源欧姆接触质量。接触层的制备工艺并不仅限该两种，若技术能实现，并不排除其他方案，同下其他层的制备。
3-2，采用图形化工艺，制备欧姆接触的金属电极形成源电极的欧姆接触，快速热退火：
采用光刻手段图形化，利用电子束蒸发或磁控溅射或热蒸发等方式蒸镀Ti/Au或Cr/Au 金属电极形成源电极的欧姆接触。并采用快速热退火方式，在氮气或氩气气体环境氛围退火，400-550℃退火约1分钟，提升欧姆接触的接触质量。
3-3，进行电感耦合等离子刻蚀，形成垂直于样品平面的沟槽，刻蚀深度根据1)步骤中高温退火处理的氧化层深度确定：
用BCl 3和Ar或Cl 2作为刻蚀气体，进行电感耦合等离子体刻蚀，形成垂直于样品平面的沟槽。刻蚀深度需要根据氧氛围退火或者离子注入的效果来判定，一般在百纳米到5微米范围之内。
3-4，在沟槽和样品表面生长栅介质：
使用原子层沉积或磁控溅射或电子束蒸发等镀膜方式，生长高质量的栅介质，如氧化铝、氧化铪、氧化锆、氧化硅或是以上介质的堆叠层。介质总厚度在10nm至200nm范围内。
3-5，采用图形化工艺，对栅介质进行开孔，露出电极区域：
采用光刻手段图形化，利用刻蚀方法对栅介质进行开孔10，露出电极区域。刻蚀方法采用干法刻蚀或者湿法刻蚀均可。
3-6，采用图形化工艺，制备栅电极：
采用光刻手段图形化，利用电子束蒸发或磁控溅射或热蒸发等方式蒸镀Ni/Au或其他金属或多晶Si形成栅电极。
3-7，制备能够形成欧姆接触的金属电极形成漏电极的欧姆接触，快速热退火：
利用电子束蒸发或磁控溅射或热蒸发等方式蒸镀Ti/Au或其他能够形成欧姆接触的金属电极形成漏电极的欧姆接触，并采用快速热退火方式，在氮气或氩气气体环境氛围退火400-550℃退火约1分钟，提升欧姆接触的接触质量。
其中步骤3-7可以调换至步骤3-1至3-6任何一个步骤之间，不影响最终结果。其他步骤顺序不可调换。
实施例2
基于上述实施例1的方案，本实施例提供一种更加限定的优选垂直型氧化镓晶体管的制备方法以及依靠该方法制备的垂直型氧化镓晶体管，包括如下步骤：
1)对氧化镓材料进行1150℃的纯氧气氛围退火6小时，一个标准大气压下。
2)用BCl3和Ar或Cl2作为刻蚀气体，进行电感耦合等离子体刻蚀，将背面的缺陷层(defective layer)和氧化层(oxidized layer)以及正面的缺陷层(defective layer)刻掉。
3)采用离子注入的方式，形成一层重掺杂的接触层，其中，掺杂元素Si，并退火激活，温度为950℃，氩气氛围，时间1小时，温度和时间允许误差。
4)采用光刻手段图形化，利用电子束蒸发蒸镀Ti/Au形成源电极的欧姆接触。并采用快速热退火方式，在氮气环境氛围退火，470℃退火1分钟。
5)用BCl3和Ar作为刻蚀气体，进行电感耦合等离子体刻蚀，形成垂直于样品平面的1微米深沟槽。
6)在沟槽使用原子层沉积生长高质量的50nm氧化铝。
7)采用光刻手段图形化，利用干法刻蚀方法对氧化铝栅介质进行开孔，露出下方源电极区。
8)采用光刻手段图形化，利用电子束蒸发方式蒸镀Ni/Au形成栅电极。
9)利用电子束蒸发方式蒸镀Ti/Au形成漏电极的欧姆接触，并采用快速热退火方式，在氮气环境氛围退火470℃退火约1分钟，提升欧姆接触的接触质量。
其中步骤9可以调换至步骤3-8任何一个步骤之间，不影响最终结果。其他步骤顺序不可调换。
实施例3
基于实施例1和实施例2的方案，提供另一种垂直型氧化镓晶体管的制备方法，区别在于第一步，对氧化镓材料采用N离子注入的方式制备高阻层，形成有单晶层和高阻层的初始样品；并删除第二步，其余步骤保持不变，可参考上文所述。
其中，N离子注入，能量范围100-680keV，剂量范围10 12-10 15cm -3，并在氮气或氩气环境下900-1200℃退火10～120min。
作为一种优选的方案，N离子注入，能量480keV,剂量10 14cm -3，并在氮气环境1100℃退火1小时。
实施例4：
基于实施例1-实施例3的方案，再次变形，如图3制备一种栅电极在外侧的新型氧化镓垂直晶体管，调整栅电极和源电极位置；保持上述实施例的制备步骤不变，将栅电极和源电极交换位置；在初始样品的两侧制备沟槽。
作为又一种变形，采取两个或两个以上器件多级并联的方式，如图4给出了两个器件并联的结构。
本发明器件的工作原理
本发明采用氧气氛围退火或者N离子注入的方式形成高阻层，用Si、Sn、Ge离子注入形成重掺杂层，使晶体管结构中的源极和漏极之间的通道构成“n型导电层-高阻层-n型导电层”的组成形式，导致器件常态下为电流无法导通状态。当器件栅电压施加正偏压后，高阻层积累电子，原本的通道构成“n型导电层-电子积累层-n型导电层”的组成形式，器件状态转变 为电流能够导通的状态。因此实现了晶体管的开关特性。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何在本发明揭露的技术范围内的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种垂直型氧化镓晶体管的制备方法，其特征在于，包括以下步骤：
    1)对氧化镓材料在1000～1400℃范围内的氧气氛围退火，退火时间1-24h，形成单晶层、缺陷层和氧化层；
    2)将氧化镓材料背面的缺陷层和氧化层，以及氧化镓材料正面的缺陷层去除，得到初始样品；
    3)在氧化层上制备重掺杂的接触层，在接触层上制备源电极层，以及制备垂直于样品平面的沟槽，在沟槽制备栅介质层，制备栅电极和漏电极。
  2. 根据权利要求1所述的一种垂直型氧化镓晶体管的制备方法，其中，步骤1)退火氛围还包括：气压不小于一个标准大气压，氧气氛围是纯氧氛围或者氧气与氮气或氩气的混合氛围。
  3. 根据权利要求1所述的一种垂直型氧化镓晶体管的制备方法，其中，步骤3)包括以下制备工艺：
    3-1，在样品正面氧化层上制备重掺杂的接触层，退火激活；
    3-2，采用图形化工艺，制备欧姆接触的金属电极形成源电极的欧姆接触，快速热退火；
    3-3，进行电感耦合等离子刻蚀，形成垂直于样品平面的沟槽，刻蚀深度根据1)步骤中高温退火处理的氧化层深度确定；
    3-4，在沟槽和样品表面生长栅介质；
    3-5，采用图形化工艺，对栅介质进行开孔，露出电极区域；
    3-6，采用图形化工艺，制备栅电极；
    3-7，制备能够形成欧姆接触的金属电极形成漏电极的欧姆接触，快速热退火。
  4. 根据权利要求3所述的一种垂直型氧化镓晶体管的制备方法，其中，步骤3-1，所述退火激活包括：在氮气或氩气环境氛围退火，温度100至1100℃，时间1小时之内。
  5. 根据权利要求3所述的一种垂直型氧化镓晶体管的制备方法，其中，所述快速热退火包括：在氮气或氩气环境氛围退火，温度400-550℃，时间1分钟。
  6. 根据权利要求1或3所述的一种垂直型氧化镓晶体管的制备方法，其中，制备重掺杂的接触层中，掺杂元素为施主杂质，包括Si、Sn或Ge。
  7. 根据权利要求1或3所述的一种垂直型氧化镓晶体管的制备方法，其中，制备栅电极、漏电极和源电极的方法包括：利用电子束蒸发、磁控溅射或热蒸发方式蒸镀Ti/Au。
  8. 一种垂直型氧化镓晶体管的制备方法，其特征在于，1)对氧化镓材料采用N离子注入的方式制备高阻层，形成有单晶层和高阻层的初始样品；
    2)在氧化层上制备重掺杂的接触层，在接触层上制备源电极层，以及制备垂直于样品平 面的沟槽，在沟槽制备栅介质层，制备栅电极和漏电极。
  9. 根据权利要求8所述的一种垂直型氧化镓晶体管的制备方法，其特征在于，N离子注入，能量范围100-680keV，剂量范围10 12-10 15cm -3，并在氮气或氩气环境下900-1200℃退火10～120min。
  10. 一种垂直型氧化镓晶体管，其特征在于，包括根据权利要求1-7任一所述的一种制备方法制备的垂直型氧化镓晶体管；
    或，包括根据权利要求8或9所述的制备方法制备的垂直型氧化镓晶体管。
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