WO2021248879A1 - 一种mps二极管器件及其制备方法 - Google Patents

一种mps二极管器件及其制备方法 Download PDF

Info

Publication number
WO2021248879A1
WO2021248879A1 PCT/CN2020/140006 CN2020140006W WO2021248879A1 WO 2021248879 A1 WO2021248879 A1 WO 2021248879A1 CN 2020140006 W CN2020140006 W CN 2020140006W WO 2021248879 A1 WO2021248879 A1 WO 2021248879A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
epitaxial layer
substrate
diode device
buffer
Prior art date
Application number
PCT/CN2020/140006
Other languages
English (en)
French (fr)
Inventor
林苡任
陈道坤
曾丹
史波
Original Assignee
珠海格力电器股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 珠海格力电器股份有限公司 filed Critical 珠海格力电器股份有限公司
Priority to EP20939599.5A priority Critical patent/EP4167297A4/en
Priority to JP2022570212A priority patent/JP7400128B2/ja
Publication of WO2021248879A1 publication Critical patent/WO2021248879A1/zh
Priority to US18/063,891 priority patent/US20230105596A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02601—Nanoparticles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/0485—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/0495—Schottky electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/122—Single quantum well structures
    • H01L29/127—Quantum box structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched

Definitions

  • the present disclosure relates to the technical field of electronic devices, in particular to an MPS diode device and a preparation method thereof.
  • SiC As a third-generation new semiconductor, SiC has the characteristics of wide band gap, high critical breakdown electric field, and high thermal conductivity. Its application in high temperature, high voltage, high frequency, high power and other fields has a lot to do with traditional silicon-based devices. Big advantage.
  • SiC SBD Silicon Carbide Schottky Barrier Diode
  • JBS junction barrier schottky
  • MPS merge pin schottky
  • the depletion region formed at the p-type heavily doped region can withstand a large reverse voltage on the one hand
  • the depletion region is connected to each other to wrap the Schottky junction, which can prevent the increase of reverse leakage caused by the reduction of the Schottky barrier when the device is operating in the reverse direction, but the reverse leakage and forward operating voltage are usually required The two performance parameters are compromised.
  • the related technology cannot reduce the reverse leakage of the device while reducing the forward conduction loss of the device.
  • the present disclosure provides an MPS diode device and a preparation method thereof.
  • the above-mentioned MPS diode device reduces the reverse leakage loss while reducing the forward conduction loss, so that the two performance parameters of reverse leakage and forward working voltage can be improved at the same time. So as to achieve higher performance.
  • An MPS diode device includes a plurality of cells arranged in parallel, in which:
  • Each cell includes a cathode electrode and a substrate, an epitaxial layer, a buffer layer, and an anode electrode sequentially formed on the cathode electrode.
  • Two active regions are formed on the side of the epitaxial layer away from the substrate.
  • the forbidden band width is greater than the forbidden band width of the epitaxial layer, the material of the buffer layer and the material of the epitaxial layer are allotropes, and a first position is formed in the buffer layer opposite to the active region.
  • a hole is formed, and an ohmic metal layer is formed in the first hole.
  • a buffer layer is provided between the epitaxial layer and the anode electrode, and the forbidden band width of the buffer layer is greater than the forbidden band width of the epitaxial layer, so that a high Schottky barrier in the MPS diode device can be achieved.
  • the modulation of the schottky barrier reduces the height of the Schottky barrier, thereby reducing the forward conduction loss of the MPS diode device; at the same time, because the buffer layer is made of an allotrope with the epitaxial layer, the interface between the buffer layer and the epitaxial layer The stress mismatch problem will be well improved, so the interface state will be greatly reduced, which can reduce the reverse leakage of the MPS diode device; the above-mentioned MPS diode device reduces the reverse leakage loss while reducing the forward conduction Loss, so that the two performance parameters of reverse leakage and forward working voltage can be improved at the same time, so that the performance of the MPS diode device is better.
  • the buffer layer is a nanostructured layer.
  • the buffer layer is a quantum dot layer.
  • the shape of the quantum dots in the quantum dot layer is cylindrical, spherical, or convex.
  • the quantum dots are cylindrical, the bottom surface of the cylindrical quantum dots is in contact with the epitaxial layer;
  • the quantum dots are convex, the shape of the contour line on the side of the quantum dots away from the epitaxial layer in a cut plane perpendicular to the direction of the epitaxial layer is a parabola.
  • the material of the substrate is n-type 3C-SiC
  • the material of the epitaxial layer is n-type 3C-SiC
  • the doping concentration of the substrate is higher than that of the epitaxial layer Concentration
  • the material of the buffer layer is 4H-SiC.
  • the material of the ohmic metal layer is titanium.
  • the thickness of the ohmic metal layer is 1 um.
  • the present disclosure also provides a method for manufacturing the MPS diode device, including:
  • Forming an epitaxial layer on the substrate, and the side of the epitaxial layer facing away from the substrate includes an active region forming region configured to form an active region;
  • a buffer layer with a band gap greater than that of the epitaxial layer is formed, and a portion of the buffer layer opposite to the active area is patterned to form a The first opening of the buffer layer;
  • An anode electrode is formed on the side of the buffer layer and the ohmic metal layer away from the epitaxial layer.
  • the forming an active region in the active region formation region includes:
  • a barrier layer is formed on the side of the sacrificial oxide layer away from the epitaxial layer, and a portion of the barrier layer opposite to the active region formation region is patterned to form a second opening penetrating the barrier layer. hole;
  • the sacrificial oxide layer and the barrier layer are removed to expose the epitaxial layer.
  • the ion is aluminum ion.
  • the material of the substrate is n-type 3C-SiC
  • the material of the epitaxial layer is n-type 3C-SiC
  • the doping concentration of the substrate is higher than that of the epitaxial layer
  • the material of the buffer layer is 4H-SiC.
  • the annealing treatment includes:
  • the carbon film is removed to expose the epitaxial layer.
  • the buffer layer is a quantum dot layer.
  • the method for forming the quantum dot layer is:
  • the buffer film layer is annealed to form a quantum dot layer.
  • FIGS 1 to 5 are schematic diagrams of the manufacturing process of an MPS diode device provided by the embodiments of the disclosure.
  • FIG. 6 is a schematic cross-sectional view of the first quantum dot structure provided by an embodiment of the disclosure.
  • FIG. 7 is a schematic cross-sectional view of a second quantum dot structure provided by an embodiment of the disclosure.
  • FIG. 8 is a schematic cross-sectional view of a third quantum dot structure provided by an embodiment of the disclosure.
  • the present disclosure provides an MPS diode device, including a plurality of cells arranged in parallel, wherein:
  • Each cell includes a cathode electrode 1 and a substrate 2, an epitaxial layer 3, a buffer layer 4, and an anode electrode 5 sequentially formed on the cathode electrode 1.
  • Two active regions are formed on the side of the epitaxial layer 3 away from the substrate 2 6.
  • the forbidden band width of the buffer layer 4 is greater than the forbidden band width of the epitaxial layer 3, and the material of the buffer layer 4 and the material of the epitaxial layer 3 are allotropes.
  • a buffer layer 4 is provided between the epitaxial layer 3 and the anode electrode 5, and the forbidden band width of the buffer layer 4 is greater than the forbidden band width of the epitaxial layer 3.
  • the modulation of the high barrier height reduces the height of the Schottky barrier, thereby reducing the forward conduction loss of the MPS diode device.
  • the buffer layer 4 is made of an allotrope with the epitaxial layer 3, so that the buffer The problem of stress mismatch at the interface between layer 4 and epitaxial layer 3 will be well improved, so the interface state will be greatly reduced, so that the reverse leakage of the MPS diode device can be reduced; in the above-mentioned MPS diode device, the reverse The leakage loss reduces the forward conduction loss at the same time, so that the two performance parameters of reverse leakage and forward working voltage can be improved at the same time, so that the performance of the MPS diode device is better.
  • the buffer layer 4 is a nanostructured layer.
  • the buffer layer 4 can be a thin film layer or a nanostructured layer.
  • the nanostructured layer can further adjust the energy band width of the buffer layer 4, so that the Schottky barrier height can be further modulated, thereby reducing the forward conduction loss of the device.
  • the buffer layer 4 is a quantum dot layer, as shown in FIGS. 6, 7 and 8, the shape of the quantum dots in the quantum dot layer is cylindrical, spherical or convex.
  • the quantum dots are cylindrical, The bottom surface of the cylindrical quantum dot is in contact with the epitaxial layer 3; when the quantum dot is convex, the contour of the quantum dot along the direction perpendicular to the epitaxial layer 3 has a parabolic shape.
  • the buffer layer 4 can be a nano-scale quantum dot layer, which is convenient to prepare and can control the shape and size of the quantum dots in the quantum dot layer by controlling the annealing temperature during the preparation process to achieve the adjustment of the forbidden band width of the buffer layer 4 , Thereby further adjusting the height of the Schottky barrier, making the MPS diode device achieve better performance.
  • the material of the substrate 2 is n-type 3C-SiC
  • the material of the epitaxial layer 3 is n-type 3C-SiC
  • the doping concentration of the substrate 2 is higher than that of the epitaxial layer 3
  • the material of the buffer layer 4 It is 4H-SiC.
  • the material of the buffer layer 4 is 4H-SiC, and the material of the epitaxial layer 3 is n-type 3C-SiC. Since the forbidden band width of 4H-SiC is greater than that of 3C-SiC, a high barrier to Schottky can be achieved.
  • the material of the ohmic metal layer 7 is titanium.
  • the thickness of the ohmic metal layer 7 is 1 um.
  • the present disclosure also provides a manufacturing method of the MPS diode device, as shown in Figs. 1 to 5, including:
  • An epitaxial layer 3 is formed on the substrate 2, and the side of the epitaxial layer 3 away from the substrate 2 includes an active region forming region configured to form an active region 6, as shown in FIG. 1;
  • An active area 6 is formed in the active area formation area, as shown in FIG. 2e in conjunction with FIG. 2a, FIG. 2b, FIG. 2c, and FIG. 2d;
  • S104 Form a buffer layer 4 with a band gap greater than that of the epitaxial layer 3 on the side of the epitaxial layer 3 facing away from the substrate 2, and pattern the part of the buffer layer 4 opposite to the active region 6 to form a through-buffer layer 4
  • An anode electrode 5 is formed on the side of the buffer layer 4 and the ohmic metal layer 7 away from the epitaxial layer 3, as shown in FIG. 5.
  • a buffer layer 4 between the epitaxial layer 3 and the anode electrode 5 is formed on the epitaxial layer 3.
  • the forbidden band width of the buffer layer 4 is greater than that of the epitaxial layer 3 and buffers
  • the material of layer 4 and the material of epitaxial layer 3 are allotropes, which can reduce the height of the Schottky barrier to reduce the forward conduction loss, and reduce the reverse leakage of the MPS diode device, so that the reverse leakage and the positive
  • the two performance parameters of the working voltage can be improved at the same time, so that the performance of the MPS diode device is better.
  • forming the active region 6 in the active region formation region includes:
  • a sacrificial oxide layer 9 is formed on the surface of the epitaxial layer 3 facing away from the substrate 2. It acts as a buffer during the formation of the zone to prevent the direct injection of high-energy particles during ion implantation into the surface of the epitaxial layer 3 to cause amorphization, which may cause excessive leakage.
  • the sacrificial oxide layer 9 has a thickness of 0.1um and a material of two.
  • a barrier layer 10 is formed on the side of the sacrificial oxide layer 9 away from the epitaxial layer 3, and a portion of the barrier layer 10 opposite to the active region formation area is patterned to form a second penetrating barrier layer 10 Two openings 11, the barrier layer 10 is set to prevent ion implantation to the part outside the active area formation area.
  • the material of the barrier layer 10 can be polysilicon or carbonized photoresist, etc., and the thickness can be 2um; in S203, Ions are implanted into the second opening 11 to form the active region 6 in the active region formation region in the epitaxial layer 3.
  • the energy and dose of ion implantation are determined by the forward working voltage required by the MPS diode device; in S204, remove The sacrificial oxide layer 9 and the barrier layer 10 are used to expose the epitaxial layer 3.
  • the purpose of the sacrificial oxide layer 9 and the barrier layer 10 is to facilitate ion implantation. They can be removed after the active region 6 is formed for subsequent preparation processes.
  • the ion is aluminum ion.
  • the material of the substrate 2 is n-type 3C-SiC
  • the material of the epitaxial layer 3 is n-type 3C-SiC
  • the doping concentration of the substrate 2 is higher than that of the epitaxial layer 3.
  • Doping concentration; the material of the buffer layer 4 is 4H-SiC.
  • the material of the buffer layer 4 is 4H-SiC, and the material of the epitaxial layer 3 is n-type 3C-SiC.
  • the forbidden band width of 4H-SiC is larger than that of 3C-SiC, so that the high Schottky barrier can be modulated
  • 4H-SiC and 3C-SiC are allotropes, so compared to using other wide-bandgap semiconductor materials as the buffer layer 4, when 4H-SiC is used as the buffer layer 4, the interface lattice between 3C-SiC and 4H-SiC
  • the stress mismatch problem will be well improved, so the interface state will be greatly reduced, which can alleviate the problem of excessive reverse leakage caused by the interface state.
  • the annealing treatment includes:
  • the active region 6 After the active region 6 is prepared, an annealing treatment is required. On the one hand, the electrical activity of the doped ions in the active region 6 can be enhanced, and on the other hand, the lattice damage caused by ion implantation can be repaired.
  • the epitaxial layer 3 The carbon film 12 is formed on the side away from the substrate 2. Specifically, a photoresist of 1um to 1.5um can be deposited and carbonized to form the carbon film 12. The carbon film 12 can alleviate the sublimation of Si during subsequent annealing.
  • a high temperature annealing treatment is performed, specifically an annealing treatment at a temperature of 800-1000°C for 30 minutes; in S303, the carbon film 12 is removed to expose the epitaxial layer 3
  • the carbon film 12 can be removed by thermal oxidation, that is, the carbon film 12 is dry removed at 600-800°C.
  • the buffer layer 4 is a quantum dot layer.
  • the quantum dot layer can better adjust the height of the Schottky barrier, so that the MPS diode device can achieve better performance.
  • the method for forming the quantum dot layer is as follows:
  • S402 Pattern a portion of the buffer film layer 13 opposite to the active region 6 to form a first opening 8 penetrating the buffer layer 4, as shown in FIG. 4b;
  • the buffer film layer 13 In the preparation process of the quantum dot layer, it is first necessary to grow the buffer film layer 13 on the side of the epitaxial layer 3 away from the substrate 2 at a temperature higher than 2000°C by sublimation. Since the material of the epitaxial layer 3 is n-type 3C-SiC, Then the material of the buffer film layer 13 can be selected as 4H-SiC, which is allotropic with 3C-SiC and has a band gap larger than 3C-SiC, so as to adjust the height of the Schottky barrier and reduce the interface state, so that the reverse leakage and the forward The two performance parameters of operating voltage are improved at the same time.
  • the buffer film layer 13 is annealed to form a quantum dot layer, and the structure of the buffer film layer 13 is changed into a quantum dot layer through the annealing process, and the annealing temperature is controlled.
  • the adjustment of the shape and size of the quantum dots in the quantum dot layer can be realized, and the height of the Schottky barrier can be further modulated.
  • the buffer film layer 13 needs to be formed before the annealing treatment is required to form the quantum dot layer, and the ohmic metal layer 7 is also required to be annealed when the ohmic metal layer 7 is formed in the first opening 8 of the buffer layer 4, the two annealing treatments can be combined It is one time, and the cathode electrode 1 can also be formed at the same time as the ohmic metal layer 7, so the quantum dot layer, the cathode electrode 1 and the ohmic metal layer 7 can be formed simultaneously.
  • the details are as follows: As shown in Fig. 4a, the buffer film layer 13 is formed first. Then, as shown in FIG. 4b, a first opening 8 is formed on the buffer film layer 13, and then as shown in FIG.
  • an ohmic metal layer 7 is formed in the first opening 8, and a portion of the substrate 2 away from the epitaxial layer 3
  • the cathode electrode 1 is formed on the side, and then an annealing treatment is performed at 800-1000° C. to form an ohmic contact and the buffer film layer 13 is processed into a quantum dot layer. Combining two annealing treatments can save the preparation process and the preparation time.
  • the ohmic metal layer 7 can use electron beam evaporation technology to deposit a layer of 1um titanium.
  • the preparation of the cathode electrode 1 can also use electron beam evaporation technology to deposit a layer of 1um titanium.
  • the material of the cathode electrode 1 can also be metal materials such as nickel or aluminum.
  • the anode electrode 5 can be prepared by depositing metal aluminum and annealing at 300-500° C. to form Schottky contacts.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Nanotechnology (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本公开涉及电子器件技术领域，公开了一种MPS二极管器件及其制备方法，该包括MPS二极管器件并联设置的多个元胞，其中：每个元胞包括阴极电极以及依次形成于阴极电极上的衬底、外延层、缓冲层和阳极电极，外延层背离衬底的一侧形成有两个有源区，缓冲层的禁带宽度大于外延层的禁带宽度且缓冲层的材质与外延层的材质为同素异形体，缓冲层中与有源区相对的位置形成有第一开孔，第一开孔内形成有欧姆金属层。该MPS二极管器件在降低反向漏电损耗的同时降低了正向导通损耗，使得反向漏电和正向工作电压这两个性能参数同时得以改善，从而使得该MPS二极管器件的性能更好。

Description

一种MPS二极管器件及其制备方法
本公开要求于2020年06月11日提交中国专利局、申请号为202010528815.2、发明名称为“一种MPS二极管器件及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及电子器件技术领域，特别涉及一种MPS二极管器件及其制备方法。
背景技术
SiC作为第三代新型半导体，具有禁带宽度宽、临界击穿电场高、热导率高等特点，其应用在高温、高压、高频、大功率等领域相比于传统的硅基器件有很大优势。
SiC SBD(碳化硅肖特基势垒二极管)正向导通压降低、反向恢复时间短。但在反向阻断工作条件下，存在漏电流过大的缺点。为了改善SiC SBD的反向漏电问题，发展出JBS(junction barrier schottky)或者MPS(merge pin schottky)结构，其中p型重掺杂区处形成的耗尽区一方面可以承受很大的反向电压，另一方面耗尽区互相连结包裹住肖特基结，可以防止器件在反向工作时肖特基势垒降低引起的反向漏电增大问题，但反向漏电和正向工作电压通常是需要折中的两个性能参数，为了降低漏电损耗，通常需要提高肖特基势垒高度，但这样又会导致正向工作电压的上升。因此，相关技术无法在降低器件正向导通损耗的同时降低器件的反向漏电。
发明内容
本公开提供了一种MPS二极管器件及其制备方法，上述MPS二极管器件 在降低反向漏电损耗的同时降低了正向导通损耗，使得反向漏电和正向工作电压这两个性能参数同时得以改善，从而达到更高的性能。
为达到上述目的，本公开提供以下技术方案：
一种MPS二极管器件，包括并联设置的多个元胞，其中：
每个元胞包括阴极电极以及依次形成于所述阴极电极上的衬底、外延层、缓冲层和阳极电极，外延层背离衬底的一侧形成有两个有源区，所述缓冲层的禁带宽度大于所述外延层的禁带宽度且所述缓冲层的材质与所述外延层的材质为同素异形体，所述缓冲层中与所述有源区相对的位置形成有第一开孔，所述第一开孔内形成有欧姆金属层。
上述MPS二极管器件中，在外延层和阳极电极之间设置有缓冲层，且该缓冲层的禁带宽度大于外延层的禁带宽度，从而可以实现对该MPS二极管器件中肖特基势垒高的调制，使得肖特基势垒高度得到降低，从而降低该MPS二极管器件的正向导通损耗；同时由于缓冲层采用与外延层为同素异形体的材质，使得缓冲层与外延层之间界面的应力失配问题会被很好地改善，因此界面态就会大大降低，从而可以降低该MPS二极管器件的反向漏电；上述MPS二极管器件中在降低反向漏电损耗的同时降低了正向导通损耗，使得反向漏电和正向工作电压这两个性能参数同时得以改善，从而使得该MPS二极管器件的性能更好。
在一些实施方式中，所述缓冲层为纳米结构层。
在一些实施方式中，所述缓冲层为量子点层。
在一些实施方式中，所述量子点层中的量子点的形状为圆柱状、球状或凸起状，当所述量子点为圆柱状时，所述圆柱状量子点的底面与外延层接触；当所述量子点为凸起状时，所述量子点沿垂直于外延层方向的切面中，背离外延层一侧的轮廓线的形状为抛物线。
在一些实施方式中，所述衬底的材质为n型3C-SiC，所述外延层的材质为n型3C-SiC，且所述衬底的掺杂浓度高于所述外延层的掺杂浓度；所述缓冲层 的材质为4H-SiC。
在一些实施方式中，所述欧姆金属层的材质为钛。
在一些实施方式中，所述欧姆金属层的厚度为1um。
本公开还提供一种MPS二极管器件的制备方法，包括：
在衬底上形成外延层，所述外延层背离衬底一侧包括被设置为形成有源区的有源区形成区；
在所述有源区形成区内形成有源区；
退火处理；
在所述外延层背离所述衬底的一侧形成禁带宽度大于所述外延层的缓冲层，并对所述缓冲层中与所述有源区相对的部位进行图案化以形成贯穿所述缓冲层的第一开孔；
在所述第一开孔内形成欧姆金属层，在所述衬底背离所述外延层的一侧形成阴极电极；
在所述缓冲层及欧姆金属层背离外延层的一侧形成阳极电极。
在一些实施方式中，所述在所述有源区形成区内形成有源区包括：
所述在所述外延层背离所述衬底的一侧表面形成牺牲氧化层；
在所述牺牲氧化层背离所述外延层的一侧形成阻挡层，并对所述阻挡层中与所述有源区形成区相对的部位进行图案化以形成贯穿所述阻挡层的第二开孔；
在所述第二开孔内注入离子以在所述外延层中的有源区形成区形成有源区；
去除所述牺牲氧化层以及阻挡层以暴露所述外延层。
在一些实施方式中，所述离子为铝离子。
在一些实施方式中，所述衬底的材质为n型3C-SiC，所述外延层的材质为n型3C-SiC，所述衬底的掺杂浓度高于所述外延层的掺杂浓度；所述缓冲层的材质为4H-SiC。
在一些实施方式中，所述退火处理包括：
在所述外延层背离衬底的一侧形成碳膜；
进行高温退火处理；
去除所述碳膜以暴露所述外延层。
在一些实施方式中，所述缓冲层为量子点层。
在一些实施方式中，所述量子点层的形成方法为：
在所述外延层背离所述衬底的一侧通过升华法在高于2000℃条件下生长缓冲薄膜层；
对所述缓冲薄膜层进行退火处理以形成量子点层。
附图说明
图1至图5为本公开实施例提供的一种MPS二极管器件制备过程示意图；
图6为本公开实施例提供的第一种量子点结构截面示意图；
图7为本公开实施例提供的第二种量子点结构截面示意图；
图8为本公开实施例提供的第三种量子点结构截面示意图。
图标：
1-阴极电极；2-衬底；3-外延层；4-缓冲层；5-阳极电极；6-有源区；7-欧姆金属层；8-第一开孔；9-牺牲氧化层；10-阻挡层；11-第二开孔；12-碳膜；13-缓冲薄膜层，14-量子点。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
请参考图5，本公开提供一种MPS二极管器件，包括并联设置的多个元胞， 其中：
每个元胞包括阴极电极1以及依次形成于阴极电极1上的衬底2、外延层3、缓冲层4和阳极电极5，外延层3背离衬底2的一侧形成有两个有源区6，缓冲层4的禁带宽度大于外延层3的禁带宽度且缓冲层4的材质与外延层3的材质为同素异形体，缓冲层4中与有源区6相对的位置形成有第一开孔8，第一开孔8内形成有欧姆金属层7。
上述MPS二极管器件中，在外延层3和阳极电极5之间设置有缓冲层4，且该缓冲层4的禁带宽度大于外延层3的禁带宽度，从而可以实现对该MPS二极管器件中肖特基势垒高的调制，使得肖特基势垒高度得到降低，从而降低该MPS二极管器件的正向导通损耗；同时由于缓冲层4采用与外延层3为同素异形体的材质，使得缓冲层4与外延层3之间界面的应力失配问题会被很好地改善，因此界面态就会大大降低，从而可以降低该MPS二极管器件的反向漏电；上述MPS二极管器件中在降低反向漏电损耗的同时降低了正向导通损耗，使得反向漏电和正向工作电压这两个性能参数同时得以改善，从而使得该MPS二极管器件的性能更好。
具体地，缓冲层4为纳米结构层。
缓冲层4可以采用薄膜层也可以采用纳米结构层，采用纳米结构层可以进一步调节缓冲层4的能带宽度，使得肖特基势垒高度得到进一步的调制，从而降低器件的正向导通损耗。
具体地，缓冲层4为量子点层，如图6、图7和图8所示，量子点层中的量子点的形状为圆柱状、球状或凸起状，当量子点为圆柱状时，圆柱状量子点的底面与外延层3接触；当量子点为凸起状时，量子点沿垂直于外延层3方向的切面中，背离外延层3一侧的轮廓线的形状为抛物线。
缓冲层4可以采用纳米级的量子点层，制备方便且可以在制备过程中通过控制退火温度来控制量子点层中量子点的形状和尺寸等，来达到对缓冲层4的禁带宽度的调节，从而进一步调节肖特基势垒高度，使得MPS二极管器件达 到更好的性能。
具体地，衬底2的材质为n型3C-SiC，外延层3的材质为n型3C-SiC，且衬底2的掺杂浓度高于外延层3的掺杂浓度；缓冲层4的材质为4H-SiC。
缓冲层4的材质为4H-SiC、外延层3的材质为n型3C-SiC，由于4H-SiC的禁带宽度大于3C-SiC的禁带宽度，从而可以实现对肖特基势垒高的调制，且由于4H-SiC与3C-SiC为同素异型体，所以比起采用其他的宽禁带半导体材质作为缓冲层4，采用4H-SiC作为缓冲层4时，4H-SiC材质的缓冲层与3C-SiC材质的外延层之间界面晶格的应力失配问题会被很好地改善，因此界面态就会大大降低，从而可以缓解界面态带来的反向漏电过大的问题。
具体地，欧姆金属层7的材质为钛。
具体地，欧姆金属层7的厚度为1um。
本公开还提供了一种MPS二极管器件的制备方法，如图1至图5所示，包括：
S101：在衬底2上形成外延层3，外延层3背离衬底2一侧包括被设置为形成有源区6的有源区形成区，如图1所示；
S102：有源区形成区内形成有源区6，结合图2a、图2b、图2c和图2d，如图2e所示；
S103：退火处理，如图3所示；
S104：在外延层3背离衬底2的一侧形成禁带宽度大于外延层3的缓冲层4，并对缓冲层4中与有源区6相对的部位进行图案化以形成贯穿缓冲层4的第一开孔8，结合图4a，如图4b和图4c所示；
S105：在第一开孔8内形成欧姆金属层7，在衬底2背离外延层3的一侧形成阴极电极1，如图4c所示；
S106：在缓冲层4及欧姆金属层7背离外延层3的一侧形成阳极电极5，如图5所示。
上述MPS二极管器件的制备方法中，在外延层3上形成了一层位于外延 层3与阳极电极5之间的缓冲层4，缓冲层4的禁带宽度大于外延层3的禁带宽度且缓冲层4的材质与外延层3的材质为同素异形体，从而可以在降低肖特基势垒高度从而降低正向导通损耗的同时，降低该MPS二极管器件的反向漏电，使得反向漏电和正向工作电压这两个性能参数同时得以改善，从而使得该MPS二极管器件的性能更好。
具体地，如图2a、图2b、图2c和图2e所示，在有源区形成区内形成有源区6包括：
S201：在外延层3背离衬底2的一侧表面形成牺牲氧化层9，如图2a所示；
S202：在牺牲氧化层9背离外延层3的一侧形成阻挡层10，并对阻挡层10中与有源区形成区相对的部位进行图案化以形成贯穿阻挡层10的第二开孔11，如图2b和图2c所示；
S203：在第二开孔11内注入离子以在外延层3中的有源区形成区形成有源区6，如图2d所示；
S204：去除牺牲氧化层9以及阻挡层10以暴露外延层3，如图2e所示。
在上述形成有源区6的步骤中，在S201中，在外延层3背离衬底2的一侧表面形成牺牲氧化层9，牺牲氧化层9作为可在后续有源区6离子注入有源区形成区时起到缓冲作用，防止离子注入时的高能粒子直接注入对外延层3表面造成非晶化，从而引起漏电过大的问题，其中，牺牲氧化层9的厚度为0.1um、材质为二氧化硅；在S202中，在牺牲氧化层9背离外延层3的一侧形成阻挡层10，并对阻挡层10中与有源区形成区相对的部位进行图案化以形成贯穿阻挡层10的第二开孔11，阻挡层10被设置为防止离子注入到有源区形成区以外的部分，阻挡层10的材质可以为多晶硅或碳化的光刻胶等，厚度可以为2um；在S203中，在第二开孔11内注入离子以在外延层3中的有源区形成区形成有源区6，离子注入的能量和剂量由MPS二极管器件所需的正向工作电压决定；在S204中，去除牺牲氧化层9以及阻挡层10以暴露外延层3，牺牲氧化层9以及阻挡层10目的是为了便于离子注入，当有源区6形成后去除即可，以便 进行后续的制备流程。
具体地，离子为铝离子。
具体地，上述制备方法制备的MPS二极管器件中，衬底2的材质为n型3C-SiC，外延层3的材质为n型3C-SiC，衬底2的掺杂浓度高于外延层3的掺杂浓度；缓冲层4的材质为4H-SiC。
缓冲层4的材质为4H-SiC、外延层3的材质为n型3C-SiC，4H-SiC的禁带宽度大于3C-SiC的禁带宽度，从而可以实现对肖特基势垒高的调制，且4H-SiC与3C-SiC为同素异型体，所以比起采用其他的宽禁带半导体材质作为缓冲层4，采用4H-SiC作为缓冲层4时与3C-SiC之间界面晶格的应力失配问题会被很好地改善，因此界面态就会大大降低，从而可以缓解界面态带来的反向漏电过大的问题。
具体地，退火处理包括：
S301：在外延层3背离衬底2的一侧形成碳膜12，如图3所示；
S302：进行高温退火处理；
S303：去除碳膜12以暴露外延层3。
在制备完成有源区6后需要进行退火处理，一方面可以增强有源区6内掺杂离子的电活性，另一方面可以修复离子注入造成的晶格损伤，在S301中，在外延层3背离衬底2的一侧形成碳膜12，具体地可以采用沉积1um至1.5um的光刻胶，并对其进行碳化处理以形成碳膜12，碳膜12可以在后续退火中缓解由于Si升华而造成的外延层3表面粗糙化问题；在S302中，进行高温退火处理，具体为在800-1000℃的温度下进行30分钟的退火处理；在S303中，去除碳膜12以暴露外延层3，以便于进行后续的制备流程，碳膜12可以采用热氧化法去除，即在600-800℃条件下对碳膜12进行干法去除。
具体地，缓冲层4为量子点层。
采用量子点层可以更好的达到对肖特基势垒高度的调节，使得MPS二极管器件达到更好的性能。
具体地，如图4a、4b和4c所示，量子点层的形成方法为：
S401：在外延层3背离衬底2的一侧通过升华法在高于2000℃条件下生长缓冲薄膜层13，如图4a所示；
S402：对缓冲薄膜层13与有源区6相对的部位进行图案化以形成贯穿缓冲层4的第一开孔8，如图4b所示；
S403：对缓冲薄膜层13进行退火处理以形成量子点层，如图4c所示。
量子点层的制备过程中，首先需要在外延层3背离衬底2的一侧通过升华法在高于2000℃条件下生长缓冲薄膜层13，由于外延层3的材质为n型3C-SiC，则缓冲薄膜层13的材质为可以选用与3C-SiC同素异性且禁带宽度比3C-SiC大的4H-SiC，从而调节肖特基势垒高度并降低界面态，使得反向漏电和正向工作电压这两个性能参数同时得以改善，在S403中，对缓冲薄膜层13进行退火处理以形成量子点层，通过退火处理将缓冲薄膜层13的结构变为量子点层，并通过控制退火温度实现对量子点层中量子点形状及尺寸的调节，可以进一步实现对肖特基势垒高度的调制。
由于在形成量子点层时需要先形成缓冲薄膜层13再进行退火处理，而缓冲层4的第一开孔8内形成欧姆金属层7时也需要进行退火处理，因此可将两次退火处理合并为一次，而且阴极电极1也可以与欧姆金属层7同时形成，因此可以同步形成量子点层、阴极电极1以及欧姆金属层7，具体如下：如图4a所示，先形成缓冲薄膜层13，然后如图4b所示，在缓冲薄膜层13上形成第一开孔8，然后如图4c所示，在第一开孔8内形成欧姆金属层7、在衬底2背离外延层3的一侧形成阴极电极1，然后再在800-1000℃条件下进行退火处理，以形成欧姆接触并将缓冲薄膜层13处理为量子点层，合并两次退火处理可节省制备工序、节省制备时间。
欧姆金属层7可以利用电子束蒸发技术沉积一层1um的钛，阴极电极1的制备也可以利用电子束蒸发技术沉积一层1um的钛，阴极电极1的材质也可以为镍或铝等金属材质；如图5所示，阳极电极5的制备可以采用沉积金属 铝并在300-500℃条件下退火形成肖特基接触。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (14)

  1. 一种MPS二极管器件，包括并联设置的多个元胞，其中：
    每个元胞包括阴极电极以及依次形成于所述阴极电极上的衬底、外延层、缓冲层和阳极电极，所述外延层背离衬底的一侧形成有两个有源区，所述缓冲层的禁带宽度大于所述外延层的禁带宽度且所述缓冲层的材质与所述外延层的材质为同素异形体，所述缓冲层中与所述有源区相对的位置形成有第一开孔，所述第一开孔内形成有欧姆金属层。
  2. 根据权利要求1所述的MPS二极管器件，其中，所述缓冲层为纳米结构层。
  3. 根据权利要求2所述的MPS二极管器件，其中，所述缓冲层为量子点层。
  4. 根据权利要求3所述的MPS二极管器件，其中，所述量子点层中的量子点的形状为圆柱状、球状或凸起状，当所述量子点为圆柱状时，所述圆柱状量子点的底面与外延层接触；当所述量子点为凸起状时，所述量子点沿垂直于外延层方向的切面中，背离外延层一侧的轮廓线的形状为抛物线。
  5. 根据权利要求1所述的MPS二极管器件，其中，所述衬底的材质为n型3C-SiC，所述外延层的材质为n型3C-SiC，且所述衬底的掺杂浓度高于所述外延层的掺杂浓度；所述缓冲层的材质为4H-SiC。
  6. 根据权利要求1所述的MPS二极管器件，其中，所述欧姆金属层的材质为钛。
  7. 根据权利要求1所述的MPS二极管器件，其中，所述欧姆金属层的厚度为1um。
  8. 一种MPS二极管器件的制备方法，包括：
    在衬底上形成外延层，所述外延层背离衬底一侧包括被设置为形成有源区的有源区形成区；
    在所述有源区形成区内形成有源区；
    退火处理；
    在所述外延层背离所述衬底的一侧形成禁带宽度大于所述外延层的缓冲层，并对所述缓冲层中与所述有源区相对的部位进行图案化以形成贯穿所述缓冲层的第一开孔；
    在所述第一开孔内形成欧姆金属层，在所述衬底背离所述外延层的一侧形成阴极电极；
    在所述缓冲层及欧姆金属层背离外延层的一侧形成阳极电极。
  9. 根据权利要求8所述的制备方法，其中，所述在所述有源区形成区内形成有源区包括：
    所述在所述外延层背离所述衬底的一侧表面形成牺牲氧化层；
    在所述牺牲氧化层背离所述外延层的一侧形成阻挡层，并对所述阻挡层中与所述有源区形成区相对的部位进行图案化以形成贯穿所述阻挡层的第二开孔；
    在所述第二开孔内注入离子以在所述外延层中的有源区形成区形成有源区；
    去除所述牺牲氧化层以及阻挡层以暴露所述外延层。
  10. 根据权利要求9所述的制备方法，其中，所述离子为铝离子。
  11. 根据权利要求10所述的制备方法，其中，所述衬底的材质为n型3C-SiC，所述外延层的材质为n型3C-SiC，所述衬底的掺杂浓度高于所述外延层的掺杂浓度；所述缓冲层的材质为4H-SiC。
  12. 根据权利要求8所述的制备方法，其中，所述退火处理包括：
    在所述外延层背离衬底的一侧形成碳膜；
    进行高温退火处理；
    去除所述碳膜以暴露所述外延层。
  13. 根据权利要求8所述的制备方法，其中，所述缓冲层为量子点层。
  14. 根据权利要求13所述的制备方法，其中，所述量子点层的形成方法为：
    在所述外延层背离所述衬底的一侧通过升华法在高于2000℃条件下生长缓冲薄膜层；
    对所述缓冲薄膜层进行退火处理以形成量子点层。
PCT/CN2020/140006 2020-06-11 2020-12-28 一种mps二极管器件及其制备方法 WO2021248879A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP20939599.5A EP4167297A4 (en) 2020-06-11 2020-12-28 MPS DIODE DEVICE AND MANUFACTURING METHOD THEREOF
JP2022570212A JP7400128B2 (ja) 2020-06-11 2020-12-28 Ｍｐｓダイオードデバイス及びその作製方法
US18/063,891 US20230105596A1 (en) 2020-06-11 2022-12-09 Mps diode device and preparation method therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010528815.2A CN113809183A (zh) 2020-06-11 2020-06-11 一种mps二极管器件及其制备方法
CN202010528815.2 2020-06-11

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/063,891 Continuation US20230105596A1 (en) 2020-06-11 2022-12-09 Mps diode device and preparation method therefor

Publications (1)

Publication Number Publication Date
WO2021248879A1 true WO2021248879A1 (zh) 2021-12-16

Family

ID=78846904

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/140006 WO2021248879A1 (zh) 2020-06-11 2020-12-28 一种mps二极管器件及其制备方法

Country Status (5)

Country Link
US (1) US20230105596A1 (zh)
EP (1) EP4167297A4 (zh)
JP (1) JP7400128B2 (zh)
CN (1) CN113809183A (zh)
WO (1) WO2021248879A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140284620A1 (en) * 2013-03-22 2014-09-25 Kabushiki Kaisha Toshiba Semiconductor device
CN108028285A (zh) * 2015-08-11 2018-05-11 Hrl实验室有限责任公司 隧道势垒肖特基
CN109860273A (zh) * 2018-12-29 2019-06-07 厦门芯光润泽科技有限公司 Mps二极管器件及其制备方法
CN110571281A (zh) * 2019-08-01 2019-12-13 山东天岳电子科技有限公司 一种混合PiN结肖特基二极管及制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4873448B2 (ja) 2006-01-06 2012-02-08 独立行政法人産業技術総合研究所 整流ダイオード
US9570436B2 (en) 2012-06-20 2017-02-14 National Institute Of Advanced Industrial Science And Technology Semiconductor device
JP6010773B2 (ja) 2014-03-10 2016-10-19 パナソニックＩｐマネジメント株式会社 半導体素子及びその製造方法
EP3067935A1 (en) 2015-03-10 2016-09-14 ABB Technology AG Power semiconductor rectifier with controllable on-state voltage
JP2018186160A (ja) 2017-04-25 2018-11-22 パナソニックＩｐマネジメント株式会社 半導体素子

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140284620A1 (en) * 2013-03-22 2014-09-25 Kabushiki Kaisha Toshiba Semiconductor device
CN108028285A (zh) * 2015-08-11 2018-05-11 Hrl实验室有限责任公司 隧道势垒肖特基
CN109860273A (zh) * 2018-12-29 2019-06-07 厦门芯光润泽科技有限公司 Mps二极管器件及其制备方法
CN110571281A (zh) * 2019-08-01 2019-12-13 山东天岳电子科技有限公司 一种混合PiN结肖特基二极管及制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4167297A4 *

Also Published As

Publication number Publication date
EP4167297A4 (en) 2024-04-03
JP7400128B2 (ja) 2023-12-18
EP4167297A1 (en) 2023-04-19
CN113809183A (zh) 2021-12-17
US20230105596A1 (en) 2023-04-06
JP2023526377A (ja) 2023-06-21

Similar Documents

Publication Publication Date Title
US9419133B2 (en) Semiconductor device and fabrication method of semiconductor device
WO2018010545A1 (zh) 一种异质结终端的碳化硅功率器件及其制备方法
JP5341373B2 (ja) ダイオード
JP6194779B2 (ja) 半導体装置および半導体装置の製造方法
CN108346688B (zh) 具有CSL输运层的SiC沟槽结势垒肖特基二极管及其制作方法
CN102163627A (zh) 具有肖特基势垒二极管的碳化硅半导体装置及其制造方法
CN103346169A (zh) SiC结势垒肖特基二极管及其制造方法
US9722029B2 (en) Semiconductor device and method of manufacturing semiconductor device
CN106952957B (zh) 一种纵向型氮化镓基半导体器件及制造方法
WO2021139041A1 (zh) 氧化镓肖特基二极管及其制备方法
JP2005051096A (ja) 半導体装置及び半導体装置の製造方法
JP2017152732A (ja) 半導体装置および半導体装置の製造方法
JP2013058668A (ja) 半導体素子及びその製造方法
CN212517215U (zh) 一种mps二极管器件
WO2021248879A1 (zh) 一种mps二极管器件及其制备方法
JP2017199926A (ja) 半導体装置および半導体装置の製造方法
CN117457710A (zh) 基于p型Ga2O3的肖特基二极管及制备方法
WO2024050865A1 (zh) 一种垂直型氧化镓晶体管及其制备方法
WO2023071284A1 (zh) 沟槽栅半导体器件及其制造方法
JP3635956B2 (ja) 炭化けい素ショットキーバリアダイオードの製造方法
CN112397566A (zh) 碳化硅器件及其制备方法
JP4211480B2 (ja) 半導体装置及びその製造方法
WO2015111177A1 (ja) 半導体装置，パワーモジュール，電力変換装置，および鉄道車両
JP2006210693A (ja) 半導体装置及び半導体装置の製造方法
JP3879697B2 (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20939599

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2022570212

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2020939599

Country of ref document: EP

Effective date: 20230111