WO2020221222A1 - 一种高阈值电压常关型高电子迁移率晶体管及其制备方法 - Google Patents

一种高阈值电压常关型高电子迁移率晶体管及其制备方法 Download PDF

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WO2020221222A1
WO2020221222A1 PCT/CN2020/087347 CN2020087347W WO2020221222A1 WO 2020221222 A1 WO2020221222 A1 WO 2020221222A1 CN 2020087347 W CN2020087347 W CN 2020087347W WO 2020221222 A1 WO2020221222 A1 WO 2020221222A1
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layer
gate
drain
barrier layer
threshold voltage
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黄火林
孙仲豪
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Dalian University of Technology
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Dalian University of Technology
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Definitions

  • the invention belongs to the technical field of semiconductor devices, and in particular relates to a high threshold voltage normally-off type high electron mobility transistor and a preparation method thereof.
  • GaN gallium nitride
  • GaN-based semiconductor materials have a large forbidden band width, high electron saturation speed, high temperature and high pressure resistance, and excellent characteristics such as radiation resistance, which can make up for the first
  • the shortcomings of the first and second generation semiconductor materials have broad application prospects in the fields of power switching devices and microwave radio frequency.
  • the spontaneous polarization and piezoelectric polarization charge at the interface of the GaN-based heterojunction will induce the generation of high-density two-dimensional electron gas (2DEG) ( ⁇ 10 13 cm -2 ).
  • 2DEG high-density two-dimensional electron gas
  • HEMT high-performance high-electron mobility transistors
  • GaN-based power devices There have been more than 20 years of research in the field of GaN-based power devices at home and abroad. At present, there are a small number of GaN-based device products below 200V on the market, and their applications are mainly in the fields of low-voltage radio frequency and consumer power conversion. But in the 400-1000V range, GaN technology is not mature enough, and its products have not yet been tested by the market. There are two main reasons. On the one hand, the device back-end packaging, matching circuit, and reliability verification require further in-depth research; on the other hand, the design and research of normally-off devices have a long way to go to market.
  • Power switching devices are classified into two types: normally-on type and normally-off type, according to whether a turn-on bias is required to be applied to the gate when the device is turned on.
  • Normally-off power switching devices are in the off state when the gate is not biased.
  • the normally-off type devices are safer, more energy-saving, and simplify circuit design in practical applications. Advantages, so it has more important research value and broader application market.
  • This patent application is for structural innovation and technical production of normally-off GaN-based power devices.
  • HEMT power devices there are a variety of technologies for realizing the normally-off operation of HEMT power devices, mainly including three schemes of etching the gate barrier layer to form a groove gate, fluorine ion implantation to form a fluorinated gate, and gate growth of a p-type cap layer.
  • the recessed gate solution weakens or directly cuts off the 2DEG by partially or completely etching the AlGaN barrier layer to obtain a normally-off operation. This solution requires precise etching of the barrier layer.
  • the gate etching depth is uniform It is difficult to control the performance; the fluoride ion implantation scheme uses the negatively charged fluoride ion to repel 2DEG to achieve the purpose of normally-off operation, but in the process of application and promotion, the thermal stability and performance reliability of the fluoride ion distribution in the device are difficult Overcome; the gate p-type cap layer is a better technical solution.
  • This technology retains a good 2DEG channel, and uses its additional built-in electric field to raise the conduction band of the 2DEG channel interface above the Fermi level to obtain a normally off
  • This technical solution can obtain a higher on-current density and is suitable for industrialization.
  • the main problem at present is that the gate withstand voltage and threshold voltage are small. Therefore, in view of this problem, how to innovate the device structure design and introduce new processing technologies to improve the withstand voltage and threshold voltage of the device in the p-type cap layer solution is a technical problem that needs to be solved urgently in the industry.
  • the present invention provides a high-threshold voltage normally-off high electron mobility transistor and a preparation method thereof.
  • the transistor realizes a normally-off device type while maintaining a large on-current density. , On this basis, the device gate withstand voltage and threshold voltage are further increased.
  • a high-threshold voltage normally-off high electron mobility transistor including: substrate, nucleation layer, epitaxial layer, barrier layer, passivation layer, gate cap layer, composite gate dielectric insertion layer, gate, and source And a drain, a nucleation layer and an epitaxial layer are sequentially grown on the substrate, above the epitaxial layer are a barrier layer, a source and a drain, the barrier layer and the epitaxial layer form a heterojunction structure, two The contact interface is induced by polarized charges to generate two-dimensional electron gas.
  • barrier layer Above the barrier layer is a passivation layer, above the barrier layer in the gate region is a gate cap layer, and above the gate cap layer is a composite gate dielectric insertion layer A gate is located above the composite gate dielectric insertion layer, the gate is in contact with the passivation layer, and a field plate extends from the gate to the drain on the passivation layer.
  • the substrate is any one of silicon, sapphire, silicon carbide, diamond, and GaN free-standing substrate;
  • the nucleation layer is AlN or AlGaN superlattice;
  • the epitaxial layer is GaN or GaAs;
  • the barrier layer is any one of AlGaN, InAlN, AlN, and AlGaAs;
  • the passivation layer is SiO 2 , Si 3 N 4 or a composite structure of the two.
  • the gate cap layer is p-GaN or p-InGaN or p-AlGaN.
  • the composite gate dielectric insertion layer is a single-layer structure formed of any material of gallium oxide, silicon dioxide, silicon nitride, aluminum oxide, and hafnium oxide, or a composite multiple structure formed of any combination of the foregoing materials.
  • the composite gate dielectric insertion layer can be used as an insulating barrier layer, and can also be used as a dielectric layer to realize the carrier tunneling effect.
  • the position of the composite gate dielectric insertion layer can also be inserted below the gate cap layer.
  • the composite gate dielectric can also be a high-resistance semiconductor.
  • the present invention also includes a method for preparing a high-threshold voltage normally-off high electron mobility transistor, the steps are as follows:
  • step S1 is:
  • a nucleation layer, an epitaxial layer, a barrier layer, and a gate cap layer are sequentially used on the MOCVD equipment substrate.
  • step S2 are:
  • the sample is evenly spin-coated with photoresist; the sample is placed on a hot plate for heating and soft-bake; the sample is placed in the exposure machine for continuous exposure; the developer is developed in the developer; the hard film is heated on the hot plate; through Cl-based plasma
  • the epitaxial layer structure is etched to form a mesa isolation, and then the sample is cleaned and removed by an acetone solution; this step is repeated to etch away the barrier layer in the source and drain regions to form a groove; repeat this step to etch Etch off the cap layer outside the gate area to form a gate cap layer.
  • step S3 are:
  • the composite metal structure is transformed into an alloy to form ohmic contacts; plasma enhanced chemistry Any one of vapor deposition method, low pressure chemical vapor deposition method, magnetron sputtering method, electron beam evaporation method is deposited to form a passivation layer on the surface of the device;
  • the required regions of the source and drain are defined by semiconductor photolithography, the source and drain metals of the device are deposited by electron beam evaporation, and then the sample is stripped in an acetone solution, cleaned and removed; by annealing in a nitrogen high temperature environment, The composite metal structure becomes an alloy to form an ohmic contact; the PECVD technology deposition method is used for deposition to form a passivation layer on the surface of the device.
  • step S4 are:
  • the gate area is defined by semiconductor photolithography, the surface of the gate cap layer is oxidized, and the gate dielectric insertion layer is formed by processing; or it can be deposited by any method of PECVD, LPCVD, MOCVD, ALD, and magnetron sputtering. Single-layer or composite multi-gate dielectric insertion layer;
  • the gate area is defined by semiconductor photolithography, the surface of the gate cap layer is pretreated with low-power oxygen ions, and then deposited by LPCVD to form the gate dielectric insertion layer.
  • step S5 are:
  • the gate and field plate areas are defined by semiconductor photolithography, the gate metal of the device and the field plate metal extending to the drain are deposited by metal deposition, and finally a passivation layer is deposited on the surface of the device, and then defined by semiconductor photolithography
  • the opening area required for the source, gate and drain is removed, the passivation layer in the defined area is removed, and the surface of the metal electrode is exposed, and finally a metal film is deposited to make a lead, complete the electrode production, and obtain the final device structure;
  • the gate and field plate areas are defined by semiconductor photolithography, and the gate and extended field plate metal of the device are deposited by electron beam evaporation technology, and then the sample is stripped and cleaned in acetone solution to remove glue; the surface of the device is passivated by PECVD deposition Layer, use semiconductor photolithography to define the opening area required for the source, gate and drain, remove the passivation layer in the defined area to expose the surface of the metal electrode, and deposit the electrode metal by magnetron sputtering to obtain the final Device structure.
  • the high-threshold voltage normally-off high electron mobility transistor and the preparation method thereof of the present invention realize the normally-off device type while maintaining a large on-current density; adopting the p-GaN (or p-InGaN or p- The AlGaN) gate cap layer is subjected to surface oxidation technology to form a gate oxide dielectric layer or directly deposit a gate dielectric insertion layer or form a multiple gate dielectric insertion layer.
  • the conduction band position of the barrier layer is improved to improve the normally-off device Gate withstand voltage and threshold voltage.
  • FIG. 1 is a schematic cross-sectional view of a high threshold voltage normally-off HEMT device of the present invention
  • Figure 2 is an example diagram a of the manufacturing process of the device of the present invention.
  • Figure 3 is an example diagram b of the manufacturing process flow of the device of the present invention.
  • Figure 4 is an example diagram c of the manufacturing process flow of the device of the present invention.
  • FIG. 5 is an example diagram d of the manufacturing process flow of the device of the present invention.
  • Fig. 6 is an example diagram e of the manufacturing process flow of the device of the present invention.
  • FIG. 7 is an example diagram f of the manufacturing process flow of the device of the present invention.
  • FIG. 8 is a schematic diagram of the energy band comparison of devices in technical solutions with and without composite gate dielectric insertion layer
  • FIG. 9 is a schematic diagram of the comparison of the threshold voltage characteristics of the devices in the technical solutions with and without the composite gate dielectric insertion layer.
  • the high-threshold voltage normally-off type high electron mobility transistor and the preparation method thereof will be further described below with reference to FIGS. 1-9.
  • the p-GaN (or p-InGaN or p-AlGaN) gate cap layer is subjected to surface oxidation technology to form the gate oxide dielectric layer or directly deposit the gate dielectric insert Layer or form a multiple gate dielectric insertion layer, as shown in FIG. 1, by increasing the conduction band position of the barrier layer to increase the gate withstand voltage and threshold voltage of the normally-off device.
  • the gate p-type cap layer is currently a technical solution that can better realize normally-off devices in the industry. This technology does not damage the 2DEG channel, so the on-current density (or on-resistance) characteristics of the device have not decreased.
  • the additional built-in electric field formed by the p-GaN (or p-InGaN or p-AlGaN) gate cap layer raises the conduction band of the 2DEG channel interface above the Fermi level, thereby obtaining a normally-off operation, but the threshold voltage Generally only about 1V, the maximum withstand voltage of the grid is generally less than 10V.
  • This patent application introduces a single layer or a composite multiple gate dielectric insertion layer above the gate cap layer, which will further improve the conduction band position of the barrier layer and the 2DEG channel interface, and obtain a significantly increased gate withstand voltage (>20V) And threshold voltage (>2V).
  • Fig. 1 is a schematic cross-sectional view of a high-threshold voltage normally-off HEMT device proposed in this patent application.
  • the introduction of a gate dielectric insertion layer between the gate metal electrode and the p-type cap layer is its main feature.
  • the bottom is the substrate, which can be a silicon, sapphire, silicon carbide, diamond or GaN free-standing substrate, etc.; the upper part of the substrate is an AlN or AlGaN superlattice nucleation layer; Above the core layer is an epitaxial layer of GaN or GaAs; above the epitaxial layer is an AlGaN, InAlN, AlN or AlGaAs barrier layer.
  • the barrier layer and the epitaxial layer form a heterojunction structure.
  • the interface is induced by polarized charges to generate two-dimensional electron gas ( 2DEG); above the barrier layer is silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ) or their composite structure to form a passivation layer; above the barrier layer in the gate region is p-GaN or p-InGaN respectively Or p-AlGaN cap layer and gallium oxide (Ga 2 O 3 ), silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ) or hafnium oxide (HfO 2 ), etc.
  • Various materials form a single layer or a composite multiple gate dielectric insertion layer; the source electrode and the drain electrode in contact with the epitaxial layer, the gate electrode above the gate dielectric insertion layer and the field plate extending to the drain electrode.
  • the advantage of the device structure proposed in this patent application is to realize a normally-off device type while maintaining a large on-current density, and on this basis, further increase the gate withstand voltage and threshold voltage of the device.
  • Step 1 Wafer growth.
  • MOCVD metal-organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • other semiconductor material growth techniques to sequentially grow AlN or AlGaN superlattice nucleation layers on silicon, sapphire, silicon carbide, diamond or GaN free-standing substrates, 2 ⁇ 10 ⁇ m GaN or GaAs epitaxial layer, 5 ⁇ 100nm AlGaN, InAlN, AlN or AlGaAs barrier layer (Al composition is 0.05 ⁇ 0.3), 30 ⁇ 100nm p-GaN or p-InGaN or p-AlGaN
  • the gate cap layer is shown in Figure 2 and Figure 3.
  • Step 2 Etching the epitaxial layer structure.
  • the semiconductor photolithography technology includes a complete step of homogenization, soft baking, exposure, development, and film hardening.
  • Step 3 Fabrication of source and drain electrodes.
  • the required regions of the source and drain are defined by the semiconductor photolithography technology described in step 2, and the source and drain metals of the device are deposited by metal deposition techniques such as magnetron sputtering and electron beam evaporation, and high temperature annealing is used to make The composite metal structure becomes an alloy, forming an ohmic contact.
  • metal deposition techniques such as magnetron sputtering and electron beam evaporation, and high temperature annealing is used to make The composite metal structure becomes an alloy, forming an ohmic contact.
  • PECVD plasma enhanced chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • magnetron sputtering or electron beam evaporation to deposit SiO 2 , Si 3 N 4 or their composite structure to form the device surface Passivation layer, as shown in Figure 5.
  • Step 4 Preparation of the gate dielectric insertion layer.
  • the gate area is defined by the semiconductor photolithography technology described in step 2, and the p-GaN (or p-InGaN or p-AlGaN) gate cap layer is subjected to surface oxidation technology to form a Ga 2 O 3 dielectric layer, or PECVD , LPCVD, MOCVD, atomic layer deposition (ALD) or magnetron sputtering and other technologies to directly deposit SiO 2 , Si 3 N 4 , aluminum oxide (Al 2 O 3 ) or hafnium oxide (HfO 2 ) and other single-layer or composite multiple media Insert the layer, as shown in Figure 6.
  • PECVD p-GaN (or p-InGaN or p-AlGaN) gate cap layer is subjected to surface oxidation technology to form a Ga 2 O 3 dielectric layer, or PECVD , LPCVD, MOCVD, atomic layer deposition (ALD) or magnetron sputtering and other technologies to directly deposit Si
  • Step 5 Fabrication of the gate electrode.
  • the gate and field plate regions are defined by the semiconductor photolithography technique described in step 2, and the metal deposition technique described in step 3 deposits the gate metal of the device and the field plate metal extending to the drain, as shown in FIG. 7. Finally, a 300-5000nm thick passivation layer is deposited on the surface of the device, and then the semiconductor photolithography technology described in step 2 is used to define the opening area required for the source, gate and drain, and the passivation layer in the defined area is removed. The surface of the metal electrode is exposed, and finally a metal film is deposited to make a lead to complete the electrode production, and the final device structure is obtained.
  • Step 1 GaN structure epitaxial growth.
  • the structure and size of the device are designed as follows: the distance between the source and the gate of the device is 2 ⁇ m, the length of the gate is 3 ⁇ m, the width is 200 ⁇ m, the length of the field plate extending from the gate to the drain is 1 ⁇ m, and the distance between the gate and the drain is 10 ⁇ m.
  • the electrode area is 200 ⁇ 200 ⁇ m 2 .
  • Step 2 Etching the epitaxial layer structure.
  • the sample was uniformly spin-coated with AZ5214 photoresist at a rate of 4000r/min for 30s;
  • the Cl-based plasma ICP etching technology 150W power is selected, the epitaxial layer structure with a depth of 500nm is etched to form mesa isolation, and then the sample is cleaned by acetone solution to remove the glue. Repeat this step, select a lower power supply power of 30W, and etch away the 20nm barrier layer in the source and drain regions to form grooves; repeat this step, select a lower power supply power of 30W, and etch away the p outside the gate area -GaN, forming a gate cap layer.
  • Step 3 Fabrication of source and drain electrodes.
  • step 2 Define the source and drain regions required by the semiconductor photolithography technology described in step 2, and deposit the source and drain metals of the device by electron beam evaporation technology, namely Ti/Al/Ni/Au (20/100/45/55nm) , And then the sample is peeled off in acetone solution, cleaned to remove glue. By annealing at 875°C in a nitrogen high temperature environment for 30s, the composite metal structure is transformed into an alloy to form an ohmic contact. Use PECVD technology to deposit 200nm SiO 2 passivation layer.
  • Step 4 Preparation of the gate dielectric insertion layer.
  • the gate area is defined by the semiconductor photolithography technology described in step 2, the surface of the p-GaN gate cap layer is pretreated with low power (30W) oxygen ions, and then a 5nm thick Si 3 N 4 gate is deposited by LPCVD technology Media insertion layer.
  • Step 5 Fabrication of the gate electrode.
  • the gate and field plate areas are defined by the semiconductor photolithography technology described in step 2, and the gate and extended field plate metal of the device are deposited by electron beam evaporation technology, namely Ni/Au (100/100nm), and then the sample is in acetone solution Stripping, cleaning and removing glue.
  • PECVD technology is used to deposit a 1000nm SiO 2 passivation layer on the surface of the device, and then the semiconductor photolithography technology described in step 2 is used to define the opening area required for the source, gate and drain, and the passivation layer of the defined area Remove and expose the surface of the metal electrode, and deposit Al metal with a thickness of 1500 nm by magnetron sputtering to obtain the final device structure.
  • Figures 8 and 9 show the comparison results of the energy band and threshold voltage characteristics of the devices in the technical solutions with and without a gate dielectric insertion layer obtained by using the device structure parameters of this embodiment. It can be seen from the figure that the introduction of the gate dielectric insertion layer can significantly improve the band step and conduction band position of the barrier layer, thereby increasing the gate withstand voltage and threshold voltage of the normally-off device, and the threshold voltage of the device is increased from 1.5V to 4.5V , While retaining the good conduction current level of the device.
  • any other passivation layer growth including different growth technologies, different combinations of passivation layers, or the passivation process steps can also be omitted directly
  • ohmic contact electrode production process including different metal selection, deposition methods, annealing conditions
  • mesa mesa
  • the etching process is based on realizing the basic function of the normally-off HEMT device with the characteristics of the p-type gate capping layer surface undergoing plasma treatment to form a dielectric layer or the additional introduction of a single layer or multiple composite dielectric insertion layer structure of the present invention, All are applicable to the scope of the present invention proposal.
  • the composite gate dielectric insertion layer may be an insulating barrier layer or a dielectric layer that realizes the carrier tunneling effect.
  • the position of the composite gate dielectric insertion layer can also be inserted under the gate cap layer according to claim 1.
  • the composite gate dielectric can also be a high resistance semiconductor.

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  • Junction Field-Effect Transistors (AREA)

Abstract

一种高阈值电压常关型高电子迁移率晶体管及其制备方法。技术方案：在衬底上依次生长成核层和外延层，外延层上方为势垒层、源极和漏极，势垒层和外延层形成异质结结构，二者接触界面由极化电荷诱导产生二维电子气，势垒层上方为钝化层，栅区势垒层上方为栅极盖帽层，栅极盖帽层上方为经表面等离子体氧化技术处理形成氧化物介质层或者直接沉积单层或者多重栅介质插入层，栅介质插入层上方为栅极，栅极与钝化层接触，在钝化层上、栅极向漏极方向延伸有场板。有益效果：实现常关型器件类型的同时能保持大的导通电流密度；通过提高势垒层导带位置提高常关型器件的栅极耐压和阈值电压。

Description

一种高阈值电压常关型高电子迁移率晶体管及其制备方法 技术领域
本发明属于半导体器件技术领域，尤其涉及一种高阈值电压常关型高电子迁移率晶体管及其制备方法。
背景技术
继第一代半导体材料(Ge、Si等)与第二代化合物半导体材料(GaAs、InP等)之后，氮化镓(GaN)作为第三代新型宽禁带半导体材料的重要代表得到迅速发展，并成为功率半导体领域研究的前沿和热点。GaN基(以GaN为主，包含GaN、AlN、InN以及它们的成分组合等)半导体材料具有大的禁带宽度、高的电子饱和速度以及耐高温高压、抗辐照等优良特性，可以弥补第一、二代半导体材料的不足，在功率开关器件和微波射频领域具有广泛的应用前景。另外，GaN基异质结(以AlGaN/GaN为代表)界面的自发极化和压电极化电荷将诱导产生高密度的二维电子气(2DEG)(～10 13cm -2)，由于受输运维数限制以及材料无需故意掺杂，该2DEG沟道具有明显增大的电子迁移率(～2000cm 2V -1s -1)。这一特性使GaN基异质结构在研制高性能高电子迁移率晶体管(HEMT)方面具有明显的优势，特别是在1000V以下的中低压芯片市场具有明显的技术优势。
国内外在GaN基功率器件领域开展研究已经有超过20年的时间，目前市场上已经有少量200V以下的GaN基器件产品，其应用主要是在低压射频和消费类电源转换领域。但是在400～1000V范围，GaN技术不够成熟，其产品还未受市场检验，主要原因有两方面。一方面是器件后端封装、匹配电路以及可靠性验证方面需要进一步深入研究；另一方面是常关型器件设计和研究距离向市场推广还有较大距离。功率开关器件按照器件导通时是否需要在栅极施加开启偏压分为常开型和常关型两种类型。常关型功率开关器件在栅极不施加偏压情况下，器件即处于关断状态，相对于常开型类型，常关型器件在实际应用中具有更安全、节能、简化电路设计等方面的优势，因此具有更加重要的研究价值和更加广阔的应用市场。本专利申请即针对常关型GaN基材料功率器件进行结构创新和技术制作。
目前实现HEMT功率器件的常关型操作有多种技术，主要有栅极势垒层刻蚀形成凹槽栅、氟离子注入形成氟化栅以及栅极生长p型盖帽层三种方案。凹槽栅 方案通过部分或者全部刻蚀掉AlGaN势垒层来削弱或者直接切断2DEG，从而获得常关型操作，该方案要求精确刻蚀势垒层，对于大面积器件，栅极刻蚀深度均匀性较难控制；氟离子注入栅极方案利用带负电荷的氟离子排斥2DEG可以达到常关型操作目的，但在应用推广过程中，器件中氟离子分布的热稳定性和性能可靠性问题难以克服；栅极p型盖帽层是个较好的技术方案，该技术保留良好的2DEG沟道，利用其附加内建电场将2DEG沟道界面的导带提升到费米能级上方，从而获得常关型操作，该技术方案能获得较高的导通电流密度，适合产业化推广，目前主要存在的问题是栅耐压和阈值电压较小。因此，针对该问题，如何对器件结构进行创新设计，引入新型加工技术，从而提高p型盖帽层方案中器件耐压和阈值电压，是业内急需解决的技术难题。
发明内容
为了解决上述现有技术中存在的问题，本发明提供一种高阈值电压常关型高电子迁移率晶体管及其制备方法，该晶体管实现常关型器件类型的同时能保持大的导通电流密度，在此基础上进一步增大的器件栅极耐压和阈值电压。
技术方案如下：
一种高阈值电压常关型高电子迁移率晶体管，包括：衬底、成核层、外延层、势垒层、钝化层、栅极盖帽层、复合栅介质插入层、栅极、源极和漏极，在所述衬底上依次生长成核层和外延层，所述外延层上方为势垒层、源极和漏极，所述势垒层和外延层形成异质结结构，二者接触界面由极化电荷诱导产生二维电子气，所述势垒层上方为钝化层，栅区势垒层上方为栅极盖帽层，所述栅极盖帽层上方为复合栅介质插入层，所述复合栅介质插入层上方为栅极，所述栅极与所述钝化层接触，在所述钝化层上、所述栅极向所述漏极方向延伸有场板。
进一步的，所述衬底是硅、蓝宝石、碳化硅、金刚石、GaN自支撑衬底中的任意一种；所述成核层是AlN或者AlGaN超晶格；所述外延层是GaN或者GaAs；所述势垒层是AlGaN、InAlN、AlN、AlGaAs中的任意一种；所述钝化层是SiO 2、Si 3N 4或者二者的复合结构。
进一步的，所述栅极盖帽层是p-GaN或者p-InGaN或者p-AlGaN。
进一步的，所述复合栅介质插入层是氧化镓、二氧化硅、氮化硅、氧化铝、氧化铪中的任意材料形成的单层结构、或者是由上述材料任意组合的复合多重结 构。这种复合栅介质插入层可以作为绝缘阻挡层，还可以作为实现载流子隧穿效应的介质层。同时，这种复合栅介质插入层的位置还可以插入到所述栅极盖帽层下方，此时，这种复合栅介质还可以是高阻半导体。
本发明还包括一种高阈值电压常关型高电子迁移率晶体管制备方法，步骤如下：
S1、晶片生长；
S2、外延层结构刻蚀；
S3、源、漏电极制作；
S4、栅介质插入层制备；
S5、栅电极制作。
进一步的，步骤S1具体步骤为：
采用金属有机物化学气相沉积或分子束外延方法在衬底上依次生长成核层、外延层、势垒层、栅极盖帽层；
或者
采用MOCVD设备衬底上依次成核层、外延层、势垒层、栅极盖帽层。
进一步的，步骤S2具体步骤为：
利用半导体光刻法和刻蚀法制作器件台面，通过半导体刻蚀方法对表面刻蚀，实现台面隔离；重复该步骤，在源、漏极区域刻蚀掉势垒层形成凹槽；进一步刻蚀掉栅极区域外面的栅极盖帽层；
或者
将样品均匀旋涂光刻胶；样品放置在热板上加热，进行软烘；把样品放置在曝光机中持续曝光；在显影液中进行显影；在热板上加热坚膜；通过Cl基等离子体ICP刻蚀方法，刻蚀外延层结构，形成台面隔离，然后样品通过丙酮溶液清洗去胶；重复该步骤，在源、漏极区域刻蚀掉势垒层形成凹槽；重复该步骤，刻蚀掉栅极区域外面的盖帽层，形成栅极盖帽层。
进一步的，步骤S3具体步骤为：
通过半导体光刻法定义出源、漏极所需区域，并通过金属沉积法沉积器件的源、漏极金属，通过高温退火，使复合金属结构变为合金，形成欧姆接触；利用等离子体增强化学气相沉积法、低压化学气相沉积法、磁控溅射法、电子束蒸发 法中的任意一种方法进行沉积，形成器件表面钝化层；
或者
通过半导体光刻法定义出源、漏极所需区域，通过电子束蒸发法沉积器件的源、漏极金属，然后样品在丙酮溶液中剥离、清洗去胶；通过在氮气高温环境中退火，使复合金属结构变为合金，形成欧姆接触；利用PECVD技术沉积法进行沉积，形成器件表面钝化层。
进一步的，步骤S4具体步骤为：
通过半导体光刻法定义出栅极区域，对栅极盖帽层进行表面氧化，处理形成栅介质插入层；或者采用PECVD、LPCVD、MOCVD、ALD、磁控溅射法中的任意方法进行沉积，形成单层或者复合多重栅介质插入层；
或者
通过半导体光刻法定义出栅极区域，对栅极盖帽层表面进行低功率氧离子预处理，后采用LPCVD进行沉积，形成栅极介质插入层。
进一步的，步骤S5具体步骤为：
通过半导体光刻法定义出栅极和场板区域，通过金属沉积法沉积器件的栅极金属和向漏极延伸的场板金属，最后在器件表面沉积钝化层，然后采用半导体光刻法定义出源极、栅极和漏极所需的开口区域，将定义区域的钝化层去除，暴露出金属电极表面，最后沉积金属薄膜制作引线，完成电极制作，得到最后器件结构；
或者
通过半导体光刻法定义出栅极和场板区域，通过电子束蒸发技术沉积器件的栅极和延伸场板金属，然后样品在丙酮溶液中剥离、清洗去胶；在器件表面采用PECVD沉积钝化层，采用半导体光刻法定义出源极、栅极和漏极所需的开口区域，将定义区域的钝化层去除，暴露出金属电极表面，通过磁控溅射法沉积电极金属，得到最后器件结构。
本发明的有益效果是：
本发明所述的高阈值电压常关型高电子迁移率晶体管及其制备方法实现常关型器件类型的同时能保持大的导通电流密度；采用对p-GaN(或p-InGaN或者p-AlGaN)栅极盖帽层进行表面氧化技术处理，形成栅极氧化物介质层或者直接 沉积栅介质插入层或者形成多重栅介质插入层，通过提高势垒层导带位置从而提高该常关型器件的栅极耐压和阈值电压。
附图说明
图1是本发明高阈值电压常关型HEMT器件截面示意图；
图2是本发明器件制作工艺流程示例图a；
图3是本发明器件制作工艺流程示例图b；
图4是本发明器件制作工艺流程示例图c；
图5是本发明器件制作工艺流程示例图d；
图6是本发明器件制作工艺流程示例图e；
图7是本发明器件制作工艺流程示例图f；
图8是有、无复合栅介质插入层技术方案中器件能带对比示意图；
图9是有、无复合栅介质插入层技术方案中器件阈值电压特性对比示意图。
具体实施方式
下面结合附图1-9对高阈值电压常关型高电子迁移率晶体管及其制备方法做进一步说明。
本专利申请针对栅极生长p型盖帽层方案，采用对p-GaN(或p-InGaN或者p-AlGaN)栅极盖帽层进行表面氧化技术处理形成栅极氧化物介质层或者直接沉积栅介质插入层或者形成多重栅介质插入层，如图1所示，通过提高势垒层导带位置从而提高该常关型器件的栅极耐压和阈值电压。栅极p型盖帽层在产业界目前是个能较好实现常关型器件的技术方案，该技术并未损伤2DEG沟道，因此器件的导通电流密度(或者导通电阻)特性并未下降。而p-GaN(或p-InGaN或者p-AlGaN)栅极盖帽层形成的附加内建电场将2DEG沟道界面的导带提升到费米能级上方，从而获得常关型操作，但是阈值电压一般只有1V左右，栅极最高耐压一般小于10V。本专利申请在栅极盖帽层上方引入单层或者复合多重栅介质插入层后，将进一步提升势垒层和2DEG沟道界面的导带位置，获得明显增大的栅极耐压(＞20V)和阈值电压(＞2V)。
图1是本专利申请提出的高阈值电压常关型HEMT器件截面示意图，栅金属电极和p型盖帽层之间引入栅介质插入层为其主要特征。
本专利申请所提器件的基本结构说明如下：底部为衬底，可以是硅、蓝宝石、 碳化硅、金刚石或者GaN自支撑衬底等；衬底上方为AlN或者AlGaN超晶格成核层；成核层上方为GaN或者GaAs外延层；外延层上方为AlGaN、InAlN、AlN或AlGaAs势垒层，势垒层和外延层形成异质结结构，该界面由极化电荷诱导产生二维电子气(2DEG)；势垒层上方是二氧化硅(SiO 2)、氮化硅(Si 3N 4)或者它们的复合结构形成钝化层；栅区势垒层上方分别是p-GaN或者p-InGaN或者p-AlGaN盖帽层以及氧化镓(Ga 2O 3)、二氧化硅(SiO 2)、氮化硅(Si 3N 4)、氧化铝(Al 2O 3)或者氧化铪(HfO 2)等各种材料形成单层或者复合多重栅介质插入层；与外延层接触的源极、漏极，以及栅介质插入层上方的栅极和向漏极延伸的场板。
本专利申请所提器件结构方案的优势是实现常关型器件类型的同时能保持大的导通电流密度，在此基础上进一步增大的器件栅极耐压和阈值电压。
实施例1
本专利申请具体实施过程如下：
步骤①：晶片生长。
采用金属有机物化学气相沉积(MOCVD)或分子束外延(MBE)等半导体材料生长技术依次在硅、蓝宝石、碳化硅、金刚石或者GaN自支撑衬底上依次生长AlN或者AlGaN超晶格成核层、2～10μm的GaN或者GaAs外延层、5～100nm的AlGaN、InAlN、AlN或AlGaAs势垒层(其中Al组分为0.05～0.3)、30～100nm的p-GaN或者p-InGaN或者p-AlGaN栅极盖帽层，如图2、图3所示。
步骤②：外延层结构刻蚀。
利用半导体光刻技术和刻蚀技术制作器件台面，通过如基于Cl基气体的感应耦合等离子体(ICP)或者反应离子刻蚀(RIE)等半导体刻蚀技术，将表面刻蚀300～800nm，实现台面隔离。重复该步骤，在源、漏极区域刻蚀掉势垒层形成凹槽；进一步刻蚀掉栅极区域外面的p型盖帽层，如图4所示。其中半导体光刻技术包含完整的匀胶、软烘、曝光、显影、坚膜等步骤。
步骤③：源、漏电极制作。
通过步骤②所述的半导体光刻技术定义出源、漏极所需区域，并通过如磁控溅射、电子束蒸发等金属沉积技术沉积器件的源、漏极金属，并且通过高温退火，使复合金属结构变为合金，形成欧姆接触。利用等离子体增强化学气相沉积法(PECVD)、低压化学气相沉积法(LPCVD)、磁控溅射法或者电子束蒸发法等技术 沉积SiO 2、Si 3N 4或者它们的复合结构，形成器件表面钝化层，如图5所示。
步骤④：栅介质插入层制备。
通过步骤②所述的半导体光刻技术定义出栅极区域，对p-GaN(或p-InGaN或者p-AlGaN)栅极盖帽层进行表面氧化技术处理形成Ga 2O 3介质层，或者采用PECVD、LPCVD、MOCVD、原子层沉积(ALD)或者磁控溅射等技术直接沉积SiO 2、Si 3N 4、氧化铝(Al 2O 3)或者氧化铪(HfO 2)等单层或者复合多重介质插入层，如图6所示。
步骤⑤：栅电极制作。
通过步骤②所述的半导体光刻技术定义出栅极和场板区域，步骤③所述的金属沉积技术沉积器件的栅极金属和向漏极延伸的场板金属，如图7所示。最后在器件表面沉积300～5000nm的厚钝化层，然后采用步骤②所述的半导体光刻技术定义出源极、栅极和漏极所需的开口区域，将定义区域的钝化层去除，暴露出金属电极表面，最后沉积金属薄膜制作引线，完成电极制作，得到最后器件结构。
实施例2
本专利申请具体实施过程如下(详细参数和步骤)：
步骤①：GaN结构外延生长。
采用MOCVD设备在6英寸p型Si衬底上依次生长100nm的AlGaN超晶格成核层、2μm的GaN外延层、20nm的AlGaN势垒层(Al组分为0.25)、50nm的p-GaN盖帽层。器件结构和尺寸设计如下：器件的源极和栅极距离为2μm，栅极长为3μm、宽为200μm，栅极向漏极延伸场板长为1μm、栅极和漏极距离为10μm，各电极面积为200×200μm 2。
步骤②：外延层结构刻蚀。
利用半导体光刻技术，其具体过程为：
(1)将样品以4000r/min的速率持续30s均匀旋涂AZ5214光刻胶；
(2)将样品放置在100℃的热板上加热进行软烘90s；
(3)把样品放置在光强为7mW/cm 2的曝光机中持续曝光20s；
(4)在显影液中显影45s；
(5)在105℃的热板上加热坚膜60s。
通过Cl基等离子体ICP刻蚀技术，选择150W电源功率，刻蚀500nm深度的 外延层结构形成台面隔离，然后样品通过丙酮溶液清洗去胶。重复该步骤，选择30W的较低电源功率，在源、漏极区域刻蚀掉20nm势垒层形成凹槽；重复该步骤，选择30W的较低电源功率，刻蚀掉栅极区域外面的p-GaN，形成栅极盖帽层。
步骤③：源、漏电极制作。
通过步骤②所述的半导体光刻技术定义出源、漏极所需区域，通过电子束蒸发技术沉积器件的源漏极金属，即Ti/Al/Ni/Au(20/100/45/55nm)，然后样品在丙酮溶液中剥离、清洗去胶。通过在875℃的氮气高温环境中退火30s，使复合金属结构变为合金，形成欧姆接触。利用PECVD技术沉积200nm的SiO 2钝化层。
步骤④：栅介质插入层制备。
通过步骤②所述的半导体光刻技术定义出栅极区域，对p-GaN栅极盖帽层表面进行低功率(30W)氧离子预处理，后采用LPCVD技术沉积5nm厚度的Si 3N 4栅极介质插入层。
步骤⑤：栅电极制作。
通过步骤②所述的半导体光刻技术定义出栅极和场板区域，通过电子束蒸发技术沉积器件的栅极和延伸场板金属，即Ni/Au(100/100nm)，然后样品在丙酮溶液中剥离、清洗去胶。最后在器件表面采用PECVD技术沉积1000nm的SiO 2钝化层，然后采用步骤②所述的半导体光刻技术定义出源极、栅极和漏极所需的开口区域，将定义区域的钝化层去除，暴露出金属电极表面，通过磁控溅射法沉积1500nm厚度的Al金属，得到最后器件结构。
图8和图9为采用本实施例器件结构参数获得的，在有、无栅介质插入层技术方案中的器件能带对比和阈值电压特性对比结果。由图中可以看出，引入栅介质插入层可以明显提高势垒层带阶和导带位置，从而提高常关型器件的栅极耐压和阈值电压，器件阈值电压从1.5V提高到4.5V，同时保留器件良好的导通电流等级。
以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明披露的技术范围内，根据本发明的技术方案及其发明构思加以等同替换或改变，都应涵盖在本发明的保护范围之内。本发明所述的实施例，并非对本发明内容进行限定，其他具有2DEG的异质结HEMT器件都适用于本发明提案涉及范围。任何其他钝化层生长(包括不同的 生长技术、不同的钝化层组合或者也可直接省略钝化工艺步骤)、欧姆接触电极制作工艺(包括不同的金属选择、沉积方法、退火条件)或者台面刻蚀工艺，在基于实现本发明所述具有p型栅极盖帽层表面进行等离子体处理形成介质层或者额外引入单层或多重复合介质插入层结构特点的常关型HEMT器件基本功能目的下，都适用于本发明提案涉及范围。所述复合栅介质插入层即可以是绝缘阻挡层，还可以是实现载流子隧穿效应的介质层。同时，这种复合栅介质插入层的位置还可以插入到权利要求1所述的栅极盖帽层下方，此时，这种复合栅介质还可以是高阻半导体。同样地，材料结构参数和电极尺寸的改变，或等同替换等，都应涵盖在本发明的保护范围之内。

Claims (10)

  1. 一种高阈值电压常关型高电子迁移率晶体管，其特征在于，包括：衬底、成核层、外延层、势垒层、钝化层、栅极盖帽层、复合栅介质插入层、栅极、源极和漏极，在所述衬底上依次生长成核层和外延层，所述外延层上方为势垒层、源极和漏极，所述势垒层和外延层形成异质结结构，二者接触界面由极化电荷诱导产生二维电子气，所述势垒层上方为钝化层，栅区势垒层上方为栅极盖帽层，所述栅极盖帽层上方为复合栅介质插入层，所述复合栅介质插入层上方为栅极，所述栅极与所述钝化层接触，在所述钝化层上、所述栅极向所述漏极方向延伸有场板。
  2. 如权利要求1所述的高阈值电压常关型高电子迁移率晶体管，其特征在于，所述衬底是硅、蓝宝石、碳化硅、金刚石、GaN自支撑衬底中的任意一种；所述成核层是AlN或者AlGaN超晶格；所述外延层是GaN或者GaAs；所述势垒层是AlGaN、InAlN、AlN、AlGaAs中的任意一种；所述钝化层是SiO 2、Si 3N 4或者二者的复合结构。
  3. 如权利要求1所述的高阈值电压常关型高电子迁移率晶体管，其特征在于，所述栅极盖帽层是p-GaN或者p-InGaN或者p-AlGaN；所述复合栅介质插入层是氧化镓、二氧化硅、氮化硅、氧化铝、氧化铪的任意材料形成的单层结构、或者是由上述材料任意组合的复合多重结构、或者是高阻半导体。
  4. 如权利要求1-3任一项所述的高阈值电压常关型高电子迁移率晶体管，其特征在于，所述复合栅介质插入层插入到所述栅极盖帽层下方。
  5. 一种高阈值电压常关型高电子迁移率晶体管制备方法，其特征在于，步骤如下：
    S1、晶片生长；
    S2、外延层结构刻蚀；
    S3、源、漏电极制作；
    S4、栅介质插入层制备；
    S5、栅电极制作。
  6. 如权利要求5所述的高阈值电压常关型高电子迁移率晶体管制备方法，其特征在于，步骤S1具体步骤为：
    采用金属有机物化学气相沉积或分子束外延方法在衬底上依次生长成核层、 外延层、势垒层、栅极盖帽层；
    或者
    采用MOCVD设备衬底上依次成核层、外延层、势垒层、栅极盖帽层。
  7. 如权利要求5所述的高阈值电压常关型高电子迁移率晶体管制备方法，其特征在于，步骤S2具体步骤为：
    利用半导体光刻法和刻蚀法制作器件台面，通过半导体刻蚀方法对表面刻蚀，实现台面隔离；重复该步骤，在源、漏极区域刻蚀掉势垒层形成凹槽；进一步刻蚀掉栅极区域外面的栅极盖帽层；
    或者
    将样品均匀旋涂光刻胶；样品放置在热板上加热，进行软烘；把样品放置在曝光机中持续曝光；在显影液中进行显影；在热板上加热坚膜；通过Cl基等离子体ICP刻蚀方法，刻蚀外延层结构，形成台面隔离，然后样品通过丙酮溶液清洗去胶；重复该步骤，在源、漏极区域刻蚀掉势垒层形成凹槽；重复该步骤，刻蚀掉栅极区域外面的盖帽层，形成栅极盖帽层。
  8. 如权利要求5所述的高阈值电压常关型高电子迁移率晶体管制备方法，其特征在于，步骤S3具体步骤为：
    通过半导体光刻法定义出源、漏极所需区域，并通过金属沉积法沉积器件的源、漏极金属，通过高温退火，使复合金属结构变为合金，形成欧姆接触；利用等离子体增强化学气相沉积法、低压化学气相沉积法、磁控溅射法、电子束蒸发法中的任意一种方法进行沉积，形成器件表面钝化层；
    或者
    通过半导体光刻法定义出源、漏极所需区域，通过电子束蒸发法沉积器件的源、漏极金属，然后样品在丙酮溶液中剥离、清洗去胶；通过在氮气高温环境中退火，使复合金属结构变为合金，形成欧姆接触；利用PECVD技术沉积法进行沉积，形成器件表面钝化层。
  9. 如权利要求5所述的高阈值电压常关型高电子迁移率晶体管制备方法，其特征在于，步骤S4具体步骤为：
    通过半导体光刻法定义出栅极区域，对栅极盖帽层进行表面氧化，处理形成栅介质插入层；或者采用PECVD、LPCVD、MOCVD、ALD、磁控溅射法中的任意方 法进行沉积，形成单层或者复合多重栅介质插入层；
    或者
    通过半导体光刻法定义出栅极区域，对栅极盖帽层表面进行低功率氧离子预处理，后采用LPCVD进行沉积，形成栅极介质插入层。
  10. 如权利要求5所述的高阈值电压常关型高电子迁移率晶体管制备方法，其特征在于，步骤S5具体步骤为：
    通过半导体光刻法定义出栅极和场板区域，通过金属沉积法沉积器件的栅极金属和向漏极延伸的场板金属，最后在器件表面沉积钝化层，然后采用半导体光刻法定义出源极、栅极和漏极所需的开口区域，将定义区域的钝化层去除，暴露出金属电极表面，最后沉积金属薄膜制作引线，完成电极制作，得到最后器件结构；
    或者
    通过半导体光刻法定义出栅极和场板区域，通过电子束蒸发技术沉积器件的栅极和延伸场板金属，然后样品在丙酮溶液中剥离、清洗去胶；在器件表面采用PECVD沉积钝化层，采用半导体光刻法定义出源极、栅极和漏极所需的开口区域，将定义区域的钝化层去除，暴露出金属电极表面，通过磁控溅射法沉积电极金属，得到最后器件结构。
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