CN105895526A - 一种GaN基功率电子器件及其制备方法 - Google Patents
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Abstract
一种GaN基功率电子器件,包括衬底和衬底之上的外延层,所述外延层包括GaN基异质结构层、超晶格结构层和P型盖帽层,所述超晶格结构层设置于所述异质结构层之上,所述P型盖帽层设置于所述超晶格结构层之上。以及一种GaN基功率电子器件的制备方法。通过该电子器件,进一步扩展了基于P‑Al(In,Ga)N盖帽层技术制备的GaN基功率电子器件的栅压摆幅和安全栅压范围,并且提高器件的动态特性,从而推动基于P‑Al(In,Ga)N盖帽层技术的GaN基功率电子器件的应用进程。
Description
技术领域
本发明涉及GaN基功率电子应用技术领域,尤其涉及一种GaN基功率电子器件,以及该电子器件的制备方法。
背景技术
高效功率电子器件(又称功率开关器件)在智能电网、工业控制、新能源发电、电动汽车以及消费电子等领域具有重大应用价值,全球70%以上的电力电子系统均由基于功率半导体器件的电力管理系统来调控管理。传统Si功率电子器件性能已经接近Si半导体材料的物理极限,以SiC和GaN为代表的新型宽禁带半导体器件凭借更高的击穿电场、更高的工作频率和更低的导通电阻有望成为下一代高效功率电子技术的强有力竞争者。
增强型是功率电子器件安全工作的关键要求,即在高压工作时,器件即使失去栅控的状态下也是安全的,不会导致系统的烧毁。这就要求功率电子器件必须是增强型的(enhancement-mode,也称normally-off),即器件的阈值要在0V以上。而目前GaN基增强型功率电子器件主要是基于Al(In,Ga)N/GaN异质结构制备的,依靠Al(In,Ga)N势垒层和GaN缓冲层间较强的自发和压电极化效应,在Al(In,Ga)N/GaN异质结沟道中会诱导出高达1013cm-2的二维电子气(2DEG),因此基于该结构制备的GaN基功率电子器件(包括HEMTs和MIS-HEMTs)一般是耗尽型的,为了实现GaN基增强型器件,目前国际上主要有五种技术:1)栅槽刻蚀减薄Al(In,Ga)N势垒层;2)在Al(In,Ga)N势垒层中注入带负电的氟离子;3)在势垒层表面生长P-(Al)GaN盖帽层;4)在势垒层表面生长InGaN或厚GaN反极化层;5)增强型Si-MOSFET与GaN基耗尽型HEMT/MIS-HEMT级联结构。
P-Al(In,Ga)N盖帽层技术是利用PN结的空间电荷区效应耗尽Al(In,Ga)N/GaN异质结沟道的二维电子气以实现增强型,它是通过MOCVD或MBE在Al(In,Ga)N/GaN异质结构上继续原位外延生长P-Al(In,Ga)N层,由于外延技术对厚度和均匀性的控制比较精确,利用P-Al(In,Ga)N盖帽层技术一般能获得较好的阈值一致性,特别是P-Al(In,Ga)N技术已经有相关的示范产品报道,其中包括美国宜普电源转换公司EPC,日本松下(panasonic),韩国三星(samsung),加拿大GaN systems,甚至是中国台湾TSMC。
尽管P-Al(In,Ga)N盖帽层技术能将GaN基增强型器件阈值推进到+1.5V,然而当栅压超过P-N结的正向开启电压时,栅极正向漏电会迅速增大,很可能导致栅极的击穿,影响器件的安全性。因此,研发基于P-Al(In,Ga)N盖帽层的栅极漏电抑制技术,对推动P-Al(In,Ga)N盖帽层技术在GaN基功率电子中的应用和产业化至关重要。
另一方面,由于表面态的存在,GaN基功率电子器件在高压工作时存在严重的电流坍塌,直接导致器件动态导通电阻和功耗的增加。多项研究表明,这些表面态很难被完全去除。因此,研发促进表面态快速恢复的技术,避开界面态处理难题具有重要的应用价值。
但是上述电子器件的低栅极漏电性能还不能满足电子器件需求,而且阈值控制能力包括电流塌陷自我修复能力上,也不能满足电子器件日益苛刻的要求。
发明内容
(一)要解决的技术问题
有鉴于此,本发明的主要目的在于提供一种GaN基功率电子器件结构及其制备方法,以解决以上所述的至少一项问题。
(二)技术方案
为实现上述目的,根据本发明的一方面,提供一种GaN基功率电子器件,包括衬底和衬底之上的外延层,中:
所述外延层包括GaN基异质结构层、超晶格结构层和P型盖帽层,
所述超晶格结构层设置于所述异质结构层之上,所述P型盖帽层设置于所述超晶格结构层之上。
根据本发明的一具体实施方案,所述超晶格结构层为AlN/GaN超晶格结构、AlGaN/GaN超晶格结构、AlN/GaN/AlN量子阱结构或者AlGaN/GaN/AlGaN量子阱结构。
根据本发明的一具体实施方案,所述AlGaN/GaN超晶格中单周期的AlGaN和GaN的厚度分别为x纳米、y纳米,1≤x≤4,1≤y≤4。
根据本发明的一具体实施方案,所述超晶格结构层是P型掺杂的,或者是非掺杂的。
根据本发明的一具体实施方案,所述异质结构层包括缓冲层和其上方的势垒层,所述缓冲层为GaN缓冲层,所述势垒层为Al(In,Ga)N势垒层。
根据本发明的一具体实施方案,所述P型盖帽层是P-GaN,P-InN或P-AlN二元合金层,也可以是P-AlGaN,P-AlInN或P-InGaN三元合金层,或者是AlInGaN四元合金层。
根据本发明的一方面,提供一种GaN基功率电子器件的制备方法,包括以下步骤:
(1)准备衬底;
(2)在衬底上制备外延层,所述外延层包括GaN基异质结构层、超晶格结构层和P型盖帽层,所述超晶格结构层制备于所述异质结构层之上,所述P型盖帽层制备于所述超晶格结构层之上。
(3)在外延层上制备栅极,源极,漏极以及钝化层。
根据本发明的一具体实施方案,所述栅极与源极,栅极与漏极之间具有或者不具有超晶格层。
根据本发明的一具体实施方案,所述栅极与源极,栅极与漏极之间的P型盖帽层采用干法刻蚀去除,制备时所述超晶格结构层作为停止层。
根据本发明的一具体实施方案,所述器件的栅极是肖特基接触,或者是欧姆接触。
(三)有益效果
从上述技术方案可以看出,本发明具有以下有益效果:
1、本发明提供的GaN基功率电子器件结构及制备方法,从材料生长和能带工程角度提供一种抑制基于P型Al(In,Ga)N盖帽层技术的GaN基增强型功率电子器件的栅极正反向漏电的技术,通过在P型盖帽层与异质结构之间插入一层Al(Ga)N/GaN超晶格以提高栅极的势垒高度,从而抑制栅极的正反向漏电,进一步扩展了基于p型盖帽层技术制备的GaN基功率电子器件的栅压摆幅和安全栅压范围,从而推动基于P型盖帽层技术的GaN基功率电子器件的应用进程,促进GaN基功率电子器件的产业化;
2、本发明提供的GaN基功率电子器件结构及制备方法,在栅极正向开启时,位于P型盖帽层与异质结构之间的超晶格中的电子空穴复合发光能促进栅漏和栅源间异质结表面和体内深能级捕获电子的释放,实现器件电流坍塌的同步自我恢复,从而有效抑制器件动态导通电阻的升高;
3、本发明提供的GaN基功率电子器件结构及制备方法,位于P型盖帽层与异质结构之间的超晶格可充当干法刻蚀P型盖帽层的停止层,从而提高器件导通电阻的均匀性和器件的成品率。
附图说明
图1a和1b是根据本发明具体实施方案提供的两种GaN基功率电子器件结构示意图;
图2a和2b是干法刻蚀图1中栅极以外区域P型Al(In,Ga)N层的示意图;
图3是根据对比在P型Al(In,Ga)N层与Al(In,Ga)N/GaN异质结构之间插入Al(Ga)N/GaN超晶格层前后的能带图对比。
图4a和4b分别是图1a和1b中本发明提供的两种GaN基功率电子器件在栅极正向开启时栅下Al(Ga)N/GaN超晶格插入层的发光和传播示意图。
具体实施方式
本发明中,“之上”及“之下”用语仅表示相应层结构的相对位置关系,相应层可以为接触与非接触。另外,在下面的详细描述中,为便于解释,阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显 地,一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其他情况下,公知的结构和装置以附图的方式体现以简化附图。
根据本发明总体上的发明构思,提供一种GaN基功率电子器件,包括衬底和衬底之上的外延层,其中,所述外延层包括GaN基异质结构层、超晶格结构层和P型盖帽层,所述超晶格结构层设置于所述异质结构层之上,所述p型盖帽层设置于所述超晶格结构层之上。
对于所述衬底,可以为硅衬底、SiC衬底、蓝宝石衬底或者是同质外延的GaN衬底。
对于各外延层的制备方法,可以采用金属有机物化学气相沉积或分子束外延技术进行制备。对于包含GaN基异质结构层、超晶格结构层和P型盖帽层的外延层结构,其具有增强型栅结构。
对于超晶格结构层,优选的,所述超晶格结构层为多周期Al(Ga)N/GaN超晶格结构;进一步优选的,所述多周期Al(Ga)N/GaN超晶格结构为AlN/GaN超晶格结构、AlGaN/GaN超晶格结构、AlN/GaN/AlN量子阱结构或者AlGaN/GaN/AlGaN量子阱结构;对于超晶格中周期层的厚度选择,优选的,所述Al(Ga)N/GaN超晶格中单周期的Al(Ga)N和GaN的厚度分别为x纳米、y纳米,1≤x≤4,1≤y≤4。处于P型盖帽层与GaN基异质结构之间的超晶格不仅能有效抑制GaN基电子器件的栅极正反向漏电,同时在栅极正向开启时该超晶格中的电子空穴复合发光能促进栅漏和栅源间异质结表面和体内深能级捕获电子的释放,实现器件电流坍塌的同步自我恢复。
对于超晶格层的组成,所述超晶格结构层可以是P型掺杂层或者非掺杂层。
对于异质结构层,所述异质结构层包括缓冲层和其上方的势垒层,所述缓冲层为GaN缓冲层,所述势垒层为Al(In,Ga)N势垒层。
所述势垒层的厚度为3-30nm。优选的,上述Al(In,Ga)N势垒层为AlGaN或AlInN三元合金势垒层,或者是AlInGaN四元合金势垒层。
对于P型盖帽层选择,优选P型盖帽层为P-Al(In,Ga)N层,进一步优选的是P-GaN,P-InN或P-AlN二元合金层,也可以是P-AlGaN,P-AlInN或P-InGaN三元合金层,或者是AlInGaN四元合金层。
优选的,在所述p型盖帽层之上还设置有栅极金属,它可以是欧姆接触,也可以是肖特基接触。
优选的,电子器件还包括源极和漏极,源极和漏极通过刻蚀掉P型盖帽层或超晶格层后制备,与相应层为欧姆接触。
在某些方案中,电子器件优选为场效应晶体管。其中,栅源和栅漏间P型盖帽层被刻蚀掉,但是栅源和栅漏间的超晶格结构层可以刻蚀掉,也可以保留。
基于同一发明构思,本发明提供一种GaN基功率电子器件的制备方法,其特征在于包括以下步骤:
(1)准备衬底;
(2)在衬底上制备外延层,所述外延层包括GaN基异质结构层、超晶格结构层和P型盖帽层,所述超晶格结构层制备于所述异质结构层之上,所述p型盖帽层制备于所述超晶格结构层之上。
对于各外延层的制备,在制备过程中,可以采用金属有机物化学气相沉积或分子束外延技术进行制备。
对于栅极与源极,栅极与漏极之间的P型盖帽层采用干法刻蚀去除,制备时所述超晶格结构层成作为停止层。
优选的,在步骤(2)后,采用先栅工艺或后栅工艺在该外延层结构之上形成栅极、源极、漏极以及钝化保护层。
上述方案中,所述先栅工艺是先在外延层结构之上制备栅极,然后刻蚀去掉栅极以外的P型盖帽层制备源极及漏极欧姆接触,最后在栅极与源极以及栅极与漏极之间的接入区域制备钝化保护层;
上述方案中,所述后栅工艺是在外延层结构之上,首先刻蚀去掉源极和漏极区域的P型盖帽层制备源漏欧姆接触,然后在P型盖帽层上制备栅极,最后刻蚀去掉栅源以及栅漏间的P型盖帽层层制备钝化保护层。
下面通过实施方案,并结合附图,对本发明的技术方案作进一步具体的说明。下述参照附图对本发明实施方式的说明旨在对本发明的总体发明构思进行解释,而不应当理解为对本发明的一种限制。
本发明提供的两种GaN基功率电子器件结构,如图1a和1b所示,包括:衬底;形成于衬底之上的GaN基高电子迁移率Al(In,Ga)N/GaN异质 结构;形成于高电子迁移率Al(In,Ga)N/GaN异质结构之上的多周期Al(Ga)N/GaN超晶格结构;形成于超晶格结构之上的P型Al(In,Ga)N层。该电子器件是一种场效应晶体管结构,包含源极,栅极和漏极,其中栅极是制作在P-Al(In,Ga)N上,栅极是欧姆接触或肖特基接触。源极和漏极通过刻蚀掉P-Al(In,Ga)N层或P-Al(In,Ga)N/(Al(Ga)N/GaN)SL后制备的,是欧姆接触。另外,栅源和栅漏间P-Al(In,Ga)N层是被刻蚀掉的,但是栅源和栅漏间的Al(Ga)N/GaN超晶格结构层可以刻蚀掉(图1a),也可以保留(图1b)。
图1a和1b中,P-Al(In,Ga)N/(Al(Ga)N/GaN)SL/Al(In,Ga)N/GaN外延层结构是利用金属有机物化学气相沉积或分子束外延技术直接在衬底上依次外延GaN缓冲层,Al(In,Ga)N势垒层,(Al(Ga)N/GaN)SL超晶格,P型Al(In,Ga)N层而形成,以实现增强型栅结构。Al(In,Ga)N势垒层是AlGaN或AlInN三元合金势垒层,或者是AlInGaN四元合金势垒层。(Al(Ga)N/GaN)SL超晶格层是AlN/GaN超晶格结构,或者是AlGaN/GaN超晶格结构,或者是AlN/GaN/AlN量子阱结构,或者是AlGaN/GaN/AlGaN量子阱结构;它可以是Al(Ga)N/GaN(2nm/2nm)超晶格,或者是Al(Ga)N/GaN(x nm/y nm)超晶格;它可以是P型掺杂层,或者是非掺杂的。P-Al(In,Ga)N层是P-GaN,P-InN或P-AlN二元合金层,也可以是P-AlGaN,P-AlInN或P-InGaN三元合金层,或者是AlInGaN四元合金层。衬底为硅衬底、SiC衬底、蓝宝石衬底或同质外延的GaN衬底。
图2a和2b是干法刻蚀图1中栅极以外区域P型Al(In,Ga)N层的示意图。在栅极掩膜的掩蔽下,用Cl基等离子体(Cl2,BCl3)干法刻蚀栅极以外区域P型Al(In,Ga)N层(图2a),直到Al(Ga)N/GaN超晶格停止层(图2b)。
图3是对比了在P型Al(In,Ga)N层与Al(In,Ga)N/GaN异质结构之间插入Al(Ga)N/GaN超晶格层前后的能带图对比。可以看出,由于Al(Ga)N/GaN超晶格的存在,P型Al(In,Ga)N层与Al(In,Ga)N/GaN间的势垒高度明显升高,从而能有效抑制栅极的正反向漏电。
本发明提供的两种具有自恢复能力的低栅极漏电GaN基增强型功率电子器件中,其中处于P型Al(In,Ga)N层与GaN基高电子迁移率 Al(In,Ga)N/GaN异质结构之间的Al(Ga)N/GaN超晶格不仅能有效抑制GaN基增强型功率电子器件的栅极正反向漏电,同时在栅极正向开启时该Al(Ga)N/GaN超晶格中的电子空穴复合发光,如图4a和4b发光示意图所示,该发光能促进栅漏和栅源间Al(In,Ga)N/GaN异质结表面和体内深能级捕获电子的释放,实现器件电流坍塌的同步自我恢复。
以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (10)
1.一种GaN基功率电子器件,包括衬底和衬底之上的外延层,其特征在于:
所述外延层包括GaN基异质结构层、超晶格结构层和P型盖帽层,
所述超晶格结构层设置于所述异质结构层之上,所述P型盖帽层设置于所述超晶格结构层之上。
2.根据权利要求1所述的GaN基功率电子器件,其特征在于,所述超晶格结构层为AlN/GaN超晶格结构、AlGaN/GaN超晶格结构、AlN/GaN/AlN量子阱结构或者AlGaN/GaN/AlGaN量子阱结构。
3.根据权利要求2所述的GaN基功率电子器件,其特征在于,所述AlGaN/GaN超晶格中单周期的AlGaN和GaN的厚度分别为x纳米、y纳米,1≤x≤4,1≤y≤4。
4.根据权利要求2所述的GaN基功率电子器件,其特征在于,所述超晶格结构层是P型掺杂的,或者是非掺杂的。
5.根据权利要求1所述的GaN基功率电子器件,其特征在于,所述异质结构层包括缓冲层和其上方的势垒层,所述缓冲层为GaN缓冲层,所述势垒层为Al(In,Ga)N势垒层。
6.根据权利要求1所述的GaN基功率电子器件,其特征在于,所述P型盖帽层是P-GaN,P-InN或P-AlN二元合金层,也可以是P-AlGaN,P-AlInN或P-InGaN三元合金层,或者是AlInGaN四元合金层。
7.一种GaN基功率电子器件的制备方法,其特征在于包括以下步骤:
(1)准备衬底;
(2)在衬底上制备外延层,所述外延层包括GaN基异质结构层、超晶格结构层和P型盖帽层,所述超晶格结构层制备于所述异质结构层之上,所述P型盖帽层制备于所述超晶格结构层之上;
(3)在外延层上制备栅极,源极,漏极以及钝化层。
8.根据权利要求7所述的GaN基功率电子器件的制备方法,其特征在于,所述栅极与源极,栅极与漏极之间具有或者不具有超晶格层。
9.根据权利要求8所述的GaN基功率电子器件的制备方法,其特征在于,所述栅极与源极,栅极与漏极之间的P型盖帽层采用干法刻蚀去除,制备时所述超晶格结构层作为停止层。
10.根据权利要求7所述的GaN基功率电子器件的制备方法,其特征在于,所述器件的栅极是肖特基接触,或者是欧姆接触。
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