CN106783945A - 一种GaN基增强型电子器件的材料结构 - Google Patents
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Abstract
本发明公开了一种GaN基增强型电子器件的材料结构，涉及GaN基功率电子和微波功率放大器应用技术领域。该材料结构包括：衬底、依次形成于衬底之上的GaN缓冲层、Al(In，Ga)N势垒层构成薄势垒Al(In，Ga)N/GaN异质结构；其中，该增强型电子器件的材料结构还包括形成于薄势垒Al(In，Ga)N层之上的钝化层，所述的钝化层采用n‑GaN、SiO2或SiNx材料制备，因此，本结构无需刻蚀Al(In，Ga)N势垒层就能形成增强型栅结构，同时利用钝化层的极化或n型掺杂效应显著提高了栅极以外薄势垒Al(In，Ga)N/GaN异质结沟道中的二维电子气密度，有助于制备阈值一致性良好，低动态导通电阻的GaN基增强型功率电子器件，提高器件成品率，推动GaN基功率电子器件的产业化进程。
Description
技术领域
本发明涉及GaN基功率电子和微波功率放大器应用技术领域，尤其涉及一种GaN基增强型电子器件的材料结构。
背景技术
高效功率电子器件(又称功率开关器件)在智能电网、工业控制、新能源发电、电动汽车以及消费电子等领域具有重大应用价值，全球70％以上的电力电子系统均由基于功率半导体器件的电力管理系统来调控管理。传统Si功率电子器件性能已经接近Si半导体材料的物理极限，以SiC和GaN为代表的新型宽禁带半导体器件凭借更高的击穿电场、更高的工作频率和更低的导通电阻有望成为下一代高效功率电子技术的强有力竞争者。
增强型是功率电子器件安全工作的关键要求，即在高压工作时，器件即使失去栅控的状态下也是安全的，不会导致系统的烧毁。这就要求功率电子器件必须是增强型的(enhancement-mode，也称normally-off)，即器件的阈值要在0V以上。而目前GaN基增强型功率电子器件主要是基于Al(In，Ga)N/GaN异质结构制备的，依靠Al(In，Ga)N势垒层和GaN缓冲层间较强的自发和压电极化效应，在Al(In，Ga)N/GaN异质结沟道中会诱导出高达1013cm-2的二维电子气(2-D Electron Gas，2-DEG)，因此基于该结构制备的GaN基功率电子器件(包括HEMTs和MIS-HEMTs)一般是耗尽型的，为了实现GaN基增强型器件，目前国际上主要有五种技术：1)栅槽刻蚀减薄Al(In，Ga)N势垒层；2)在Al(In，Ga)N势垒层中注入带负电的氟离子；3)在势垒层表面生长P-(Al)GaN盖帽层；4)在势垒层表面生长InGaN或厚GaN反极化层；5)增强型Si-MOSFET与GaN基耗尽型HEMT/MIS-HEMT级联结构。
栅槽刻蚀是通过等离子体干法刻蚀Al(In，Ga)N势垒层实现，由于势垒层一般只有20nm左右，通过该技术很难实现同一批次不同晶圆之间，尤其是不同批次的晶圆之间刻蚀深度的重复性，制约了该技术的产业化。氟离子注入技术同样面临工艺的重复性问题。P-(Al)GaN盖帽层和厚GaN反极化层技术是通过MOCVD或MBE外延生长厚度和掺杂控制来实现增强型，一般能获得较好的阈值一致性，特别是P-(Al)GaN技术已经有相关的示范产品报道。第5种级联技术利用成熟的Si-MOSFET(已产业化)实现增强型，也推出了相关的600V功率电子产品。
因此，采用无需栅槽刻蚀的薄势垒Al(In，Ga)N/GaN异质结构，以及具有极化或n型掺杂效应的表面钝化层恢复栅极以外薄势垒Al(In，Ga)N/GaN异质结沟道中的二维电子气(2-DEG)，有助于制备阈值一致性良好，低动态导通电阻的GaN基增强型功率电子器件，从而有效提高GaN基增强型器件的工艺重复性和成品率，推动GaN基功率电子器件的产业化进程。
发明内容
(一)要解决的技术问题
有鉴于此，本发明的主要目的在于提供一种GaN基增强型电子器件的材料结构，以解决GaN基功率电子器件的增强型阈值一致性和重复性，提高GaN基功率电子器件的工艺成品率，促进GaN基功率电子器件的产业化。
(二)技术方案
为达到上述目的，本发明提供了一种GaN基增强型电子器件的材料结构，该材料结构包括：衬底、薄势垒Al(In，Ga)N/GaN异质结构，薄势垒Al(In，Ga)N/GaN异质结构位于衬底之上，其中，材料结构还包括：钝化层，钝化层的制备材料是n-GaN、SiO2或SiNx，其位于薄势垒Al(In，Ga)N/GaN异质结构之上。
钝化层是具有极化特性的薄膜，或是能在Al(In，Ga)N表面产生n型掺杂效果的薄膜。
钝化层厚度介于1nm至200nm之间。
薄势垒Al(In，Ga)N/GaN异质结构包括GaN缓冲层、Al(In，Ga)N势垒层，GaN缓冲层位于衬底上，Al(In，Ga)N势垒层位于GaN缓冲层上。
Al(In，Ga)N势垒层厚度介于0nm至10nm之间。
Al(In，Ga)N势垒层可以是AlxGa(1-x)N三元合金势垒层，其中Al组分介于0至100％之间；Al(In，Ga)N势垒层还可以是AlxIn(1-x)N三元合金势垒层，其中Al组分介于75％至90％之间；Al(In，Ga)N势垒层还可以是AlxInyGa(1-x-y)N四元合金势垒层，其中Al和In组分介于0至100％之间。
除此之外，基于本发明提出的上述GaN基增强型电子器件的材料结构，本发明同时提出了该材料结构的制备方法，包括：
S1、在衬底上制备薄势垒Al(In，Ga)N/GaN异质结构；
S2、在薄势垒Al(In，Ga)N/GaN异质结构上制备钝化层。
其中，在步骤S2中，采用n-GaN、SiO2或SiNx材料制备钝化层，采用金属有机化学气相沉积法、分子束外延法、原子层沉积法、低压化学气相沉积法、等离子增强化学气相沉积法制备钝化层。
(三)有益效果
从上述技术方案可以看出，本发明具有以下有益效果：
1、本发明提供的GaN基增强型电子器件的材料结构，从材料结构角度提供一种精确调控GaN基增强型功率电子器件阈值电压的技术，通过采用薄势垒Al(In，Ga)N/GaN异质结构和n-GaN，SiO2或SiNx钝化层，能有效提高GaN基增强型器件阈值电压的可控度和一致性，解决了GaN基增强型器件的工艺重复性，有助于提高GaN基增强型电子器件的成品率，促进GaN基功率电子器件的产业化。
2、本发明提供的GaN基增强型电子器件的材料结构，由于在薄势垒Al(In，Ga)N/GaN异质结构中，势垒层厚度介于0到10nm之间，无需栅槽刻蚀即能形成增强型栅结构。
3、本发明提供的GaN基增强型电子器件的材料结构，由于在薄势垒Al(In，Ga)N/GaN异质结构中，势垒层厚度介于0到10nm之间，能有效降低欧姆接触的合金温度(850℃以下)。
4、本发明提供的GaN基增强型电子器件的材料结构，为了弥补上述Al(In，Ga)N/GaN薄势垒技术导致的沟道电阻的增加，利用n型掺杂GaN，SiNx或SiO2钝化层提高薄势垒Al(In，Ga)N/GaN异质结沟道的2-DEG密度，从而有效降低电子器件的导通电阻。
5、本发明提供的GaN基增强型电子器件的材料结构，所采用的n型掺杂GaN，SiNx或SiO2钝化层不仅能够降低平面型GaN基增强型电子器件的沟道电阻，而且能有效钝化Al(In，Ga)N/GaN异质结构的表面态，显著抑制其制备的功率电子器件的高压电流坍塌。
附图说明
图1是本发明提出的GaN基增强型电子器件的材料结构具体实施例的示意图；
图2是用于实现无栅槽刻蚀工艺的GaN基增强型电子器件的材料结构薄势垒Al(In，Ga)N/GaN异质结构的示意图；
图3是利用n型掺杂GaN，SiNx或SiO2钝化层实现GaN基增强型功率电子器件2-DEG恢复的示意图。
其中，1是衬底，2是GaN缓冲层，3是Al(In，Ga)N势垒层，4是钝化层，5是栅极，6是二维电子气(2-DEG)
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明。
本发明提供的GaN基增强型电子器件的材料结构，如图1所示，包括：衬底；形成于衬底之上的薄势垒Al(In，Ga)N/GaN异质结构；形成于薄势垒Al(In，Ga)N层之上的n-GaN，SiO2或SiNx钝化层。
图1中，薄势垒Al(In，Ga)N/GaN异质结构是利用金属有机物化学气相沉积或分子束外延技术直接在衬底上依次外延GaN缓冲层和Al(In，Ga)N势垒层而形成，以实现增强型栅结构。在薄势垒Al(In，Ga)N/GaN异质结构中，Al(In，Ga)N势垒层是厚度介于0到10nm的AlGaN或AlInN三元合金势垒层，或者是AlInGaN四元合金势垒层。
图1中，形成于薄势垒Al(In，Ga)N层之上的n-GaN，SiO2或SiNx钝化层，可采用金属有机化学气相沉积法(MOCVD)、分子束外延法(MBE)、原子层沉积法(ALD)、低压化学气相沉积法(LPCVD)、等离子增强化学气相沉积法(PECVD)等方法制备，钝化层厚度介于1到200nm之间。钝化层可以是具有极化特性的薄膜，也可以是能在Al(In，Ga)N表面产生n型掺杂效果的薄膜。
图2显示了用于实现GaN基增强型的薄势垒Al(In，Ga)N/GaN异质结构，通过在MOCVD或MBE外延过程中控制Al(In，Ga)N势垒层厚度(0到10nm)，削弱势垒层的自发和压电极化，从而降低该异质结沟道中的2-DEG密度，实现增强型阈值。
图3显示了利用n型掺杂GaN，SiNx或SiO2钝化层恢复其下沟道中的二维电子气(2-DEG)，而栅极区域的2-DEG仍然保持耗尽状态，从而实现了增强型器件结构。n型掺杂GaN，SiNx或SiO2钝化层同样抑制了GaN基增强型功率电子器件的高压电流坍塌，进一步提高了器
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
Claims (8)
1.一种GaN基增强型电子器件的材料结构，所述材料结构包括：衬底、薄势垒Al(In，Ga)N/GaN异质结构，所述的薄势垒Al(In，Ga)N/GaN异质结构位于衬底之上，其特征在于，所述材料结构还包括：钝化层，所述的钝化层的制备材料是n-GaN、SiO2或SiNx，其位于所述薄势垒Al(In，Ga)N/GaN异质结构之上。
2.根据权利要求1所述的GaN基增强型电子器件的材料结构，其特征在于，所述的钝化层是具有极化特性的薄膜，或是能在Al(In，Ga)N表面产生n型掺杂效果的薄膜。
3.根据权利要求2所述的GaN基增强型电子器件的材料结构，其特征在于，所述的钝化层厚度介于1nm至200nm之间。
4.根据权利要求1所述的GaN基增强型电子器件的材料结构，其特征在于，所述薄势垒Al(In，Ga)N/GaN异质结构包括GaN缓冲层、Al(In，Ga)N势垒层，所述的GaN缓冲层位于衬底上，所述的Al(In，Ga)N势垒层位于GaN缓冲层上。
5.根据权利要求4所述的GaN基增强型电子器件的材料结构，其特征在于，所述的Al(In，Ga)N势垒层厚度介于0nm至10nm之间。
6.根据权利要求5所述的GaN基增强型电子器件的材料结构，其特征在于，所述的Al(In，Ga)N势垒层可以是AlxGa(1-x)N三元合金势垒层，其中Al组分介于0至100％之间；所述的Al(In，Ga)N势垒层还可以是AlxIn(1-x)N三元合金势垒层，其中Al组分介于75％至90％之间；所述的Al(In，Ga)N势垒层还可以是AlxInyGa(1-x-y)N四元合金势垒层，其中Al和In组分介于0至100％之间。
7.一种GaN基增强型电子器件的材料结构制备方法，包括：
S1、在衬底上制备薄势垒Al(In，Ga)N/GaN异质结构；
S2、在薄势垒Al(In，Ga)N/GaN异质结构上制备钝化层；
其特征在于，在所述的步骤S2中，采用n-GaN、SiO2或SiNx材料制备钝化层。
8.根据权利要求7所述的GaN基增强型电子器件的材料结构制备方法，其特征在于，在所述的步骤S2中，采用金属有机化学气相沉积法、分子束外延法、原子层沉积法、低压化学气相沉积法、等离子增强化学气相沉积法制备钝化层。
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