WO2020172971A1 - 一种显示装置及其制作方法 - Google Patents

一种显示装置及其制作方法 Download PDF

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Publication number
WO2020172971A1
WO2020172971A1 PCT/CN2019/083246 CN2019083246W WO2020172971A1 WO 2020172971 A1 WO2020172971 A1 WO 2020172971A1 CN 2019083246 W CN2019083246 W CN 2019083246W WO 2020172971 A1 WO2020172971 A1 WO 2020172971A1
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Prior art keywords
layer
insulating layer
display area
integrated circuit
gate
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PCT/CN2019/083246
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English (en)
French (fr)
Inventor
方亮
丁玎
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武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/489,402 priority Critical patent/US11239291B2/en
Publication of WO2020172971A1 publication Critical patent/WO2020172971A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present invention relates to the field of display, in particular to a display device and a manufacturing method thereof.
  • OLED Organic electroluminescent display devices
  • the mainstream driving method of OLED display devices is current driving.
  • the working current is transmitted by the display device through the source and drain (SD: Source/Drain).
  • SD Source/Drain
  • the signal transmission has a voltage drop (IR Drop) phenomenon.
  • IR Drop voltage drop
  • the voltage and current are too large, and the area far away from the driving circuit is too small. Therefore, the brightness at both ends of the display area is significantly different, and the display device has uneven brightness, which affects the product. Use performance.
  • the current method for solving the uneven brightness of the OLED display device is a double-layer SD structure, which includes a first source drain 131 and a second source drain 132.
  • the second source and drain layer 132 adopts a mesh structure design, and the voltage drop is controlled through a parallel circuit, thereby improving the uneven brightness of the product.
  • the double-layer SD structure design restricts its popularization and application due to its complicated manufacturing process and high cost.
  • the purpose of the present invention is to provide a display device and a manufacturing method thereof, so as to solve the problems in the prior art that the manufacturing process of the source-drain double-layer structure is complicated, expensive, the luminous brightness of the display device is uneven, and the application range is narrow. technical problem.
  • the present invention provides a display device including a display area and a non-display area, the display area is surrounded by the non-display area, and the display area sequentially includes a substrate, a first insulating layer, a first gate layer, and a second insulating layer.
  • the non-display area includes an integrated circuit area; the thickness of the second insulating layer gradually decreases from a direction closer to the integrated circuit area to a direction away from the integrated circuit area.
  • the display area is divided into N sub-display areas arranged side by side; the N sub-display areas are sequentially arranged from a direction close to the integrated circuit area to a direction away from the integrated circuit area.
  • the thickness of the second insulating layer located in the (X+1)th sub-display area is less than the thickness of the second insulating layer located in the Xth sub-display area; and/or, the capacitance of the (X+1)th sub-display area Greater than the capacitance of the X-th sub-display area; where N ⁇ X ⁇ 2.
  • the first gate layer is provided on a surface of the first insulating layer away from the substrate; the second insulating layer is provided on the first gate layer away from the first A side surface of an insulating layer; the second gate layer is arranged on a surface of the second insulating layer away from the first gate layer.
  • the display area includes a barrier layer, a buffer layer, an active layer, a first insulating layer, a first gate layer, a second insulating layer, a second gate layer, a dielectric layer, a source and drain layer, and a flat layer.
  • the barrier layer is provided on one side surface of the substrate; the buffer layer is provided on the side surface of the barrier layer away from the substrate; the active layer is provided on the buffer layer away from the barrier layer Side surface; the first insulating layer is provided on the active layer and the buffer layer is away from the barrier layer; the first gate layer is provided on the first insulating layer away from the active Layer side surface; the second insulating layer is provided on the first gate layer and the first insulating layer on the side surface away from the active layer; the second gate layer is provided on the second The insulating layer is away from the surface of the first gate layer; the dielectric layer is disposed on the surface of the second gate layer and the second insulating layer away from the first insulating layer; the source and drain An electrode layer sequentially penetrates the dielectric layer, the first insulating layer, and the second insulating layer, and is connected to the active layer; and the flat layer is disposed on the source drain layer and the dielectric layer.
  • the layer is away from the side surface of the substrate.
  • the present invention also provides a manufacturing method of a display device.
  • the display device includes a display area and a non-display area, the display area is surrounded by the non-display area, and the non-display area includes an integrated circuit area;
  • the manufacturing method It includes the following steps in sequence: a substrate setting step; a first insulating layer preparation step; a first gate layer preparation step; a second insulating layer preparation step; and a second gate layer preparation step; in the second insulating layer preparation step
  • the thickness of the second insulating layer gradually decreases from a position close to the integrated circuit region to a direction away from the integrated circuit region.
  • the step of preparing the second insulating layer sequentially includes the following steps: a photoresist layer coating step, coating a photoresist solution on the second insulating layer to form a photoresist layer; an exposure step, using halftone light The mask exposes the photoresist layer so that the thickness of the photoresist layer gradually decreases from the position close to the integrated circuit area to the direction away from the integrated circuit area; and the etching step, taking the photoresist layer as The mask is used for etching the second insulating layer.
  • the display area is divided into N sub-display areas arranged side by side; the N sub-display areas are arranged in sequence from a direction close to the integrated circuit area to a direction away from the integrated circuit area; in the exposure step, The thickness of the photoresist layer in the (X+1)th sub-display area is smaller than the thickness of the photoresist layer in the Xth sub-display area; where N ⁇ X ⁇ 2.
  • the first insulating layer preparation step the first insulating layer is deposited on the upper surface of the substrate; in the first gate layer preparation step, the first insulating layer is deposited on the upper surface of the first insulating layer Depositing to form the first gate layer; in the second insulating layer preparation step, depositing the second insulating layer on the upper surface of the first gate layer; in the second gate layer preparation step In this step, the second gate layer is deposited on the upper surface of the second insulating layer.
  • the substrate setting step includes the following steps in sequence: a barrier layer deposition step, forming a barrier layer on the upper surface of the substrate; a buffer layer deposition step, forming a buffer layer on the upper surface of the barrier layer; In the source layer deposition step, an active layer is deposited on the upper surface of the buffer layer to form a side surface away from the barrier layer.
  • the manufacturing method of the display device further includes the following steps: a dielectric layer deposition step, depositing and forming a dielectric layer on the upper surface of the second gate layer; At least two source and drain holes are provided, which sequentially penetrate the dielectric layer, the second insulating layer and the first insulating layer; the source and drain layer deposition step is to deposit a source and drain in each source and drain hole The drain layer is connected to the active layer; the flat layer deposition step is to deposit a flat layer on the upper surface of the source drain layer and the dielectric layer.
  • the technical effect of the present invention is to provide a display device and a manufacturing method thereof.
  • the voltage gradually decreases from a position close to the integrated circuit area to a direction away from the integrated circuit area, so the input current also gradually decreases.
  • the two gate layers and the insulating layer between the two together form a storage capacitor.
  • the capacitance value of the storage capacitor changes from close to The integrated circuit area gradually increases away from the integrated circuit area, and the uneven brightness of the display device is improved by current compensation, and the product manufacturing process is simplified, the production cost is reduced, and the product's wide range of usability is improved.
  • Figure 1 is a cross-sectional view of a display device in the background art
  • FIG. 2 is a schematic diagram of the structure of a display device in an embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of another display device in an embodiment of the present invention.
  • FIG. 4 is a flowchart of a manufacturing method of a display device in an embodiment of the present invention.
  • Figure 5 is a flowchart of substrate formation in an embodiment of the present invention.
  • FIG. 6 is a cross-sectional view of a display device with a second insulating layer in an embodiment of the present invention
  • FIG. 7 is a flowchart of a second insulating layer in an embodiment of the present invention.
  • FIG. 8 is a cross-sectional view of the display device after exposure in the embodiment of the present invention.
  • FIG 9 is a cross-sectional view of the display device after the second insulating layer is etched in the embodiment of the present invention.
  • this embodiment provides a display device including a display area 1000 and a non-display area 2000.
  • the display area 1000 is surrounded by the non-display area 2000.
  • the non-display area 2000 includes an integrated circuit area 4000 (IC chip).
  • the signal is transmitted from the integrated circuit area 4000 to the display area 1000 through the signal transmission line 5000.
  • the display area 1000 is divided into N (N ⁇ 2) sub-display areas arranged side by side; the N sub-display areas are arranged in sequence from the direction close to the integrated circuit area 4000 to away from the integrated circuit area 4000, and are respectively the first sub display area 1000, The second sub-display area 200, the X-th sub-display area 300, and the N-th sub-display area 400 (N ⁇ X ⁇ 2).
  • Each sub-display area contains multiple pixel points 3000.
  • the design of the pixel points 3000 in the same sub-display area is exactly the same.
  • Each pixel point 3000 is a circuit control unit that independently controls the OLED light-emitting unit for display, and each pixel point 3000 Contains a storage capacitor, and the size of the storage capacitor corresponding to the pixel in the different sub-display areas is different.
  • the storage capacitor in this embodiment gradually increases from a position close to the integrated circuit area 4000 to a direction away from the integrated circuit area 4000, by means of current compensation This makes the device in the display area emit light more uniformly, simplifies the product manufacturing process, reduces the production cost, and improves the wide applicability of the product.
  • the display area 1000 sequentially includes a substrate 1, a barrier layer 2, a buffer layer 3, an active layer 4, a first insulating layer 5, a first gate layer 6, a second insulating layer 8, and a second gate layer. 10.
  • the substrate 1 is a flexible PI substrate.
  • a barrier layer 2, a buffer layer 3, and an active layer 4 are arranged on the substrate 1 from bottom to top.
  • the upper surface of the active layer 4 is provided with a first insulating layer 5 and a first gate layer. 6.
  • the second insulating layer 8 and the second gate layer 10, the two gate layers 6, 10 and the second insulating layer 8 between them form a storage capacitor.
  • the display area when the thickness of the second insulating layer 8 in the (X+1)th sub-display area 300 is the same as that in the X-th sub-display area 301, due to the certain resistance of the source and drain, the voltage changes from close to the integrated circuit
  • the area gradually decreases away from the integrated circuit area, so the current of the (X+1)th sub-display area 301 is smaller than the current of the Xth sub-display area 300, and the brightness of the (X+1)th sub-display area 301 is higher than that of the Xth sub-display area.
  • the brightness of the display area 300 is weak, which in turn causes the brightness of the entire display area to be uneven.
  • the storage of the (X+1)-th sub-display area 301 The capacitance value of the capacitor is greater than the capacitance value of the storage capacitor of the Xth sub-display area 300, and the real-time current of the (X+1)th sub-display area 301 is approximately equal to the real-time current of the Xth sub-display area 300 through current compensation. , Which in turn makes the brightness of the entire display area more uniform.
  • a dielectric layer 11 and a flat layer 14 are sequentially arranged above the second insulating layer 8 from bottom to top.
  • the source and drain layers 13 pass through the dielectric layer 11 and the flat layer 14 and are connected to the active layer 4.
  • a pixel electrode layer 16, a pixel defining layer 17 and a photoresist gap layer 18 are sequentially arranged above the flat layer 14 from bottom to top, and the pixel electrode layer 16 is connected to the source and drain layer 13.
  • this embodiment also provides the manufacturing method of the aforementioned display device, including steps S1 to S12.
  • the S1 substrate setting step includes the following steps S101 to S103 in sequence.
  • barrier layer deposition a layer of inorganic material is deposited on the upper surface of the flexible PI substrate 1 to form a barrier layer 2 for protecting the substrate 1 and other components.
  • S102 buffer layer deposition step a layer of inorganic material is deposited on the upper surface of the barrier layer 2 to form the buffer layer 3 for forming a buffer between the substrate and other components.
  • active layer deposition in S103 the active layer 4 is deposited on the upper surface of the buffer layer 3, and the active layer 4 is polysiliconized by the excimer laser crystallization technology, see FIG. 6.
  • the first insulating layer 5 is deposited on the upper surface of the active layer 4, see FIG. 6.
  • the first gate layer 6 is deposited and formed on the upper surface of the first insulating layer 5, and the first gate layer 6 is patterned by using a single photolithography mask method. Using the patterned first gate layer 6 as a photomask, ion implantation is performed on the active layer 4 to form a P-type semiconductor layer on the active layer 4, see FIG. 6.
  • a second insulating layer 8 is deposited on the upper surface of the first gate layer 6, and the thickness of the second insulating layer 8 at different positions is the same, see FIG. 6.
  • the step of preparing the second insulating layer in S4 includes the following steps S401 to S403 in sequence.
  • the photoresist layer coating step is to coat a photoresist solution on the second insulating layer 8 to form a photoresist layer.
  • the thickness of the photoresist layer 9 in the Xth sub-display area 300 is equal to that of the photoresist layer 9 in the (X+ 1)
  • the thickness of the photoresist layer 9 in the sub-display area 301 is the same.
  • the photoresist layer 9 is exposed to the photoresist layer 9 using a halftone mask, so that the thickness of the photoresist layer located in the Xth sub-display area 300 is greater than that of the photoresist layer located in the (X +1) The thickness of the photoresist layer in the sub-display area 301, see FIG. 8.
  • the halftone mask adjusts the transmittance of light so that the transmittance of each sub-display area gradually increases from the position close to the integrated circuit area to the direction away from the integrated circuit area. Therefore, the thickness of the photoresist layer 9 It gradually decreases from the place close to the integrated circuit area to the direction away from the integrated circuit area, see Figure 8.
  • the second insulating layer 8 is etched by dry etching using the photoresist layer 9 as a shield. At this time, the thickness of the second insulating layer 8 in the X-th sub-display area 300 is It is larger than the second insulating layer 8 located in the (X+1)th sub-display area 301, see FIG. 9.
  • the first gate layer 6 is the lower electrode plate of the capacitor
  • the second gate layer 10 is the upper electrode plate of the capacitor
  • the second insulating layer 8 collectively forms a storage capacitor.
  • the thickness of the second insulating layer 8 in the (X+1)th sub-display area 301 is smaller than that in the Xth sub-display area 300, and the capacitance value of the storage capacitor of the (X+1)th sub-display area 301 is greater than that of the Xth sub-display area.
  • the capacitance value of the storage capacitor of the sub-display area 300 is compensated so that the real-time current of the (X+1)th sub-display area 301 is approximately equal to the real-time current of the X-th sub-display area 300, thereby making the entire display area
  • the brightness is more uniform.
  • a dielectric layer 11 is deposited on the upper surface of the second gate layer. See Figure 2.
  • step S7 at least two source and drain holes (not shown) are provided in the dielectric layer 11 by a single photolithography mask method, and the source and drain holes penetrate from the dielectric layer 11 to the active Layer 4. See Figure 3.
  • the source-drain layer deposition step is to deposit a source-drain layer 13 in the source-drain hole, and pattern the source-drain layer 13 through a single photolithography mask method, and the source-drain layer 13 Connect to the active layer 4.
  • the voltage gradually decreases from near the integrated circuit area to away from the integrated circuit area, so the input current also gradually decreases. Therefore, the prior art adopts a mesh structure to design the second source and drain layer , Control the voltage drop through the parallel circuit, thereby improving the uneven brightness of the product.
  • the source and drain layer 12 is a single-layer structure.
  • the unevenness of the luminous brightness of the display device is improved by setting storage capacitors in each sub-display area, and the production of the source and drain layers can also be simplified. Process, thereby reducing production costs, and improving the wide range of product use, see Figure 3.
  • a flat layer 14 is deposited on the upper surface of the source and drain layer 13, and at least one through hole (not shown) is provided in the flat layer 14, and the through hole penetrates to the upper surface of the source and drain layer 13 , See Figure 3.
  • the pixel electrode layer deposition step is to deposit and form a pixel electrode layer 16 in the through hole.
  • the pixel electrode layer 16 covers a part of the flat layer 14.
  • the pixel electrode layer 16 is made into the pixel electrode layer 16 through a single photolithography mask method. For patterning, see Figure 3.
  • the pixel definition layer 17 is deposited on the upper surface of the pixel electrode layer 16, and the pixel definition layer 17 is patterned through a single photolithography mask or two photolithography mask methods, see figure 3.
  • a photoresist gap layer 18 is formed on the upper surface of the pixel definition layer 17, and the photoresist gap layer 18 is patterned through a single photolithography mask or a two photolithography mask method, See Figure 3.
  • an opening process is performed in the pixel definition layer, and a light-emitting layer is prepared in the opening area to form the basic structure of the display device.
  • a display device and a manufacturing method thereof are provided.
  • the voltage gradually decreases from a position close to the integrated circuit area to a direction away from the integrated circuit area, so the input current also gradually decreases, and the two gates
  • the polar layer and the insulating layer between the two together form a storage capacitor.
  • the capacitance value of the storage capacitor changes from close to the integrated circuit area to away from the integrated circuit area.
  • the direction of the circuit area is gradually increasing, and the uneven brightness of the display device is improved by the way of current compensation, and the production process of the product is simplified, the production cost is reduced, and the wide use of the product is improved.

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Abstract

一种显示装置及其制作方法，显示装置包括显示区（1000）及非显示区（2000）；显示区（1000）包括基板（1）、第一绝缘层（5）、第一栅极层（6）、第二绝缘层（8）以及第二栅极层（10）；非显示区（2000）包括集成电路区（4000）；第二绝缘层（8）的厚度从靠近集成电路区（4000）处向远离集成电路区（4000）方向逐渐递减。显示装置的制作方法包括基板（1）设置步骤（S1）、第一绝缘层（5）制备步骤（S2）、第一栅极层（6）制备步骤（S3）、第二绝缘层（8）制备步骤（S4）以及第二栅极层（10）制备步骤（S5）；第二绝缘层（8）的厚度从靠近集成电路区（4000）处向远离集成电路区（4000）方向逐渐递减。通过电流补偿的方式，改善显示装置发光亮度不均的现象。

Description

一种显示装置及其制作方法 技术领域
本发明涉及显示领域，尤其涉及一种显示装置及其制作方法。
 背景技术
有机电致发光显示装置（OLED）以其低功耗、高饱和度、快响应时间及宽视角等独特优势逐渐成为显示领域的主流技术，未来在车载、手机、平板、电脑及电视产品上具有广阔的应用空间。
         OLED显示装置主流驱动方式为电流驱动，工作电流由显示装置通过源漏极（SD：Source/Drain）进行传输，因为SD自身存在一定电阻，信号传输存在电压下降（IR Drop）现象，在显示区内，靠近驱动电路的区域内，电压及电流偏大，远离驱动电路的区域内，电压及电流偏小，因此，显示区两端的亮度有明显差异，显示装置出现亮度不均现象，影响产品的使用性能。
如图1所示，目前，解决OLED显示装置发光亮度不均的方法为双层SD结构，包括第一源漏极131以及第二源漏极132。其中，第二源漏极层132采用网状结构设计，通过并联电路控制电压下降，进而改善产品亮度不均现象。但双层SD结构设计因制作工艺复杂、成本高昂等缺点制约其普及应用。
 技术问题
本发明的目的在于，提供一种显示装置及其制作方法，以解决现有技术中存在的源漏极双层结构的制作工艺复杂、成本昂贵、显示装置发光亮度不均以及应用范围较窄的技术问题。
 技术解决方案
本发明提供一种显示装置，包括显示区及非显示区，所述显示区被所述非显示区环绕，所述显示区依次包括基板、第一绝缘层、第一栅极层、第二绝缘层以及第二栅极层；所述非显示区包括集成电路区；所述第二绝缘层的厚度从靠近所述集成电路区向远离所述集成电路区方向依次递减。
进一步地，所述显示区被分成N个并排设置的子显示区；所述N个子显示区从靠近所述集成电路区向远离所述集成电路区方向依次排列。
进一步地，位于第（X+1）子显示区的第二绝缘层的厚度小于位于第X子显示区的第二绝缘层的厚度；和/或，第（X+1）子显示区的电容大于第X子显示区的电容；其中，N≥X≥2。
进一步地，在所述显示区中，所述第一栅极层设于所述第一绝缘层远离所述基板一侧表面；所述第二绝缘层设于所述第一栅极层远离第一绝缘层一侧表面；所述第二栅极层设于所述第二绝缘层远离第一栅极层一侧表面。
进一步地，所述显示区包括屏障层、缓冲层、有源层、第一绝缘层、第一栅极层、第二绝缘层、第二栅极层、介电层、源漏极层以及平坦层；所述屏障层设于所述基板一侧表面；所述缓冲层设于所述屏障层远离所述基板一侧表面；所述有源层设于所述缓冲层远离所述屏障层一侧表面；所述第一绝缘层设于所述有源层及所述缓冲层远离所述屏障层一侧表面；所述第一栅极层设于所述第一绝缘层远离所述有源层一侧表面；所述第二绝缘层设于所述第一栅极层及所述第一绝缘层远离所述有源层一侧表面；所述第二栅极层设于所述第二绝缘层远离所述第一栅极层一侧表面；所述介电层设于所述第二栅极层及所述第二绝缘层远离所述第一绝缘层一侧表面；所述源漏极层依次贯穿所述介电层、所述第一绝缘层、所述第二绝缘层，连接至所述有源层；以及所述平坦层设于所述源漏极层及所述介电层远离所述基板一侧表面。
本发明还提供一种显示装置的制作方法，所述显示装置包括显示区及非显示区，所述显示区被所述非显示区环绕，所述非显示区包括集成电路区；所述制作方法依次包括如下步骤：基板设置步骤；第一绝缘层制备步骤；第一栅极层制备步骤；第二绝缘层制备步骤；以及第二栅极层制备步骤；在所述第二绝缘层制备步骤中，所述第二绝缘层的厚度从靠近所述集成电路区处向远离所述集成电路区方向逐渐递减。
进一步地，所述第二绝缘层制备步骤依次包括如下步骤：光阻层涂覆步骤，在所述第二绝缘层上涂覆光阻溶液，形成一光阻层；曝光步骤，利用半色调光罩对所述光阻层进行曝光处理，使得所述光阻层的厚度从靠近所述集成电路区处向远离所述集成电路区方向逐渐递减；以及刻蚀步骤，以所述光阻层为遮蔽物，对所述第二绝缘层进行刻蚀处理。
进一步地，所述显示区被分成N个并排设置的子显示区；所述N个子显示区从靠近所述集成电路区向远离所述集成电路区方向依次排列；在所述曝光步骤中，位于第（X+1）子显示区的光阻层的厚度小于位于第X子显示区的光阻层的厚度；其中，N≥X≥2。
进一步地，在所述第一绝缘层制备步骤中，在所述基板上表面沉积形成所述第一绝缘层；在所述第一栅极层制备步骤中，在所述第一绝缘层上表面沉积形成所述第一栅极层；在所述第二绝缘层制备步骤中，在所述第一栅极层上表面沉积形成所述第二绝缘层；在所述第二栅极层制备步骤中，在所述第二绝缘层上表面沉积形成所述第二栅极层。
进一步地，所述基板设置步骤，依次包括如下步骤：屏障层沉积步骤，在所述基板上表面沉积形成一屏障层；缓冲层沉积步骤，在所述屏障层上表面沉积形成一缓冲层；有源层沉积步骤，在所述缓冲层上表面沉积形成一有源层远离所述屏障层一侧面。在形成第二栅极层沉积步骤之后，所述显示装置的制作方法还包括如下步骤：介电层沉积步骤，在所述第二栅极层上表面沉积形成一介电层；挖孔步骤，设置至少两个源漏极孔，依次贯穿所述介电层、所述第二绝缘层及所述第一绝缘层；源漏极层沉积步骤，在每一源漏极孔内沉积形成一源漏极层，连接至所述有源层；平坦层沉积步骤，在所述源漏极层及所述介电层上表面沉积形成一平坦层。
 有益效果
本发明的技术效果在于，提供一种显示装置及其制作方法，在所述显示装置的显示区中，电压从靠近集成电路区处向远离集成电路区方向逐渐递减，因而输入电流也逐渐减小，本发明中两个栅极层及二者之间的绝缘层共同形成存储电容，当绝缘层的厚度从靠近集成电路区处向远离集成电路区方向逐渐递减时，存储电容的电容值从靠近集成电路区处向远离集成电路区方向逐渐递增，通过电流补偿的方式，改善显示装置发光亮度不均的现象，并简化产品制作工艺、降低生产成本，提升产品的广泛使用性。
 附图说明
图1是背景技术中显示装置的剖面图；
图2是本发明实施例中显示装置的结构示意图；
图3是本发明实施例中另一显示装置的剖面图；
图4是本发明实施例中显示装置的制作方法的流程图；
图5是本发明实施例中基板形成的流程图；
图6是本发明实施例中第二绝缘层的显示装置的剖面图；
图7是本发明实施例中第二绝缘层的流程图；
图8是本发明实施例中在曝光后的显示装置的剖面图；
图9是本发明实施例中第二绝缘层被刻蚀后的显示装置的剖面图。
图中部件标识如下：
1基板；2屏障层；3缓冲层；4有源层；5第一绝缘层；6第一栅极层；7 P型半导体层；8第二绝缘层；9光阻层；10第二栅极层；11介电层； 13源漏极层；131第一源漏极；132第二源漏极；14平坦层；16像素电极层；17像素定义层；18光阻间隙层；100第一子显示区；200第二子显示区；300第X子显示区；301第（X+1）子显示区；400第N子显示区；1000显示区；2000非显示区；3000像素点；4000 集成电路区；5000信号传输线。
 本发明的实施方式
以下参考说明书附图介绍本发明的一个优选实施例，证明本发明可以实施，这些实施例可以向本领域中的技术人员完整介绍本发明,使其技术内容更加清楚和便于理解。本发明可以通过许多不同形式的实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例。
在附图中，结构相同的部件以相同数字标号表示，各处结构或功能相似的组件以相似数字标号表示。附图所示的每一组件的尺寸和厚度是任意示出的，本发明并没有限定每个组件的尺寸和厚度。为了使图示更清晰，附图中有些地方适当夸大了部件的厚度。
本发明所提到的方向用语，例如[上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是附图中的方向，只是用来解释和说明本发明，而不是用来限定本发明的保护范围。
如图2所示，本实施例提供一种显示装置，包括显示区1000及非显示区2000，显示区1000被非显示区2000环绕，非显示区2000包括集成电路区4000（IC芯片），工作信号通过信号传输线5000从集成电路区4000向显示区1000进行传输。
显示区1000被分成N（N≥2）个并排设置的子显示区；所述N个子显示区从靠近集成电路区4000向远离集成电路区4000方向依次排列，分别为第一子显示区1000、第二子显示区200、第X子显示区300、第N子显示区400（N≥X≥2）。
每个子显示区均包含多个像素点3000，同一子显示区内像素点3000的设计完全相同，每个像素点3000为一个电路控制单元，独自控制OLED发光单元进行显示，而且每个像素点3000包含一个储存电容，不同子显示区内对应像素点的存储电容的大小不一样，本实施例中的存储电容从靠近集成电路区4000处向远离集成电路区4000方向逐渐递增，通过电流补偿的方式使得显示区装置发光更加均匀，并简化产品制作工艺、降低生产成本，提升产品的广泛应用性。
下文将以第X子显示区300、第（X+1）子显示区301为例进行详细说明。
如图3所示，显示区1000依次包括基板1、屏障层2、缓冲层3、有源层4第一绝缘层5、第一栅极层6、第二绝缘层8、第二栅极层10、介电层11、源漏极孔12、源漏极层13、平坦层14、像素电极层16、像素定义层17、光阻间隙层18。
基板1为柔性的PI基板，基板1上方从下至上依次设有屏障层2、缓冲层3及有源层4，有源层4上表面依次设有第一绝缘层5、第一栅极层6、第二绝缘层8及第二栅极层10，两个栅极层6、10及二者之间的第二绝缘层8形成存储电容。
在显示区中，当第二绝缘层8在第（X+1）子显示区300的厚度与其在第X子显示区301的厚度一致时，由于源漏极存在一定电阻，电压从靠近集成电路区处向远离集成电路区方向逐渐递减，因而第（X+1）子显示区301的电流小于第X子显示区300的电流，第（X+1）子显示区301的亮度比第X子显示区300的亮度弱，进而导致整个显示区的亮度不均匀。
当位于第X子显示区300的第二绝缘层8的厚度大于位于第（X+1）子显示区301的第二绝缘层8的厚度时，第（X+1）子显示区301的存储电容的电容值大于第X子显示区300的存储电容的电容值，通过电流补偿的方式，使得第（X+1）子显示区301的实时电流与第X子显示区300的实时电流近似相等，进而使得整个显示区的亮度更加均匀。
第二绝缘层8上方从下至上依次设有介电层11、平坦层14，源漏极层13穿过介电层11、平坦层14且连接至有源层4。
平坦层14上方从下至上依次设有像素电极层16、像素定义层17及光阻间隙层18，像素电极层16连接至源漏极层13。
如图4所示，本实施例还提供前文所述的显示装置的制作方法，包括步骤S1~S12。
如图5所示，S1基板设置步骤，依次包括如下步骤S101~S103。S101屏障层沉积步骤，在柔性PI基板1上表面沉积一层无机材料形成屏障层2，用于保护基板1等部件。S102缓冲层沉积步骤，在屏障层2上表面沉积一层无机材料形成缓冲层3，用于在基板与其他部件之间形成缓冲。S103有源层沉积步骤，在缓冲层3上表面沉积形成有源层4，利用准分子激光晶化技术使有源层4实现多晶硅化，参见图6。
S2第一绝缘层制备步骤，在有源层4上表面沉积形成第一绝缘层5，参见图6。
S3第一栅极层制备步骤，在第一绝缘层5上表面沉积形成第一栅极层6，并利用单次光刻掩模的方法，使得第一栅极层6进行图案化处理。以图案化后的第一栅极层6为光罩，对有源层4进行离子植入，在有源层4形成P型半导体层，参见图6。
S4第二绝缘层制备步骤，在第一栅极层6上表面沉积形成第二绝缘层8，第二绝缘层8在不同位置处的厚度相同，参见图6。
如图7所示，S4所述第二绝缘层制备步骤，依次包括如下步骤S401~S403。
S401光阻层涂覆步骤，在第二绝缘层8上涂覆光阻溶液，形成一光阻层，此时，位于第X子显示区300的光阻层9的厚度与位于第（X+1）子显示区301的光阻层9的厚度相同。
S402曝光步骤，在曝光强度、曝光时长一定的条件下，利用半色调光罩对光阻层9进行曝光处理，使得位于第X子显示区300的所述光阻层的厚度大于位于第（X+1）子显示区301的所述光阻层的厚度，参见图8。
本实施例中，半色调光罩通过调节光的透过率，使得各子显示区的透过率从靠近集成电路区处向远离集成电路区方向逐渐升高，因此，光阻层9的厚度从靠近集成电路区处向远离集成电路区方向逐渐递减，参见图8。
S403刻蚀步骤，以光阻层9为遮蔽物，采用干法刻蚀的方法对第二绝缘层8进行刻蚀处理，此时，位于第X子显示区300的第二绝缘层8的厚度大于位于第（X+1）子显示区301的第二绝缘层8，参见图9。
S5第二栅极层制备步骤，在第二绝缘层8的上表面沉积第二栅极层10，并对第二栅极层10通过单次光刻掩模的方法，使得第二栅极层10进行图案化处理，参见图3。
本实施例中，第一栅极层6为电容的下极板，第二栅极层10为电容的上极板；第一栅极层6、第二栅极层10以及二者之间的第二绝缘层8共同形成存储电容。第二绝缘层8在第（X+1）子显示区301内的厚度小于在第X子显示区300内的厚度，第（X+1）子显示区301的存储电容的电容值大于第X子显示区300的存储电容的电容值，通过电流补偿的方式，使得第（X+1）子显示区301的实时电流与第X子显示区300的实时电流近似相等，进而使得整个显示区的亮度更加均匀。
S6介电层沉积步骤，在第二栅极层上表面沉积形成介电层11。参见图2。
S7挖孔步骤，通过单次光刻掩模的方法在介电层11设置至少两个源漏极孔（图未示），所述源漏极孔从介电层11贯穿至所述有源层4。参见图3。
S8源漏极层沉积步骤，在所述源漏极孔内沉积形成源漏极层13，并通过单次光刻掩模的方法使得源漏极层13进行图案化处理，源漏极层13连接至所述有源层4。在所述显示装置的显示区中，电压从靠近集成电路区处向远离集成电路区方向逐渐递减，因而输入电流也逐渐减小，因此，现有技术采用网状结构设计第二源漏极层，通过并联电路控制电压下降，进而改善产品亮度不均现象。而本实施例中的源漏极层12为单层结构，本实施例通过设置各子显示区的存储电容来改善显示装置发光亮度不均的现象，还可以简化所述源漏极层的制作工艺，进而降低生产成本，提升产品使用的广泛性，参见图3。
S9平坦层沉积步骤，在源漏极层13的上表面沉积形成平坦层14，在平坦层14设置至少一个通孔（图未示），所述通孔贯穿至源漏极层13的上表面，参见图3。
S10像素电极层沉积步骤，在所述通孔内沉积形成像素电极层16，像素电极层16覆盖一部分的平坦层14，该像素电极层16通过单次光刻掩模的方法使得像素电极层16进行图案化处理，参见图3。
S11像素定义层沉积步骤，在像素电极层16上表面沉积形成像素定义层17，并通过单次光刻掩模或两次光刻掩模的方法使得像素定义层17进行图案化处理，参见图3。
S12光阻间隙层沉积步骤，在像素定义层17上表面形成光阻间隙层18，并通过单次光刻掩模或两次光刻掩模的方法使得光阻间隙层18进行图案化处理，参见图3。
在后续的步骤中，在所述像素定义层进行开孔处理，在开孔区域进行发光层制备，进而形成显示装置的基本结构。
本实施例中，提供显示装置及其制作方法，在所述显示装置的显示区中，电压从靠近集成电路区处向远离集成电路区方向逐渐递减，因而输入电流也逐渐减小，两个栅极层及二者之间的绝缘层共同形成存储电容，当绝缘层的厚度从靠近集成电路区处向远离集成电路区方向逐渐递减时，存储电容的电容值从靠近集成电路区处向远离集成电路区方向逐渐递增，通过电流补偿的方式改善显示装置发光亮度不均的现象，并简化产品制作工艺、降低生产成本，提升产品的广泛使用性。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种显示装置，包括显示区及非显示区，所述显示区被所述非显示区环绕，
    所述显示区包括基板、第一绝缘层、第一栅极层、第二绝缘层以及第二栅极层；
    所述非显示区包括集成电路区；其中，
    所述第二绝缘层的厚度从靠近所述集成电路区处向远离所述集成电路区方向逐渐递减。
  2. 如权利要求1所述的显示装置，其中，
    所述显示区被分成N个并排设置的子显示区；
    所述N个子显示区从靠近所述集成电路区向远离所述集成电路区方向依次排列。
  3. 如权利要求2所述的显示装置，其中，
    位于第（X+1）子显示区的第二绝缘层的厚度小于位于第X子显示区的第二绝缘层的厚度；和/或，
    第（X+1）子显示区的电容大于第X子显示区的电容；
    其中，N≥X≥2。
  4. 如权利要求1所述的显示装置，其中，在所述显示区中，
    所述第一栅极层设于所述第一绝缘层远离所述基板一侧表面；
    所述第二绝缘层设于所述第一栅极层远离第一绝缘层一侧表面；
    所述第二栅极层设于所述第二绝缘层远离第一栅极层一侧表面。
  5. 如权利要求1所述的显示装置，其中，所述显示区包括
    屏障层，设于所述基板一侧表面；
    缓冲层，设于所述屏障层远离所述基板一侧表面；
    有源层，设于所述缓冲层远离所述屏障层一侧表面；
    第一绝缘层，设于所述有源层及所述缓冲层远离所述屏障层一侧表面；
    第一栅极层，设于所述第一绝缘层远离所述有源层一侧表面；
    第二绝缘层，设于所述第一栅极层及所述第一绝缘层远离所述有源层一侧表面；
    第二栅极层，设于所述第二绝缘层远离所述第一栅极层一侧表面；
    介电层，设于所述第二栅极层及所述第二绝缘层远离所述第一绝缘层一侧表面；
    源漏极层，依次贯穿所述介电层、所述第一绝缘层、所述第二绝缘层，连接至所述有源层；以及
    平坦层，设于所述源漏极层及所述介电层远离所述基板一侧表面。
  6. 一种显示装置的制作方法，所述显示装置包括显示区及非显示区，所述显示区被所述非显示区环绕，所述非显示区包括集成电路区；
    其中，所述制作方法依次包括如下步骤：
    基板设置步骤；
    第一绝缘层制备步骤；
    第一栅极层制备步骤；
    第二绝缘层制备步骤；以及
    第二栅极层制备步骤；
    在所述第二绝缘层制备步骤中，
    所述第二绝缘层的厚度从靠近所述集成电路区处向远离所述集成电路区方向逐渐递减。
  7. 如权利要求6所述的显示装置的制作方法，其中，
    所述第二绝缘层制备步骤，依次包括如下步骤：
    光阻层涂覆步骤，在所述第二绝缘层上涂覆光阻溶液，形成一光阻层；
    曝光步骤，利用半色调光罩对所述光阻层进行曝光处理，使得所述光阻层的厚度从靠近所述集成电路区处向远离所述集成电路区方向逐渐递减；以及
    刻蚀步骤，以所述光阻层为遮蔽物，对所述第二绝缘层进行刻蚀处理。
  8. 如权利要求6所述的显示装置的制作方法，其中，
    所述显示区被分成N个并排设置的子显示区；
    所述N个子显示区从靠近所述集成电路区向远离所述集成电路区方向依次排列；
    在所述曝光步骤中，
    位于第（X+1）子显示区的光阻层的厚度小于位于第X子显示区的光阻层的厚度；其中，N≥X≥2。
  9. 如权利要求6所述的显示装置的制作方法，其中，
    在所述第一绝缘层制备步骤中，在所述基板上表面沉积形成所述第一绝缘层；
    在所述第一栅极层制备步骤中，在所述第一绝缘层上表面沉积形成所述第一栅极层；
    在所述第二绝缘层制备步骤中，在所述第一栅极层上表面沉积形成所述第二绝缘层；
    在所述第二栅极层制备步骤中，在所述第二绝缘层上表面沉积形成所述第二栅极层。
  10. 如权利要求6所述的显示装置的制作方法，其中，
    所述基板设置步骤，依次包括如下步骤：屏障层沉积步骤，在所述基板上表面沉积形成一屏障层；缓冲层沉积步骤，在所述屏障层上表面沉积形成一缓冲层；有源层沉积步骤，在所述缓冲层上表面沉积形成一有源层远离所述屏障层一侧面；
    在形成第二栅极层沉积步骤之后，包括如下步骤：
    介电层沉积步骤，在所述第二栅极层上表面沉积形成一介电层；
    挖孔步骤，设置至少两个源漏极孔，依次贯穿所述介电层、所述第二绝缘层及所述第一绝缘层；
    源漏极层沉积步骤，在每一源漏极孔内沉积形成一源漏极层，连接至所述有源层；以及
    平坦层沉积步骤，在所述源漏极层及所述介电层上表面沉积形成一平坦层。
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