WO2020042078A1 - 存储单元、存储器件以及存储单元的操作方法 - Google Patents

存储单元、存储器件以及存储单元的操作方法 Download PDF

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Publication number
WO2020042078A1
WO2020042078A1 PCT/CN2018/103223 CN2018103223W WO2020042078A1 WO 2020042078 A1 WO2020042078 A1 WO 2020042078A1 CN 2018103223 W CN2018103223 W CN 2018103223W WO 2020042078 A1 WO2020042078 A1 WO 2020042078A1
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Prior art keywords
voltage
gate
fuse transistor
fuse
source
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PCT/CN2018/103223
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English (en)
French (fr)
Inventor
王文轩
沈健
李运宁
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深圳市为通博科技有限责任公司
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Application filed by 深圳市为通博科技有限责任公司 filed Critical 深圳市为通博科技有限责任公司
Priority to CN201880001356.3A priority Critical patent/CN109219884A/zh
Priority to PCT/CN2018/103223 priority patent/WO2020042078A1/zh
Priority to EP18917583.9A priority patent/EP3683833A4/en
Priority to US16/683,140 priority patent/US20200083236A1/en
Publication of WO2020042078A1 publication Critical patent/WO2020042078A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a memory cell, a memory device, and a method of operating a memory cell.
  • Programmable read-only memory also known as one-time programmable memory, refers to a read-only memory that can only be written once.
  • Common one-time programmable memory structures include: fuse structure, anti-fuse structure, floating gate structure, and so on.
  • the one-time programmable memory structure of the anti-fuse structure is superior to the one-time programmable memory of the fuse structure and the floating gate structure in terms of safety and reliability.
  • the one-time programmable memory structure of the anti-fuse structure generally includes at least one control tube and an anti-fuse capacitor.
  • a control tube and a capacitor can also be integrated to form an integrated structure to form a storage unit of a one-time programmable memory.
  • a gate oxide layer of two thicknesses is generated by a dual gate process, and then a control tube and an anti-fuse capacitor are used together.
  • the one-time programmable memory of this anti-fuse structure is limited by the area of the anti-fuse structure, and the storage capacity is not high.
  • the invention provides a storage unit, a storage device, and a method of operating the storage unit to increase the storage capacity of a one-time programmable memory of an anti-fuse structure.
  • an embodiment of the present invention provides a storage unit, including:
  • An anti-fuse transistor including a gate, a source, and a drain, the anti-fuse transistor being composed of a metal-oxide semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET); and
  • a gate which is electrically connected to the gate of the anti-fuse transistor, the gate and the source form the two ends of the first anti-fuse capacitor, and the gate and the drain form the gate The two ends of the second antifuse capacitor.
  • two ends of the first anti-fuse capacitor are respectively connected to a power supply terminal of an external circuit
  • two ends of the second anti-fuse capacitor are respectively connected to a power supply terminal of an external circuit
  • the oxide dielectric layer between the gate of the anti-fuse transistor and the drain of the anti-fuse transistor is partially penetrated, so that the gate and the drain of the anti-fuse transistor become conductive Path to complete programming of the second antifuse capacitor.
  • the gate comprises a metal oxide semiconductor field effect transistor (MOSFET).
  • MOSFET metal oxide semiconductor field effect transistor
  • an embodiment of the present invention provides a method for operating a storage unit, which is applied to the storage unit in any one of the first aspects, and the method includes:
  • a first voltage difference is formed between the gate and source of the anti-fuse transistor, or Forming a second voltage difference between the gate and the drain of the fuse transistor;
  • the first voltage difference is greater than the breakdown voltage of the oxide dielectric layer between the gate and the source of the anti-fuse transistor, completing the first anti-fuse of the gate and source of the anti-fuse transistor Programming of wire capacitors;
  • the gate voltage, source voltage, drain voltage, and substrate voltage of the anti-fuse transistor are controlled in the anti-fuse transistor.
  • the first voltage difference between the gate and the source includes:
  • the gate voltage, source voltage, drain voltage, and substrate voltage of the anti-fuse transistor are controlled in the anti-fuse transistor.
  • a second voltage difference is formed between the gate and the drain, including:
  • the gate voltage, source voltage, drain voltage, and substrate voltage of the anti-fuse transistor are controlled in the anti-fuse transistor.
  • the first voltage difference between the gate and the source includes:
  • the gate voltage, source voltage, drain voltage, and substrate voltage of the anti-fuse transistor are controlled in the anti-fuse transistor.
  • a second voltage difference is formed between the gate and the drain, including:
  • an embodiment of the present invention provides a method for operating a storage unit, which is applied to the storage unit according to any one of the first aspects, and the method includes:
  • An electric signal of a source or a drain of the anti-fuse transistor is obtained; wherein the electric signal of the source of the anti-fuse transistor corresponds to a programming result of the first anti-fuse capacitor; The electrical signal of the drain corresponds to the programming result of the second antifuse capacitor.
  • obtaining the electric signal of the source of the anti-fuse transistor includes:
  • the gate voltage of the anti-fuse transistor is controlled to be a high voltage, and the source voltage of the anti-fuse transistor is zero voltage or the same low voltage as the base voltage, and no voltage is applied to the drain of the anti-fuse transistor.
  • obtaining the electrical signal of the drain of the anti-fuse transistor includes:
  • obtaining the electric signal of the source of the anti-fuse transistor includes:
  • the gate voltage of the anti-fuse transistor is controlled to be a high voltage, and the source voltage of the anti-fuse transistor is zero voltage or the same low voltage as the base voltage, and no voltage is applied to the drain of the anti-fuse transistor.
  • obtaining the electrical signal of the drain of the anti-fuse transistor includes:
  • an embodiment of the present invention provides a memory device, including: at least one memory unit according to any one of the first aspect, and a control signal input circuit; wherein the control signal input circuit is configured to generate anti-fuse A gate voltage, a source voltage, a drain voltage, and a substrate voltage of the wire transistor are used to perform the method of operating a memory cell according to any one of claims 5-9 on the memory cell.
  • a storage unit reading circuit which is configured to perform the storage unit operation method according to any one of the third aspects on the storage unit.
  • an embodiment of the present invention provides a programming device for a storage unit, including:
  • a processor configured to execute the program stored in the memory, and when the program is executed, the processor is configured to perform any of the operations in the first aspect through the operation method of the storage unit in any one of the second aspects
  • One item of the memory cell is programmed.
  • an embodiment of the present invention provides a reading device for a storage unit, including:
  • a processor configured to execute the program stored in the memory, and when the program is executed, the processor is configured to perform any of the operations in the first aspect through the operation method of the storage unit in any one of the third aspects
  • One item of the memory cell reads the programming result.
  • an embodiment of the present invention provides a computer-readable storage medium including instructions that, when run on a computer, cause the computer to execute the method of operating a storage unit according to any one of the second aspects on the first
  • the memory cell of any one of the aspects is programmed.
  • an embodiment of the present invention provides a computer-readable storage medium, including instructions that, when run on a computer, cause the computer to execute the method for operating a storage unit according to any one of the third aspects on the first
  • the memory cell according to any one of the aspects reads a programming result.
  • the memory cell, the memory, and the method of operating the memory cell provided by the present invention construct a memory cell through a gate and an anti-fuse transistor, where the anti-fuse transistor is composed of a metal oxide semiconductor field effect transistor (MOSFET); the gate The tube is electrically connected to the gate of the anti-fuse transistor; wherein the gate and source of the anti-fuse transistor respectively form two ends of a first anti-fuse capacitor, and the gate of the anti-fuse transistor and The drains constitute two ends of the second antifuse capacitor, respectively. Therefore, the area of the anti-fuse structure can be reduced, and the storage capacity of the memory cell can be improved.
  • MOSFET metal oxide semiconductor field effect transistor
  • FIG. 1 is a schematic structural diagram of two anti-fuse capacitors formed by a P-type MOSFET provided in Embodiment 1 of the present invention
  • FIG. 2 is a schematic diagram of an equivalent circuit of two anti-fuse capacitors formed by a P-type MOSFET provided in Embodiment 2 of the present invention
  • FIG. 3 is a schematic diagram of an equivalent circuit after a P-type MOSFET is provided according to a third embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a storage unit according to a fourth embodiment of the present invention.
  • FIG. 5 is a flowchart of a method for operating a storage unit according to a fifth embodiment of the present invention.
  • FIG. 6 is a flowchart of a method for operating a storage unit according to a sixth embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a memory device according to a seventh embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a memory device according to an eighth embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a programming device for a storage unit according to a ninth embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a reading device of a storage unit provided in Embodiment 10 of the present invention.
  • PROM Programmable read-only memory
  • OTP-ROM One Time Programmable ROM
  • FIG. 1 is a schematic structural diagram of a P-type MOSFET provided by the first embodiment of the present invention to form two anti-fuse capacitors. As shown in FIG. 1, it includes: an N-type well doped region 11, a P-type source doped region 12, and a P-type The drain doped region 13, a gate region 14 made of polysilicon or metal (in this embodiment, the gate material is not limited), and an oxide dielectric layer 15.
  • the N-type doping element may be an element such as phosphorus; the P-type doping element may be an element such as boron; the oxidizing medium layer 15 may be an insulating layer such as silicon oxide or a dielectric layer such as zirconia HfO2 In the examples, the material for forming the oxidation medium layer is not limited).
  • a P-type MOSFET works as an anti-fuse capacitor
  • the gate, source, drain, and substrate of the P-type MOSFET are connected to external circuits (the external circuit is applied to the gate, source, drain,
  • the voltage on the substrate is denoted as V1, V2, V3, and V4, respectively.
  • the first antifuse capacitor is denoted as TR1
  • the second antifuse capacitor is denoted as TR2.
  • control V1 to be high level.
  • control V3 and V4 to be the same high level as V1
  • control V2 to be low or 0 potential (the purpose is to A voltage difference is generated that can break through the oxide dielectric layer 15 between the gate and the source).
  • the first anti-fuse capacitor TR1 Since the breakdown voltage of the oxide dielectric layer 105 is much smaller than the breakdown voltage of the PN junction, the first anti-fuse capacitor TR1 is partially broken down after a certain period of voltage pulse action (or continuous voltage action), making the P-type MOSFET The gate and source portions form conductive paths to achieve the memory function of a cell.
  • the programming principle of the second anti-fuse capacitor TR2 of the P-type MOSFET is similar to that of the first anti-fuse capacitor TR1. Specifically, control V1 to be high level. To achieve breakdown TR2, control V2 and V4 to be the same as V1. High level, and control V3 to low potential or 0 potential (the purpose is to generate a voltage difference at the gate of the P-type MOSFET that can penetrate the oxide dielectric layer 15 between the gate and the drain).
  • FIG. 2 is a schematic diagram of an equivalent circuit of two anti-fuse capacitors formed by the P-type MOSFET provided in the second embodiment of the present invention.
  • the capacitances formed by the drain and gate of the MOSFET correspond to the first anti-fuse capacitor TR1 and the second anti-fuse capacitor TR2, respectively.
  • the capacitance C2 is a capacitance formed by the substrate and the gate of the MOSFET.
  • the diode D1 and the diode D2 respectively correspond to an equivalent PN junction diode formed by the source of the MOSFET and the substrate, and an equivalent PN junction diode formed by the drain of the MOSFET and the substrate.
  • FIG. 3 is a schematic diagram of the equivalent circuit after the P-type MOSFET provided in the third embodiment of the present invention is programmed. As shown in FIG. 3, since the capacitor C1 is broken down to form the equivalent resistance R1, the programming for the capacitor C1 is completed.
  • FIG. 4 is a schematic structural diagram of a memory cell provided in Embodiment 4 of the present invention.
  • the memory cell in this embodiment includes a gate 21 and an anti-fuse transistor 22.
  • the anti-fuse transistor is made of metal oxide.
  • the semiconductor field effect transistor MOSFET is formed; the gate 21 is electrically connected to the gate of the anti-fuse transistor; wherein the gate and the source of the anti-fuse transistor 22 constitute two ends of the first anti-fuse capacitor, respectively, and the anti-fuse The gate and drain of the transistor form two ends of the second antifuse capacitor, respectively.
  • the anti-fuse transistor may be an N-type MOSFET or a P-type MOSFET.
  • P-type MOSFET For specific principles and implementation processes of the P-type MOSFET, refer to the description in FIG. 1 to FIG. 3, and details are not described herein again.
  • the specific principle and implementation process of N-type MOSFET and P-type MOSFET are similar. The only difference is that the size of the voltage, V1, V2, V3, and V4 on the gate, source, and drain of the N-type MOSFET is similar to that of P.
  • MOSFETs There are different types of MOSFETs.
  • a voltage is applied to both ends of the first anti-fuse capacitor through the power supply terminal of the external circuit to partially penetrate the gate of the anti-fuse transistor and the anti-fuse transistor.
  • the oxidized dielectric layer between the sources causes the gate and source of the antifuse transistor to form a conductive path to complete the programming of the first antifuse capacitor.
  • the gate can be a metal oxide semiconductor field effect transistor MOSFET. It should be noted that this embodiment does not limit the specific type of the gate.
  • the gate can also select other switching devices, and its role is to complete the selection of the anti-fuse transistor. Taking the MOSFET gate as an example, a voltage is applied to the gate of the gate so that the gate is turned on. When a voltage is applied to the source / drain of the gate, the gate can be applied to the anti-fuse transistor. A voltage is applied to the gate of the anti-fuse transistor to turn on the anti-fuse transistor.
  • a voltage is applied to both ends of the second anti-fuse capacitor through the power supply terminal of the external circuit to partially penetrate the gate of the anti-fuse transistor and the anti-fuse transistor.
  • An oxide dielectric layer between the drains of the electrodes causes the gates and drains of the anti-fuse transistors to form conductive paths, completing the programming of the second anti-fuse capacitor.
  • the gate can be a metal oxide semiconductor field effect transistor MOSFET. Taking the MOSFET gate as an example, a voltage is applied to the gate of the gate so that the gate is turned on. When a voltage is applied to the source / drain of the gate, the gate can be applied to the anti-fuse transistor. A voltage is applied to the gate of the anti-fuse transistor to turn on the anti-fuse transistor.
  • the external circuit described herein may be a circuit other than the strobe 21, and for details, refer to FIG. 8 and the corresponding description.
  • a memory cell is constructed by a gate and an anti-fuse transistor.
  • the anti-fuse transistor is composed of a metal oxide semiconductor field effect transistor (MOSFET); the gate is electrically connected to the gate of the anti-fuse transistor;
  • the gate and the source of the fuse transistor constitute the two ends of the first antifuse capacitor respectively, and the gate and the drain of the antifuse transistor constitute the two ends of the second antifuse capacitor, respectively.
  • MOSFET metal oxide semiconductor field effect transistor
  • one MOSFET can directly constitute two anti-fuse capacitors, which makes the memory storage capacity on the same integrated area much larger. Promotion.
  • FIG. 5 is a flowchart of a method for operating a storage unit provided in Embodiment 5 of the present invention. As shown in FIG. 5, the method in this embodiment may include:
  • a first voltage difference is formed between the gate and the source of the anti-fuse transistor, or the anti-fuse transistor is formed.
  • a second voltage difference is formed between the gate and the drain of the transistor.
  • the operation method of the memory cell in this embodiment can be applied to the memory cell shown in FIG. 4.
  • the gate, source, drain, and substrate of the anti-fuse transistor can be connected to an external power source, respectively, and
  • the voltages applied to the gate, source, drain, and substrate of the anti-fuse transistor by an external power source are denoted as V1, V2, V3, and V4, respectively.
  • the programming of the second antifuse capacitor formed by the gate and the drain of the antifuse transistor is completed.
  • the control voltages V1, V3, and V4 are high voltages, and the control voltage V2 is a low voltage or zero voltage, so that A first voltage difference is formed between the electrode and the source.
  • V1, V2, and V4 are controlled to be a high voltage
  • V3 is controlled to be a low voltage or a zero voltage to form a second voltage difference between the gate and the source of the anti-fuse transistor.
  • V1, V3, and V4 are controlled to be a low voltage, and V2 is controlled to be a high voltage or a zero voltage, so that A first voltage difference is formed with the source.
  • V1, V2, and V4 are controlled to be a low voltage, and V3 is controlled to be a high voltage or a zero voltage to form a second voltage difference between the gate and the source of the anti-fuse transistor.
  • the specific values of the high level and the low level are not limited.
  • the high level and the low level are relative quantities, and the purpose is to form a voltage difference between the gate and the source of the anti-fuse transistor.
  • the gate and source of the anti-fuse transistor are oxidized
  • the dielectric layer is partially penetrated.
  • a conductive path will be formed between the gate and source of the anti-fuse transistor, thereby changing the gate of the anti-fuse transistor.
  • the state of the first anti-fuse capacitor formed by the electrode and the source achieves the effect of programming the first anti-fuse capacitor.
  • the specific values of the high level and the low level are not limited.
  • the high level and the low level are relative quantities, and the purpose is to form a voltage difference between the gate and the drain of the anti-fuse transistor.
  • the second voltage difference By controlling the second voltage difference to be greater than the breakdown voltage of the oxide dielectric layer between the gate and the drain of the anti-fuse transistor, and by maintaining the voltage difference for a period of time, the The oxidation medium layer was partially penetrated.
  • a first voltage difference is formed between the gate and the source, or a second voltage difference is formed between the gate and the drain of the antifuse transistor; the first voltage difference is controlled to be greater than the gate and source of the antifuse transistor
  • the breakdown voltage of the oxidized dielectric layer is used to program the first anti-fuse capacitor formed by the gate and source of the anti-fuse transistor; control the second voltage difference to be greater than the gate and drain of the anti-fuse transistor
  • the breakdown voltage between the oxidizing dielectric layers performs programming of the second antifuse capacitor formed by the gate and drain of the antifuse transistor.
  • one MOSFET can directly constitute two anti-fuse capacitors, which makes the memory storage capacity on the same integrated area much larger. Promotion.
  • any one or two of the two anti-fuse capacitors formed by the MOSFET can be programmed, and the programming method is flexible and efficient.
  • FIG. 6 is a flowchart of a method for operating a storage unit according to Embodiment 6 of the present invention. As shown in FIG. 6, the method in this embodiment may include:
  • S201 Apply a gate voltage V1 to the gate of the anti-fuse transistor through the gate, so that the anti-fuse transistor is in an on state; and apply a source voltage V2 to the source, drain, and substrate of the anti-fuse transistor, respectively. Drain voltage V3 and base voltage V4.
  • the anti-fuse transistor may be a P-type MOSFET or an N-type MOSFET, and both control V1 to a high voltage so that the anti-fuse transistor is in a conducting state.
  • An electric signal of a source or a drain of the anti-fuse transistor is obtained.
  • the electric signal of the source of the anti-fuse transistor corresponds to a programming result of the first anti-fuse capacitor.
  • the signal corresponds to the programming result of the second antifuse capacitor.
  • V1 is controlled to be a high voltage
  • V2 and V4 are zero voltage or the same low voltage
  • V3 is not applied with a voltage to obtain an anti-fuse transistor source.
  • the voltage or current signal at the pole; among them, the voltage difference between V1 and V2 is far smaller than the breakdown voltage of the oxide layer dielectric of the anti-fuse transistor.
  • the first anti-fuse capacitor and the second anti-fuse capacitor share the power supply terminal of the external circuit. Therefore, no matter whether the writing or reading process is performed in parallel. Specifically, data reading or data writing operations need to be performed on the first anti-fuse capacitor and the second anti-fuse capacitor in order.
  • a voltage V1 is applied to the gate of the anti-fuse transistor through the gate; a voltage V2, V3, and V4 are respectively applied to the source, drain, and substrate of the anti-fuse transistor; and the control voltages V1, V2, and V3 are applied.
  • V4 the electrical signal of the source or drain of the anti-fuse transistor is obtained; the electrical signal of the source of the anti-fuse transistor corresponds to the programming result of the first anti-fuse capacitor; the leakage of the anti-fuse transistor The electric signal of the pole corresponds to the programming result of the second anti-fuse capacitor.
  • one MOSFET can directly constitute two anti-fuse capacitors, which makes the memory storage capacity on the same integrated area much larger. Promotion.
  • the states in the two anti-fuse capacitors formed by the MOSFET can be flexibly read, thereby conveniently obtaining the programming result of the memory cell.
  • FIG. 7 is a schematic structural diagram of a memory device provided in Embodiment 7 of the present invention. As shown in FIG. 7, the memory device in this embodiment may include:
  • the storage unit 31 shown may be at least one storage unit as shown in FIG. 4. When the number of the storage units 31 is multiple, the storage units 31 may be arranged into a certain array of storage units.
  • the control signal input circuit 32 is used to perform a memory cell operation method as shown in FIG. 5.
  • the memory device shown in FIG. 7 may further include a memory unit reading circuit 33, and the memory unit reading circuit 33 is configured to execute the memory unit operation method shown in FIG.
  • the memory device in this embodiment can execute the methods shown in FIG. 5 and FIG. 6.
  • FIG. 5 and FIG. 6 For specific implementation processes and technical principles, refer to related descriptions in the methods shown in FIG. 5 and FIG. 6, and details are not described herein again.
  • FIG. 8 is a schematic structural diagram of a memory device according to an eighth embodiment of the present invention.
  • the memory device in this embodiment may include a two-row and four-column memory array composed of four memory cells.
  • Each memory cell includes two antifuse capacitors.
  • the gate of the first antifuse transistor is connected to the drain of the gate T1
  • the gate of the gate T1 is connected to the input terminal of the first control signal WL1
  • the base of the gate T1 is grounded
  • the gate of the gate T1 is The pole is connected to the input terminal of the third control signal SL1.
  • the source of the first anti-fuse transistor is connected to the first read terminal RL1, the drain of the first anti-fuse transistor is connected to the second read terminal RL2, and the base of the first anti-fuse transistor is connected to the G1 terminal.
  • the gate of the second antifuse transistor is connected to the drain of the gate T2.
  • the gate of the gate T2 is connected to the input terminal of the first control signal WL1.
  • the base of the gate T2 is grounded, and the gate of the gate T2 is connected.
  • the pole is connected to the input terminal of the fourth control signal SL2.
  • the source of the second antifuse transistor is connected to the third read terminal RL3, the drain of the second antifuse transistor is connected to the fourth read terminal RL4, and the base of the second antifuse transistor is connected to the G1 terminal.
  • the gate of the third antifuse transistor is connected to the drain of the gate T3, the gate of the gate T3 is connected to the input terminal of the second control signal WL2, the base of the gate T3 is grounded, and the gate of the gate T3 is The pole is connected to the input terminal of the third control signal SL1.
  • the source of the third anti-fuse transistor is connected to the first read terminal RL1, the drain of the third anti-fuse transistor is connected to the second read terminal RL2, and the base of the third anti-fuse transistor is connected to the G1 terminal.
  • the gate of the fourth anti-fuse transistor is connected to the drain of the gate T4, the gate of the gate T4 is connected to the input terminal of the second control signal WL2, the base of the gate T4 is grounded, and the gate of the gate T4 is The pole is connected to the input terminal of the fourth control signal SL2.
  • the source of the fourth anti-fuse transistor is connected to the third read terminal RL3, the drain of the fourth anti-fuse transistor is connected to the fourth read terminal RL4, and the substrate of the fourth anti-fuse transistor is connected to the G1 terminal.
  • the source of the first column selection control tube BL1 constitutes a first read end RL1
  • the source of the second column selection control tube BL2 constitutes a second read end RL2
  • the source of the third column selection control tube BL3 constitutes a third read
  • the fetch terminal RL3 and the source of the fourth column selection control tube BL4 constitute a fourth read terminal RL4.
  • the grid of the first column selection control tube BL1, the grid of the second column selection control tube BL2, the grid of the third column selection control tube BL3, and the grid of the fourth column selection control tube BL4 are connected to the first column control signals, respectively. Terminal, the second column control signal terminal, the third column control signal terminal, and the fourth column control signal terminal.
  • the substrate of BL1, the substrate of the second column selection control tube BL2, the substrate of the third column selection control tube BL3, and the substrate of the fourth column selection control tube BL4 are all grounded.
  • the first control signal WL1 is used to control the opening of the first and second gates T1 and T2.
  • the third control signal SL1 can apply a voltage to the gates of TR1 and TR2 through the first gate T1; or the third control signal SL1 passes the third
  • the gate T3 applies a voltage to the gates of TR5 and TR6.
  • the second control signal WL2 is used to control the turning on of the third strobe T3 and the fourth strobe T4.
  • the fourth control signal SL2 can apply a voltage to the gates of TR3 and TR4 through the second gate T2; or the fourth control signal SL2 passes the first
  • the quad gate T4 applies a voltage to the gates of TR7 and TR8.
  • the substrate control signal G1 is used to supply a voltage to the substrate of the antifuse transistor.
  • BL1, BL2, BL3, and BL4 are the column selection control tubes of the array structure (MOS transistors can be used), and RL1, RL2, RL3, and RL4 are the reading ends of the columns.
  • the storage process of the anti-fuse capacitor TR1 is taken as an example for description.
  • the operation methods of other anti-fuse capacitors are similar and will not be described again.
  • the oxide dielectric layers of all antifuse transistors remain intact and without breakdown.
  • programming first, a voltage is applied to the first gate T1 through the first control signal WL1 and the third control signal SL1, so that the first gate T1 is turned on.
  • the third control signal SL1 provides a high voltage, which is used as an anti-fuse Programming voltage of the capacitor TR1; then, the control tube BL1 is turned on to provide a current path for programming the anti-fuse capacitor TR1, and at the same time, the substrate control signal G1 is the same or similar voltage as the third control signal SL1, thereby improving programming rate. Maintaining this voltage state for a certain period of time causes the oxide dielectric layer of the anti-fuse capacitor TR1 to be broken down, thereby programming the anti-fuse capacitor TR1.
  • the reading process of the anti-fuse capacitor TR1 is taken as an example for description.
  • the operation methods of other anti-fuse capacitors are similar and will not be described again.
  • a voltage is applied to the first gate T1 through the first control signal WL1 and the third control signal SL1, so that the first gate T1 is turned on.
  • the first strobe T1 is an NMOS device
  • the voltage of the first control signal WL1 may be the same or different from that during programming.
  • the purpose is to provide a certain positive voltage to make the first strobe T1 conductive; at the same time, the third control signal SL1 is a positive voltage that is less than the programming voltage.
  • This positive voltage is to read the breakdown or non-breakdown status of the anti-fuse capacitor TR1, so it is much smaller than the breakdown voltage so that it will not affect the status of TR1.
  • the G1 terminal is grounded, and then the control tube BL1 is turned on to provide a current path for programming the anti-fuse capacitor TR1, and the state of the anti-fuse capacitor TR1 is read at the read terminal RL1. (If the anti-fuse capacitor TR1 has been programmed, a high level can be read at RL1, and if the anti-fuse capacitor TR1 has not been programmed, a low level can be read at RL1).
  • FIG. 9 is a schematic structural diagram of a programming device of a storage unit according to a ninth embodiment of the present invention.
  • the programming device 40 of the storage unit in this embodiment may include: a processor 41 and a memory 42;
  • a memory 42 for storing a program
  • the processor 41 is configured to execute a program stored in the memory 42.
  • the processor 41 is configured to program the storage unit of FIG. 4 by using the operation method of the storage unit of FIG. 5.
  • the memory 42 may be independent or integrated with the processor 41.
  • the programming device 40 of the memory unit may further include a bus 43 for connecting the memory 42 and the processor 41.
  • FIG. 10 is a schematic structural diagram of a reading device of a storage unit provided in Embodiment 10 of the present invention.
  • the reading device 50 of the storage unit in this embodiment may include: a processor 51 and a memory 52;
  • the processor 51 is configured to execute a program stored in the memory 52.
  • the processor 51 is configured to read a programming result of the storage unit in FIG. 4 through an operation method of the storage unit in FIG.
  • the memory 52 may be independent or integrated with the processor 51.
  • the reading device 50 of the storage unit may further include a bus 53 for connecting the memory 52 and the processor 51.
  • An embodiment of the present invention further provides a computer-readable storage medium including instructions that, when run on a computer, cause the computer to execute the operation method of the storage unit of FIG. 5 to program the storage unit of FIG. 4.
  • An embodiment of the present invention further provides a computer-readable storage medium including instructions that, when run on a computer, cause the computer storage unit operating method of FIG. 6 to read a programming result of the storage unit of FIG. 4.
  • the computer-readable medium includes a computer storage medium and a communication medium, and the communication medium includes any medium that facilitates transfer of a computer program from one place to another.
  • a storage media may be any available media that can be accessed by a general purpose or special purpose computer.
  • An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.
  • the storage medium may also be an integral part of the processor.
  • the processor and the storage medium may reside in an application-specific integrated circuit (ASIC).
  • ASIC application-specific integrated circuit
  • the application specific integrated circuit may be located in a user equipment.
  • the processor and the storage medium may also exist as discrete components in a communication device.

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Abstract

本发明提供一种存储单元、存储器件及存储单元的操作方法，该存储单元，包括：反熔丝晶体管，其包括栅极、源极和漏极，所述反熔丝晶体管由金属氧化物半导体场效应晶体管构成；以及选通管，所述选通管与所述反熔丝晶体管的栅极电连接，所述栅极与源极分别构成第一反熔丝电容的两端，所述栅极与漏极分别构成第二反熔丝电容的两端。从而可以减小反熔丝结构的面积，提高存储单元的存储容量。

Description

存储单元、存储器件以及存储单元的操作方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种存储单元、存储器件以及存储单元的操作方法。
背景技术
可编程只读存储器又称一次可编程存储器，是指只允许写入一次的只读存储器，常用的一次可编程存储器结构包括：熔丝结构、反熔丝结构、浮栅结构等等。而反熔丝结构的一次可编程存储器结构在安全性和可靠性上要优于熔丝结构和浮栅结构的一次可编程存储器。
目前，反熔丝结构的一次可编程存储器结构一般包括：至少一个控制管和一个反熔丝电容。在集成电路中，还可以将一个控制管与一个电容集成在一起，形成一体结构，以构成一次可编程存储器的一个存储单元。
但是，现有的反熔丝结构的一次可编程存储器，在原理上仍然是要通过双栅工艺(dual gate)产生两种厚度的栅氧化层，然后由一个控制管与一个反熔丝电容共同组成一个存储单元。这种反熔丝结构的一次可编程存储器受反熔丝结构面积的限制，存储容量不高。
发明内容
本发明提供一种存储单元、存储器件以及存储单元的操作方法，以提高反熔丝结构的一次可编程存储器的存储容量。
第一方面，本发明实施例提供一种存储单元，包括：
反熔丝晶体管，其包括栅极、源极和漏极，所述反熔丝晶体管由金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)构成；以及
选通管，所述选通管与所述反熔丝晶体管的栅极电连接，所述栅极与源极分别构成第一反熔丝电容的两端，所述栅极与漏极分别构成第二反熔 丝电容的两端。
可选地，所述第一反熔丝电容的两端分别与外部电路的电源端相连；
通过所述外部电路的电源端向所述第一反熔丝电容的两端施加电压，以局部击穿所述反熔丝晶体管的栅极与所述反熔丝晶体管的源极之间的氧化介质层，使得所述反熔丝晶体管的栅极和源极形成导电通路，完成对所述第一反熔丝电容的编程。
可选地，所述第二反熔丝电容的两端分别与外部电路的电源端相连；
在外部电压作用下，局部击穿所述反熔丝晶体管的栅极与所述反熔丝晶体管的漏极之间的氧化介质层，使得所述反熔丝晶体管的栅极和漏极形成导电通路，完成对所述第二反熔丝电容的编程。
可选地，所述选通管包括：金属氧化物半导体场效应晶体管MOSFET。
第二方面，本发明实施例提供一种存储单元的操作方法，应用于第一方面中任一项所述的存储单元，所述方法包括：
通过控制反熔丝晶体管的栅极电压、源极电压、漏极电压、基底电压的大小，在所述反熔丝晶体管的栅极与源极之间形成第一电压差，或者在所述反熔丝晶体管的栅极与漏极之间形成第二电压差；
若所述第一电压差大于所述反熔丝晶体管的栅极与源极之间氧化介质层的击穿电压，完成对所述反熔丝晶体管的栅极与源极构成的第一反熔丝电容的编程操作；
若所述第二电压差大于所述反熔丝晶体管的栅极与漏极之间氧化介质层的击穿电压，完成对所述反熔丝晶体管的栅极与漏极构成的第二反熔丝电容的编程。
可选地，当所述反熔丝晶体管为P型MOSFET时，所述通过控制反熔丝晶体管的栅极电压、源极电压、漏极电压、基底电压的大小，在所述反熔丝晶体管的栅极与源极之间形成第一电压差，包括：
控制反熔丝晶体管的栅极电压、漏极电压、基底电压为高电压，控制反熔丝晶体管的源极电压为低电压或者零电压，以在所述反熔丝晶体管的栅极与源极之间形成第一电压差。
可选地，当所述反熔丝晶体管为P型MOSFET时，所述通过控制反熔丝晶体管的栅极电压、源极电压、漏极电压、基底电压的大小，在所述反熔丝晶体管的栅极与漏极之间形成第二电压差，包括：
控制反熔丝晶体管的栅极电压、源极电压、基底电压为高电压，控制反熔丝晶体管的漏极电压为低电压或者零电压，以在所述反熔丝晶体管的栅极与源极之间形成第二电压差。
可选地，当所述反熔丝晶体管为N型MOSFET时，所述通过控制反熔丝晶体管的栅极电压、源极电压、漏极电压、基底电压的大小，在所述反熔丝晶体管的栅极与源极之间形成第一电压差，包括：
控制反熔丝晶体管的栅极电压、漏极电压、基底电压为低电压，控制反熔丝晶体管的源极电压为高电压或者零电压，以在所述反熔丝晶体管的栅极与源极之间形成第一电压差。
可选地，当所述反熔丝晶体管为N型MOSFET时，所述通过控制反熔丝晶体管的栅极电压、源极电压、漏极电压、基底电压的大小，在所述反熔丝晶体管的栅极与漏极之间形成第二电压差，包括：
控制反熔丝晶体管的栅极电压、源极电压、基底电压为低电压，控制反熔丝晶体管的漏极电压为高电压或者零电压，以在所述反熔丝晶体管的栅极与源极之间形成第二电压差。
第三方面，本发明实施例提供一种存储单元的操作方法，应用于第一方面中任一项所述的存储单元，所述方法包括：
通过选通管对反熔丝晶体管的栅极施加栅极电压，使得所述反熔丝晶体管处于导通状态；对所述反熔丝晶体管的源极、漏极、基底分别施加源极电压、漏极电压、基底电压；
获取到所述反熔丝晶体管的源极或者漏极的电信号；其中，所述反熔丝晶体管的源极的电信号对应第一反熔丝电容的编程结果；所述反熔丝晶体管的漏极的电信号对应第二反熔丝电容的编程结果。
可选地，当所述反熔丝晶体管为P型MOSFET时，获取到所述反熔丝晶体管的源极的电信号，包括：
控制反熔丝晶体管的栅极电压为高电压，所述反熔丝晶体管的源极电压与基底电压为零电压或相同的低电压，所述反熔丝晶体管的漏极不施加电压，获取所述反熔丝晶体管源极处的电压或电流信号；其中，所述反熔丝晶体管的栅极与源极之间的电压差远远小于所述反熔丝晶体管的氧化层介质击穿电压；
当所述反熔丝晶体管为P型MOSFET时，获取到所述反熔丝晶体管的 漏极的电信号，包括：
控制反熔丝晶体管的栅极电压为高电压，所述反熔丝晶体管的漏极电压与基底电压为零电压或相同低电压，所述反熔丝晶体管的源极不施加电压，获取所述反熔丝晶体管漏极处的电压或电流信号；其中，所述反熔丝晶体管的栅极与漏极之间的电压差远远小于所述反熔丝晶体管的氧化层介质击穿电压。
可选地，当所述反熔丝晶体管为N型MOSFET时，获取到所述反熔丝晶体管的源极的电信号，包括：
控制反熔丝晶体管的栅极电压为高电压，所述反熔丝晶体管的源极电压与基底电压为零电压或相同的低电压，所述反熔丝晶体管的漏极不施加电压，获取所述反熔丝晶体管源极处的电压或电流信号；获取所述反熔丝晶体管源极处的电压或电流信号；其中，所述反熔丝晶体管的栅极与源极之间的电压差远远小于所述反熔丝晶体管的氧化层介质击穿电压；
当所述反熔丝晶体管为N型MOSFET时，获取到所述反熔丝晶体管的漏极的电信号，包括：
控制反熔丝晶体管的栅极电压为高电压，所述反熔丝晶体管的漏极电压与基底电压为零电压或相同低电压，所述反熔丝晶体管的源极不施加电压，获取所述反熔丝晶体管漏极处的电压或电流信号；其中，所述反熔丝晶体管的栅极与漏极之间的电压差远远小于所述反熔丝晶体管的氧化层介质击穿电压。
第四方面，本发明实施例提供一种存储器件，包括：至少一个如第一方面中任一项所述的存储单元、控制信号输入电路；其中，所述控制信号输入电路用于生成反熔丝晶体管的栅极电压、源极电压、漏极电压、基底电压，以对所述存储单元执行如权利要求5-9中任一项所述的存储单元的操作方法。
可选地，还包括：存储单元读取电路，所述存储单元读取电路用于对所述存储单元执行如第三方面中任一项所述的存储单元操作方法。
第五方面，本发明实施例提供一种存储单元的编程设备，包括：
存储器，用于存储程序；
处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于通过第二方面中任一项所述的存储单元的操作方法对第一 方面中任一项所述存储单元进行编程。
第六方面，本发明实施例提供一种存储单元的读取设备，包括：
存储器，用于存储程序；
处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于通过第三方面中任一项所述的存储单元的操作方法对第一方面中任一项所述存储单元进行编程结果读取。
第七方面，本发明实施例提供一种计算机可读存储介质，包括：指令，当其在计算机上运行时，使得计算机执行第二方面中任一项所述的存储单元的操作方法对第一方面中任一项所述存储单元进行编程。
第八方面，本发明实施例提供一种计算机可读存储介质，包括：指令，当其在计算机上运行时，使得计算机执行第三方面中任一项所述的存储单元的操作方法对第一方面中任一项所述存储单元进行编程结果读取。
本发明提供的存储单元、存储器以及存储单元的操作方法，通过选通管和反熔丝晶体管来构建存储单元，所述反熔丝晶体管由金属氧化物半导体场效应晶体管MOSFET构成；所述选通管与所述反熔丝晶体管的栅极电连接；其中，所述反熔丝晶体管的栅极与源极分别构成第一反熔丝电容的两端，所述反熔丝晶体管的栅极与漏极分别构成第二反熔丝电容的两端。从而可以减小反熔丝结构的面积，提高存储单元的存储容量。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例一提供的P型MOSFET构成两个反熔丝电容的结构示意图；
图2为本发明实施例二提供的P型MOSFET构成两个反熔丝电容的等效电路示意图；
图3为本发明实施例三提供的P型MOSFET被编程后的等效电路示意图；
图4为本发明实施例四提供的存储单元的结构示意图；
图5为本发明实施例五提供的存储单元的操作方法的流程图；
图6为本发明实施例六提供的存储单元的操作方法的流程图；
图7为本发明实施例七提供的存储器件的结构示意图；
图8为本发明实施例八提供的存储器件的结构示意图；
图9为本发明实施例九提供的存储单元的编程设备的结构示意图；
图10为本发明实施例十提供的存储单元的读取设备的结构示意图。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本发明的实施例例如能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
下面以具体地实施例对本发明的技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
以下，对本申请中的部分用语进行解释说明，以便于本领域技术人员 理解。
1)可编程只读存储器(Programmable read-only memory，PROM)只允许写入一次，所以也被称为"一次可编程只读存储器"(One Time Programmable ROM，OTP-ROM)。PROM在出厂时，存储的内容全为1，用户可以根据需要将其中的某些单元写入数据0(部分的PROM在出厂时数据全为0，则用户可以将其中的部分单元写入1)，以实现对其编程的目的。
下面以具体地实施例对本发明的技术方案以及本申请的技术方案如何解决上述技术问题进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例中不再赘述。下面将结合附图，对本发明的实施例进行描述。
图1为本发明实施例一提供的P型MOSFET构成两个反熔丝电容的结构示意图，如图1所示，包括：N型阱掺杂区域11、P型源掺杂区域12、P型漏掺杂区域13、多晶硅或金属等制作的栅极区域14(本实施例中，对栅极的制作材料不予限定)、氧化介质层15。其中，N型掺杂元素可以为磷等元素；P型掺杂元素可以为硼等元素；氧化介质层15可以为二氧化硅等氧化层绝缘介质，也可为氧化锆HfO2等介质层(本实施例中，对氧化介质层的制作材料不予限定)。
当P型MOSFET作为反熔丝电容工作时，P型MOSFET的栅极、源极、漏极、基底分别与外部电路连接(将外部电路施加在P型MOSFET的栅极、源极、漏极、基底上的电压分别记为V1、V2、V3、V4)，将第一反熔丝电容记为TR1，第二反熔丝电容记为TR2。具体地，控制V1为高电平，若要实现击穿TR1，则控制V3、V4为与V1相同的高电平，同时控制V2为低电位或0电位(目的是为了在P型MOSFET栅极产生可以击穿栅极和源极之间的氧化介质层15的电压差)。由于氧化介质层105的击穿电压远远小于PN结击穿电压，在经过一定时间的电压脉冲作用(或者持续电压作用)后，第一反熔丝电容TR1局部被击穿，使得P型MOSFET的栅极和源极部分形成导电通路，从而实现一个单元的存储功能。P型MOSFET的第二反熔丝电容TR2的编程原理与第一反熔丝电容TR1类似，具体地，控制V1为高电平，若要实现击穿TR2，则控制V2、V4为与V1相同的高电平，同时控制V3为低电位或0电位(目的是为了在P型MOSFET栅极产生可以击穿栅极和漏极之间的氧化介质层15的电压差)。
图2为本发明实施例二提供的P型MOSFET构成两个反熔丝电容的等效电路示意图，如图2所示，电容C1与电容C3分别对应MOSFET源极与栅极所形成的电容、MOSFET漏极与栅极所形成的电容，分别相当于第一反熔丝电容TR1和第二反熔丝电容TR2。电容C2为MOSFET的衬底与栅极形成的电容。二极管D1与二极管D2分别对应MOSFET的源极与衬底形成的等效PN结二极管、MOSFET的漏极与衬底形成的等效PN结二极管。
具体地，若对电容C1进行编程，则需要施加相同的高电平V1、V3、V4(以保证电容C2、电容C3不被击穿)，同时施加低电平或零电平V2。在PN结反向击穿电压远远大于栅氧化层击穿电压的前提下，经过一段时间的电压的作用下，电容C1被击穿，同时二极管D1与二极管D2保持完整、未被击穿。此时，等效电路变为图3所示电路，图3为本发明实施例三提供的P型MOSFET被编程后的等效电路示意图。如图3所示，由于电容C1被击穿，从而形成等效电阻R1，针对电容C1的编程就完成了。
图4为本发明实施例四提供的存储单元的结构示意图，如图4所示，本实施例中的存储单元包括：选通管21、反熔丝晶体管22，反熔丝晶体管由金属氧化物半导体场效应晶体管MOSFET构成；选通管21与反熔丝晶体管的栅极电连接；其中，反熔丝晶体管22的栅极与源极分别构成第一反熔丝电容的两端，反熔丝晶体管的栅极与漏极分别构成第二反熔丝电容的两端。
本实施例中，反熔丝晶体管可以是N型MOSFET，也可以是P型MOSFET，P型MOSFET的具体原理和实现过程参见图1～图3中的描述内容，此处不再赘述。N型MOSFET与P型MOSFET的具体原理和实现过程类似，唯一区别之处在于在N型MOSFET的栅极、源极、漏极、基底上的电压V1、V2、V3、V4的大小设置与P型MOSFET存在不同。
在一种可选的实施方式中，通过所述外部电路的电源端向所述第一反熔丝电容的两端施加电压，以局部击穿反熔丝晶体管的栅极与反熔丝晶体管的源极之间的氧化介质层，使得反熔丝晶体管的栅极和源极形成导电通路，完成对第一反熔丝电容的编程。可选地，选通管可以是金属氧化物半导体场效应晶体管MOSFET。需要说明的是本实施例不限定选通管的具体类型，选通管也可以选择其他开关器件，其作用是完成对反熔丝晶体管的选择。以MOSFET的选通管为例，在选通管的栅极施加电压，使得选通管 处于导通状态，当选通管的源极/漏极施加电压时，选通管可以向反熔丝晶体管的栅极施加电压，以使得反熔丝晶体管处于导通状态。
在另一种可选的实施方式中，通过所述外部电路的电源端向所述第二反熔丝电容的两端施加电压，以局部击穿反熔丝晶体管的栅极与反熔丝晶体管的漏极之间的氧化介质层，使得反熔丝晶体管的栅极和漏极形成导电通路，完成对第二反熔丝电容的编程。可选地，选通管可以是金属氧化物半导体场效应晶体管MOSFET。以MOSFET的选通管为例，在选通管的栅极施加电压，使得选通管处于导通状态，当选通管的源极/漏极施加电压时，选通管可以向反熔丝晶体管的栅极施加电压，以使得反熔丝晶体管处于导通状态。这里所述的外部电路，可以是除选通管21以外的电路，具体可以参看图8以及对应的描述。
本实施例，通过选通管和反熔丝晶体管来构建存储单元，反熔丝晶体管由金属氧化物半导体场效应晶体管MOSFET构成；选通管与反熔丝晶体管的栅极电连接；其中，反熔丝晶体管的栅极与源极分别构成第一反熔丝电容的两端，反熔丝晶体管的栅极与漏极分别构成第二反熔丝电容的两端。相较于现有的一个选通管加上一个反熔丝电容的存储单元结构，本实施例中一个MOSFET就可以直接构成两个反熔丝电容，使得同样的集成面积上存储器的存储容量大大提升。
图5为本发明实施例五提供的存储单元的操作方法的流程图，如图5所示，本实施例中的方法可以包括：
S101、通过控制反熔丝晶体管的栅极电压、源极电压、漏极电压、基底电压的大小，在反熔丝晶体管的栅极与源极之间形成第一电压差，或者在反熔丝晶体管的栅极与漏极之间形成第二电压差。
本实施例中的存储单元的操作方法可以应用于图4所示的存储单元中，参见图4，可以将反熔丝晶体管的栅极、源极、漏极、基底分别连接外部电源，并将外部电源对反熔丝晶体管的栅极、源极、漏极、基底施加的电压分别记为V1、V2、V3、V4。
S102、若第一电压差大于反熔丝晶体管的栅极与源极之间氧化介质层的击穿电压，完成对反熔丝晶体管的栅极与源极构成的第一反熔丝电容的编程；
若第二电压差大于反熔丝晶体管的栅极与漏极之间氧化介质层的击穿电 压，完成对反熔丝晶体管的栅极与漏极构成的第二反熔丝电容的编程。
在一种可选的实施方式中，当反熔丝晶体管为P型MOSFET时，控制电压V1、V3、V4为高电压，控制电压V2为低电压或者零电压，以在反熔丝晶体管的栅极与源极之间形成第一电压差。或者，控制V1、V2、V4为高电压，控制电压V3为低电压或者零电压，以在反熔丝晶体管的栅极与源极之间形成第二电压差。
在另一种可选的实施方式中，当反熔丝晶体管为N型MOSFET时，控制V1、V3、V4为低电压，控制V2为高电压或者零电压，以在反熔丝晶体管的栅极与源极之间形成第一电压差。或者，控制V1、V2、V4为低电压，控制V3为高电压或者零电压，以在反熔丝晶体管的栅极与源极之间形成第二电压差。
本实施例中，不限定高电平和低电平的具体数值，高电平和低电平是一个相对的量，其目的是在反熔丝晶体管的栅极与源极之间形成电压差。通过控制第一电压差大于反熔丝晶体管的栅极与源极之间氧化介质层的击穿电压，并通过维持一段时长的电压差，使得反熔丝晶体管的栅极与源极之间氧化介质层被局部击穿。当反熔丝晶体管的栅极与源极之间氧化介质层被局部击穿之后，在反熔丝晶体管的栅极与源极之间将会形成导电通路，从而改变了反熔丝晶体管的栅极与源极构成的第一反熔丝电容的状态，达到对第一反熔丝电容编程的效果。
本实施例中，不限定高电平和低电平的具体数值，高电平和低电平是一个相对的量，其目的是在反熔丝晶体管的栅极与漏极之间形成电压差。通过控制第二电压差大于反熔丝晶体管的栅极与漏极之间氧化介质层的击穿电压，并通过维持一段时长的电压差，使得反熔丝晶体管的栅极与漏极之间的氧化介质层被局部击穿。当反熔丝晶体管的栅极与漏极之间的氧化介质层被局部击穿之后，在反熔丝晶体管的栅极与漏极之间将会形成导电通路，从而改变了反熔丝晶体管的栅极与漏极构成的第二反熔丝电容的状态，达到对第二反熔丝电容编程的效果。
本实施例，通过对反熔丝晶体管的栅极、源极、漏极、基底分别施加电压V1、V2、V3、V4；通过控制电压V1、V2、V3、V4的大小，在反熔丝晶体管的栅极与源极之间形成第一电压差，或者在反熔丝晶体管的栅极与漏极之间形成第二电压差；控制第一电压差大于反熔丝晶体管的栅极与 源极之间氧化介质层的击穿电压，执行对反熔丝晶体管的栅极与源极构成的第一反熔丝电容的编程操作；控制第二电压差大于反熔丝晶体管的栅极与漏极之间氧化介质层的击穿电压，执行对反熔丝晶体管的栅极与漏极构成的第二反熔丝电容的编程。相较于现有的一个选通管加上一个反熔丝电容的存储单元结构，本实施例中一个MOSFET就可以直接构成两个反熔丝电容，使得同样的集成面积上存储器的存储容量大大提升。通过本实施例中的方法可以对MOSFET构成的两个反熔丝电容中的任一个或者任两个进行编程操作，编程方式灵活，效率高。
图6为本发明实施例六提供的存储单元的操作方法的流程图，如图6所示，本实施例中的方法可以包括：
S201、通过选通管对反熔丝晶体管的栅极施加栅极电压V1，使得反熔丝晶体管处于导通状态；对反熔丝晶体管的源极、漏极、基底分别施加源极电压V2、漏极电压V3、基底电压V4。
本实施例中，反熔丝晶体管可以为P型MOSFET或者N型MOSFET，均控制V1为高电压，以使得反熔丝晶体管处于导通状态。
S202、获取到反熔丝晶体管的源极或者漏极的电信号；其中，反熔丝晶体管的源极的电信号对应第一反熔丝电容的编程结果；反熔丝晶体管的漏极的电信号对应第二反熔丝电容的编程结果。
在一种可选的实施方式中，当反熔丝晶体管为P型MOSFET时，控制V1为高电压，V2与V4为零电压或相同的低电压，V3不施加电压，获取反熔丝晶体管源极处的电压或电流信号；其中，V1与V2之间的电压差远远小于反熔丝晶体管的氧化层介质击穿电压。或者，控制V1为高电压，V3与V4为零电压或相同低电压，V2不施加电压，获取反熔丝晶体管漏极处的电压或电流信号；其中，V1与V3的之间的电压差远远小于反熔丝晶体管的氧化层介质击穿电压。需要说明的是，第一反熔丝电容、第二反熔丝电容共用外部电路的电源端，因此，无论是写入还是读取过程，均不能并行执行。具体地，需要依次对第一反熔丝电容、第二反熔丝电容进行数据的读取，或者数据的写入操作。
在另一种可选的实施方式中，当反熔丝晶体管为N型MOSFET时，控制V1为高电压，V2与V4为零电压或相同的低电压，V3不施加电压，获取反熔丝晶体管源极处的电压或电流信号；获取反熔丝晶体管源极处的电压或电 流信号；其中，V1与V2之间的电压差远远小于反熔丝晶体管的氧化层介质击穿电压。或者，控制V1为高电压，V3与V4为零电压或相同低电压，V2不施加电压，获取反熔丝晶体管漏极处的电压或电流信号；其中，V1与V3的之间的电压差远远小于反熔丝晶体管的氧化层介质击穿电压。
本实施例，通过选通管对反熔丝晶体管的栅极施加电压V1；对反熔丝晶体管的源极、漏极、基底分别施加电压V2、V3、V4；通过控制电压V1、V2、V3、V4的大小，获取到反熔丝晶体管的源极或者漏极的电信号；其中，反熔丝晶体管的源极的电信号对应第一反熔丝电容的编程结果；反熔丝晶体管的漏极的电信号对应第二反熔丝电容的编程结果。相较于现有的一个选通管加上一个反熔丝电容的存储单元结构，本实施例中一个MOSFET就可以直接构成两个反熔丝电容，使得同样的集成面积上存储器的存储容量大大提升。通过本实施例中的方法可以对MOSFET构成的两个反熔丝电容中的状态进行灵活读取，从而方便地获取到存储单元的编程结果。
图7为本发明实施例七提供的存储器件的结构示意图，如图7所示，本实施例中的存储器件可以包括：
存储单元31、控制信号输入电路32；
其中，所示存储单元31可以是至少一个如图4所示的存储单元，当存储单元31的数量为多个时，存储单元31可以设置成一定排布规律的存储单元阵列。控制信号输入电路32用于执行如图5所示的存储单元操作方法。
可选地，图7所示的存储器件还可以包括：存储单元读取电路33，存储单元读取电路33用于执行如图6所示的存储单元操作方法。
本实施例的存储器件可以执行图5、图6所示的方法，其具体实现过程和技术原理参见图5、图6所示方法中的相关描述，此处不再赘述。
具体地，图8为本发明实施例八提供的存储器件的结构示意图，如图8所示，本实施例中的存储器件可以包括：四个存储单元所构成的2行4列存储阵列。其中每个存储单元包括两个反熔丝电容。第一反熔丝晶体管的栅极与选通管T1的漏极连接，选通管T1的栅极连接第一控制信号WL1的输入端，选通管T1的基底接地，选通管T1的栅极连接第三控制信号SL1的输入端。第一反熔丝晶体管的源极连接第一读取端RL1、第一反熔丝晶体管的漏极连接第二读取端RL2，第一反熔丝晶体管的基底连接G1端。第二反熔丝晶体管 的栅极与选通管T2的漏极连接，选通管T2的栅极连接第一控制信号WL1的输入端，选通管T2的基底接地，选通管T2的栅极连接第四控制信号SL2的输入端。第二反熔丝晶体管的源极连接第三读取端RL3、第二反熔丝晶体管的漏极连接第四读取端RL4，第二反熔丝晶体管的基底连接G1端。第三反熔丝晶体管的栅极与选通管T3的漏极连接，选通管T3的栅极连接第二控制信号WL2的输入端，选通管T3的基底接地，选通管T3的栅极连接第三控制信号SL1的输入端。第三反熔丝晶体管的源极连接第一读取端RL1、第三反熔丝晶体管的漏极连接第二读取端RL2，第三反熔丝晶体管的基底连接G1端。第四反熔丝晶体管的栅极与选通管T4的漏极连接，选通管T4的栅极连接第二控制信号WL2的输入端，选通管T4的基底接地，选通管T4的栅极连接第四控制信号SL2的输入端。第四反熔丝晶体管的源极连接第三读取端RL3、第四反熔丝晶体管的漏极连接第四读取端RL4，第四反熔丝晶体管的基底连接G1端。第一列选择控制管BL1的源极构成第一读取端RL1、第二列选择控制管BL2的源极构成第二读取端RL2、第三列选择控制管BL3的源极构成第三读取端RL3、第四列选择控制管BL4的源极构成第四读取端RL4。第一列选择控制管BL1的栅极、第二列选择控制管BL2的栅极、第三列选择控制管BL3的栅极、第四列选择控制管BL4的栅极分别连接第一列控制信号端、第二列控制信号端、第三列控制信号端、第四列控制信号端。第一列选择控制管BL1的漏极、第二列选择控制管BL2的漏极、第三列选择控制管BL3的漏极、第四列选择控制管BL4的漏极、第一列选择控制管BL1的基底、第二列选择控制管BL2的基底、第三列选择控制管BL3的基底、第四列选择控制管BL4的基底均接地。
如图8所示，第一控制信号WL1用来控制第一选通管T1与第二选通管T2的开启。当第一选通管T1与第二选通管T2处于开启时，第三控制信号SL1可以通过第一选通管T1向TR1、TR2的栅极施加电压；或者第三控制信号SL1通过第三选通管T3向TR5、TR6的栅极施加电压。第二控制信号WL2用来控制第三选通管T3与第四选通管T4的开启。当第三选通管T3与第四选通管T4处于开启状态时，第四控制信号SL2可以通过第二选通管T2向TR3、TR4的栅极施加电压；或者第四控制信号SL2通过第四选通管T4向TR7、TR8的栅极施加电压。基底控制信号G1用于向反熔丝晶体管的基底提供电压。BL1、BL2、BL3、BL4分别为阵列结构的列选择控制管(可以采用MOS管)， RL1、RL2、RL3、RL4分别为各列的读取端。
具体地，以反熔丝电容TR1的存储过程为例进行说明，其他反熔丝电容的操作方法类似，不再赘述。当存储单元阵列结构未被编程时，所有反熔丝晶体管的氧化介质层均保持完好未被击穿。编程时，首先通过第一控制信号WL1和第三控制信号SL1向第一选通管T1施加电压，使得第一选通管T1导通。(若第一选通管T1为NMOS器件，则为第一控制信号WL1提供一定正电压使得第一选通管T1导通，同时第三控制信号SL1提供高电压，该高电压作为反熔丝电容TR1的编程电压)；然后使得控制管BL1导通，为反熔丝电容TR1的编程提供电流通路，同时使得基底控制信号G1为与第三控制信号SL1电压相同或相近的电压，从而提高编程率。保持此电压状态一定时间，使得反熔丝电容TR1的氧化介质层被击穿，从而实现对反熔丝电容TR1的编程。
具体地，以反熔丝电容TR1的读取过程为例进行说明，其他反熔丝电容的操作方法类似，不再赘述。首先，通过第一控制信号WL1和第三控制信号SL1向第一选通管T1施加电压，使得第一选通管T1导通。(若第一选通管T1为NMOS器件，第一控制信号WL1的电压可与编程时相同或不同，其目的是提供一定正电压使得第一选通管T1导通；同时使得第三控制信号SL1为小于编程电压的正电压，此正电压是为了读取反熔丝电容TR1的击穿或未击穿状态，因此要远远小于击穿电压，使其不会对TR1状态产生影响。)令G1端接地，然后使得控制管BL1导通，为反熔丝电容TR1的编程提供电流通路，在读取端RL1处读取反熔丝电容TR1的状态。(若反熔丝电容TR1已被编程，则在RL1处可读取到高电平，若反熔丝电容TR1未被编程，则RL1处读取到低电平)。
图9为本发明实施例九提供的存储单元的编程设备的结构示意图，如图9所示，本实施例中的存储单元的编程设备40可以包括：处理器41以及存储器42；
存储器42，用于存储程序；
处理器41，用于执行存储器42存储的程序，当程序被执行时，处理器41用于通过图5的存储单元的操作方法对图4的存储单元进行编程。
可选地，存储器42既可以是独立的，也可以跟处理器41集成在一起。
当存储器42是独立于处理器41之外的器件时，存储单元的编程设备 40还可以包括：总线43，用于连接存储器42和处理器41。
图10为本发明实施例十提供的存储单元的读取设备的结构示意图，如图10所示，本实施例中的存储单元的读取设备50可以包括：处理器51以及存储器52；
存储器52，用于存储程序；
处理器51，用于执行存储器52存储的程序，当程序被执行时，处理器51用于通过图6的存储单元的操作方法对图4存储单元进行编程结果读取。
可选地，存储器52既可以是独立的，也可以跟处理器51集成在一起。
当存储器52是独立于处理器51之外的器件时，存储单元的读取设备50还可以包括：总线53，用于连接存储器52和处理器51。
本发明实施例还提供一种计算机可读存储介质，包括：指令，当其在计算机上运行时，使得计算机执行图5的存储单元的操作方法对图4存储单元进行编程。
本发明实施例还提供一种计算机可读存储介质，包括：指令，当其在计算机上运行时，使得计算机图6的存储单元的操作方法对图4存储单元进行编程结果读取。
其中，计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是通用或专用计算机能够存取的任何可用介质。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于应用专用集成电路(ASIC)中。另外，该应用专用集成电路可以位于用户设备中。当然，处理器和存储介质也可以作为分立组件存在于通信设备中。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本发明旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求书指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所 附的权利要求书来限制。

Claims (18)

  1. 一种存储单元，其特征在于，包括：
    反熔丝晶体管，其包括栅极、源极和漏极，所述反熔丝晶体管由金属氧化物半导体场效应晶体管MOSFET构成；以及
    选通管，所述选通管与所述反熔丝晶体管的栅极电连接，所述栅极与源极分别构成第一反熔丝电容的两端，所述栅极与漏极分别构成第二反熔丝电容的两端。
  2. 根据权利要求1所述的存储单元，其特征在于，所述第一反熔丝电容的两端分别与外部电路的电源端相连；
    通过所述外部电路的电源端向所述第一反熔丝电容的两端施加电压，以局部击穿所述反熔丝晶体管的栅极与所述反熔丝晶体管的源极之间的氧化介质层，使得所述反熔丝晶体管的栅极和源极形成导电通路，完成对所述第一反熔丝电容的编程。
  3. 根据权利要求1所述的存储单元，其特征在于，所述第二反熔丝电容的两端分别与外部电路的电源端相连；
    通过所述外部电路的电源端向所述第二反熔丝电容的两端施加电压，以局部击穿所述反熔丝晶体管的栅极与所述反熔丝晶体管的漏极之间的氧化介质层，使得所述反熔丝晶体管的栅极和漏极形成导电通路，完成对所述第二反熔丝电容的编程。
  4. 根据权利要求1-3中任一项所述的存储单元，其特征在于，所述选通管包括：金属氧化物半导体场效应晶体管MOSFET。
  5. 一种存储单元的操作方法，其特征在于，应用于权利要求1-4中任一项所述的存储单元，所述方法包括：
    通过控制反熔丝晶体管的栅极电压、源极电压、漏极电压、基底电压的大小，在所述反熔丝晶体管的栅极与源极之间形成第一电压差，或者在所述反熔丝晶体管的栅极与漏极之间形成第二电压差；
    若所述第一电压差大于所述反熔丝晶体管的栅极与源极之间氧化介质层的击穿电压，完成对所述反熔丝晶体管的栅极与源极构成的第一反熔丝电容的编程操作；
    若所述第二电压差大于所述反熔丝晶体管的栅极与漏极之间氧化介质 层的击穿电压，完成对所述反熔丝晶体管的栅极与漏极构成的第二反熔丝电容的编程。
  6. 根据权利要求5所述的方法，其特征在于，当所述反熔丝晶体管为P型MOSFET时，所述通过控制反熔丝晶体管的栅极电压、源极电压、漏极电压、基底电压的大小，在所述反熔丝晶体管的栅极与源极之间形成第一电压差，包括：
    控制反熔丝晶体管的栅极电压、漏极电压、基底电压为高电压，控制反熔丝晶体管的源极电压为低电压或者零电压，以在所述反熔丝晶体管的栅极与源极之间形成第一电压差。
  7. 根据权利要求5所述的方法，其特征在于，当所述反熔丝晶体管为P型MOSFET时，所述通过控制反熔丝晶体管的栅极电压、源极电压、漏极电压、基底电压的大小，在所述反熔丝晶体管的栅极与漏极之间形成第二电压差，包括：
    控制反熔丝晶体管的栅极电压、源极电压、基底电压为高电压，控制反熔丝晶体管的漏极电压为低电压或者零电压，以在所述反熔丝晶体管的栅极与源极之间形成第二电压差。
  8. 根据权利要求5所述的方法，其特征在于，当所述反熔丝晶体管为N型MOSFET时，所述通过控制反熔丝晶体管的栅极电压、源极电压、漏极电压、基底电压的大小，在所述反熔丝晶体管的栅极与源极之间形成第一电压差，包括：
    控制反熔丝晶体管的栅极电压、漏极电压、基底电压为低电压，控制反熔丝晶体管的源极电压为高电压或者零电压，以在所述反熔丝晶体管的栅极与源极之间形成第一电压差。
  9. 根据权利要求5所述的方法，其特征在于，当所述反熔丝晶体管为N型MOSFET时，所述通过控制反熔丝晶体管的栅极电压、源极电压、漏极电压、基底电压的大小，在所述反熔丝晶体管的栅极与漏极之间形成第二电压差，包括：
    控制反熔丝晶体管的栅极电压、源极电压、基底电压为低电压，控制反熔丝晶体管的漏极电压为高电压或者零电压，以在所述反熔丝晶体管的栅极与源极之间形成第二电压差。
  10. 一种存储单元的操作方法，其特征在于，应用于权利要求1-4中 任一项所述的存储单元，所述方法包括：
    通过选通管对反熔丝晶体管的栅极施加栅极电压，使得所述反熔丝晶体管处于导通状态；对所述反熔丝晶体管的源极、漏极、基底分别施加源极电压、漏极电压、基底电压；
    获取到所述反熔丝晶体管的源极或者漏极的电信号；其中，所述反熔丝晶体管的源极的电信号对应第一反熔丝电容的编程结果；所述反熔丝晶体管的漏极的电信号对应第二反熔丝电容的编程结果。
  11. 根据权利要求10所述的方法，其特征在于，当所述反熔丝晶体管为P型MOSFET时，获取到所述反熔丝晶体管的源极的电信号，包括：
    控制反熔丝晶体管的栅极电压为高电压，所述反熔丝晶体管的源极电压与基底电压为零电压或相同的低电压，所述反熔丝晶体管的漏极不施加电压，获取所述反熔丝晶体管源极处的电压或电流信号；其中，所述反熔丝晶体管的栅极与源极之间的电压差远远小于所述反熔丝晶体管的氧化层介质击穿电压；
    当所述反熔丝晶体管为P型MOSFET时，获取到所述反熔丝晶体管的漏极的电信号，包括：
    控制反熔丝晶体管的栅极电压为高电压，所述反熔丝晶体管的漏极电压与基底电压为零电压或相同低电压，所述反熔丝晶体管的源极不施加电压，获取所述反熔丝晶体管漏极处的电压或电流信号；其中，所述反熔丝晶体管的栅极与漏极之间的电压差远远小于所述反熔丝晶体管的氧化层介质击穿电压。
  12. 根据权利要求10所述的方法，其特征在于，当所述反熔丝晶体管为N型MOSFET时，获取到所述反熔丝晶体管的源极的电信号，包括：
    控制反熔丝晶体管的栅极电压为高电压，所述反熔丝晶体管的源极电压与基底电压为零电压或相同的低电压，所述反熔丝晶体管的漏极不施加电压，获取所述反熔丝晶体管源极处的电压或电流信号；获取所述反熔丝晶体管源极处的电压或电流信号；其中，所述反熔丝晶体管的栅极与源极之间的电压差远远小于所述反熔丝晶体管的氧化层介质击穿电压；
    当所述反熔丝晶体管为N型MOSFET时，获取到所述反熔丝晶体管的漏极的电信号，包括：
    控制反熔丝晶体管的栅极电压为高电压，所述反熔丝晶体管的漏极电 压与基底电压为零电压或相同低电压，所述反熔丝晶体管的源极不施加电压，获取所述反熔丝晶体管漏极处的电压或电流信号；其中，所述反熔丝晶体管的栅极与漏极之间的电压差远远小于所述反熔丝晶体管的氧化层介质击穿电压。
  13. 一种存储器件，其特征在于，包括：至少一个如权利要求1-4中任一项所述的存储单元、控制信号输入电路；其中，所述控制信号输入电路用于生成反熔丝晶体管的栅极电压、源极电压、漏极电压、基底电压，以对所述存储单元执行如权利要求5-9中任一项所述的存储单元的操作方法。
  14. 根据权利要求13所述的存储器件，其特征在于，还包括：存储单元读取电路，所述存储单元读取电路用于对所述存储单元执行如权利要求10-12中任一项所述的存储单元操作方法。
  15. 一种存储单元的编程设备，其特征在于，包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于通过权利要求5-9中任一项所述的存储单元的操作方法对权利要求1-4中任一项所述存储单元进行编程。
  16. 一种存储单元的读取设备，其特征在于，包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于通过权利要求10-12中任一项所述的存储单元的操作方法对权利要求1-4中任一项所述存储单元进行编程结果读取。
  17. 一种计算机可读存储介质，其特征在于，包括：指令，当其在计算机上运行时，使得计算机执行权利要求5-9中任一项所述的存储单元的操作方法对权利要求1-4中任一项所述存储单元进行编程。
  18. 一种计算机可读存储介质，其特征在于，包括：指令，当其在计算机上运行时，使得计算机执行权利要求10-12中任一项所述的存储单元的操作方法对权利要求1-4中任一项所述存储单元进行编程结果读取。
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