WO2019184957A1 - 沟槽分离栅器件及其制造方法 - Google Patents

沟槽分离栅器件及其制造方法 Download PDF

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WO2019184957A1
WO2019184957A1 PCT/CN2019/079932 CN2019079932W WO2019184957A1 WO 2019184957 A1 WO2019184957 A1 WO 2019184957A1 CN 2019079932 W CN2019079932 W CN 2019079932W WO 2019184957 A1 WO2019184957 A1 WO 2019184957A1
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trench
oxide layer
layer
floating gate
sidewall
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PCT/CN2019/079932
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English (en)
French (fr)
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方冬
卞铮
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无锡华润上华科技有限公司
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Priority to US17/041,980 priority Critical patent/US20210028289A1/en
Priority to KR1020207030950A priority patent/KR102413945B1/ko
Priority to EP19777812.9A priority patent/EP3780067A4/en
Publication of WO2019184957A1 publication Critical patent/WO2019184957A1/zh

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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Definitions

  • the present application relates to the field of semiconductor manufacturing technology, and in particular, to a trench isolation gate device and a method of fabricating the same.
  • the vertical double-diffused metal-Oxide-Semiconductor Field-Effect Transistor (Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor) Field effect transistor) products are gradually being replaced by trench-split gate VDMOS devices.
  • the implementation of the lower partial oxide layer in the trench is performed by thermal oxidation or thermal oxidation to grow a thin oxide layer, and an oxide layer is grown on the surface of the thin oxide layer by furnace oxidation or deposition.
  • the thickness of the oxide layer at the bottom of the trench is actually thinner than the thickness of the sidewall oxide layer, and the bottom of the trench is oxidized as the thickness of the oxide layer at the bottom of the trench increases and the depth of the trench increases.
  • the ratio of the layer thickness to the thickness of the sidewall oxide layer tends to be small.
  • the thickness of the oxide layer at the bottom of the trench is smaller than the thickness of the sidewall oxide layer, a thicker trench is achieved.
  • the thickness of the oxide layer at the bottom of the groove increases, and the oxidation process increases, so that the thickness of the sidewall oxide layer is thicker, and a wider groove width is required to adapt to the thicker sidewall sidewall oxide layer, thereby resulting in a larger chip area and higher specific on-resistance. .
  • a trench separation gate device and a method of fabricating the same are provided.
  • a method of fabricating a trench isolation gate device comprising: etching a semiconductor substrate to form a trench; depositing an oxide in the trench to form a floating gate oxide layer The floating gate oxide layer is gradually thickened from top to bottom along the sidewall of the trench, and the thickness of the floating gate oxide layer in the lower portion of the trench sidewall is the same as the thickness of the floating gate oxide layer at the bottom of the trench; Depositing polysilicon in the trench to form a floating gate polycrystalline layer; growing an insulating dielectric on the surface of the floating gate polycrystalline layer to form an isolation layer; forming a control gate on the isolation layer in the trench.
  • a trench-split gate device comprising: a semiconductor substrate having a trench formed therein, the trench inner wall having a floating gate oxide layer, the floating gate The thickness of the oxide layer is gradually thickened along the sidewall of the trench to the bottom of the trench, and the thickness of the floating gate oxide layer under the sidewall of the trench is the same as the thickness of the floating gate oxide layer at the bottom of the trench; the surface of the floating gate oxide layer A floating gate polycrystalline layer is disposed; the floating gate polycrystalline layer has an isolation layer; and the isolation layer has a control gate for controlling conduction and shutdown of the device.
  • FIG. 1 is a flow chart of a method for fabricating a trench isolation gate device according to an embodiment of the present application
  • FIG. 2 is a flow chart of a method for fabricating a trench isolation gate device according to an embodiment of the present application
  • 3A-3G are schematic cross-sectional views of a cell of a trench isolation gate device fabricated by the method of FIG. 2;
  • FIG. 4 is a flow chart of a method for fabricating a trench isolation gate device according to still another embodiment of the present application.
  • 5A-5H are schematic cross-sectional views of a cell of a trench isolation gate device fabricated by the method of FIG. 4.
  • the present application provides a method for fabricating a trench isolation gate device, including the following steps:
  • S100 etching the semiconductor substrate to form a trench.
  • S110 depositing an oxide in the trench to form a floating gate oxide layer, gradually increasing the floating gate oxide layer from top to bottom along the sidewall of the trench, and the thickness of the floating gate oxide layer in the lower portion of the trench sidewall is The floating gate oxide layer at the bottom of the trench has the same thickness.
  • S120 depositing polysilicon into the trench to form a floating gate polycrystalline layer.
  • S130 forming an isolation layer by growing an insulating medium on the surface of the floating gate polycrystalline layer.
  • a gradually changing floating gate oxide layer is grown on the sidewall of the trench, so that the thickness of the floating gate oxide layer is gradually thickened from the position of the isolation layer to the bottom of the trench, and the sidewall of the trench.
  • the thickness of the lower floating gate oxide layer is the same as the thickness of the floating gate oxide layer at the bottom of the trench.
  • the gradually varying thickness of the floating gate oxide layer can reduce the trench width, thereby further reducing the cell area and reducing the specific on-resistance of the device.
  • the floating gate oxide layer which gradually thickens from the sidewall of the trench and has the same thickness as the bottom of the trench at the lower side of the trench also accommodates the increasing voltage from the control gate to the bottom of the trench, so that the device does not suffer from non-adaptation. The voltage is broken down.
  • etching the semiconductor substrate to form the trench comprises: vertically etching the semiconductor substrate such that the sidewalls of the trench are vertically up and down.
  • the step of depositing an oxide in the trench to form the floating gate oxide layer includes: forming a first oxide layer on the inner surface of the trench; forming a second oxide on the first oxide layer by a high-density plasma chemical vapor deposition process The layer controls the second oxide layer to gradually thicken from top to bottom along the sidewall of the trench, and the thickness of the second oxide layer in the lower portion of the sidewall of the trench is the same as the thickness of the second oxide layer at the bottom of the trench.
  • controlling the second oxide layer to gradually thicken from top to bottom along the sidewall of the trench can be realized by controlling the pressure of the reaction chamber and the flow rate of the reaction gas flowing into the reaction chamber.
  • the manufacturing method of the trench isolation gate device of this embodiment specifically includes the following steps:
  • S200 etching the semiconductor substrate to form a trench.
  • Semiconductor substrates are semiconductor materials that provide mechanical support and electrical performance for making transistors and integrated circuits.
  • the semiconductor substrate may include a semiconductor element such as a single crystal, polycrystalline or amorphous silicon or germanium, and may also include a mixed semiconductor structure such as silicon carbide, indium antimonide, lead telluride, arsenic. Indium, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof.
  • the semiconductor substrate includes a highly doped body layer 100 and a low doped epitaxial layer 110.
  • the body layer 100 and the epitaxial layer 110 have the same doping type and may be N-type impurities.
  • a dry etching process is used to etch vertically from top to bottom on the epitaxial layer 110 so that the sidewalls of the trench 120 formed by etching are vertically up and down.
  • the first oxide layer may be formed on the inner surface of the trench by a furnace tube oxidation method, and the first oxide layer may be silicon oxide.
  • the semiconductor substrate can be placed in a certain gas atmosphere and a certain temperature atmosphere during preparation to react the semiconductor substrate with oxygen or water vapor to form silicon dioxide.
  • the gas atmosphere refers to nitrogen gas and/or oxygen gas and/or hydrogen gas, and the temperature ranges from about 700 degrees Celsius to about 1100 degrees and then falls back to about 700 degrees.
  • the first oxide layers 121 located throughout the trenches 120 have the same thickness.
  • S220 forming a second oxide layer on the first oxide layer by a high-density plasma chemical vapor deposition process, and controlling the flow rate of the reaction chamber and the flow rate of the reaction gas flowing into the reaction chamber to make the second oxide layer along the trench
  • the sidewalls gradually become thicker from top to bottom, and the thickness of the second oxide layer in the lower portion of the trench sidewall is the same as the thickness of the second oxide layer at the bottom of the trench.
  • a surface of the first oxide layer 121 at the bottom of the trench 120 is deposited by a High Density Plasma Chemical Vapor Deposition (HDP CVD) process.
  • a second oxide layer 122 is formed.
  • the second oxide layer 122 may be silicon oxide.
  • a reaction gas such as silane, oxygen, hydrogen, helium or the like is introduced into the reaction chamber, and during the deposition process, the silica formed by the reaction is controlled by controlling the pressure of the reaction chamber and the flow rate of the introduced reaction gas. The amount of sidewalls and bottom of the trench 120.
  • a certain amount of reaction gas is introduced into the reaction chamber under a certain pressure condition, and the reaction gas reaches the bottom of the trench 120 under the pressure of the cavity and reacts at the bottom of the trench 120 to form a thick oxide product. Then, the pressure is lowered at intervals and the flow rate of the reaction gas introduced into the reaction chamber is decreased. At a small pressure, the reaction gas gradually goes upward and deposits a reaction on the sidewall of the trench 120 to form a thin oxide product. . Further, the second oxide layer 122 deposited on the sidewall of the trench 120 is gradually thinned from bottom to top, and the thickness of the second oxide layer 122 at the lower portion of the sidewall of the trench is the thickness of the second oxide layer 122 deposited at the bottom of the trench 120.
  • the thickness is the same. Therefore, the thickness of the floating gate oxide layer formed by the first oxide layer 121 and the second oxide layer 22 is gradually thickened from top to bottom along the sidewall of the trench, and the thickness of the floating gate oxide layer at the lower portion of the trench sidewall is at the bottom of the trench
  • the floating gate oxide layer has the same thickness.
  • the flow rate of the reaction gas may be 15%-20% of silane, 20%-25% of oxygen, 25%-35% of hydrogen, and 20%-40% of helium.
  • the HDP CVD process employed in the embodiment of the present application can control the thickness of the deposited second oxide layer 122 to be deposited on the sidewall of the trench 120, as compared to the conventional pressure chemical vapor deposition method.
  • the oxide layer 122 gradually thickens from top to bottom, and the thickness of the second oxide layer 122 at the bottom of the trench 120 is the same as the thickness of the second oxide layer 122 at the lower portion of the sidewall of the trench 120.
  • the thickness of the floating gate oxide layer at the bottom of the thickened trench allows the device to adapt to withstand voltage and is not broken down by high voltage.
  • the floating gate oxide layer of the trench sidewall in the present application is thinner than the floating gate oxide layer of the trench sidewall in the conventional process, and the trench width ratio is In the conventional process, the groove width is narrower, thereby reducing the cell area, so that the number of cells on the chip per unit area is increased, and the specific on-resistance of the device is lowered.
  • polysilicon is deposited in the trench to form the floating gate poly layer 123 by low pressure chemical vapor deposition.
  • the polysilicon may be etched or ground such that the upper surface of the floating gate poly layer 123 is lower than the lower surface of the P-type well region formed in the subsequent process.
  • S240 forming an isolation layer by growing an insulating medium on the surface of the floating gate polycrystalline layer.
  • an insulating medium may be grown on the surface of the floating gate poly layer 123 by thermal oxidation or chemical vapor deposition to form the isolation layer 124.
  • the insulating medium may be silicon nitride or silicon oxide or silicon oxynitride, and the isolation layer 124 is used to isolate the floating gate poly layer 123 and the control gate formed in the subsequent process.
  • the step of removing the first oxide layer 121 above the floating gate poly layer 123 is further included.
  • the first oxide layer 121 above the floating gate poly layer 123 may be removed by a dry etching technique.
  • forming a control gate on the isolation layer 124 in the trench 120 specifically includes: forming a gate oxide layer 125 on the sidewall of the trench above the isolation layer 124; and an isolation layer 124 in the trench 120.
  • Polysilicon is deposited over the gate to form a control gate poly layer 126 that is adjacent to the control gate oxide layer 125; the control gate poly layer 126 is etched or ground.
  • the control gate oxide layer 125 and the control gate poly layer 126 together form a control gate.
  • polysilicon can be deposited in the trench 120 by low-pressure chemical vapor deposition while doping the polysilicon.
  • the polysilicon outside the trench 120 may be etched using a dry etch process to form a control gate.
  • the trench isolation gate device provided in this embodiment is fabricated by using a high-density plasma chemical vapor deposition process, so that the thickness of the second oxide layer at the bottom of the trench and the sidewall can be adjusted by adjusting the pressure and reaction of the reaction chamber. The flow rate of the gas is adjusted.
  • the thickness of the floating gate oxide layer on the sidewall of the trench is gradually thickened from top to bottom, and the thickness of the floating gate oxide layer in the lower portion of the trench sidewall is the same as the thickness of the floating gate oxide layer at the bottom of the trench.
  • the gradually changing floating gate oxide thickness can reduce the groove width, thereby further reducing the cell area and increasing the number of cells that can be accommodated per unit area of the chip. , reduce the specific on-resistance of the device.
  • the step of forming a control gate on the isolation layer in the trench further includes: the P-type impurity implant is pushed to form a P-type well region 130 on both sides of the trench 120.
  • An N-type heavily doped region 131 is formed in the P-type well region 130 on both sides of the trench 120 by implanting a highly doped N-type impurity.
  • An isolation oxide layer 140 is then formed on the control gate by thermal oxidation. The isolation oxide layer 140 is etched to form a contact hole 141 penetrating the P-type well region, and the N-type heavily doped region 131 is located between the contact hole 141 and the trench 120.
  • the P-type heavily doped P-type impurity is implanted into the P-type well region through the contact hole 141 to form a P-type heavily doped region 132.
  • the contact hole 141 is then filled, and finally a source is formed on the isolation oxide layer 140, and a drain is formed on the lower surface of the body layer 100, thereby forming a basic structure of the trench isolation gate device.
  • the trench isolation gate device includes a semiconductor substrate including a body layer 100 and an epitaxial layer 110.
  • a trench 120 is disposed in the semiconductor substrate, the trench 120 is disposed in the epitaxial layer 110, and the sidewalls of the trench 120 are vertically up and down.
  • the inner wall of the trench 120 has a floating gate oxide layer including a first oxide layer 121 on the inner wall of the trench 120 and a second oxide layer 122 on the first oxide layer 121.
  • the first oxide layer 121 located at the sidewall of the trench 120 is uniform in thickness
  • the second oxide layer 122 is gradually thickened from top to bottom along the sidewall of the trench 120
  • the second oxide in the lower portion of the sidewall of the trench 120 is formed.
  • the thickness of layer 122 is the same as the thickness of second oxide layer 122 at the bottom of trench 120. Therefore, the total thickness of the floating gate oxide layer formed by the first oxide layer 121 and the second oxide layer 122 gradually increases from top to bottom along the sidewall of the trench 120, and the thickness and trench of the floating gate oxide layer in the lower portion of the sidewall of the trench 120
  • the floating gate oxide layer at the bottom of 120 has the same thickness.
  • a floating gate polycrystalline layer 123 is provided on the surface of the floating gate oxide layer.
  • the floating gate poly layer 123 and the floating gate oxide layer together constitute a floating gate structure.
  • the upper surface of the floating gate polycrystalline layer 123 has an isolation layer 124.
  • the isolation gate 124 is provided with a control gate poly layer 126 and a control gate oxide layer 125.
  • the control gate poly layer 126 and the control gate oxide layer 125 together form a control gate structure.
  • the trench isolation gate device provided by the embodiment of the present invention passes through the second oxide layer formed by the HDP CVD process at the bottom and sidewalls of the trench, so that the thickness of the second oxide layer gradually changes from top to bottom along the sidewall of the trench.
  • the thickness of the second oxide layer under the thick, trench sidewall is the same as the thickness of the second oxide layer at the bottom of the trench.
  • the total thickness of the floating gate oxide layer formed by the first oxide layer and the second oxide layer gradually increases from top to bottom along the sidewall of the trench, and the thickness of the floating gate oxide layer at the lower portion of the trench sidewall and the floating gate at the bottom of the trench
  • the oxide layer has the same thickness. Therefore, on the one hand, it satisfies the gradually changing withstand voltage requirement, and at the same time, the gradually changing floating gate oxide thickness can reduce the groove width, thereby further reducing the cell area and reducing the specific on-resistance of the device.
  • etching the semiconductor substrate to form the trenching comprises: etching the semiconductor substrate to form a vertical upper half trench. Etching the semiconductor substrate obliquely downward from the bottom of the upper half trench to form a lower half trench extending downward from the bottom of the half trench and gradually widening from top to bottom, and the bottom of the lower half trench is recessed arc.
  • the step of depositing an oxide in the trench to form the floating gate oxide layer comprises: forming a first oxide layer on the inner surface of the trench; etching the first oxide layer to make the sidewall of the first oxide layer vertically up and down; using a high-density plasma a bulk chemical vapor deposition process to form a second oxide layer on the first oxide layer at the bottom of the lower half trench such that the first oxide layer and the second oxide layer form a floating gate oxide layer along the sidewall of the trench
  • the thickness of the floating gate oxide layer in the lower portion of the lower half trench sidewall is the same as the thickness of the floating gate oxide layer at the bottom of the lower half trench.
  • the manufacturing method of the trench isolation gate device in this embodiment specifically includes the following steps:
  • S300 etching the semiconductor substrate to form a vertical upper half trench.
  • the semiconductor substrate includes a body layer 200 and an epitaxial layer 210.
  • the semiconductor substrate is vertically etched by a dry etching technique to form a vertically downward upper half trench 221 in the epitaxial layer 210.
  • the polymer formed by the reaction of the etching gas with the silicon substrate is retained to protect the upper half trench 221, and the surface of the upper half trench 221 is not etched in the next step.
  • S310 etching the semiconductor substrate obliquely downward from the bottom of the upper half trench to form a lower half trench extending downward from the bottom of the upper half trench and gradually widening from top to bottom.
  • the epitaxial layer 211 is obliquely etched from the bottom of the vertical upper half trench 221 by a dry etching technique to form a downward extension from the bottom of the upper half trench 221, and the width is from top to bottom.
  • the lower half groove 222 is gradually widened, and the bottom of the lower half groove 222 is concavely curved.
  • the upper half groove 221 and the lower half groove 222 together form a groove 220.
  • a pickling step is performed to remove the etch-producing polymer attached to the surface of the trench 220.
  • the first oxide layer 223 may be formed on the inner surface of the trench 220 by a furnace tube oxidation method or a CVD process. Specifically, in the present embodiment, the first oxide layer 223 is oxidized and grown on the surface of the trench 220 by a furnace tube oxidation method.
  • S330 etching the first oxide layer so that the sidewalls of the first oxide layer are vertically up and down.
  • the first oxide layer 223 is dry etched so that the sidewalls of the first oxide layer 223 on the inner wall of the trench are vertically up and down, and the thickness of the first oxide layer 223 on the sidewall of the lower trench 222 is from above. It gradually thickens.
  • S340 forming a second oxide layer on the first oxide layer at the bottom of the lower half trench by a high-density plasma chemical vapor deposition process to form a floating gate oxide layer formed by combining the first oxide layer and the second oxide layer
  • the sidewall of the trench is gradually thicker from top to bottom, and the thickness of the floating gate oxide layer under the sidewall of the trench is the same as the thickness of the floating gate oxide layer at the bottom of the trench.
  • a second oxide layer 224 is deposited on the first oxide layer 223 at the bottom of the lower trench 222 by HDP CVD deposition to thicken the floating gate oxide layer at the bottom of the lower trench 222 to increase the device. Pressure resistance. Since the first oxide layer 223 of the sidewall of the lower half trench 222 is gradually thicker from the top to the bottom along the lower half trench 222, the second oxide layer 224 is located on the first oxide layer 223 at the bottom of the lower trench 222, so The total thickness of the floating gate oxide layer formed by the oxide layer 223 and the second oxide layer 224 gradually increases from top to bottom along the sidewall of the lower half trench 222, and the thickness of the floating gate oxide layer under the sidewall of the lower half trench 222 is lower. The floating gate oxide layer at the bottom of the half trench 222 has the same thickness.
  • polysilicon is deposited in the trench 220 by a low pressure chemical vapor deposition method to form a floating gate polycrystalline layer 225. Further, after the polysilicon is filled in the trench 220, the polysilicon may be etched or ground such that the upper surface of the floating gate polycrystalline layer 225 is lower than the lower surface of the P-type well region formed in the subsequent process.
  • an insulating layer 226 may be formed by depositing an insulating medium on the surface of the floating gate polycrystalline layer 225 by thermal oxidation or chemical vapor deposition.
  • the insulating dielectric can be silicon nitride or silicon oxide or silicon oxynitride for isolating the floating gate poly layer 225 and the control gate formed in subsequent processes.
  • the step of removing the first oxide layer 222 over the floating gate polycrystalline layer 225 is further included.
  • the first oxide layer 223 over the floating gate poly layer 225 may be removed by a dry etching technique.
  • forming a control gate on the isolation layer 226 in the trench 220 specifically includes: forming a gate oxide layer 227 on the sidewall of the trench above the isolation layer 226; and an isolation layer in the trench 220 Polysilicon is deposited over 226 to form a control gate poly layer 228, control gate poly layer 228 abuts control gate oxide layer 227, and control gate poly layer 228 is etched or ground to form a control gate.
  • the control gate includes a control gate oxide layer 227 and a control gate poly layer 228.
  • polysilicon can be deposited in the trench 220 by low-pressure chemical vapor deposition while doping the polysilicon.
  • the polysilicon outside the trench 220 may be etched using a dry etch process to form a control gate.
  • the trench isolation gate device provided in this embodiment is formed by first etching the vertical upper half trench and then obliquely etching from the bottom of the upper trench to form a width gradually widening from top to bottom. A half groove, the upper half groove and the lower half groove together forming a groove. A first oxide layer is then grown on the inner wall of the trench, wherein the thickness of the first oxide layer in the lower half trench gradually increases from top to bottom along the sidewall of the lower half trench.
  • a second oxide layer is deposited on the first oxide layer at the bottom of the lower half trench for thickening the thickness of the floating gate oxide layer at the bottom of the lower half trench, so that the floating gate formed by the first oxide layer and the second oxide layer
  • the total thickness of the oxide layer gradually increases from top to bottom along the sidewall of the lower half trench, and the thickness of the floating gate oxide layer in the lower portion of the lower half trench sidewall is the same as the thickness of the floating gate oxide layer at the bottom of the lower half trench. Therefore, on the one hand, it satisfies the gradually changing withstand voltage requirement, and at the same time, the cell area can be reduced, and the specific on-resistance of the device can be reduced.
  • the step of forming a control gate on the isolation layer in the trench further includes: the P-type impurity implant is pushed to form a P-type well region 230 on both sides of the trench 220.
  • An N-type heavily doped region 231 is formed in the P-type well region 230 on both sides of the trench 220 by implanting a highly doped N-type impurity.
  • the isolation oxide layer 240 can be formed on the control gate by thermal oxidation.
  • the isolation oxide layer 240 is etched to form a contact hole 241 penetrating the P-type well region, and the N-type heavily doped region 231 is located between the contact hole 241 and the trench 220.
  • the P-type well region is implanted with a heavily doped P-type impurity through the contact hole 241 to form a P-type heavily doped region 232.
  • the contact hole 241 is then filled, and finally a source is formed on the isolation oxide layer 240, and a drain is formed on the lower surface of the body layer 200, thereby forming a basic structure of the separation gate device.
  • This embodiment also provides a trench isolation gate device fabricated in accordance with the method steps shown in FIG. Specifically, as shown in FIG. 5H, a semiconductor substrate including a body layer 200 and an epitaxial layer 210 is included. A trench 220 is disposed in the epitaxial layer 210.
  • the groove 220 includes an upper half groove 221 which is vertically upper and lower sides of the side wall, and a lower half groove 222 which extends downward from the bottom of the upper half groove and gradually widens from top to bottom, and the bottom of the lower half groove is concavely curved.
  • the inner wall of the trench 220 has an oxide layer including a first oxide layer 223 on the inner wall of the trench and a second oxide layer 224 on the first oxide layer 223 at the bottom of the trench.
  • the thickness of the first oxide layer 223 located on the inner wall of the lower half trench 222 gradually increases from top to bottom along the sidewall of the lower half trench 222, and the second oxide layer 224 is used to thicken the floating gate at the bottom of the lower half trench 222.
  • Oxide layer thickness Therefore, the total thickness of the floating gate oxide layer formed by the first oxide layer 223 and the second oxide layer 224 gradually increases from top to bottom along the sidewall of the lower half trench 222, and the floating gate oxide layer in the lower portion of the sidewall of the lower trench 222 The thickness is the same as the thickness of the floating gate oxide layer at the bottom of the lower half trench 222.
  • a floating gate polycrystalline layer 225 is provided on the surface of the floating gate oxide layer.
  • the upper surface of the floating gate polycrystalline layer 225 has an isolation layer 226.
  • the sidewall of the upper trench 221 above the isolation layer 226 has a control gate oxide layer 227.
  • the control gate poly layer 228 is on the isolation layer 226 and adjacent to the control gate oxide layer 227.
  • the control gate oxide layer 227 and the control gate poly layer 228 together form the control gate of the trench discrete device.
  • the width of the lower half trench is gradually widened from top to bottom, and the thickness of the first oxide layer grown on the inner wall of the lower half trench is gradually thickened from top to bottom.
  • the dioxide layer is used to thicken the bottom of the trench such that the total thickness of the floating gate oxide layer formed by the first oxide layer and the second oxide layer gradually increases from top to bottom along the sidewall of the lower half trench, and the lower half trench sidewall
  • the thickness of the lower floating gate oxide layer is the same as the thickness of the floating gate oxide layer at the bottom of the lower half trench. Therefore, on the one hand, it satisfies the gradually changing withstand voltage requirement, and at the same time, the gradually changing floating gate oxide thickness can reduce the groove width, thereby further reducing the cell area and reducing the specific on-resistance of the device.
  • steps in the flowcharts of FIGS. 1, 2, and 4 are sequentially displayed in accordance with the indication of the arrows, these steps are not necessarily performed in the order indicated by the arrows. Except as explicitly stated herein, the execution of these steps is not strictly limited, and may be performed in other sequences. Moreover, at least some of the steps in FIG. 1, FIG. 2, and FIG. 4 may include a plurality of sub-steps or stages, which are not necessarily performed at the same time, but may be executed at different times. The order of execution is not necessarily performed sequentially, but may be performed alternately or alternately with at least a portion of other steps or sub-steps or stages of other steps.

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Abstract

一种沟槽分离栅器件的制造方法，包括：刻蚀半导体衬底形成沟槽（120）；于沟槽内淀积氧化物形成浮栅氧化层，使浮栅氧化层沿沟槽侧壁从上至下逐渐增厚，沟槽侧壁下部的浮栅氧化层厚度与沟槽底部的浮栅氧化层厚度相同；向沟槽内淀积多晶硅形成浮栅多晶层（123）；在浮栅多晶层上表面生长绝缘介质形成隔离层（124）；在沟槽内的隔离层上形成控制栅。

Description

沟槽分离栅器件及其制造方法
本申请要求于2018年3月27日提交中国专利局、申请号为2018102597833、发明名称为“沟槽分离栅器件及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体制造技术领域，特别是涉及一种沟槽分离栅器件及其制作方法。
背景技术
自分离栅器件结构提出至今，由于分离栅结构低阻低栅电容等优势，中低压普通沟槽型VDMOS(Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor，垂直双扩散金属-氧化物半导体场效应晶体管)产品渐有被沟槽分离栅VDMOS器件取代的趋势。
目前，沟槽中下部分氧化层的实现方式有采用热氧化方式生长或热氧化生长一层薄的氧化层后，在薄氧化层表面采用炉管氧化方式或淀积方式生长一层氧化层。采用以上方式生长的氧化层，实际得到的沟槽底部氧化层厚度往往薄于沟槽侧壁氧化层厚度，且随着沟槽底部氧化层厚度的增加以及沟槽深度的增加，沟槽底部氧化层厚度与侧壁氧化层厚度的比值趋小。在VDMOS源漏两端施加反向电压时，为适应耐压，需较厚的沟槽底部的氧化层，由于沟槽底部氧化层厚度小于沟槽侧壁氧化层厚度，为达到更厚的沟槽底部氧化层厚度，氧化过程增加，从而侧壁氧化层厚度更厚，需要更宽的沟槽宽度适应较厚的沟槽侧壁氧化层，进而导致芯片面积较大，比导通电阻较高。
申请内容
根据本申请的各种实施例，提供一种沟槽分离栅器件及其制造方法。
根据本申请的一个方面，提供了一种沟槽分离栅器件的制造方法，该方法包括：刻蚀半导体衬底形成沟槽；于所述沟槽内淀积氧化物形成浮栅氧化层，使所述浮栅氧化层沿沟槽侧壁从上至下逐渐增厚，所述沟槽侧壁下部的浮栅氧化层厚度与所述沟槽底部的浮栅氧化层厚度相同；向所述沟槽内淀积多晶硅形成浮栅多晶层；在所述浮栅多晶层上表面生长绝缘介质 形成隔离层；在所述沟槽内的所述隔离层上形成控制栅。
根据本申请的另一个方面，提供了一种沟槽分离栅器件，包括：半导体衬底，所述半导体衬底内设有沟槽，所述沟槽内壁具有浮栅氧化层，所述浮栅氧化层厚度沿沟槽侧壁至沟槽底部逐渐变厚，所述沟槽侧壁下部的浮栅氧化层厚度与所述沟槽底部的浮栅氧化层厚度相同；所述浮栅氧化层表面设有浮栅多晶层；所述浮栅多晶层上具有隔离层；所述隔离层上具有控制栅，用于控制器件的导通与关断。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些申请的实施例或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的申请、目前描述的实施例和/或示例以及目前理解的这些申请的最佳模式中的任何一者的范围的限制。
图1为本申请的一个实施例提供的沟槽分离栅器件制造方法流程图；
图2为本申请的一个具体实施例提供的沟槽分离栅器件制造方法流程图；
图3A～图3G为图2方法所制造的沟槽分离栅器件元胞剖面示意图；
图4为本申请的又一个具体实施例提供的沟槽分离栅器件制造方法流程图；
图5A～图5H为图4方法所制造的沟槽分离栅器件元胞剖面示意图。
具体实施方式
请参见图1，本申请提供一种沟槽分离栅器件制造方法，包括以下步骤：
S100:刻蚀半导体衬底形成沟槽。
S110:于沟槽内淀积氧化物形成浮栅氧化层，使浮栅氧化层沿沟槽侧壁从上至下逐渐增厚，所述沟槽侧壁下部的浮栅氧化层厚度与所述沟槽底部的浮栅氧化层厚度相同。
S120:向沟槽内淀积多晶硅形成浮栅多晶层。
S130:在浮栅多晶层上表面生长绝缘介质形成隔离层。
S140:在沟槽内的所述隔离层上形成控制栅。
上述沟槽分离栅器件的制造方法中，在沟槽侧壁上生长逐渐变化的浮栅氧化层，使浮栅氧化层的厚度从隔离层位置至沟槽底部位置逐渐变厚， 沟槽侧壁下部的浮栅氧化层厚度与沟槽底部浮栅氧化层厚度相同。逐渐变化的浮栅氧化层厚度可以缩小沟槽宽度，从而进一步减小元胞面积，降低器件的比导通电阻。此外，从沟槽侧壁逐渐变厚且沟槽侧壁下部与沟槽底部厚度相同的浮栅氧化层也适应从控制栅到沟槽底部不断增强的电压，使得器件不会因为承受非适应的电压而被击穿。
在其中一个实施例中，刻蚀半导体衬底形成沟槽具体包括：垂直刻蚀半导体衬底，使沟槽侧壁上下竖直。于沟槽内淀积氧化物形成浮栅氧化层的步骤包括：于沟槽内表面形成第一氧化层；采用高密度等离子体化学气相淀积工艺于所述第一氧化层上形成第二氧化层，控制第二氧化层沿沟槽侧壁从上至下逐渐变厚，沟槽侧壁下部的第二氧化层厚度与沟槽底部的第二氧化层厚度相同。其中，控制第二氧化层沿沟槽侧壁从上至下逐渐变厚具体可通过控制反应腔室的压力和通入反应腔室的反应气体流量实现。
具体的，请参见图2，本实施例沟槽分离栅器件的制造方法具体包括以下步骤：
S200：刻蚀半导体衬底形成沟槽。
半导体衬底是为制作晶体管和集成电路提供机械支撑和电气性能的半导体材料。在本实施例中，半导体衬底可以包括半导体元素，例如单晶、多晶或非晶结构的硅或锗，也可以包括混合的半导体结构，例如碳化硅、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓、合金半导体或其组合等。
具体的，请参见图3A，半导体衬底包括高掺杂的本体层100和低掺杂的外延层110。本体层100和外延层110的掺杂类型相同，可以是N型杂质。本申请中采用干法刻蚀工艺，在外延层110上从上至下垂直刻蚀，以使刻蚀形成的沟槽120侧壁上下竖直。
S210：于沟槽内表面形成第一氧化层。
在本实施例中，可采用炉管氧化法在沟槽内表面形成第一氧化层，且第一氧化层可以是氧化硅。
具体的，制备时可将半导体衬底放置在一定气体氛围和一定温度氛围中，使半导体衬底与氧气或水蒸气反应生成二氧化硅。其中，所述气体氛围是指氮气和/或氧气和/或氢气，温度范围为从700度左右升温至1100度左右再降回700度左右。如图3B所示，在本实施例中，位于沟槽120各处的第一氧化层121厚度均相同。
S220:采用高密度等离子体化学气相淀积工艺于第一氧化层上形成第二氧化层，通过控制反应腔室的压力和通入反应腔室的反应气体流量，使第二氧化层沿沟槽侧壁从上至下逐渐变厚，沟槽侧壁下部的第二氧化层厚 度与沟槽底部的第二氧化层厚度相同。
如图3C所示，第一氧化层121制备完成后，采用高密度等离子体化学气相淀积工艺(High Density Plasma Chemical Vapor Deposition，HDP CVD)工艺在沟槽120底部的第一氧化层121表面淀积第二氧化层122。其中，第二氧化层122可以是氧化硅。制备时将硅烷、氧气、氢气、氦气等反应气体通入反应腔室中，淀积过程中，通过控制反应腔室的压力和通入的反应气体的流量控制反应生成的二氧化硅附着在沟槽120侧壁和底部的量。首先，在一定的压力条件下向反应腔室内通入一定量的反应气体，反应气体在腔体压力作用下到达沟槽120底部并在沟槽120底部反应生成厚度较厚的氧化产物。然后每隔一段时间降低压力，并减小通入反应腔室的反应气体流量，在较小的压力下，反应气体逐渐往上并在沟槽120侧壁淀积反应，生成较薄的氧化产物。进而使淀积在沟槽120侧壁的第二氧化层122从下至上逐渐变薄，沟槽侧壁下部的第二氧化层122厚度与淀积在沟槽120底部的第二氧化层122的厚度相同。因此，第一氧化层121和第二氧化层22构成的浮栅氧化层的厚度沿沟槽侧壁从上至下逐渐增厚，沟槽侧壁下部的浮栅氧化层厚度与沟槽底部的浮栅氧化层厚度相同。在本实施例中，反应气体的流量可以为硅烷占15％-20％，氧气占20％-25％，氢气占25％-35％，氦气占20％-40％。
相较于使用普通常压化学气相淀积方式，本申请的实施例所采用的HDP CVD工艺可以控制淀积形成的第二氧化层122的厚度，使淀积于沟槽120侧壁的第二氧化层122从上至下逐渐变厚，沟槽120底部的第二氧化层122厚度与沟槽120侧壁下部的第二氧化层122厚度相同。一方面，加厚沟槽底部的浮栅氧化层厚度可使器件适应耐压，不至于被高压击穿。另一方面，在沟槽底部浮栅氧化层厚度相同的条件下，本申请中沟槽侧壁的浮栅氧化层比传统工艺中沟槽侧壁的浮栅氧化层更薄，沟槽宽度比传统工艺中的沟槽宽度更窄，进而缩小了元胞面积，使得单位面积芯片上的元胞数量增加，降低器件的比导通电阻。
S230：向沟槽内淀积多晶硅形成浮栅多晶层。
请参见图3D，在本实施例中，可采用低压化学气相淀积的方法在沟槽内淀积多晶硅形成浮栅多晶层123。在沟槽120内填充多晶硅后，可对多晶硅进行回刻或研磨，使得浮栅多晶层123的上表面低于后续工艺中形成的P型阱区的下表面。
S240：在浮栅多晶层上表面生长绝缘介质形成隔离层。
请参见图3E，在本实施例中，可以利用热氧化法或化学气相淀积法在浮栅多晶层123上表面生长绝缘介质以形成隔离层124。其中，绝缘介质 可以是氮化硅或氧化硅或氮氧化硅，隔离层124用于隔离浮栅多晶层123和后续工艺中形成的控制栅。
进一步的，在浮栅多晶层123上表面形成隔离层124的步骤之前，还包括去除浮栅多晶层123上方的第一氧化层121的步骤。具体的，可采用干法刻蚀技术去除浮栅多晶层123上方的第一氧化层121。
S250：在沟槽内的隔离层上形成控制栅。
进一步的，请参见图3F，在沟槽120内的隔离层124上形成控制栅具体包括：在隔离层124上方的沟槽侧壁形成控制栅氧化层125；在沟槽120内的隔离层124上淀积多晶硅形成控制栅多晶层126，所述控制栅多晶层126邻接控制栅氧化层125；对控制栅多晶层126进行回刻或研磨。控制栅氧化层125和控制栅多晶层126共同构成控制栅。
具体的，在本实施例中，可采用低压化学气相淀积的方法在沟槽120内淀积多晶硅，同时对多晶硅进行掺杂。可采用干法刻蚀工艺对沟槽120外部的多晶硅进行刻蚀形成控制栅。
本实施例所提供的沟槽分离栅器件的制作方法，通过使用高密度等离子体化学气相淀积工艺，使得沟槽底部与侧壁的第二氧化层的厚度可以通过调节反应室的压力和反应气体的流量进行调节。沟槽侧壁的浮栅氧化层厚度从上至下逐渐增厚，沟槽侧壁下部的浮栅氧化层厚度与沟槽底部的浮栅氧化层厚度相同。因此，其一方面满足了逐渐变化的耐压需求，同时，逐渐变化的浮栅氧化层厚度可以缩小沟槽宽度，从而进一步减小元胞面积，使单位面积芯片上可容纳的元胞数量增加，降低器件的比导通电阻。
请参见图3G，在沟槽内隔离层上形成控制栅的步骤之后还包括：所述P型杂质注入推结于沟槽120两侧形成P型阱区130。通过注入高掺杂N型杂质在所述沟槽120两侧的P型阱区130内形成N型重掺杂区131。然后利用热氧化法在控制栅上形成隔离氧化层140。刻蚀所述隔离氧化层140形成贯穿所述P型阱区的接触孔141，N型重掺杂区131位于接触孔141和沟槽120之间。通过接触孔141对P型阱区注入重掺杂P型杂质形成P型重掺杂区132。之后对接触孔141进行填充，最后在所述隔离氧化层140上形成源极，在本体层100下表面形成漏极，从而形成沟槽分离栅器件的基本结构。
本实施例还提供一种沟槽分离栅器件，该沟槽分离栅器件按图2所示方法步骤制造。具体的，如图3G所示，该沟槽分离栅器件包括半导体衬底，所述半导体衬底包括本体层100和外延层110。半导体衬底内设有沟槽120，沟槽120设置于外延层110内，且沟槽120侧壁上下竖直。沟槽120内壁具有浮栅氧化层，所述浮栅氧化层包括位于沟槽120内壁的第一氧化层 121，和位于第一氧化层121上的第二氧化层122。其中，位于沟槽120侧壁各处的第一氧化层121厚度为均匀的，第二氧化层122沿沟槽120侧壁从上至下逐渐变厚，沟槽120侧壁下部的第二氧化层122厚度与沟槽120底部的第二氧化层122厚度相同。因此，第一氧化层121与第二氧化层122构成的浮栅氧化层总厚度沿沟槽120侧壁从上至下逐渐变厚，沟槽120侧壁下部的浮栅氧化层厚度与沟槽120底部的浮栅氧化层厚度相同。在浮栅氧化层表面设有浮栅多晶层123。浮栅多晶层123和浮栅氧化层共同构成浮栅结构。浮栅多晶层123上表面具有隔离层124。隔离层124上设有控制栅多晶层126和控制栅氧化层125，控制栅多晶层126和控制栅氧化层125共同构成控制栅结构。
本发明实施例所提供的沟槽分离栅器件，在沟槽底部和侧壁通过采用HDP CVD工艺形成的第二氧化层，使得第二氧化层的厚度沿沟槽侧壁从上至下逐渐变厚，沟槽侧壁下部的第二氧化层厚度与沟槽底部的第二氧化层厚度相同。进而，第一氧化层和第二氧化层构成的浮栅氧化层总厚度沿沟槽侧壁从上至下逐渐变厚，沟槽侧壁下部的浮栅氧化层厚度与沟槽底部的浮栅氧化层厚度相同。因此，其一方面满足了逐渐变化的耐压需求，同时，逐渐变化的浮栅氧化层厚度可以缩小沟槽宽度，从而进一步减小元胞面积，降低器件的比导通电阻。
在另一个实施例中，刻蚀半导体衬底形成沟槽具体包括：刻蚀半导体衬底形成垂直的上半沟槽。从所述上半沟槽底部往下倾斜刻蚀半导体衬底，形成从半沟槽底部向下延伸、且宽度从上至下逐渐变宽的下半沟槽，且下半沟槽底部呈凹陷弧形。于沟槽内淀积氧化物形成浮栅氧化层的步骤包括：于沟槽内表面形成第一氧化层；刻蚀第一氧化层，使第一氧化层侧壁上下竖直；采用高密度等离子体化学气相淀积工艺于所述下半沟槽底部的第一氧化层上形成第二氧化层，以使第一氧化层和第二氧化层构成的浮栅氧化层沿沟槽侧壁从上至下逐渐变厚，下半沟槽侧壁下部的浮栅氧化层厚度与下半沟槽底部的浮栅氧化层厚度相同。
具体的，请参见图4，本实施例中沟槽分离栅器件的制造方法具体包括以下步骤：
S300：刻蚀半导体衬底形成垂直的上半沟槽。
请参见图5A，半导体衬底包括本体层200和外延层210。本实施例中，采用干法刻蚀技术垂直刻蚀半导体衬底，以在外延层210内形成垂直向下的上半沟槽221。刻蚀过程中，保留刻蚀气体与硅衬底反应生成的聚合物，用于保护上半沟槽221，在进行下一步时，上半沟槽221表面不会被刻蚀。
S310：从上半沟槽底部往下倾斜刻蚀半导体衬底，形成从所述上半沟 槽底部向下延伸、且宽度从上至下逐渐变宽的下半沟槽。
请参见图5B，同样利用干法刻蚀技术，从垂直的上半沟槽221底部往下，倾斜刻蚀外延层211，形成从上半沟槽221底部向下延、且宽度从上至下逐渐变宽的下半沟槽222，且下半沟槽222的底部呈凹陷弧形。上半沟槽221和下半沟槽222共同构成沟槽220。沟槽220刻蚀完成后，进行酸洗步骤，以去除沟槽220表面附着的刻蚀产生的聚合物。
S320：于沟槽内表面形成第一氧化层。
请参见图5C，可采用炉管氧化法或CVD工艺在沟槽220内表面氧化形成第一氧化层223。具体的，在本实施例中，采用炉管氧化法在沟槽220表面氧化生长第一氧化层223。
S330：刻蚀第一氧化层，使第一氧化层侧壁上下竖直。
生长过程完成后，对第一氧化层223进行干法刻蚀，以使沟槽内壁的第一氧化层223侧壁上下竖直，下半沟槽222侧壁的第一氧化层223厚度从上至下逐渐变厚。
S340：采用高密度等离子体化学气相淀积工艺于所述下半沟槽底部的第一氧化层上形成第二氧化层，以使第一氧化层和第二氧化层组合形成的浮栅氧化层沿沟槽侧壁从上至下逐渐变厚，沟槽侧壁下部的浮栅氧化层厚度与沟槽底部的浮栅氧化层厚度相同。
请参见图5D，采用HDP CVD淀积方式于下半沟槽222底部的第一氧化层223上淀积第二氧化层224，以加厚下半沟槽222底部的浮栅氧化层，增加器件的耐压性能。由于下半沟槽222侧壁的第一氧化层223沿下半沟槽222从上至下逐渐变厚，第二氧化层224位于下半沟槽222底部的第一氧化层223上，故第一氧化层223与第二氧化层224构成的浮栅氧化层总厚度沿下半沟槽222侧壁从上至下逐渐变厚，下半沟槽222侧壁下部的浮栅氧化层厚度与下半沟槽222底部的浮栅氧化层厚度相同。
S350：向所述沟槽内淀积多晶硅形成浮栅多晶层。
如图5E所示，在本实施例中，可采用低压化学气相淀积的方法在沟槽220内淀积多晶硅形成浮栅多晶层225。进一步的，在沟槽220内填充多晶硅后，可对多晶硅进行回刻或研磨，使得浮栅多晶层225的上表面低于后续工艺中形成的P型阱区的下表面。
S360：在所述浮栅多晶层上表面生长绝缘介质形成隔离层。
如图5F所示，可以利用热氧化法或化学气相淀积法在浮栅多晶层225上表面淀积绝缘介质形成隔离层226。绝缘介质可以是氮化硅或氧化硅或氮氧化硅，用于隔离浮栅多晶层225和后续工艺中形成的控制栅。
进一步的，在浮栅多晶层225上表面形成隔离层226的步骤之前，还 包括去除浮栅多晶层225上方的第一氧化层222的步骤。具体的，可采用干法刻蚀技术去除浮栅多晶层225上方的第一氧化层223。
S370：在沟槽内的隔离层上形成控制栅。
进一步的，如图5G所示，在沟槽220内的隔离层226上形成控制栅具体包括：在隔离层226上方的沟槽侧壁形成控制栅氧化层227；在沟槽220内的隔离层226上淀积多晶硅形成控制栅多晶层228，控制栅多晶层228邻接控制栅氧化层227；对控制栅多晶层228进行回刻或研磨，形成控制栅。其中，控制栅包括控制栅氧化层227和控制栅多晶层228。
具体的，在本实施例中，可采用低压化学气相淀积的方法在沟槽220内淀积多晶硅，同时对多晶硅进行掺杂。可采用干法刻蚀工艺对沟槽220外部的多晶硅进行刻蚀形成控制栅。
本实施例所提供的沟槽分离栅器件的制作方法，通过采用先刻蚀垂直的上半沟槽，再从上半沟槽底部往下倾斜刻蚀，形成宽度从上至下逐渐变宽的下半沟槽，所述上半沟槽和下半沟槽共同构成沟槽。然后在沟槽内壁成长第一氧化层，其中下半沟槽中第一氧化层的厚度沿下半沟槽侧壁从上至下逐渐变厚。接下来在下半沟槽底部的第一氧化层上淀积第二氧化层，用于增厚下半沟槽底部的浮栅氧化层厚度，使得第一氧化层和第二氧化层构成的浮栅氧化层总厚度沿下半沟槽侧壁从上至下逐渐变厚，下半沟槽侧壁下部的浮栅氧化层厚度与下半沟槽底部的浮栅氧化层厚度相同。因此，其一方面满足了逐渐变化的耐压需求，同时可以减小元胞面积，降低器件的比导通电阻。
请参见图5H，在沟槽内的隔离层上形成控制栅的步骤之后还包括：所述P型杂质注入推结于沟槽220两侧形成P型阱区230。通过注入高掺杂N型杂质在所述沟槽220两侧的P型阱区230内形成N型重掺杂区231。可利用热氧化法在控制栅上形成隔离氧化层240。刻蚀所述隔离氧化层240形成贯穿所述P型阱区的接触孔241，N型重掺杂区231位于接触孔241和沟槽220之间。通过接触孔241对P型阱区注入重掺杂P型杂质形成P型重掺杂区232。之后对接触孔241进行填充，最后在所述隔离氧化层240上形成源极，在本体层200下表面形成漏极，从而形成分离栅器件的基本结构。
本实施例还提供一种沟槽分离栅器件，该沟槽分离栅器件按图4所示方法步骤制造。具体的，如图5H所示，包括半导体衬底，半导体衬底包括本体层200和外延层210。外延层210内设有沟槽220。沟槽220包括侧壁上下竖直的上半沟槽221和从上半沟槽底部向下延伸且从上至下逐渐变宽的下半沟槽222，下半沟槽的底部为凹陷弧形。沟槽220内壁具有氧化层， 包括位于沟槽内壁的第一氧化层223和位于沟槽底部的第一氧化层223上的第二氧化层224。其中，位于下半沟槽222内壁的第一氧化层223厚度沿下半沟槽222侧壁从上至下逐渐变厚，第二氧化层224用于加厚下半沟槽222底部的浮栅氧化层厚度。因此，第一氧化层223和第二氧化层224构成的浮栅氧化层总厚度沿下半沟槽222侧壁从上至下逐渐变厚，下半沟槽222侧壁下部的浮栅氧化层厚度与下半沟槽222底部的浮栅氧化层厚度相同。在浮栅氧化层表面设有浮栅多晶层225。浮栅多晶层225上表面具有隔离层226。隔离层226上方的上半沟槽221侧壁具有控制栅氧化层227。控制栅多晶层228位于隔离层226上并且邻接控制栅氧化层227，控制栅氧化层227和控制栅多晶层228共同构成沟槽分立器件的控制栅。
本发明实施例所提供的沟槽分离栅器件，下半沟槽宽度从上至下逐渐变宽，生长于下半沟槽内壁的第一氧化层的厚度也从上至下逐渐变厚，第二氧化层用于加厚沟槽底部，使得第一氧化层和第二氧化层构成的浮栅氧化层总厚度沿下半沟槽侧壁从上至下逐渐变厚，下半沟槽侧壁下部的浮栅氧化层厚度与下半沟槽底部的浮栅氧化层厚度相同。因此，其一方面满足了逐渐变化的耐压需求，同时，逐渐变化的浮栅氧化层厚度可以缩小沟槽宽度，从而进一步减小元胞面积，降低器件的比导通电阻。
应该理解的是，虽然图1、图2、图4的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，其可以以其他的顺序执行。而且，图1、图2、图4中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，其执行顺序也不必然是依次进行，而是可以与其他步骤或者其他步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。

Claims (15)

  1. 一种沟槽分离栅器件的制造方法，所述方法包括：
    刻蚀半导体衬底形成沟槽；
    于所述沟槽内淀积氧化物形成浮栅氧化层，使所述浮栅氧化层沿沟槽侧壁从上至下逐渐增厚，所述沟槽侧壁下部的浮栅氧化层厚度与所述沟槽底部的浮栅氧化层厚度相同；
    向所述沟槽内淀积多晶硅形成浮栅多晶层；
    在所述浮栅多晶层上表面生长绝缘介质形成隔离层；及
    在所述沟槽内的所述隔离层上形成控制栅。
  2. 根据权利要求1所述的方法，其特征在于，刻蚀所述半导体衬底形成沟槽具体包括：垂直刻蚀所述半导体衬底，使所述沟槽侧壁上下竖直。
  3. 根据权利要求2所述的方法，其特征在于，所述于所述沟槽内淀积氧化物形成浮栅氧化层的步骤包括：
    于所述沟槽内表面形成第一氧化层；
    于所述第一氧化层上形成第二氧化层；
    控制所述第二氧化层沿沟槽侧壁从上至下逐渐变厚，所述沟槽侧壁下部的第二氧化层厚度与所述沟槽底部的第二氧化层厚度相同。
  4. 根据权利要求3所述的方法，其特征在于，位于所述沟槽内表面各处的第一氧化层厚度相同。
  5. 根据权利要求4所述的方法，其特征在于，所述控制所述第二氧化层沿沟槽侧壁从上至下逐渐变厚包括：
    通过控制反应腔室的压力和通入所述反应腔室的气体流量，使所述第二氧化层沿沟槽侧壁从上至下逐渐变厚，所述沟槽侧壁下部的第二氧化层厚度与所述沟槽底部的第二氧化层厚度相同。
  6. 根据权利要求5所述的方法，其特征在于，所述反应气体流量包括：硅烷占15％-20％，氧气占20％-25％，氢气占25％-35％，氦气占20％-40％。
  7. 根据权利要求1所述的方法，其特征在于，所述刻蚀半导体衬底形成沟槽具体包括：刻蚀所述半导体衬底形成垂直的上半沟槽；
    从所述上半沟槽底部往下倾斜刻蚀所述半导体衬底，形成从所述上半沟槽底部向下延伸、且宽度从上至下逐渐变宽的下半沟槽，且所述下半沟槽底部呈凹陷弧形，所述上半沟槽与所述下半沟槽共同构成所述沟槽。
  8. 根据权利要求7所述的方法，其特征在于，所述于沟槽内淀积氧化物形成浮栅氧化层的步骤包括：
    于所述沟槽内表面形成第一氧化层；
    刻蚀所述第一氧化层，使所述第一氧化层侧壁上下竖直；
    采用高密度等离子体化学气相淀积工艺于所述下半沟槽底部的第一氧化层上形成第二氧化层，以使所述浮栅氧化层沿下半沟槽侧壁从上至下逐渐变厚，所述下半沟槽侧壁下部的浮栅氧化层厚度与所述下半沟槽底部的浮栅氧化层厚度相同。
  9. 根据权利要求8所述的方法，其特征在于，所述于所述沟槽内表面形成第一氧化层具体包括：采用热氧化法与所述沟槽内表面形成第一氧化层。
  10. 根据权利要求1所述的方法，其特征在于，所述在所述浮栅多晶层上表面生长绝缘介质形成隔离层的步骤之前，还包括去除所述浮栅多晶层上方的第一氧化层的步骤。
  11. 根据权利要求1-10中任一项所述的方法，其特征在于，在所述沟槽内的所述隔离层上形成控制栅的步骤包括：
    在所述隔离层上方的沟槽侧壁形成控制栅氧化层；
    在所述沟槽内的所述隔离层上淀积多晶硅形成控制栅多晶层；
    对所述控制栅多晶层进行回刻或研磨，形成所述控制栅。
  12. 一种沟槽分离栅器件，包括：
    半导体衬底，所述半导体衬底内设有沟槽；
    浮栅氧化层，设于所述沟槽内壁，所述浮栅氧化层厚度沿沟槽侧壁至沟槽底部逐渐变厚，所述沟槽侧壁下部的浮栅氧化层厚度与所述沟槽底部的浮栅氧化层厚度相同；
    浮栅多晶层，设于所述浮栅氧化层表面；
    隔离层，设于所述浮栅多晶层上；控制栅，设于所述隔离层上，用于控制器件的导通与关断。
  13. 根据权利要求12所述的沟槽分离栅器件，其特征在于，所述沟槽侧壁上下竖直，所述浮栅氧化层包括位于所述沟槽内壁的第一氧化层，和位于所述第一氧化层上沿沟槽侧壁从上至下逐渐变厚的第二氧化层，其中，所述沟槽内壁各处的第一氧化层厚度相同；
    所述沟槽侧壁下部的第二氧化层厚度与所述沟槽底部的第二氧化层厚度相同。
  14. 根据权利要求13所述的沟槽分离栅器件，其特征在于，所述沟槽包括上半沟槽和下半沟槽，所述下半沟槽宽度从所述隔离层位置至所述下半沟槽底部位置逐渐变宽，且所述下半沟槽底部呈凹陷弧形。
  15. 根据权利要求14所述的沟槽分离栅器件，其特征在于，所述浮栅氧化层包括位于所述沟槽内壁的第一氧化层，和位于所述沟槽底部位置且设置于所述第一氧化层上的第二氧化层，所述第一氧化层沿下半沟槽侧壁 从上至下逐渐变厚。
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