WO2021228269A1 - 埋入式字线结构制备方法 - Google Patents

埋入式字线结构制备方法 Download PDF

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Publication number
WO2021228269A1
WO2021228269A1 PCT/CN2021/096669 CN2021096669W WO2021228269A1 WO 2021228269 A1 WO2021228269 A1 WO 2021228269A1 CN 2021096669 W CN2021096669 W CN 2021096669W WO 2021228269 A1 WO2021228269 A1 WO 2021228269A1
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Prior art keywords
trench
layer
semiconductor substrate
epitaxial growth
word line
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PCT/CN2021/096669
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English (en)
French (fr)
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陆勇
沈宏坤
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长鑫存储技术有限公司
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Priority to US17/445,595 priority Critical patent/US20220037478A1/en
Publication of WO2021228269A1 publication Critical patent/WO2021228269A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • the invention relates to the field of semiconductors, and in particular to a method for preparing a buried word line structure and a buried word line structure.
  • the conventional process of forming the buried word line structure is: etching the semiconductor substrate to open a first trench on the semiconductor substrate, and filling the word line structure in the first trench to form a buried word line structure.
  • Type word line structure since the etching environment inside the first trench is difficult to control, the semiconductor substrate at different positions is etched unevenly, and the bottom of the first trench formed by the etching is uneven. Tips or burrs are prone to appear at the bottom of the groove. For semiconductor devices, a tip appears at the bottom of the word line, which is prone to tip discharge and damage the semiconductor device.
  • One aspect of the present application provides a method for preparing a buried word line structure, including:
  • a gate dielectric layer is formed on the inner wall of the first trench and a gate conductive layer is filled in the first trench to form a buried word line structure.
  • a buried word line structure including:
  • a trench isolation structure formed on the semiconductor substrate, and a surface layer of the semiconductor substrate is divided into a plurality of independent regions by the trench isolation structure;
  • a first trench is opened on the semiconductor substrate, and the bottom of the first trench is flat;
  • the second trench is opened on the trench isolation structure, the bottom of the second trench has a tip, the first trench and the second trench communicate with each other to form a communication trench, the first trench
  • the depth of the second groove is greater than the depth of the first groove
  • the gate conductive layer is filled in the first trench and the second trench.
  • FIG. 1 is a flowchart of steps of a method for preparing a buried word line according to an embodiment
  • FIG. 2 is a schematic diagram of an embodiment after a mask layer is formed on a semiconductor substrate
  • 3a is a top view of the positional relationship of a semiconductor substrate, a trench isolation structure, and a communication trench according to an embodiment
  • Figure 3b is a side cross-sectional view of an embodiment along the BB' section line in Figure 3a;
  • FIG. 4 is a schematic diagram of the structure after epitaxial growth according to an embodiment
  • FIG. 5 is a schematic structural diagram of an embodiment after a gate dielectric layer and a conductive liner layer are sequentially formed on the inner wall of the first trench and the wall of the second trench;
  • Fig. 6 is a schematic diagram of an embodiment after the main conductive layer is deposited
  • FIG. 7 is a schematic diagram of a buried word line structure formed according to an embodiment.
  • FIG. 1 is a flow chart of the steps of a method for preparing a buried word line structure in an embodiment of the application, wherein the method for preparing a buried word line structure includes the following steps.
  • Step S100 A first trench is opened on the semiconductor substrate, and the bottom of the first trench has a tip.
  • a semiconductor substrate 100 is provided.
  • the constituent material of the semiconductor substrate 100 can be monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), or germanium-on-insulator. Silicon (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc.
  • the constituent material of the semiconductor substrate 100 is single crystal silicon.
  • a mask layer is formed on the semiconductor substrate 100, and an etching window is defined on the upper surface of the semiconductor substrate 100 through the mask layer.
  • the mask layer can be a single layer or multiple layers, and different selections can be made according to process requirements.
  • the mask layer has three stacked layers, and the mask layer includes a first mask layer 210, a second mask layer 220, and a third mask layer 230 that are sequentially stacked on the semiconductor substrate 100.
  • the first mask layer 210 is silicon nitride
  • the second mask layer 220 is spin-coated carbon
  • the third mask layer 230 is silicon oxynitride. It can be understood that the surface of the semiconductor substrate 100 is easily oxidized.
  • a thin silicon oxide layer is also formed on the surface of the semiconductor substrate 100.
  • a photoresist layer 240 is also formed on the third mask layer 230.
  • the photoresist layer 240 defines an etching window for the third mask layer 230 on the third mask layer 230, and the third mask layer 230 is etched in sequence.
  • the mask layer 230, the second mask layer 220 and the first mask layer 210 are etched, the etching window is moved down to the first mask layer 210 and the semiconductor substrate 100 to be etched is exposed, and then the semiconductor substrate 100 is exposed.
  • the substrate 100 is etched.
  • a first trench 121 is formed on the semiconductor substrate 100.
  • the etching ions at the bottom are relatively small, resulting in a sharp tip at the bottom of the first trench 121.
  • the second mask layer 220, the third mask layer 230, and the photoresist layer 240 may be removed.
  • a trench isolation structure 110 extending into the semiconductor substrate 100 is formed on the semiconductor substrate 100, and the trench isolation structure 110 can be specifically formed by opening an isolation depth in the semiconductor substrate 100.
  • the groove is formed by filling the isolation material in the isolation deep groove.
  • the trench isolation structure 110 includes one or more of isolation materials such as silicon nitride, silicon oxide, and silicon oxynitride.
  • the trench isolation structure 110 includes silicon oxide.
  • a plurality of independent regions are divided on the semiconductor substrate 100 by the trench isolation structure 110 to form an active region. In one embodiment, as shown in FIG. 3a and FIG.
  • the semiconductor substrate 100 and the trench isolation structure 110 may be etched respectively to form first trenches 121 in the semiconductor substrate 100, and A second trench 122 is defined in the isolation structure 110, and the second trench 122 and the first trench 121 communicate with each other to form a communication trench 120. Further, the depth of the first trench 121 is smaller than the depth of the second trench 122. As shown in FIG. 3a, a plurality of communicating trenches 120 are arranged side by side along the X-axis direction, each communicating trench 120 extends laterally along the Y-axis direction, and the same communicating trench 120 laterally penetrates the semiconductor substrate 100 and the trenches along the Y-axis direction.
  • the X-axis direction is different from the Y-axis direction, that is, the included angle between the X-axis direction and the Y-axis direction is greater than 0° and less than 180°.
  • the X-axis is perpendicular to the Y-axis.
  • the trench opened on the semiconductor substrate 100 is the first trench 121
  • the trench opened on the trench isolation structure 110 is the second trench 122.
  • first groove 121 and the second groove 122 shown in FIG. 3b are on different communicating grooves 120, therefore, the first groove 121 and the second groove shown in FIG. 3b The groove 122 is not connected.
  • Step S200 Perform epitaxial growth in the first trench to reduce the depth of the bottom tip of the first trench.
  • the epitaxial growth is performed to grow an epitaxial layer on the inner wall of the first trench 121.
  • the epitaxial growth rate at the bottom tip of the first trench 121 is greater than the epitaxial growth rate at the sidewall of the first trench 121.
  • the layer quickly fills the bottom tip of the first trench 121 to make the bottom of the first trench 121 gradually flat. Further, the depth of the bottom tip of the first trench 121 can be reduced by epitaxial growth until the bottom tip of the first trench 121 disappears, that is, the bottom tip of the first trench 121 is filled with the epitaxial layer, and the first trench after the epitaxial growth 121 has a flat bottom.
  • the opening width of the first trench 121 ranges from 30 nm to 50 nm, and the depth range of the first trench 121 ranges from 60 nm to 80 nm.
  • the smaller the width of the trench opening the smaller the bottom tip angle. The faster the growth fills the tip, but the smaller the trench opening width will affect the filling of the word line structure.
  • the first trench 121 within the above-mentioned size can quickly eliminate the tip through epitaxial growth.
  • the word line structure can be filled in smoothly.
  • the mask layer formed in step S100 is not completely removed.
  • the first mask layer 210 of the mask layer covers the semiconductor substrate 100 outside the trench, and When epitaxial growth is performed in the trench 121, the mask layer is used as a protective layer to avoid epitaxial growth on the surface of the semiconductor substrate 100 outside the first trench 121, that is, the structure formed in step S100 is placed in the epitaxial chamber, and only the first An epitaxial layer is grown in the trench 121, and other areas are not affected.
  • an epitaxial layer may also be grown on the surface of the semiconductor substrate 100 outside the trench, and after the epitaxial growth is completed, the epitaxial layer outside the trench is polished away by a polishing process.
  • the trench isolation structure 110 is provided with a second trench 122. Since the epitaxial growth only occurs on the semiconductor substrate 100, no epitaxial growth is performed in the second trench 122, that is, the second trench 122 The depth of the trench 122 is not affected by epitaxial growth. After the epitaxial growth, the depth of the first trench 121 becomes shallower, the depth difference between the first trench 121 and the second trench 122 becomes larger, and the width of the conductive channel increases, so that the saturation current of the device can be increased.
  • the inner wall of the first trench 121 needs to be cleaned in situ.
  • the above structure is exposed to the air, and there may be an oxide layer and impurities (such as particles, organics, inorganic metal ions) on the inner wall of the first trench 121.
  • oxides and impurities will affect the epitaxial growth. Therefore, the inner wall of the first groove 121 needs to be cleaned in situ.
  • liquid No. 1 can be used to remove fine particles.
  • Liquid No. 1 is made up of NH 4 OH with a concentration of 28%, H 2 O 2 with a concentration of 30%, and deionized water.
  • DHF diluted HF
  • the above-mentioned epitaxial growth has selective chemical vapor epitaxial growth, and the growth rate of chemical vapor epitaxial growth is relatively fast and easy to control.
  • Step S300 A gate dielectric layer is formed on the inner wall of the first trench and a gate conductive layer is filled in the first trench 121 to form a buried word line structure.
  • a gate dielectric layer 130 is formed on the inner wall of the first trench 121.
  • the gate dielectric layer 130 may be an oxide layer, or may be other high dielectric constant dielectric materials.
  • an oxide layer may be formed on the inner wall of the first trench 121 as the gate dielectric layer 130 by a thermal oxidation process.
  • an in-situ steam generation (ISSG) method can also be used to grow an oxide layer in a high-temperature water vapor atmosphere to serve as the gate dielectric layer 130. This method grows the oxide layer at a faster rate.
  • the oxide layer generated by the in-situ water vapor generation method has better electrical properties.
  • the gate dielectric layer 130 may also be formed by a deposition process, for example, the gate dielectric layer 130 may be formed by an atomic layer deposition process.
  • the trench is filled with a gate conductive layer 140 (see FIG. 7), and the gate dielectric layer 130 and the gate conductive layer 140 can form a word line structure.
  • the gate conductive layer 140 includes a conductive liner layer 141 and a main conductive layer 142.
  • the conductive liner layer 141 is formed on the gate dielectric layer 130 through a deposition process, specifically, an atomic layer deposition process, a chemical vapor deposition process, etc. may be selected.
  • the conductive liner layer 141 may be a titanium nitride film.
  • the main conductive layer 142 is continuously filled in the first trench 121 through the deposition process.
  • the main conductive layer 142 may specifically be a metal layer, such as metal tungsten.
  • the main conductive layer 142 deposited by the deposition process not only fills the first trench 121, but also extends beyond the first trench 121 and covers the structure outside the first trench 121. At this time, The grinding process removes the main conductive layer 142 outside the first trench 121.
  • the conductive liner layer 141 covers the entire inner wall of the first trench 121 and the main conductive layer 142 fills the first trench 121.
  • the upper surface of the main conductive layer 142 and the conductive liner 141 are flush.
  • continue The conductive liner layer 141 and the main conductive layer 142 are etched back to reduce the height of the conductive liner layer 141 and the main conductive layer 142, as shown in FIG. 7.
  • the etching selection ratio of the etching agent selected for the etching back to the conductive liner layer 141 and the main conductive layer 142 is greater than 1, that is, the etching speed of the etching agent on the conductive liner layer 141 is greater than that of the main conductive layer 142
  • the middle area of the gate conductive layer 140 after the etch-back is raised upward, and the upper surface of the gate conductive layer 140 is ⁇ -shaped.
  • the above-mentioned etch-back can select isotropic etching. Through isotropic etching, the gate conductive layer 140 can be etched from the side, which makes it easier to control the upper surface of the gate conductive layer 140 to be ⁇ -shaped.
  • the above isotropic etching is dry etching, and the etchant includes NF 3 and Cl 2 .
  • the dry etching is easy to control, and the etching conditions can be adjusted in real time, so that the gate conductive layer 140 has a better etching morphology.
  • the upper surface of the gate conductive layer 140 is ⁇ -shaped, and after the source region and the drain region are formed on both sides of the word line structure, the overlap area of the word line structure and the drain region can be reduced, thereby reducing leakage and improving Device performance.
  • the semiconductor substrate 100 is provided with a first trench 121 and the trench isolation structure 110 is also provided with a second trench 122.
  • the conductive liner layer 141 and the main conductive layer 142 are deposited by a deposition process.
  • the conductive liner layer 141 and the main conductive layer 142 are formed in the trench 121 and the second trench 122, and when the conductive liner layer 141 and the main conductive layer 142 are etched through the etch-back process, the first trench 121 and the second trench Both the conductive liner layer 141 and the main conductive layer 142 in the groove 122 will be etched.
  • the mask layer on the surface of the semiconductor substrate 100 may be removed to expose the surface of the semiconductor substrate 100, and then the semiconductor substrate 100 may be doped to be embedded A source region and a drain region are formed on both sides of the word line, thereby forming a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Further, the drain area is connected to the bit line, a storage capacitor is formed above the source area, and the bottom plate of the storage capacitor is electrically connected to the source area to form a semiconductor memory, such as a dynamic random access memory (DRAM). Of course, Other types of memory can also be formed.
  • DRAM dynamic random access memory
  • the first trench 121 is formed by an epitaxial growth process. In-grown epitaxial layer.
  • the epitaxial growth rate of the bottom tip of the first trench 121 is greater than the epitaxial growth rate of the sidewall of the first trench 121, so a thicker epitaxial layer can be grown faster at the tip to fill the tip.
  • the depth of the tip of the bottom of the first trench 121 becomes smaller, and the bottom of the first trench 121 tends to be flat, thereby reducing the tip discharge phenomenon and improving the stability of the device.
  • the depth of the first trench 121 becomes shallower, which can increase the height difference between the bottom of the first trench 121 and the bottom of the second trench 122, thereby increasing the width of the conductive channel, and then increasing the saturation current of the switch tube. Improve the electrical performance of the device.
  • the present application also relates to a buried word line structure.
  • the buried word line structure includes:
  • semiconductor substrate 100 specifically, the constituent material of the above-mentioned semiconductor substrate 100 can be monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon germanium-on-insulator (S -SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.
  • the constituent material of the semiconductor substrate 100 is single crystal silicon.
  • the trench isolation structure 110 is formed on the semiconductor substrate 100, and the surface layer of the semiconductor substrate 100 is divided into a plurality of independent regions by the trench isolation structure 110.
  • a trench isolation structure 110 extending into the semiconductor substrate 100 is formed on the semiconductor substrate 100.
  • the trench isolation structure 110 can be specifically formed by opening deep isolation trenches in the semiconductor substrate 100 and The isolation deep groove is filled with isolation material.
  • the trench isolation structure 110 includes one or more of isolation materials such as silicon nitride, silicon oxide, and silicon oxynitride.
  • the trench isolation structure 110 includes silicon oxide.
  • a plurality of independent regions are divided on the semiconductor substrate 100 by the trench isolation structure 110 to form an active region.
  • the first trench 121 is opened on the semiconductor substrate 100, and the bottom of the first trench 121 is flat;
  • the second trench 122 is opened on the trench isolation structure 110, the bottom of the second trench 122 has a tip, and the first trench 121 and the second trench 122 located in the same extending direction are mutually Connected to form a communicating groove 120, and the depth of the second groove 122 is greater than the depth of the first groove 121.
  • the connecting trench 120 laterally penetrates the semiconductor substrate 100 and the trench isolation structure 110 located in the extending direction of its length, wherein the trench opened on the semiconductor substrate 100 is the first trench 121.
  • the trench opened on the trench isolation structure 110 is the second trench 122, and the first trench 121 and the second trench 122 are in communication with each other.
  • the gate dielectric layer 130 is formed on the inner wall of the first trench 121.
  • the gate dielectric layer 130 may be an oxide layer, or may be other high dielectric constant dielectric materials.
  • the gate conductive layer 140 is filled in the first trench 121 and the second trench 122.
  • the gate conductive layer 140 includes a conductive liner layer 141 and a main conductive layer 142, wherein the conductive liner layer 141 is sandwiched between the main conductive layer 142 and the gate dielectric layer 130.
  • the conductive liner layer 141 may be a titanium nitride film.
  • the main conductive layer 142 may specifically be a metal layer, such as metal tungsten.
  • a trench isolation structure 110 is formed on the semiconductor substrate 100.
  • the trench isolation structure 110 divides the semiconductor substrate 100 into a plurality of independent regions to form a plurality of active regions.
  • the semiconductor substrate 100 A first trench 121 is formed on the trench isolation structure 110, a second trench 122 is formed on the trench isolation structure 110, the first trench 121 and the second trench 122 communicate with each other to form a communication trench 120, and a gate conductive layer is formed in the communication trench 120 140, so that multiple active regions can be controlled by one communication trench 120.
  • the bottom of the first trench 121 is flat, which can avoid tip discharge, while the bottom of the second trench 122 has a tip, which is generated in the trench isolation structure 110, and no tip discharge occurs, leaving the second trench 122
  • the height difference between the bottom of the first trench 121 and the bottom of the second trench 122 is larger, which can increase the width of the conductive trench and increase the saturation current of the device.
  • the upper surface of the gate conductive layer 140 is ⁇ -shaped. After the source region and the drain region are formed on both sides of the word line structure, the overlap area between the word line structure and the drain region can be reduced, thereby reducing leakage and improving the device. performance.
  • the active region and the drain region are formed on both sides of the buried word line, and the buried word line structure, the source region and the drain region form a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Field effect tube).
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • Field effect tube Further, the drain area is connected to the bit line, a storage capacitor is formed above the source area, and the bottom plate of the storage capacitor is electrically connected to the source area to form a semiconductor memory, such as a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • Other types of memory can also be formed.

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Abstract

本申请涉及一种埋入式字线结构及其制备方法，其中，制备方法包括：在半导体衬底上开设第一沟槽，第一沟槽底部具有尖端；在第一沟槽内进行外延生长，减小第一沟槽底部尖端的深度；以及在第一沟槽内壁上形成栅介质层并在第一沟槽内填入栅导电层，形成埋入式字线结构。

Description

埋入式字线结构制备方法
本申请要求于2020年5月15日提交的申请号为202010410658.5、名称为“埋入式字线结构制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体领域，尤其涉及一种埋入式字线结构制备方法及埋入式字线结构。
背景技术
在半导体工艺制程中，形成埋入式字线结构的常规工序为：刻蚀半导体衬底以在半导体衬底上开设第一沟槽，在第一沟槽内填入字线结构以形成埋入式字线结构。然而，在刻蚀半导体衬底期间，由于第一沟槽内部的刻蚀环境难以控制，对不同位置的半导体衬底刻蚀并不均匀，刻蚀形成的第一沟槽底部不平整，第一沟槽底部容易出现尖端或毛刺。对于半导体器件，字线底部出现尖端，容易发生尖端放电而损伤半导体器件。
发明内容
本申请一方面提供一种埋入式字线结构制备方法，包括：
在半导体衬底上开设第一沟槽，所述第一沟槽底部具有尖端；
在所述第一沟槽内进行外延生长，减小所述第一沟槽底部尖端的深度；以及
在所述第一沟槽内壁上形成栅介质层并在所述第一沟槽内填入栅导电层，形成埋入式字线结构。
本申请另一方面提供一种埋入式字线结构，包括：
半导体衬底；
沟槽隔离结构，形成于所述半导体衬底上，所述半导体衬底的表层被所述沟槽隔离结构划分出多个独立的区域；
第一沟槽，开设于所述半导体衬底上，所述第一沟槽的底部平整；
第二沟槽，开设于所述沟槽隔离结构上，所述第二沟槽的底部具有尖端，所述第一沟槽和所述第二沟槽相互连通以形成连通沟槽，所述第二沟槽的深度大于所述第一沟槽的深度；
栅介质层，形成于所述第一沟槽的内壁上；
栅导电层，填充于所述第一沟槽和所述第二沟槽内。
本发明的一个或多个实施例的细节在下面的附图和描述中提出。本发明的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明本申请的实施例，可参考一幅或多幅附图，但用于描述附图的附加细节或示例不应当被认为是对本申请的发明创造、目前所描述的实施例或优选方式中任何一者的范围的限制。
图1为一实施例的埋入式字线制备方法的步骤流程图；
图2为一实施例的在半导体衬底上形成掩膜层后的示意图；
图3a为一实施例的半导体衬底、沟槽隔离结构以及连通沟槽的位置关系俯视图；
图3b为一实施例的沿图3a中的BB’剖面线的侧剖图；
图4为一实施例的进行外延生长后的结构示意图；
图5为一实施例的在第一沟槽内壁和第二沟槽壁上依次形成栅介质层和导电衬层后的结构示意图；
图6为一实施例的沉积主导电层后的示意图；
图7为一实施例的所形成的埋入式字线结构的示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。
如图1所示为本申请一实施例中埋入式字线结构制备方法的步骤流程图，其中，埋入式字线结构制备方法包括以下步骤。
步骤S100：在半导体衬底上开设第一沟槽，所述第一沟槽底部具有尖端。
如图2所示，提供半导体衬底100，半导体衬底100的构成材料可以采用掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，半导体衬底100的构成材料选用单晶硅。
在半导体衬底100上形成掩膜层，通过掩膜层在半导体衬底100上表面定 义出刻蚀窗口。其中，掩膜层可为单层，也可为多层，可根据工艺要求进行不同的选择。在本实施例中，掩膜层具有叠设的三层，掩膜层包括依次叠设于半导体衬底100上的第一掩膜层210、第二掩膜层220和第三掩膜层230，其中，第一掩膜层210为氮化硅，第二掩膜层220为旋涂碳，第三掩膜层230为氮氧化硅。可以理解的，在半导体衬底100表面容易被氧化，因此，在半导体衬底100表面还形成有薄氧化硅层。进一步的，第三掩膜层230上还形成有光刻胶层240，通过光刻胶层240在第三掩膜层230上定义出第三掩膜层230的刻蚀窗口，依次对第三掩膜层230、第二掩膜层220和第一掩膜层210进行刻蚀，将刻蚀窗口下移至第一掩膜层210并暴露出待刻蚀的半导体衬底100，然后对半导体衬底100进行刻蚀，如图3b所示，在半导体衬底100上形成第一沟槽121。此时，由于第一沟槽121内部刻蚀不均匀，底部的刻蚀离子较小，导致第一沟槽121底部出现尖端。在一实施例中，在对半导体衬底100刻蚀出第一沟槽121后，第二掩膜层220、第三掩膜层230和光刻胶层240可被去除。
在一实施例中，如图2所示，半导体衬底100上形成有延伸至半导体衬底100内的沟槽隔离结构110，沟槽隔离结构110具体可通过在半导体衬底100内开设隔离深槽并在隔离深槽内填充隔离材料所形成。具体的，沟槽隔离结构110包括氮化硅、氧化硅、氮氧化硅等隔离材料中的一种或几种，在本实施例中，沟槽隔离结构110包括氧化硅。通过沟槽隔离结构110在半导体衬底100上划分出多个独立的区域以形成有源区。在一实施例中，结合图3a和图3b所示，可分别对半导体衬底100和沟槽隔离结构110进行刻蚀，以分别在半导体衬底100中开设第一沟槽121，在沟槽隔离结构110中开设第二沟槽122，第二沟槽122和第一沟槽121相互连通形成连通沟槽120。进一步的，第一沟槽121的深度小于第二沟槽122的深度。如图3a所示，多个连通沟槽120沿X轴方向并列 分布，各连通沟槽120沿Y轴方向横向延伸，同一连通沟槽120沿Y轴方向横向穿透半导体衬底100和沟槽隔离结构110，X轴方向不同于Y轴方向，即X轴方向与Y轴方向之间的夹角大于0°小于180°，可选的，X轴垂直于Y轴。其中，开设于半导体衬底100上的沟槽为第一沟槽121，开设于沟槽隔离结构110上的沟槽为第二沟槽122。后续在沟槽内填充字线结构时，可同时对半导体衬底100内的第一沟槽121以及沟槽隔离结构110内的第二沟槽122进行填充，即在连通沟槽120内形成字线结构，从而通过同一字线结构同时控制多个有源区的通断。需要说明的是，图3b中示出的第一沟槽121和第二沟槽122处于不同的连通沟槽120上，因此，在图3b中的所示出的第一沟槽121和第二沟槽122并不连通。
步骤S200：在所述第一沟槽内进行外延生长，减小所述第一沟槽底部尖端的深度。
如图4所示，进行外延生长，在第一沟槽121内壁上生长出外延层，其中，第一沟槽121底部尖端的外延生长速度大于第一沟槽121侧壁的外延生长速度，外延层迅速对第一沟槽121底部尖端进行填充以使第一沟槽121底部逐渐平坦。进一步的，可通过外延生长减小第一沟槽121底部尖端的深度直至第一沟槽121底部尖端消失，即第一沟槽121底部尖端被外延层填充，且外延生长后的第一沟槽121具有平坦的底部。在一实施例中，第一沟槽121的开口宽度范围为30nm～50nm，所述第一沟槽121的深度范围为60nm～80nm，沟槽开口宽度越小，底部尖端角度越小，通过外延生长对尖端的填充速度越快，然而沟槽开口宽度过小将会影响字线结构的填充，在本实施例中，处于上述尺寸内的第一沟槽121，既可通过外延生长迅速消除尖端，又能顺利填入字线结构。
在一实施例中，在步骤S100中形成的掩膜层未被完全去除，如图4所示， 掩膜层的第一掩膜层210覆盖沟槽外的半导体衬底100，在第一沟槽121内进行外延生长时，以掩膜层作为保护层，可以避免第一沟槽121外的半导体衬底100表面进行外延生长，即将步骤S100所形成的结构置于外延腔室内，仅第一沟槽121内生长出外延层，其他区域并不受影响。在其他实施例中，也可以在沟槽外的半导体衬底100表面生长外延层，在完成外延生长后再通过研磨工艺将沟槽外的外延层研磨掉。
在一实施例中，沟槽隔离结构110上开设有第二沟槽122，由于外延生长仅发生与半导体衬底100上，因此，在第二沟槽122内不会进行外延生长，即第二沟槽122的深度不受外延生长的影响。在外延生长之后，第一沟槽121深度变浅，第一沟槽121和第二沟槽122的深度差值变大，导电沟道的宽度增加，从而可以增大器件的饱和电流。
在一实施例中，在外延生长之前，还需要对第一沟槽121内壁进行原位清洁。在外延生长之前，上述结构暴露于空气中，在第一沟槽121内壁上可能会具有氧化层以及杂质(如颗粒、有机物、无机物金属离子)，氧化物以及杂质的存在会影响外延生长的效果，因此，需要对第一沟槽121内壁进行原位清洁。具体的，可利用一号液去除微颗粒，一号液由浓度为28％的NH 4OH、浓度为30％的H 2O 2和去离子水配制而成，其中，一号液各成分的体积比为NH 4OH：H 2O 2：H 2O＝1：1：5；利用二号液去除金属离子，二号液由HCI、H 2O 2和去离子水配制而成，其中，二号液各成分的体积比为HCI：H 2O 2：H 2O＝1：1：6；利用三号液去除有机物，三号液由H 2SO 4和H 2O 2配制而成，其中，三号液各成分的体积比为H 2SO 4：H 2O 2＝4：1；利用稀释的HF(DHF)去除氧化层。
在一实施例中，上述外延生长具有选择化学气相外延生长，化学气相外延生长的生长速度较快且易于控制。在一实施例中，化学气相外延生长所使用的 反应气体包括SiCl 4和H 2，反应方程式为SiCl 4+H 2＝Si+4HCl，其具体工艺流程包括：将半导体衬底100置于外延腔室中，通入N 2以使半导体衬底100处于惰性气体环境中，然后在通入SiCl 4和H 2，将外延腔室的温度上升至1100℃～1300℃，例如1200℃，进行预设时长的外延生长，可根据所要生长的外延层的厚度决定外延生长的时长，等到预设时间后，通入H 2进行冲洗并降温，再通入N 2进行冲洗，当半导体衬底100温度降到300℃以下时，取出半导体衬底100，完成外延生长。
步骤S300：在第一沟槽内壁上形成栅介质层并在所述第一沟槽121内填入栅导电层，形成埋入式字线结构。
如图5所示，在第一沟槽121的内壁上形成栅介质层130。具体的，栅介质层130可为氧化层，也可为其他高介电常数的介质材料。在一实施例中，可通过热氧化工艺在第一沟槽121的内壁上形成氧化层作为栅介质层130。在另一实施例中，也可以通过原位水汽生成(In-Situ Steam Generation，ISSG)方法，在高温水汽氛围中生长氧化层以作为栅介质层130，该方法生长氧化层的速度较快，且通过原位水汽生成方法所生成的氧化层，其电性性能更好。在其他实施例中，也可以通过沉积工艺形成栅介质层130，例如通过原子层沉积工艺形成栅介质层130。
在形成栅介质层130后，继续向沟槽内填入栅导电层140(参图7)，栅介质层130和栅导电层140便能形成字线结构。在一实施例中，结合图5和图6所示，栅导电层140包括导电衬层141和主导电层142。在一实施例中，在形成栅介质层130后，通过沉积工艺在栅介质层130上形成导电衬层141，具体可选择原子层沉积工艺、化学气相沉积工艺等。具体的，该导电衬层141可为氮化钛膜。在形成导电衬层141后，继续通过沉积工艺在第一沟槽121内填入主导 电层142，该主导电层142具体可为金属层，例如金属钨。在一实施例中，通过沉积工艺沉积的主导电层142除了填满第一沟槽121外，还超出第一沟槽121并覆盖于第一沟槽121外的结构上，此时，可通过研磨工艺去除第一沟槽121外的主导电层142。
在一实施例中，导电衬层141覆盖整个第一沟槽121内壁且主导电层142填满第一沟槽121，主导电层142和导电衬层141的上表面齐平，此时，继续对导电衬层141和主导电层142进行回刻，减小导电衬层141和主导电层142的高度，如图7所示。具体的，回刻所选用的刻蚀剂对导电衬层141和主导电层142的刻蚀选择比大于1，即刻蚀剂对导电衬层141的刻蚀速度大于对主导电层142的刻蚀速率，由此使得回刻后的栅导电层140的中间区域向上凸起，栅导电层140的上表面呈Ω状。进一步的，上述回刻可选择各向同性刻蚀，通过各向同性刻蚀，可从侧面对栅导电层140进行刻蚀，更容易控制栅导电层140的上表面呈Ω状。具体的，上述各向同性刻蚀为干法刻蚀，其刻蚀剂包括NF 3和Cl 2。干法刻蚀易于控制，能够实时调整刻蚀条件，使栅导电层140具有较好的刻蚀形貌。在上述实施例中，使栅导电层140的上表面呈Ω状，字线结构两侧形成源区和漏区后，能够减小字线结构与漏区的重叠面积，从而减小漏电，改善器件性能。
在一实施例中，半导体衬底100上开设有第一沟槽121且沟槽隔离结构110上也开设有第二沟槽122，通过沉积工艺沉积导电衬层141、主导电层142，第一沟槽121和第二沟槽122内均会形成导电衬层141和主导电层142，且通过回刻工艺刻蚀导电衬层141和主导电层142时，第一沟槽121和第二沟槽122内的导电衬层141和主导电层142均会被刻蚀。
在一实施例中，在形成埋入式字线结构之后，可以去除半导体衬底100表 面的掩膜层，暴露出半导体衬底100表面，然后对半导体衬底100进行掺杂，以在埋入式字线两侧形成源区和漏区，从而形成MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金属氧化物半导体场效应管)。进一步的，漏区与位线连接，在源区上方形成存储电容器，存储电容器的下极板与源区电连接，则可以形成半导体存储器，例如可形成动态随机存取存储器(DRAM)，当然，也可以形成其他类型的存储器。
上述埋入式字线结构制备方法，在半导体衬底100上开设第一沟槽121后，以及在往第一沟槽121内填充字线结构之前，先通过外延生长工艺在第一沟槽121内生长外延层。在外延生长过程中，第一沟槽121底部尖端的外延生长速度大于第一沟槽121侧壁的外延生长速度，因此可以较快在尖端处生长出较厚的外延层以对尖端进行填充。进行外延生长后，第一沟槽121底部尖端深度变小，第一沟槽121底部趋近平坦，由此可以减小尖端放电现象，提高器件的稳定性。同时，第一沟槽121深度变浅，可以增大第一沟槽121底部和第二沟槽122底部之间的高度差，从而增大导电沟道的宽度，继而提升开关管的饱和电流，改善器件电性性能。
本申请还涉及一种埋入式字线结构，如图7所示，该埋入式字线结构包括：
半导体衬底100；具体的，上述半导体衬底100的构成材料可以采用掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，半导体衬底100的构成材料选用单晶硅。
沟槽隔离结构110，形成于所述半导体衬底100上，所述半导体衬底100的表层被所述沟槽隔离结构110划分出多个独立的区域。结合图3a和图3b所示，半导体衬底100上形成有延伸至半导体衬底100内的沟槽隔离结构110，沟槽隔 离结构110具体可通过在半导体衬底100内开设隔离深槽并在隔离深槽内填充隔离材料所形成。具体的，沟槽隔离结构110包括氮化硅、氧化硅、氮氧化硅等隔离材料中的一种或几种，在本实施例中，沟槽隔离结构110包括氧化硅。通过沟槽隔离结构110在半导体衬底100上划分出多个独立的区域以形成有源区。
第一沟槽121，开设于所述半导体衬底100上，所述第一沟槽121的底部平整；
第二沟槽122，开设于所述沟槽隔离结构110上，所述第二沟槽122的底部具有尖端，位于同一延伸方向的所述第一沟槽121和所述第二沟槽122相互连通以形成连通沟槽120，第二沟槽122的深度大于第一沟槽121的深度。结合图3a和图3b所示，连通沟槽120横向穿透位于其长度延伸方向的半导体衬底100和沟槽隔离结构110，其中，开设于半导体衬底100上的沟槽为第一沟槽121，开设于沟槽隔离结构110上的沟槽为第二沟槽122，第一沟槽121和第二沟槽122相互连通。
栅介质层130，形成于所述第一沟槽121的内壁上。具体的，栅介质层130可为氧化层，也可为其他高介电常数的介质材料。
栅导电层140，填充于所述第一沟槽121和所述第二沟槽122内。在一实施例中，栅导电层140包括导电衬层141和主导电层142，其中，导电衬层141夹设于主导电层142和栅介质层130之间。具体的，该导电衬层141可为氮化钛膜。该主导电层142具体可为金属层，例如金属钨。
上述埋入式字线结构，在半导体衬底100上形成沟槽隔离结构110，沟槽隔离结构110将半导体衬底100划分为多个独立的区域以形成多个有源区，半导体衬底100上开设第一沟槽121，沟槽隔离结构110上开设第二沟槽122，第一 沟槽121和第二沟槽122相互连通形成连通沟槽120，连通沟槽120内形成有栅导电层140，由此可以通过一个连通沟槽120控制多个有源区。同时，第一沟槽121底部平整，可以避免尖端放电，而第二沟槽122底部具有尖端，该尖端生成于沟槽隔离结构110中，并不会发生尖端放电，保留第二沟槽122内的尖端，使第一沟槽121底部和第二沟槽122底部的高度差较大，可以增大导电沟槽的宽度，增大器件的饱和电流。
在一实施例中，栅导电层140的上表面呈Ω状，字线结构两侧形成源区和漏区后，能够减小字线结构与漏区的重叠面积，从而减小漏电，改善器件性能。
在一实施例中，埋入式字线两侧形成有源区和漏区，埋入式字线结构、源区和漏区构成MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金属氧化物半导体场效应管)。进一步的，漏区与位线连接，在源区上方形成存储电容器，存储电容器的下极板与源区电连接，则可以形成半导体存储器，例如可形成动态随机存取存储器(DRAM)，当然，也可以形成其他类型的存储器。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种埋入式字线结构制备方法，包括：
    在半导体衬底上开设第一沟槽，所述第一沟槽底部具有尖端；
    在所述第一沟槽内进行外延生长，减小所述第一沟槽底部尖端的深度；以及
    在所述第一沟槽内壁上形成栅介质层并在所述第一沟槽内填入栅导电层，形成埋入式字线结构。
  2. 如权利要求1所述的制备方法，其中，所述半导体衬底上形成有沟槽隔离结构，所述半导体衬底的表层被所述沟槽隔离结构划分出多个独立的区域，在所述第一沟槽内进行外延生长之前，还包括：
    在所述沟槽隔离结构上开设第二沟槽，所述第二沟槽和所述第一沟槽相互连通，所述第一沟槽的深度小于所述第二沟槽的深度。
  3. 如权利要求1所述的制备方法，其中，所述第二沟槽底部具有尖端。
  4. 如权利要求1所述的制备方法，其中，所述第一沟槽的开口宽度范围为30nm～50nm，所述第一沟槽的深度范围为60nm～80nm。
  5. 如权利要求1所述的制备方法，其中，
    所述在半导体衬底上开设第一沟槽，包括：
    在所述半导体衬底上形成掩膜层，通过所述掩膜层定义出刻蚀窗口；
    通过所述刻蚀窗口对所述半导体衬底进行刻蚀，形成所述第一沟槽；
    所述在所述第一沟槽内进行外延生长，包括：以所述掩膜层为保护层，避免所述第一沟槽外的半导体衬底表面进行外延生长。
  6. 如权利要求1所述的制备方法，其中，在所述第一沟槽内进行外延生长之 前，对所述第一沟槽内壁进行原位清洁。
  7. 如权利要求1所述的制备方法，其中，所述在所述第一沟槽内进行外延生长，减小所述尖端的深度，包括：在所述第一沟槽内进行外延生长，减小所述尖端的深度直至所述尖端消失。
  8. 如权利要求1所述的制备方法，其中，所述在所述第一沟槽内进行外延生长，包括，在所述第一沟槽内进行化学气相外延生长，所述外延生长的反应气体包括SiCl 4和H 2。
  9. 如权利要求1～8任一项所述的制备方法，其中，所述在所述第一沟槽内壁上形成栅介质层并在所述第一沟槽内填入栅导电层，包括：
    在所述第一沟槽内壁上形成栅介质层；
    在所述栅介质层上形成导电衬层并在所述第一沟槽内填满主导电层，所述栅导电层包括所述导电衬层和所述主导电层；
    利用刻蚀剂回刻所述栅导电层，所述刻蚀剂对所述导电衬层和所述主导电层的刻蚀选择比大于1以使刻蚀后的栅导电层的上表面呈Ω状。
  10. 如权利要求9所述的制备方法，其中，所述回刻为各向同性刻蚀。
  11. 如权利要求10所述的制备方法，其中，所述各向同性刻蚀为干法刻蚀，所述刻蚀剂包括NF 3和Cl 2。
  12. 一种埋入式字线结构，包括：
    半导体衬底；
    沟槽隔离结构，形成于所述半导体衬底上，所述半导体衬底的表层被所述沟槽隔离结构划分出多个独立的区域；
    第一沟槽，开设于所述半导体衬底上，所述第一沟槽的底部平整；
    第二沟槽，开设于所述沟槽隔离结构上，所述第二沟槽的底部具有尖端， 所述第一沟槽和所述第二沟槽相互连通以形成连通沟槽，所述第二沟槽的深度大于所述第一沟槽的深度；
    栅介质层，形成于所述第一沟槽的内壁上；以及
    栅导电层，填充于所述第一沟槽和所述第二沟槽内。
  13. 如权利要求12所述的埋入式字线结构，其中，所述栅导电层的上表面呈Ω状。
  14. 如权利要求12所述的埋入式字线结构，其中，所述第一沟槽的开口宽度范围为30nm～50nm。
  15. 如权利要求12所述的埋入式字线结构，其中，所述第一沟槽底部具有填充的外延层以形成平整结构。
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