WO2021218219A1 - Bcd器件的沟槽的制造方法及bcd器件 - Google Patents

Bcd器件的沟槽的制造方法及bcd器件 Download PDF

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WO2021218219A1
WO2021218219A1 PCT/CN2020/140526 CN2020140526W WO2021218219A1 WO 2021218219 A1 WO2021218219 A1 WO 2021218219A1 CN 2020140526 W CN2020140526 W CN 2020140526W WO 2021218219 A1 WO2021218219 A1 WO 2021218219A1
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trench
layer
insulating oxide
hard mask
depth
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PCT/CN2020/140526
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English (en)
French (fr)
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冯冰
张建栋
李勇
缪海生
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无锡华润上华科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Definitions

  • Trench isolation is a technology that is widely used in large-scale integrated circuits to isolate and prevent crosstalk between devices. With the requirements for device breakdown voltage resistance, in order to achieve isolation of low-doped well regions, the traditional front trench isolation technology has been Can't meet the requirements.
  • the deep trench isolation technology invented by Academician Chen Xingbi more than 20 years ago has quickly occupied a certain market under the promotion of Infineon.
  • the insulation technology containing this super junction structure is widely used in the BCD process (the BCD process is a An integrated process technology capable of making BJT, CMOS and DMOS devices on the same chip) to meet the requirements of high withstand voltage.
  • the biggest challenge of BCD technology with deep trench isolation (DTI) is the insulation filling performance of the deep trench.
  • the aspect ratio of deep trenches is generally greater than 10 or even higher.
  • Traditional trench filling technology is difficult to meet its filling requirements.
  • the positions of long gap voids (Voids) in the trenches after filling are too high.
  • the subsequent CMOS process will have the phenomenon of acid or corrosive backflow, which will affect the insulation performance of the deep trench.
  • a method for manufacturing a trench of a BCD device includes: forming a hard mask on a substrate; photolithography and etching the hard mask and the substrate to form a first trench; the depth of the first trench Greater than or equal to the depth of the shallow trench isolation structure of the BCD device; forming an oxidation barrier layer on the sidewall of the first trench; using the hard mask and the oxidation barrier layer as an etch barrier layer to A trench is etched down anisotropically to form a second trench extending downward from the bottom of the first trench; an insulating oxide layer is thermally grown on the inner surface of the second trench through a thermal oxidation process; The oxidation barrier layer; and filling the first trench with an insulating oxide, so that the first trench is filled with the insulating oxide, and the top of the second trench is sealed by the insulating oxide.
  • a BCD device comprising a gate, a source region provided on one side of the gate, a drain region provided on the other side of the gate, a gate and the drain region between the shallow trench isolation structure and the deep trench isolation structure provided on the side of the source region away from the drain region, the deep trench isolation structure is described in any of the foregoing embodiments The manufacturing method of the trench of the BCD device is manufactured.
  • FIG. 1 is a flowchart of a method for manufacturing a trench of a BCD device in an embodiment
  • step S110 is completed in an embodiment
  • step S120 is completed in an embodiment
  • step S130 is a schematic cross-sectional view of the device after the silicon nitride layer is deposited in step S130 in an embodiment
  • FIG. 5 is a schematic cross-sectional view of the structure shown in FIG. 4 after removing the silicon nitride layer at the bottom of the first trench;
  • step S140 is completed in an embodiment
  • step S150 is completed in an embodiment
  • step S160 is completed and the top of the second trench is sealed in an embodiment
  • step S170 is completed in an embodiment
  • FIG. 10 is a schematic diagram of a part of the structure of a BCD device in an embodiment.
  • P-type and N-type impurities in order to distinguish the doping concentration, simply P+ type represents the heavy doping concentration of P type, and P type represents middle P-type doping concentration, P-type represents P-type with light doping concentration, N+-type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents light-doping concentration N type.
  • exemplary filling techniques include: performing repeated deposition-etching (for example, a high-density plasma chemical vapor deposition process) on the trench opening to reduce voids Location, using sub-atmospheric chemical vapor deposition (SACVD) technology to fill the trench, atomic layer deposition technology, etc.
  • repeated deposition-etching for example, a high-density plasma chemical vapor deposition process
  • SACVD sub-atmospheric chemical vapor deposition
  • the biggest disadvantage of the technology of repeatedly depositing and etching the trench opening to reduce the position of the cavity is that the silicon substrate will be damaged under the repeated action of plasma, and due to the high-density plasma chemical vapor deposition
  • the characteristics of (HDPCVD) determine that the thickness of the insulating oxide layer on the sidewall of the deep trench will be very thin, and the insulation performance will be poor; SACVD can fill the deep trench, but the position of the cavity inside the trench after filling is difficult to control. It is necessary to change the structure of the opening to adjust the position of the cavity. Therefore, there is a risk of acid or corrosive liquid being poured into the cavity during the filling process; the atomic layer deposition technology is expensive and slow, and cannot meet the demand for mass production.
  • Fig. 1 is a flowchart of a method for manufacturing a trench of a BCD device in an embodiment, including the following steps:
  • a hard mask 20 is formed on the provided substrate 10.
  • the substrate 10 may be a semiconductor substrate, and its material may be undoped single crystal silicon, single crystal silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), and germanium-on-insulator. Silicon (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc.
  • the hard mask 20 and the substrate 10 are lithographically etched and etched according to the design rules to form the first trench 11. Since in the subsequent process steps, the cavity of the deep trench will be formed under the bottom of the first trench 11, the depth of the first trench 11 formed in step S120 is set according to the height limit of the cavity. In this embodiment In the example, the depth of the first trench 11 is greater than or equal to the depth of the shallow trench isolation structure (specifically, CMOS STI) of the BCD device.
  • the shallow trench isolation structure specifically, CMOS STI
  • the depth of the first trench 11 is set to be greater than or equal to the depth of the STI structure of the BCD device, which can avoid the acid solution in the subsequent process. Or the phenomenon that the corrosive liquid erodes the insulating oxide above the cavity and pours it back into the cavity to maintain the excellent insulation performance of the trench.
  • the depth of the first trench 11 matches the depth of the shallow trench isolation structure. For example, when the STI depth of the CMOS in the BCD is 0.4 ⁇ m, the depth of the first trench 11 is set to 0.4 ⁇ m accordingly.
  • the etching in step S120 is dry etching.
  • the oxidation barrier layer protects the sidewall of the first trench 11 to prevent the substrate material of the sidewall of the first trench 11 from being oxidized in a subsequent process.
  • the oxidation barrier layer includes a silicon nitride layer 32, and step S130 includes:
  • a silicon nitride layer 32 is deposited on the surface of the wafer, see FIG. 4.
  • the silicon nitride layer 32 on the bottom of the first trench 11 and the surface of the hard mask 20 is removed, see FIG. 5.
  • the silicon nitride layer 32 on the bottom of the first trench 11 and the surface of the hard mask 20 can be removed by anisotropic etching, and the silicon nitride layer 32 on the sidewall of the first trench 11 is retained.
  • a step of forming a pad oxide layer on the inner surface of the first trench 11 is further included.
  • the material of the pad oxide layer may be silicon oxide, such as silicon dioxide.
  • the first trench 11 is anisotropically etched downward to form a second trench 13 extending downward from the bottom of the first trench 11, see FIG. 6.
  • the structure of the first trench 11 + the second trench 13 is the deep trench required by the BCD device, so the trench depth of the first trench 11 + the second trench 13 should be the design trench depth of the DTI.
  • the hard mask 20 Since the hard mask 20 is used as an etching stop layer for the deep trench etching in step S140, the surface of the hard mask 20 will also consume a certain thickness during etching. Therefore, the thickness of the hard mask 20 formed in step S110 depends on The depth of the second groove 13 is designed.
  • the hard mask 20 includes a silicon oxide layer on the upper surface of the hard mask, and the silicon oxide layer is used as a barrier layer for etching in step S140.
  • the hard mask 20 has an ONO structure, that is, the hard mask 20 includes a silicon dioxide layer 22, a silicon nitride layer 24, and a silicon dioxide layer 26 from bottom to top. The layer 26 serves as a barrier layer etched in step S140, so the thickness of the silicon dioxide layer 26 is designed according to the depth of the second trench 13.
  • a furnace tube is used to perform the thermal oxidation reaction, and a silicon dioxide layer of a certain thickness is thermally grown on the inner surface of the second trench 13 as the insulating material filled in the DTI. Since the method for manufacturing the trench of the BCD device of the present application is particularly suitable for deep trench isolation structures, the aspect ratio of the second trench 13 is generally higher, and the heat is heated from the sidewall of the second trench 13 to the middle of the trench. The grown insulating oxide layer 42 will leave a gap in the middle, as shown in FIG. 7.
  • the growth of the insulating oxide layer 42 by thermal oxidation consumes a certain amount of substrate material on the inner surface of the second trench 13.
  • the oxidation barrier layer formed on the sidewall of the first trench 11 in step S130 can prevent the thermal oxidation in step S150 from oxidizing the substrate material on the sidewall of the first trench 11, and prevent the trench from being caused by an increase in the size of the trench opening. The actual size deviates from the design size.
  • the oxidation barrier layer is removed by etching.
  • the first trench 11 is filled with insulating oxide, so that the first trench 11 is filled with the insulating oxide, and the top of the second trench 13 is sealed by the insulating oxide.
  • a step of sealing the top of the second trench 13 with an insulating oxide is further included before the step of filling the first trench 11 with an insulating oxide.
  • a high-density plasma chemical vapor deposition process with a sputtering rate greater than a deposition rate may be used to seal the top of the second trench 13, that is, to seal the top of the gap in the middle of the insulating oxide layer 42, as shown in FIG. 8.
  • the sealing method is not limited to the HDP re-deposition (Re-Dep) method, and other methods that can facilitate sealing are also applicable.
  • a high-density plasma chemical vapor deposition process with a large sputtering/deposition ratio (S/D ratio) can make the position of the seal move down relative to the top of the gap, thereby ensuring the groove depth of the first groove 11
  • the height of the cavity is lower than the bottom of the STI, which realizes more accurate control of the height of the cavity.
  • the sealing step may be performed before step S160 or after step S160.
  • step S170 is to deposit silicon oxide (such as silicon dioxide) into the first trench 11 using HDPCVD STI menu (Recipe) of the conventional CMOS process of BCD devices. Fill it.
  • silicon oxide such as silicon dioxide
  • HDPCVD STI menu Recipe
  • other suitable methods can also be used for filling. The structure after filling is shown in Figure 9.
  • the deep trench is formed by two-step etching, so that the first trench 11 can be guaranteed to be filled, and the cavity height of the deep trench is controlled under the shallow trench isolation structure, which can avoid The acid liquid or etching liquid in the subsequent process etches through the insulating oxide above the cavity and pours it back into the cavity to maintain the excellent insulation performance of the trench.
  • the above-mentioned manufacturing method has good compatibility with BCD devices, and can be applied to deep trenches with a very large aspect ratio.
  • the above-mentioned trench manufacturing method for BCD devices is particularly suitable for deep trench isolation structure processes with an aspect ratio> 15 and a trench depth greater than 20 ⁇ m, and is basically not affected by the aspect ratio of DTI, and can meet the manufacturing of DTI structures with different depths. For example, it can be used for a deep trench isolation structure process with an aspect ratio>20.
  • the preparation process of the above-mentioned manufacturing method is simple, no special equipment is required, and the production cost is low.
  • step S170 a chemical mechanical polishing (CMP) process is performed on the filled insulating oxide, and the polishing stop layer is silicon nitride 24.
  • CMP chemical mechanical polishing
  • the silicon nitride 24 is removed by etching to form a deep trench isolation structure with a super junction structure.
  • the steps of the method for manufacturing the trench of the BCD device are performed before the STI process, that is, after the DTI is formed, the conventional BCD process including the STI process is performed, which has no effect on the conventional BCD process, so it is guaranteed Compatibility with conventional BCD process.
  • the aspect ratio of the first trench 11 is smaller than the aspect ratio of the second trench 13.
  • the thickness of the oxidation barrier layer in step S130 is determined by the critical dimension (CD) etched in step S140 and the thickness of the thermal oxidation process in step S150.
  • CD critical dimension
  • FIG. 10 is a schematic diagram of a part of the structure of a BCD device in an embodiment, including a gate 140, a source region 134 provided on one side of the gate 140, a drain region 136 provided on the other side of the gate 140, a device The shallow trench isolation structure 114 between the gate 140 and the drain region 136 and the deep trench isolation structure 112 provided on the side of the source region 134 away from the drain region 136.
  • the deep trench isolation structure 112 is formed by the trench manufacturing method of the BCD device described in any of the foregoing embodiments.
  • the cross-sectional structure of the device shown in FIG. 10 is an axisymmetric structure, so only one side of the symmetrical area is marked in the figure.
  • the BCD device further includes a substrate 110, an epitaxial layer 124, a first conductivity type buried layer 122 between the substrate 110 and the epitaxial layer 124, and a first conductivity type well on the epitaxial layer 124 A region 126, a second conductive type well region 128, a drift region 132, and an interlayer dielectric (ILD) layer 150.
  • the drain region 136 is provided in the first conductivity type well region 126
  • the source region 134 is provided in the second conductivity type well region 128, and the drift region 132 is provided in the first conductivity type well region 126 and the second conductivity type well region 128 between.
  • the first conductivity type buried layer 122, the first conductivity type well region 126, the second conductivity type well region 128, the drift region 132, the source region 134 and the drain region 136 are located in the first device region, and the deep trench isolation structure 112 Set on both sides of the first device area (outside the first device area) to isolate each device structure in the first device area from the semiconductor structure outside the first device area in the lateral direction to prevent crosstalk between devices .
  • the source region 134, the drain region 136, the epitaxial layer 124, and the drift region 132 have a first conductivity type, and the substrate 110 has a second conductivity type.
  • the doping concentration of the buried layer 122 of the first conductivity type is greater than the doping concentration of the epitaxial layer 124, and the doping concentration of the source region 134 and the drain region 136 is greater than the doping concentration of the epitaxial layer 124.
  • the doping concentration of the drift region 132 is relatively low, which is lower than the doping concentration of the drain region 136 and the source region 134, which is equivalent to forming a region with higher resistance between the source and the drain. Improve the breakdown voltage and reduce the parasitic capacitance between the source and drain, which is beneficial to improve the frequency characteristics of the device.
  • the first conductivity type is N-type and the second conductivity type is P-type; in another embodiment, the first conductivity type is P-type and the second conductivity type is N-type.
  • the substrate 110 is a semiconductor substrate, and its material may be undoped single crystal silicon, single crystal silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), Silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI) are stacked on the insulator.
  • the constituent material of the substrate 110 is single crystal silicon.
  • the gate 140 is made of polysilicon material. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the material of the gate 140.
  • a gate dielectric layer is further provided under the gate 140.
  • the gate dielectric layer may include conventional dielectric materials such as silicon oxides, nitrides, and oxynitrides having a dielectric constant from about 4 to about 20 (measured in a vacuum), or the gate dielectric layer may include A generally higher dielectric constant dielectric material with a constant from about 20 to at least about 100.
  • Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

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Abstract

一种BCD器件的沟槽的制造方法及BCD器件，所述方法包括：在衬底上形成硬掩膜；光刻并刻蚀硬掩膜和衬底，形成第一沟槽；在第一沟槽的侧壁形成氧化阻挡层；以硬掩膜和氧化阻挡层为刻蚀阻挡层对第一沟槽向下进行各向异性刻蚀，形成从第一沟槽底部向下延伸的第二沟槽；通过热氧化工艺在第二沟槽的内表面热生长绝缘氧化层；去除氧化阻挡层；向第一沟槽内填充绝缘氧化物，使第一沟槽被绝缘氧化物填满，第二沟槽的顶部被绝缘氧化物封口。

Description

BCD器件的沟槽的制造方法及BCD器件
相关申请的交叉引用
本申请要求于2020年04月29日提交中国专利局、申请号为2020103552536、发明名称为“BCD器件的沟槽的制造方法及BCD器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
沟槽隔离是一种广泛用于大规模集成电路的器件间隔离防串扰技术，随着对器件抗击穿电压性能的要求，为了实现低掺杂阱区的隔离，传统的前沟槽隔离技术已经不能满足要求。陈星弼院士于20多年前发明的深沟槽隔离技术已经在英飞凌公司的推广下很快占得一定的市场，含有这种超结结构的绝缘技术被广泛用于BCD工艺(BCD工艺是一种能够在同一芯片上制作BJT、CMOS和DMOS器件的集成工艺技术)来满足高耐压的要求。目前，带有深沟槽隔离(Deep Trench Isolation，DTI)的BCD技术最大的挑战在于深沟槽的绝缘填充性能。深沟槽的深宽比一般都要大于10甚至更高，传统的沟槽填充技术很难满足其填充要求，对沟槽而言填充后沟槽内存在的长缝空洞(Void)位置太高时，后续CMOS工艺会存在酸液或腐蚀液倒灌的现象，影响深沟槽的绝缘性能。
发明内容
针对上述问题，有必要提供一种BCD器件的沟槽的制造方法及BCD器件。
一种BCD器件的沟槽的制造方法，包括：在衬底上形成硬掩膜；光刻并刻蚀所述硬掩膜和衬底，形成第一沟槽；所述第一沟槽的深度大于或等于所 述BCD器件的浅沟槽隔离结构的深度；在所述第一沟槽的侧壁形成氧化阻挡层；以所述硬掩膜和氧化阻挡层为刻蚀阻挡层对所述第一沟槽向下进行各向异性刻蚀，形成从所述第一沟槽底部向下延伸的第二沟槽；通过热氧化工艺在第二沟槽的内表面热生长绝缘氧化层；去除所述氧化阻挡层；及向所述第一沟槽内填充绝缘氧化物，使所述第一沟槽被绝缘氧化物填满，所述第二沟槽的顶部被所述绝缘氧化物封口。
一种BCD器件，包括栅极、设于所述栅极的一侧的源极区、设于所述栅极的另一侧的漏极区、设于所述栅极和所述漏极区之间的浅沟槽隔离结构、及设于所述源极区远离所述漏极区的一侧的深沟槽隔离结构，所述深沟槽隔离结构是通过前述任一实施例所述的BCD器件的沟槽的制造方法制造。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是一实施例中BCD器件的沟槽的制造方法的流程图；
图2是一实施例中步骤S110完成后器件的剖面示意图；
图3是一实施例中步骤S120完成后器件的剖面示意图；
图4是一实施例中步骤S130沉积氮化硅层后器件的剖面示意图；
图5是图4所示结构去除第一沟槽底部的氮化硅层后的剖面示意图；
图6是一实施例中步骤S140完成后器件的剖面示意图；
图7是一实施例中步骤S150完成后器件的剖面示意图；
图8是一实施例中步骤S160完成并将第二沟槽的顶部封口后器件的剖面示意图；
图9是一实施例中步骤S170完成后器件的剖面示意图；
图10是一实施例中BCD器件的部分结构的示意图。
具体实施方式
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
对于深宽比较高(例如大于10)的深沟槽，示例性的填充技术有：对沟槽开口处进行反复的沉积-刻蚀(例如高密度等离子体化学气相沉积工艺)处理来降低空洞的位置，利用次常压化学气相沉积(SACVD)技术来填充沟槽，原子层沉积技术等。然而，对沟槽开口进行反复沉积-刻蚀处理来降低空洞的位置的技术的最大缺点是在等离子体(plasma)的反复作用下会对硅基底造成损伤，且由于高密度等离子体化学气相沉积(HDPCVD)的特性决定了其在深沟槽侧壁的绝缘氧化层厚度会很薄，绝缘性能会不佳；SACVD能够填充深沟槽，但是其填充后沟槽内部的空洞位置很难控制，需要改变开口的结构才能调整空洞的位置，因此在填充后的工艺中存在酸液或腐蚀液倒灌进空洞的风险；原子层沉积技术成本高、速度慢、不能满足量产需求。
图1是一实施例中BCD器件的沟槽的制造方法的流程图，包括以下步骤：
S110，在衬底上形成硬掩膜。
如图2所示，在提供的衬底10上形成硬掩膜20。衬底10可以为半导体衬底，其材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。
S120，光刻并刻蚀硬掩膜和衬底，形成第一沟槽。
参见图3，按照设计规则光刻并刻蚀硬掩膜20和衬底10，形成第一沟槽11。由于在后续的工艺步骤中，深沟槽的空洞会形成于第一沟槽11的底部下 方，因此步骤S120中形成的第一沟槽11的深度根据空洞的限高来设定，在本实施例中第一沟槽11的深度大于或等于BCD器件的浅沟槽隔离结构(具体可以是CMOS STI)的深度。由于后续的工艺步骤中酸液或腐蚀液的腐蚀深度不会大于STI的深度，因此将第一沟槽11的深度设为大于或等于BCD器件的STI结构的深度，能够避免后续工艺的酸液或腐蚀液将空洞上方的绝缘氧化物蚀穿而倒灌进空洞的现象，保持沟槽优异的绝缘性能。
在一个实施例中，第一沟槽11的深度与浅沟槽隔离结构的深度相匹配。例如当BCD中CMOS的STI深度为0.4μm时，将第一沟槽11的深度相应设为0.4μm。
在一个实施例中，步骤S120的刻蚀采用干法刻蚀。
S130，在第一沟槽的侧壁形成氧化阻挡层。
氧化阻挡层将第一沟槽11的侧壁保护起来，以防止第一沟槽11的侧壁的衬底材料在后续工艺中被氧化。
在一个实施例中，氧化阻挡层包括氮化硅层32，步骤S130包括：
在晶圆(wafer)表面沉积氮化硅层32，参见图4。
去除第一沟槽11底部和硬掩膜20表面的氮化硅层32，参见图5。可以用各向异性刻蚀去除第一沟槽11底部和硬掩膜20表面的氮化硅层32，第一沟槽11侧壁的氮化硅层32被保留。
在一个实施例中，沉积氮化硅层32之前还包括在第一沟槽11的内表面形成衬垫氧化层的步骤。衬垫氧化层的材质可以是硅氧化物，例如二氧化硅。
S140，对第一沟槽向下刻蚀，形成从第一沟槽底部向下延伸的第二沟槽。
以硬掩膜20和氧化阻挡层32为刻蚀阻挡层对第一沟槽11向下进行各向异性刻蚀，形成从第一沟槽11底部向下延伸的第二沟槽13，参见图6。第一沟槽11+第二沟槽13的结构即为BCD器件所需的深沟槽，因此第一沟槽11+第二沟槽13的槽深应为DTI的设计槽深。
由于硬掩膜20作为步骤S140中深槽刻蚀的刻蚀阻挡层，因此硬掩膜20在刻蚀时表面也会被消耗一定的厚度，故步骤S110形成的硬掩膜20的厚度 要根据第二沟槽13的槽深来设计。在一个实施例中，硬掩膜20包括位于硬掩膜上表面的硅氧化物层，由硅氧化物层作为步骤S140刻蚀的阻挡层。在图2所示的实施例中，硬掩膜20为ONO结构，即硬掩膜20层从下到上包括二氧化硅层22、氮化硅层24、二氧化硅层26，二氧化硅层26作为步骤S140刻蚀的阻挡层，因此二氧化硅层26的厚度根据第二沟槽13的槽深来设计。
S150，通过热氧化工艺在第二沟槽的内表面热生长绝缘氧化层。
在一个实施例中，是使用炉管进行热氧化反应，在第二沟槽13内表面热生长一定厚度的二氧化硅层作为DTI中填充的绝缘物质。由于本申请的BCD器件的沟槽的制造方法特别适用于深沟槽隔离结构，因此第二沟槽13的深宽比一般会比较高，从第二沟槽13的侧壁向沟槽中间热生长的绝缘氧化层42会在中间留下缝隙，如图7所示。
热氧化生长绝缘氧化层42会将第二沟槽13内表面一定量的衬底材料消耗掉。步骤S130中在第一沟槽11侧壁形成的氧化阻挡层能够防止步骤S150中的热氧化将第一沟槽11侧壁的衬底材料氧化，防止因沟槽开口尺寸的增大导致沟槽实际尺寸偏离设计尺寸。
S160，去除氧化阻挡层。
通过刻蚀去除氧化阻挡层。
S170，向第一沟槽内填充绝缘氧化物。
向第一沟槽11内填充绝缘氧化物，使第一沟槽11被绝缘氧化物填满，第二沟槽13的顶部被绝缘氧化物封口。
在一个实施例中，向第一沟槽11内填充绝缘氧化物的步骤之前，还包括用绝缘氧化物将第二沟槽13的顶部封口的步骤。具体地，可以使用溅射速率大于沉积速率的高密度等离子体化学气相沉积工艺将第二沟槽13的顶部封口，即将绝缘氧化层42中间的缝隙的顶部封住，如图8所示。封口的方法不限于HDP再沉积(Re-Dep)方式，其他能够促进封口的方法同样适用。使用溅射/沉积比(S/D ratio)较大的高密度等离子体化学气相沉积工艺，可以使得封口的位置相对于缝隙顶部有一定的下移，从而可以保证第一沟槽11的 槽深与STI相同时，空洞的高度低于STI底部，实现对空洞高度较为准确的控制。封口的步骤可以在步骤S160之前进行，也可以在步骤S160之后进行。
封口后需要填充第一沟槽11，在一个实施例中，步骤S170是采用BCD器件的常规CMOS工艺的HDPCVD STI菜单(Recipe)向第一沟槽11内沉积硅氧化物(例如二氧化硅)进行填充。在其他实施例中也可以用其他合适的方法进行填充。填充完成后的结构如图9所示。
上述BCD器件的沟槽的制造方法，通过两步刻蚀形成深沟槽，因此可以保证第一沟槽11被填满，将深沟槽的空洞高度控制在浅沟槽隔离结构下方，能够避免后续工艺的酸液或腐蚀液将空洞上方的绝缘氧化物蚀穿而倒灌进空洞的现象，保持沟槽优异的绝缘性能。且上述制造方法与BCD器件兼容性好，能够适用于深宽比非常大的深沟槽。上述BCD器件的沟槽的制造方法特别适用于深宽比＞15，槽深大于20μm的深沟槽隔离结构工艺，并且基本不受DTI的深宽比影响，能满足不同深度DTI结构的制造，例如可以用于深宽比＞20的深沟槽隔离结构工艺。另外，上述制造方法的制备过程简单，无特殊设备要求，生产成本较低。
在一个实施例中，步骤S170完成之后还包括对填充的绝缘氧化物进行化学机械研磨(CMP)处理的步骤，研磨停止层为氮化硅24。研磨完成后再通过刻蚀将氮化硅24去除，形成超结结构的深沟槽隔离结构。
在一个实施例中，上述BCD器件的沟槽的制造方法的各步骤在STI工艺之前进行，即DTI形成后再进行包括STI工艺在内的常规BCD流程，对常规BCD工艺没有影响，因此也保证了与常规BCD工艺的兼容性。
在一个实施例中，第一沟槽11的深宽比小于第二沟槽13的深宽比。
步骤S130中氧化阻挡层的厚度根据步骤S140刻蚀的关键尺寸(CD)及步骤S150中热氧化工艺厚度决定，氧化阻挡层越厚、步骤S140刻蚀出的第二沟槽13的CD就会越小，越利于DTI的填充，因此可以在满足第一沟槽11和第二沟槽13的设计尺寸的前提下尽量加厚氧化阻挡层。
本申请相应提出一种BCD器件。图10是一实施例中BCD器件的部分结构 的示意图，包括栅极140、设于栅极140的一侧的源极区134、设于栅极140的另一侧的漏极区136、设于栅极140和漏极区136之间的浅沟槽隔离结构114、及设于源极区134远离漏极区136的一侧的深沟槽隔离结构112。其中深沟槽隔离结构112是通过前述任一实施例所述的BCD器件的沟槽的制造方法制造形成。图10中示出的器件剖面结构为轴对称结构，因此图中对于对称设置的区域只标出一侧的标号。
在图10所示的实施例中，BCD器件还包括衬底110，外延层124，衬底110和外延层124之间的第一导电类型埋层122，外延层124上的第一导电类型阱区126、第二导电类型阱区128、漂移区132，以及层间介质(ILD)层150。漏极区136设于第一导电类型阱区126中，源极区134设于第二导电类型阱区128中，漂移区132设于第一导电类型阱区126与第二导电类型阱区128之间。第一导电类型埋层122、第一导电类型阱区126、第二导电类型阱区128、漂移区132、源极区134及漏极区136位于第一器件区域中，深沟槽隔离结构112设于第一器件区域的两侧(第一器件区域的外侧)，从而在横向上将第一器件区域中的各器件结构与第一器件区域外的半导体结构进行隔离，以防止器件间相互串扰。
源极区134、漏极区136、外延层124及漂移区132具有第一导电类型，衬底110具有第二导电类型。第一导电类型埋层122的掺杂浓度大于外延层124的掺杂浓度，源极区134和漏极区136的掺杂浓度大于外延层124的掺杂浓度。一般来说，漂移区132的掺杂浓度较低，其低于漏极区136和源极区134的掺杂浓度，相当于在源极和漏极之间形成一个电阻较高的区域，能够提高击穿电压，并减小了源极和漏极之间的寄生电容，有利于提高器件的频率特性。
在图10所示的实施例中，第一导电类型是N型，第二导电类型是P型；在另一个实施例中，第一导电类型是P型，第二导电类型是N型。
在一个实施例中，衬底110为半导体衬底，其材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、 绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。在图10所示的实施例中，衬底110的构成材料选用单晶硅。
在一个实施例中，栅极140为多晶硅材料，在其他实施例中也可使用金属、金属氮化物、金属硅化物或类似化合物作为栅极140的材料。
在一个实施例中，栅极140下还设有栅极介电层。栅极介电层可以包括传统的电介质材料诸如具有电介质常数从大约4到大约20(真空中测量)的硅的氧化物、氮化物和氮氧化物，或者，栅极介电层可以包括具有电介质常数从大约20到至少大约100的通常较高电介质常数电介质材料。这种较高电介质常数电介质材料可以包括但不限于：氧化铪、硅酸铪、氧化钛、钛酸锶钡(BSTs)和锆钛酸铅(PZTs)。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。

Claims (15)

  1. 一种BCD器件的沟槽的制造方法，包括：
    在衬底上形成硬掩膜；
    光刻并刻蚀所述硬掩膜和衬底，形成第一沟槽；所述第一沟槽的深度大于或等于所述BCD器件的浅沟槽隔离结构的深度；
    在所述第一沟槽的侧壁形成氧化阻挡层；
    以所述硬掩膜和氧化阻挡层为刻蚀阻挡层对所述第一沟槽向下进行各向异性刻蚀，形成从所述第一沟槽底部向下延伸的第二沟槽；
    通过热氧化工艺在第二沟槽的内表面热生长绝缘氧化层；
    去除所述氧化阻挡层；及
    向所述第一沟槽内填充绝缘氧化物，使所述第一沟槽被绝缘氧化物填满，所述第二沟槽的顶部被所述绝缘氧化物封口。
  2. 根据权利要求1所述的方法，其特征在于，所述第二沟槽的顶部被所述绝缘氧化物封口是使用溅射速率大于沉积速率的高密度等离子体化学气相沉积工艺将所述第二沟槽的顶部封口，所述向所述第一沟槽内填充绝缘氧化物是在所述封口后进行。
  3. 根据权利要求2所述的方法，其特征在于，所述向所述第一沟槽内填充绝缘氧化物的步骤，包括采用高密度等离子体化学气相沉积工艺、所述BCD器件的浅沟槽隔离结构沉积硅氧化物的菜单向所述第一沟槽内沉积硅氧化物。
  4. 根据权利要求1所述的方法，其特征在于，所述向所述第一沟槽内填充绝缘氧化物的步骤之后还包括形成所述BCD器件的浅沟槽隔离结构的步骤。
  5. 根据权利要求1所述的方法，其特征在于，所述硬掩膜包括位于硬掩膜上表面的硅氧化物层。
  6. 根据权利要求1所述的方法，其特征在于，所述硬掩膜为二氧化硅- 氮化硅-二氧化硅三层结构。
  7. 根据权利要求6所述的方法，其特征在于，所述向所述第一沟槽内填充绝缘氧化物的步骤之后，还包括对填充的绝缘氧化物进行化学机械研磨的步骤，研磨停止层为所述硬掩膜中的氮化硅。
  8. 根据权利要求7所述的方法，其特征在于，所述对填充的绝缘氧化物进行化学机械研磨的步骤之后，还包括通过刻蚀去除所述氮化硅的步骤。
  9. 根据权利要求1所述的方法，其特征在于，所述形成第一沟槽的步骤中，所述第一沟槽的深度与所述浅沟槽隔离结构的深度相匹配。
  10. 根据权利要求1所述的方法，其特征在于，所述在所述第一沟槽的侧壁形成氧化阻挡层的步骤包括：
    沉积氮化硅层；及
    去除所述第一沟槽底部和所述硬掩膜表面的氮化硅层。
  11. 根据权利要求1所述的方法，其特征在于，所述第二沟槽的深度大于所述第一沟槽的深度。
  12. 根据权利要求10所述的方法，其特征在于，所述沉积氮化硅层的步骤之前，还包括在所述第一沟槽的内表面形成衬垫氧化层的步骤。
  13. 根据权利要求12所述的方法，其特征在于，所述衬垫氧化层的材质为氮化硅。
  14. 根据权利要求1所述的方法，其特征在于，所述第一沟槽的深宽比小于所述第二沟槽的深宽比。
  15. 一种BCD器件，包括：
    栅极；
    设于所述栅极的一侧的源极区；
    设于所述栅极的另一侧的漏极区；
    设于所述栅极和所述漏极区之间的浅沟槽隔离结构；及
    设于所述源极区远离所述漏极区的一侧的深沟槽隔离结构，所述深沟槽隔离结构是通过权利要求1-14中任一项所述的BCD器件的沟槽的制造方法制 造。
PCT/CN2020/140526 2020-04-29 2020-12-29 Bcd器件的沟槽的制造方法及bcd器件 WO2021218219A1 (zh)

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