WO2021160130A1 - 半导体器件及其制作方法 - Google Patents

半导体器件及其制作方法 Download PDF

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Publication number
WO2021160130A1
WO2021160130A1 PCT/CN2021/076304 CN2021076304W WO2021160130A1 WO 2021160130 A1 WO2021160130 A1 WO 2021160130A1 CN 2021076304 W CN2021076304 W CN 2021076304W WO 2021160130 A1 WO2021160130 A1 WO 2021160130A1
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word line
layer
trench structure
line trench
semiconductor substrate
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PCT/CN2021/076304
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English (en)
French (fr)
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雒曲
徐政业
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长鑫存储技术有限公司
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Publication of WO2021160130A1 publication Critical patent/WO2021160130A1/zh
Priority to US17/455,691 priority Critical patent/US20220077289A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/36—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/056—Making the transistor the transistor being a FinFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/413—Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires

Definitions

  • the invention relates to a semiconductor device and a manufacturing method thereof.
  • the present invention provides a method for manufacturing a semiconductor device, including:
  • first insulating layer Forming a first insulating layer, the first insulating layer covering the top of the semiconductor substrate and the first word line trench structure in the shallow trench isolation structure, and sealing the first word line trench structure ;
  • a second word line trench structure and a fin structure are formed in the active region, the depth of the second word line trench structure is smaller than the depth of the first word line trench structure, and the second word
  • the projection of the linear groove structure in the vertical direction completely overlaps the projection of the first sacrificial layer in the vertical direction;
  • the present invention also provides a semiconductor device, including:
  • a buried word line structure located in the semiconductor substrate, extending in a first direction, and straddling a plurality of the shallow trench isolation structures and the active region;
  • the fin structure is located in the area where the active region and the buried word line structure intersect, and the buried word line structure surrounds and covers the fin structure.
  • FIG. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a semiconductor substrate provided by an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a semiconductor substrate formed with a first word line trench structure according to an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a semiconductor substrate formed with a first sacrificial layer according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of a semiconductor substrate after filling the first word line trench structure in the active region according to an embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of a semiconductor substrate formed with a first insulating layer according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a semiconductor substrate formed with a second word line trench structure and a fin structure provided by an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a semiconductor substrate formed with word line tunnels according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of the buried word line structure in the dashed frame part of FIG. 8;
  • FIG. 10 is a schematic structural diagram of a semiconductor substrate formed with a buried word line structure according to an embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of a semiconductor substrate formed with a second insulating layer according to an embodiment of the present invention.
  • random access memory because of the small size of the element itself, often affects the area of the active region due to process limitations, which limits the control ability of the gate and the channel width, which leads to semiconductors.
  • the high turn-on voltage, slow turn-on speed, and low operating current of the device affect the performance of the device itself.
  • an embodiment of the present invention provides a method for manufacturing a semiconductor device, including:
  • Step S110 providing a semiconductor substrate 100 having a shallow trench isolation structure STI and a plurality of active areas AA arranged in parallel, please refer to FIG. 2;
  • Step S120 forming a first word line trench structure G1 in the semiconductor substrate 100, please refer to FIG. 3;
  • Step S130 forming a first sacrificial layer 200 at the bottom of the first word line trench structure G1, please refer to FIG. 4;
  • Step S140 using an epitaxial growth method to fill up the first word line trench structure G1 in the active area AA, please refer to FIG. 5;
  • a first insulating layer 300 is formed.
  • the first insulating layer 300 covers the top of the semiconductor substrate 100 and the first word line trench structure G1 in the shallow trench isolation structure STI, and combines the The first word line groove structure G1 is sealed, please refer to FIG. 6;
  • Step S160 forming a second word line trench structure G2 and a fin structure 400 in the active area AA, the depth of the second word line trench structure G2 is smaller than that of the first word line trench structure G1 Depth, and the projection of the second word line groove structure G2 in the vertical direction completely overlaps the projection of the first sacrificial layer 200 in the vertical direction, please refer to FIG. 7;
  • Step S170 removing the first sacrificial layer 200, forming a word line tunnel G3 in the semiconductor substrate 100 to communicate with the first word line trench structure G1, please refer to FIG. 8;
  • Step S180 filling the first word line trench structure G1, the second word line trench structure G2, and the word line tunnel G3 to form a buried word line structure 500.
  • the word line structure 500 surrounds the fin structure 400, please refer to FIGS. 9-10.
  • the first word line trench structure G1 is formed first, and then the first sacrificial layer 200 is formed at the bottom of the first word line trench structure G1, and the active area AA is filled by the epitaxial growth method.
  • the second word line trench structure G2 is formed by etching, and then the word line tunnel G3 and the first word line tunnel G3 are formed by etching the first sacrificial layer 200
  • the word line trench structure G1 is connected, and finally the first word line trench structure G1, the second word line trench structure G2, and the word line tunnel G3 are filled with aluminum, tungsten, copper, or titanium aluminum alloy
  • a low-resistance metal conductive material is used to form a buried word line structure 500, and the buried word line structure 500 surrounds the fin structure 400. Since the fin structure 400 is surrounded by the buried word line structure 500, the switching efficiency can be improved, the threshold voltage can be reduced, and the operating current can be increased, which is beneficial to improve the refresh efficiency.
  • the semiconductor substrate 100 is an SOI (Silicon-On-Insulator, silicon on insulating substrate) substrate, and includes a silicon material layer 110, a back substrate 130, and a silicon material layer 110 sandwiched therebetween. And the oxide material layer 120 between the back substrate 130.
  • SOI Silicon-On-Insulator, silicon on insulating substrate
  • the SOI substrate is used in this embodiment, and the oxide material layer 120 can be used as an etch stop layer in the process of etching the first word line trench structure G1, which is convenient for controlling the first word line trench structure.
  • the oxide material layer 120 can eliminate the influence of leakage current in the base substrate, and further improve the efficiency of the semiconductor device.
  • the silicon material layer 110 may be an undoped silicon material layer 110 or a doped silicon material layer 110, and the doped silicon material layer 110 may be an N-type or P-type doped silicon material layer 110.
  • the forming the first word line trench structure G1 in the semiconductor substrate 100 includes:
  • the remaining photoresist layer is removed.
  • a spin coating method is used to coat a layer of photoresist on the surface of the silicon material layer 110 to form the photoresist layer, and a laser is used to irradiate the photoresist layer through a photomask to cause
  • the photoresist in the exposed area undergoes a chemical reaction; the photoresist in the exposed or unexposed area is dissolved and removed by development technology (the former is called positive photoresist and the latter is called negative photoresist), and the photoresist on the photomask is removed.
  • the pattern is transferred to the photoresist layer to form a target pattern; then, the silicon material layer 110 is etched using the patterned photoresist layer as a mask layer and the oxide material layer 120 as an etch stop layer. Etching to form the first word line trench structure G1; finally, the remaining photoresist layer is removed to form the first word line trench structure G1.
  • the width of the first word line trench structure G1 is 10-25 nm.
  • first sacrificial layer 200 will be formed in the first word line trench structure G1 later, so the aspect ratio of the first word line trench structure G1 must be considered to avoid forming the first word line trench structure G1 during filling.
  • the material of a sacrificial layer 200 is sealed in advance to form a cavity, and the aspect ratio of the first word line trench structure G1 should be controlled within a reasonable range.
  • the depth of the first word line trench structure G1 is equal to the thickness of the silicon material layer 110, generally 100 to 200 nm, so the width of the first word line trench structure G1 can be set to 10 Within the range of ⁇ 25nm, the aspect ratio is further controlled within the range of 4-20nm to avoid voids in the first sacrificial layer 200. In this embodiment, the width of the first word line trench structure G1 is 21 to 23 nm.
  • the first sacrificial layer 200 is formed of a material having an etching selection ratio greater than 1 relative to the silicon material layer 110 and the oxide material layer 120.
  • the first sacrificial layer 200 when the first sacrificial layer 200 is formed with a material having an etching selection ratio greater than 1 relative to the silicon material layer 110 and the oxide material layer 120, a dry method can be used by selecting a suitable etching gas. The etching quickly etches the material forming the first sacrificial layer 200, and the silicon material layer 110 and the shallow trench isolation structure STI are etched slowly, and the silicon material layer 110 and the shallow trench isolation structure STI are hardly affected. Etching.
  • silicon nitride is used to form the first sacrificial layer 200; in addition, other insulating materials with an etching ratio greater than 1 to Si and SiO may be used instead of the silicon nitride.
  • the forming the first sacrificial layer 200 at the bottom of the first word line trench structure G1 includes:
  • a silicon nitride material is deposited by atomic layer deposition technology to form a silicon nitride material layer 110 that fills the first word line trench structure G1 and covers the semiconductor substrate 100 ;
  • the silicon nitride material layer 110 is etched back, and the thickness of the remaining silicon nitride material layer is controlled to be 20-80 nm to form the first sacrificial layer 200.
  • an atomic layer deposition technique is used to deposit silicon nitride material to form a silicon nitride material layer 110 that fills the first word line trench structure G1 and covers the semiconductor substrate 100. Then, the silicon nitride on the top surface of the semiconductor substrate 100 is etched away, and the silicon nitride in the first word line trench structure G1 is etched to within a predetermined height range to form the first sacrifice Layer 200.
  • the silicon nitride material layer 110 can also be formed by other deposition methods, such as chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), and atomic layer deposition (ALD).
  • the height H1 of the first sacrificial layer 200 is 20-80 nm.
  • the height of the first sacrificial layer 200 ranges from 20 nm to 80 nm. Since the thickness of the first sacrificial layer 200 determines the lowest high end of the fin structure 400 and determines the position of the conductive channel, it should generally not be too small to prevent gaps when the metal material is subsequently filled. Therefore, in this embodiment, the height range of the first sacrificial layer 200 is limited to 20-80 nm. In some embodiments, the height H1 of the first sacrificial layer 200 is 50-70 nm. Specifically, the height of the first sacrificial layer 200 is 50 nm, 55 nm, 60 nm, 65 nm, or 70 nm.
  • the first word line trench structure G1 is filled by the epitaxial growth method, when the first word line trench structure G1 is filled by the epitaxial growth method, only the monocrystalline silicon material is fixed and grown on the sidewalls of the silicon material layer 110, thereby realizing filling The purpose of the first word line trench structure G1 in the source area AA.
  • the single crystal silicon material grown at the same time may have the same characteristics as the silicon material layer 110, or may have different conductivity and other characteristics from the silicon material layer 110.
  • a deposition process is used to deposit silicon oxide material at a rate of 15-20 nm/s, and the first word line trench structure G1 is sealed to form the first insulating layer.
  • the thickness of the insulating layer on the surface of the semiconductor substrate 100 is 50-150 nm; in this embodiment, the thickness of the insulating layer is set in the range of 50-150 nm.
  • the insulating layer and the semiconductor substrate 100 are etched to form a second word line trench structure G2.
  • the insulating layer and the semiconductor substrate 100 are etched using a dry etching process. Due to the geometric effect of the sidewalls of the silicon material layer 110, the formation on the sidewalls of the silicon material layer 110 The silicon oxide material of the shallow trench isolation structure STI will not be etched away.
  • the first sacrificial layer 200 is removed by a wet etching process.
  • the first sacrificial layer 200 is made of silicon nitride material. Since part of the silicon nitride material is located under the fin structure 400 and cannot be etched by dry etching, hot phosphoric acid is used at a temperature of 80-120°C. The silicon nitride material can be removed under conditions, or high-temperature phosphoric acid can be used to remove the silicon nitride material at a temperature of 150-200°C.
  • the first word line trench structure G1, the second word line trench structure G2, and the word line tunnel G3 are filled to form a buried word line structure 500, as shown in Figure 9, includes:
  • the metal barrier layer 520 and the metal conductive material in the first word line trench structure G1 and the second word line trench structure G2 are etched back to a predetermined height to form the buried ⁇ 500 ⁇ Type word line structure 500.
  • the buried word line structure 500 includes a gate oxide layer 510, a metal barrier layer 520, and a metal conductive layer 530.
  • the metal conductive layer 530 is a tungsten material layer.
  • metal materials with low resistance such as aluminum, copper, or titanium aluminum alloy may be used instead.
  • the metal barrier layer 520 is made of titanium nitride (TiN) material.
  • TiN titanium nitride
  • the combination of the titanium nitride material layer and the gate oxide layer 510 is advantageous for increasing the dielectric constant, reducing the gate length, increasing the driving current, and lowering the threshold voltage compared to separately providing the gate oxide layer 510.
  • the gate oxide layer 510 is grown using in-situ steam generation (ISSG) technology.
  • the gate oxide layer 510 can also be grown by atomic layer deposition or other thermal oxidation methods.
  • the manufacturing method further includes:
  • a second insulating layer 600 is formed on the semiconductor substrate 100 on which the buried word line structure 500 is formed, and the second insulating layer 600 covers the first insulating layer 300 and the buried word line structure 500.
  • a deposition process is used to deposit silicon nitride material on the semiconductor substrate 100 on which the buried word line structure 500 is formed, to fill the first word line trench structure G1 and the second word line trench structure G2 , And cover the first insulating layer 300.
  • the thickness of the second insulating layer 600 is 20-50 nm; in some embodiments, the thickness of the second insulating layer 600 is 40 nm, 45 nm, or 50 nm. Since the silicon nitride material has good insulating properties, in addition to preventing leakage by increasing the thickness of the insulating layer, the second insulating layer 600 is usually made of a silicon nitride material.
  • the second insulating layer 600 can also be made of silicon oxynitride, silicon oxynitride, or other suitable insulating materials, but it is not limited thereto.
  • an embodiment of the present invention also provides a semiconductor device. Please refer to FIG. 11 again.
  • the semiconductor device includes a semiconductor substrate 100, a buried word line structure 500 and a fin structure 400.
  • the semiconductor substrate 100 has a shallow trench isolation structure STI and a plurality of active regions AA arranged in parallel.
  • the buried word line structure 500 is located in the semiconductor substrate 100, extends along the first direction, and straddles the plurality of shallow trench isolation structures STI and the active area AA.
  • the fin structure 400 is located in a region where the active area AA and the buried word line structure 500 intersect, and the buried word line structure 500 surrounds the fin structure 400.
  • the semiconductor device of the present invention has the buried word line structure 500 formed with a fin structure and surrounding the fin structure 400. Since the fin structure 400 is surrounded by the buried word line structure 500, The switching efficiency can be improved, the threshold voltage can be reduced, and the operating current can be increased, which is conducive to improving the refresh efficiency.
  • the semiconductor substrate 100 is an SOI (Silicon-On-Insulator, silicon on insulating substrate) substrate, and includes a silicon material layer 110, a back substrate 130, and a silicon material layer 110 sandwiched therebetween. And the oxide material layer 120 between the back substrate 130.
  • SOI Silicon-On-Insulator, silicon on insulating substrate
  • the SOI substrate is used in this embodiment, and the oxide material layer 120 can be used as an etch stop layer in the process of etching the first word line trench structure G1, which is convenient for controlling the first word line trench structure.
  • the oxide material layer 120 can eliminate the influence of leakage current in the base substrate, and further improve the efficiency of the semiconductor device.
  • the silicon material layer 110 may be an undoped silicon material layer 110 or a doped silicon material layer 110, and the doped silicon material layer 110 may be an N-type or P-type doped silicon material layer 110.
  • the height of the buried word line structure 500 located under the fin structure 400 is 20-80 nm.
  • the height of the first sacrificial layer 200 ranges from 20 nm to 80 nm. Since the thickness of the first sacrificial layer 200 determines the lowest high end of the fin structure 400 and determines the position of the conductive channel, it should generally not be too small to prevent gaps when the metal material is subsequently filled. Therefore, in this embodiment, the height range of the first sacrificial layer 200 is limited to 20-80 nm. In some embodiments, the height H1 of the first sacrificial layer 200 is 50-70 nm. Specifically, the height of the first sacrificial layer 200 is 50 nm, 55 nm, 60 nm, 65 nm or 70 nm.
  • the height of the buried word line structure above the fin structure is 10-100 nm.
  • the depth of the second trench structure formed is 50-150 nm.
  • the height of the etch back in the second trench structure is generally 50-100 nm, the height range of the buried word line structure located above the fin structure is 10-100 nm, and the specific depth should be set as required.
  • the depth of the second trench structure formed in the silicon substrate in a specific manufacturing process is 90-110 nm.
  • the height of the etch-back in the second trench structure is generally 64-75 nm, and the height of the buried word line structure above the fin structure is 30-45 nm.
  • the height of the buried word line structure above the fin structure is 30 nm, 35 nm, 40 nm, or 45 nm.
  • the position of the conductive channel can be determined by controlling the depth of the second trench structure, and the resistance value of the buried word line structure can be adjusted by controlling the height of the etch-back in the second trench structure.
  • the buried word line structure 500 includes a metal conductive layer 530 which is insulated from the fin structure 400 and surrounds the fin structure 400.
  • the metal conductive layer 530 is a tungsten material layer.
  • a metal material with low resistance such as aluminum, copper, or titanium aluminum alloy may be used instead.
  • the buried word line structure 500 further includes:
  • a gate oxide layer 510 is disposed on the surface of the base substrate facing the metal conductive layer 530, covering the buried word line structure 500;
  • the metal barrier layer 520 is disposed between the gate oxide layer 510 and the metal conductive layer 530.
  • the metal barrier layer 520 is made of titanium nitride (TiN) material.
  • TiN titanium nitride
  • the combination of the titanium nitride material layer and the gate oxide layer 510 is advantageous for increasing the dielectric constant, reducing the gate length, increasing the driving current, and lowering the threshold voltage compared to separately providing the gate oxide layer 510.
  • the gate oxide layer 510 is formed by in-situ water vapor growth technology.
  • the gate oxide layer 510 can also be grown by atomic layer deposition or other thermal oxidation methods.
  • the width of the buried word line structure 500 is 10-25 nm.
  • first sacrificial layer 200 will be formed in the first word line trench structure G1 later, so the aspect ratio of the first word line trench structure G1 must be considered to avoid forming the first word line trench structure G1 during filling.
  • the material of a sacrificial layer 200 is sealed in advance to form a cavity, and the aspect ratio of the first word line trench structure G1 should be controlled within a reasonable range.
  • the depth of the first word line trench structure G1 is equal to the thickness of the silicon material layer 110, generally 100 to 200 nm, so the width of the first word line trench structure G1 can be set to 10 In the range of -25 nm, the aspect ratio is further controlled in the range of 4-20 to avoid voids in the first sacrificial layer 200. In this embodiment, the width of the first word line trench structure G1 is 21 to 23 nm.
  • the semiconductor device further includes an insulating layer (300, 600), which includes a first insulating layer 300 and a second insulating layer 600.
  • the second insulating layer 600 covers the first insulating layer 300 and the buried word line structure 500.
  • the thickness of the second insulating layer 600 is 20-50 nm; in other embodiments, the thickness of the second insulating layer 600 is 40 nm, 45 nm, or 50nm. Since the silicon nitride material has good insulating properties, in addition to preventing leakage by increasing the thickness of the insulating layer, the second insulating layer 600 is usually made of a silicon nitride material. In addition, the second insulating layer 600 can also be made of silicon oxynitride, silicon carbide nitride or other suitable insulating materials, but it is not limited thereto.

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Abstract

一种半导体器件及其制作方法。该方法包括：提供半导体基板；形成第一字线沟槽结构；在第一字线沟槽结构底部形成第一牺牲层；利用外延生长法填满位于有源区内的第一字线沟槽结构；形成第一绝缘层，其覆盖半导体基板的顶部和第一字线沟槽结构，并将第一字线沟槽结构封口；在有源区内形成第二字线沟槽结构和鳍型结构，第二字线沟槽结构的深度小于第一字线沟槽结构的深度，且第二字线沟槽结构在竖直方向上的投影与第一牺牲层在竖直方向上的投影完全重叠；去除第一牺牲层以形成字线隧道与所述第一字线沟槽结构连通；以及对第一字线沟槽结构、第二字线沟槽结构和字线隧道进行填充，以形成埋入式字线结构，埋入式字线结构环绕鳍型结构。

Description

半导体器件及其制作方法
相关申请交叉引用
本申请要求2020年02月14日递交的、标题为“半导体器件及其制作方法”、申请号为2020100925258的中国申请，其公开内容通过引用全部结合在本申请中。
技术领域
本发明涉及一种半导体器件及其制作方法。
背景技术
为提升动态随机存取存储器的集成度以加快元件的操作速度，以及符合消费者对于小型化电子装置的需求，近年来发展出埋入式字线动态随机存取存储器，以满足上述种种需求。
发明内容
根据一些实施例，本发明提供一种半导体器件的制作方法，包括：
提供半导体基板，所述半导体基板中具有浅沟槽隔离结构和平行设置的多个有源区；
在所述半导体基板中形成第一字线沟槽结构；
在所述第一字线沟槽结构底部形成第一牺牲层；
利用外延生长法填满位于所述有源区内的所述第一字线沟槽结构；
形成第一绝缘层，所述第一绝缘层覆盖所述半导体基板的顶部和位于浅沟槽隔离结构中的所述第一字线沟槽结构，并将所述第一字线沟槽结构封口；
在所述有源区内形成第二字线沟槽结构和鳍型结构，所述第二字线沟槽结构的深度小于所述第一字线沟槽结构的深度，且所述第二字线沟槽结构在竖直方向上的投影与所述第一牺牲层在竖直方向上的投影完全重叠；
去除所述第一牺牲层，在所述半导体基板中形成字线隧道与所述第一字线沟槽结构连通；以及
对所述第一字线沟槽结构、所述第二字线沟槽结构和所述字线隧道进行 填充，以形成埋入式字线结构，所述埋入式字线结构环绕所述鳍型结构。
根据一些实施例，本发明还提供一种半导体器件，包括：
半导体基板，具有浅沟槽隔离结构和平行设置的多个有源区；
埋入式字线结构，位于所述半导体基板内，沿第一方向延伸，跨过多个所述浅沟槽隔离结构和所述有源区；以及
鳍型结构，位于所述有源区与所述埋入式字线结构相交的区域中，且所述埋入式字线结构环绕包覆所述鳍型结构。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种半导体器件的制作方法流程图；
图2为本发明实施例提供的一种半导体基板的结构示意图；
图3为本发明实施例提供的一种形成有第一字线沟槽结构的半导体基板的结构示意图；
图4为本发明实施例提供的一种形成有第一牺牲层的半导体基板的结构示意图；
图5为本发明实施例提供的一种填充位于所述有源区内的所述第一字线沟槽结构后的半导体基板的结构示意图；
图6为本发明实施例提供的一种形成有第一绝缘层的半导体基板的结构示意图；
图7为本发明实施例提供的一种形成有第二字线沟槽结构和鳍型结构的半导体基板的结构示意图；
图8为本发明实施例提供的一种形成有字线隧道的半导体基板的结构示意图；
图9为图8中虚线框部分的埋入式字线结构的示意图；
图10为本发明实施例提供的一种形成有埋入式字线结构的半导体基板的结构示意图；
图11为本发明实施例提供的一种形成有第二绝缘层的半导体基板的结构示意图。
附图标号说明
100  半导体基板         110  硅材料层
120  氧化材料层         130  背衬底
200  第一牺牲层         300  第一绝缘层
400  鳍型结构           500  埋入式字线结构
510  栅氧化层           520  金属阻挡层
530  金属导电层         600  第二绝缘层
STI  浅沟槽隔离结构     AA   有源区
G1   第一字线沟槽结构   G2   第二字线沟槽结构
G3   字线隧道。
具体实施方式
随着存储器的集成度增加，随机存取存储器因为元件本身的尺寸很小，所以往往会因为工艺限制而影响有源区的面积，使得栅极的控制能力以及沟道宽度受限，从而导致半导体器件开启电压偏高、开启速度偏慢、工作电流较低，进而影响元件本身的效能。
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本发明。但是本发明能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似改进，因此本发明不受下面公开的具体实施的限制。
请参见图1，本发明实施例提供了一种半导体器件的制作方法，包括：
步骤S110，提供半导体基板100，所述半导体基板100中具有浅沟槽隔离结构STI和平行设置的多个有源区AA，请参见图2；
步骤S120，在所述半导体基板100中形成第一字线沟槽结构G1，请参见图3；
步骤S130，在所述第一字线沟槽结构G1底部形成第一牺牲层200，请参见图4；
步骤S140，利用外延生长法填满位于所述有源区AA内的所述第一字线沟槽结构G1，请参见图5；
步骤S150，形成第一绝缘层300，所述第一绝缘层300覆盖所述半导体基板100的顶部和位于浅沟槽隔离结构STI中的所述第一字线沟槽结构G1，并将所述第一字线沟槽结构G1封口，请参见图6；
步骤S160，在所述有源区AA内形成第二字线沟槽结构G2和鳍型结构400，所述第二字线沟槽结构G2的深度小于所述第一字线沟槽结构G1的深度，且所述第二字线沟槽结构G2在竖直方向上的投影与所述第一牺牲层200在竖直方向上的投影完全重叠，请参见图7；
步骤S170，去除所述第一牺牲层200，在所述半导体基板100中形成字线隧道G3与所述第一字线沟槽结构G1连通，请参见图8；
步骤S180，对所述第一字线沟槽结构G1、所述第二字线沟槽结构G2和所述字线隧道G3进行填充，以形成埋入式字线结构500，所述埋入式字线结构500环绕所述鳍型结构400，请参见图9-10。
本实施例中，通过先形成第一字线沟槽结构G1，然后在所述第一字线沟槽结构G1底部形成第一牺牲层200，并利用外延生长法填充位于所述有源区AA内的所述第一字线沟槽结构G1，再通过刻蚀形成所述第二字线沟槽结构G2，其次通过刻蚀所述第一牺牲层200形成字线隧道G3与所述第一字线沟槽结构G1连通，最后通过在所述第一字线沟槽结构G1、所述第二字线沟槽结构G2和所述字线隧道G3中填充铝、钨、铜或钛铝合金等具有低阻值的金属导电材料，以形成埋入式字线结构500，所述埋入式字线结构500环绕所述鳍型结构400。由于所述鳍型结构400被所述埋入式字线结构500环绕，因此可以提升切换效能，降低其阈值电压，以及提高其工作电流，有利于提升刷新效能。
在其中一个实施例中，所述半导体基板100为SOI(Silicon-On-Insulator，绝缘衬底上的硅)基板，包括硅材料层110、背衬底130以及夹设在所述硅材料层110和所述背衬底130之间的氧化材料层120。
可以理解，本实施例中采用SOI基板，在刻蚀所述第一字线沟槽结构G1 的过程中可以利用所述氧化材料层120作为刻蚀停止层，便于控制第一字线沟槽结构G1的深度。并且，所述氧化材料层120可以消除衬底基板中的漏电流影响，进一步提高半导体器件的效能。所述硅材料层110可以是未掺杂的硅材料层110或掺杂的硅材料层110，掺杂的硅材料层110可以是经过N型或P型掺杂的硅材料层110。
在其中一个实施例中，所述在所述半导体基板100中形成第一字线沟槽结构G1，包括：
在所述半导体基板100上形成光刻胶层；
在所述光刻胶层中形成与所述第一字线沟槽结构G1相匹配的目标图案；
以图案化的所述光刻胶层为掩膜层，以所述氧化材料层120为刻蚀停止层对所述硅材料层110进行刻蚀，形成所述第一字线沟槽结构G1；以及
去除剩余的所述光刻胶层。
本实施例中，利用旋转涂布法，在所述硅材料层110的表面涂覆一层光刻胶，形成所述光刻胶层，利用激光器通过光罩照射所述光刻胶层，引起曝光区域的光刻胶发生化学反应；再通过显影技术溶解去除曝光区域或未曝光区域的光刻胶(前者称正性光刻胶，后者称负性光刻胶)，将光罩上的图案转移到光刻胶层，形成目标图案；然后，以图案化的所述光刻胶层为掩膜层，以所述氧化材料层120为刻蚀停止层对所述硅材料层110进行刻蚀，形成所述第一字线沟槽结构G1；最后去除掉剩余的光刻胶层，形成所述第一字线沟槽结构G1。
在其中一个实施例中，所述第一字线沟槽结构G1的宽度为10～25nm。
可以理解，后续要在所述第一字线沟槽结构G1中形成第一牺牲层200，因此必需要考虑所述第一字线沟槽结构G1的深宽比，避免在填充形成所述第一牺牲层200材料时提前封口，进而形成空洞，要将所述第一字线沟槽结构G1的深宽比控制在合理的范围内。本实施例，所述第一字线沟槽结构G1的深度等于所述硅材料层110的厚度，一般在100～200nm，因此可将所述第一字线沟槽结构G1的宽度设置在10～25nm范围内，进而将其深宽比控制在4～20nm范围内，避免在所述第一牺牲层200中产生空洞。本实施中所述第一字线沟槽结构G1的宽度为21～23nm。
在其中一个实施例中，所述第一牺牲层200由相对于所述硅材料层110 和所述氧化材料层120具有刻蚀选择比大于1的材料形成。
可以理解，采用相对于所述硅材料层110和所述氧化材料层120具有刻蚀选择比大于1的材料形成所述第一牺牲层200时，可通过选用合适的刻蚀气体，采用干法刻蚀对形成第一牺牲层200的材料进行快速的刻蚀，且对硅材料层110和浅沟槽隔离结构STI的刻蚀较慢，硅材料层110和浅沟槽隔离结构STI几乎不受刻蚀。本实施例中，采用氮化硅形成第一牺牲层200；此外还可以采用其它的与Si和SiO的刻蚀比大于1的绝缘材料代替所述氮化硅。
在其中一个实施例中，所述在所述第一字线沟槽结构G1底部形成第一牺牲层200，包括：
在形成所述金属阻挡层的半导体基板100上，利用原子层沉积技术沉积氮化硅材料以形成填充所述第一字线沟槽结构G1并覆盖所述半导体基板100的氮化硅材料层110；
对所述氮化硅材料层110进行回刻蚀，控制剩余的所述氮化硅材料层的厚度为20～80nm，形成所述第一牺牲层200。
本实施例中，利用原子层沉积技术沉积氮化硅材料以形成填充所述第一字线沟槽结构G1并覆盖所述半导体基板100的氮化硅材料层110。然后，刻蚀掉所述半导体基板100顶面上的氮化硅，并将所述第一字线沟槽结构G1内的氮化硅刻蚀至预设高度范围内，形成所述第一牺牲层200。此外，还可以其它的沉积方式形成所述氮化硅材料层110，如化学气相沉积(CVD)、低压CVD(LPCVD)、等离子体增强CVD(PECVD)以及原子层沉积(ALD)等。
在其中一个实施例中，所述第一牺牲层200的高度H1为20～80nm。
具体设计方案中，所述第一牺牲层200的高度范围为20～80nm。由于所述第一牺牲层200的厚度决定了鳍型结构400的最低高端，决定导电沟道的位置，一般不能太小，以防止后续填充金属材料时出现空隙。因此本实施例中将所述第一牺牲层200的高度范围限制在20～80nm。在一些实施例中，所述第一牺牲层200的高度H1为50～70nm。具体地，所述第一牺牲层200的高度为50nm、55nm、60nm、65nm或70nm。
形成第一牺牲层200之后，利用外延生长法填满所述第一字线沟槽结构G1时，仅在硅材料层110的侧壁上固定生长单晶硅材料，进而实现填充位于 所述有源区AA内的所述第一字线沟槽结构G1的目的。同时生长出的单晶硅材料可与硅材料层110具有相同的特性，也可与硅材料层110具有不同的导电率等特性。其次，400～500℃条件下，利用沉积工艺以15～20nm/s的速率沉积氧化硅材料，并对所述第一字线沟槽结构G1进行封口，以形成所述第一绝缘层。一般地，位于所述半导体基板100表面上的所述绝缘层的厚度为50～150nm；本实施例中，将所述绝缘层的厚度设置在50～150nm范围内。然后，对所述绝缘层和所述半导体基板100进行刻蚀，形成第二字线沟槽结构G2。本实施例中，利用干法刻蚀工艺对所述绝缘层和所述半导体基板100进行刻蚀，由于所述硅材料层110侧壁的几何效应，所述硅材料层110侧壁上的形成浅沟槽隔离结构STI的氧化硅材料不会被刻蚀掉。
在其中一个实施例中，利用湿法刻蚀工艺去除所述第一牺牲层200。
本实施例中，所述第一牺牲层200采用氮化硅材料制作，由于部分氮化硅材料位于鳍型结构400的下方，无法利用干刻刻蚀，所以采用热磷酸在80～120℃温度条件下去除氮化硅材料，或者采用高温磷酸在150～200℃温度条件下去除氮化硅材料。
在其中一个实施例中，所述对所述第一字线沟槽结构G1、所述第二字线沟槽结构G2和所述字线隧道G3中进行填充，以形成埋入式字线结构500，如图9所示，包括：
在所述第二字线沟槽结构G2的侧壁和底部以及所述字线隧道G3的侧壁和顶部形成栅氧化层510；
在形成所述栅氧化层510的半导体基板100上形成金属阻挡层520，所述金属阻挡层520覆盖所述栅氧化层510、所述第一绝缘层300和所述浅沟槽隔离结构STI；
在所述第一字线沟槽结构G1、所述第二字线沟槽结构G2和所述字线隧道G3中填充金属导电材料，以形成金属导电层530；
对所述金属阻挡层520以及所述第一字线沟槽结构G1和所述第二字线沟槽结构G2内的所述金属导电材料回刻蚀至预设高度，以形成所述埋入式字线结构500。
本实施例中，所述埋入式字线结构500包括栅氧化层510、金属阻挡层520和金属导电层530。所述金属导电层530为钨材料层，此外还可以采用铝、 铜或钛铝合金等具有低阻值的金属材料替代。所述金属阻挡层520采用氮化钛(TiN)材料制作。氮化钛材料层与栅氧化层510的组合相比于单独设置栅氧化层510，有利于提高介电常数、缩小栅长度、提高驱动电流以及降低阈值电压。所述栅氧化层510是利用原位水汽生长(in-situ steam generation,ISSG)技术生长的。此外，还可以利用原子层沉积或者其他热氧化法生长所述栅氧化层510。
请参见图11，在其中一个实施例中，所述制作方法还包括：
在形成所述埋入式字线结构500的半导体基板100上形成第二绝缘层600，所述第二绝缘层600覆盖所述第一绝缘层300和所述埋入式字线结构500。
本实施例中，采用沉积工艺在形成所述埋入式字线结构500的半导体基板100上沉积氮化硅材料，填充所述第一字线沟槽结构G1和第二字线沟槽结构G2，并覆盖所述第一绝缘层300。在所述第一绝缘层300上方，所述第二绝缘层600的厚度为20～50nm；在一些实施例中，所述第二绝缘层600的厚度为40nm、45nm或50nm。由于氮化硅材料具有良好的绝缘性能，因此除了通过增加绝缘层厚度防止漏电外，通常选择氮化硅材料制作所述第二绝缘层600。此外，所述第二绝缘层600还可以采用氮氧化硅、氮碳化硅或其他适合的绝缘材料制作，但不以此为限。
基于同一发明构思，本发明实施例还提供了一种半导体器件，请再次参见图11，所述半导体器件包括：半导体基板100、埋入式字线结构500和鳍型结构400。
所述半导体基板100具有浅沟槽隔离结构STI和平行设置的多个有源区AA。
所述埋入式字线结构500位于所述半导体基板100内，沿第一方向延伸，跨过多个所述浅沟槽隔离结构STI和所述有源区AA。
所述鳍型结构400位于所述有源区AA与所述埋入式字线结构500相交的区域中，且所述埋入式字线结构500环绕包覆所述鳍型结构400。
本发明的半导体器件具有形成有鳍型结构和环绕所述鳍型结构400的所述埋入式字线结构500，由于所述鳍型结构400被所述埋入式字线结构500环绕，因此可以提升切换效能，降低其阈值电压，以及提高其工作电流，有 利于提升刷新效能。
在其中一个实施例中，所述半导体基板100为SOI(Silicon-On-Insulator，绝缘衬底上的硅)基板，包括硅材料层110、背衬底130以及夹设在所述硅材料层110和所述背衬底130之间的氧化材料层120。
可以理解，本实施例中采用SOI基板，在刻蚀所述第一字线沟槽结构G1的过程中可以利用所述氧化材料层120作为刻蚀停止层，便于控制第一字线沟槽结构G1的深度。并且，所述氧化材料层120可以消除衬底基板中的漏电流影响，进一步提高半导体器件的效能。所述硅材料层110可以是未掺杂的硅材料层110或掺杂的硅材料层110，掺杂的硅材料层110可以是经过N型或P型掺杂的硅材料层110。
在其中一个实施例中，位于所述鳍型结构400下方的所述埋入式字线结构500的高度为20～80nm。
具体设计方案中，所述第一牺牲层200的高度范围为20～80nm。由于所述第一牺牲层200的厚度决定了鳍型结构400的最低高端，决定导电沟道的位置，一般不能太小，以防止后续填充金属材料时出现空隙。因此本实施例中将所述第一牺牲层200的高度范围限制在20～80nm。在一些实施例中，所述第一牺牲层200的高度H1为50～70nm。具体地，所述第一牺牲层200的高度为50nm、55nm、60nm、65nm或70nm
在其中一个实施例中，位于所述鳍型结构上方的所述埋入式字线结构的高度为10～100nm。
一般来说，形成的第二沟槽结构的深度为50～150nm，在对所述第二沟槽结构填充并进行回刻蚀后，所述第二沟槽结构中回刻蚀的高度一般为50～100nm，位于所述鳍型结构上方的所述埋入式字线结构的高度范围为10～100nm，具体深度应根据需要进行设定。在一些实施例中，具体制作工艺中在所述硅衬底中形成的所述第二沟槽结构的深度为90～110nm，在对所述第二沟槽结构填充并进行回刻蚀后，所述第二沟槽结构中回刻蚀的高度一般为64～75nm，位于所述鳍型结构上方的所述埋入式字线结构的高度为30～45nm。在一些实施例中，所述位于所述鳍型结构上方的所述埋入式字线结构的高度为30nm、35nm、40nm或45nm。通过控制所述第二沟槽结构的深度可确定导电沟道的位置，通过控制所述第二沟槽结构中回刻蚀的高度可调节 所述埋入式字线结构的阻值。
在其中一个实施例中，所述埋入式字线结构500包括金属导电层530，所述金属导电层530与所述鳍型结构400绝缘设置，且环绕包覆所述鳍型结构400。本实施例中，所述金属导电层530为钨材料层，此外还可以采用铝、铜或钛铝合金等具有低阻值的金属材料替代。
在其中一个实施例中，所述埋入式字线结构500还包括：
栅氧化层510，设置于所述衬底基板面向所述金属导电层530的表面上，包覆所埋入式字线结构500；和
金属阻挡层520，设置于所述栅氧化层510与所述金属导电层530之间。
本实施例中，所述金属阻挡层520采用氮化钛(TiN)材料制作。氮化钛材料层与栅氧化层510的组合相比于单独设置栅氧化层510，有利于提高介电常数、缩小栅长度、提高驱动电流以及降低阈值电压。所述栅氧化层510是利用原位水汽生长技术形成的。此外，还可以利用原子层沉积或者其他热氧化法生长所述栅氧化层510。
在其中一个实施例中，所述埋入式字线结构500的宽度为10～25nm。
可以理解，后续要在所述第一字线沟槽结构G1中形成第一牺牲层200，因此必需要考虑所述第一字线沟槽结构G1的深宽比，避免在填充形成所述第一牺牲层200材料时提前封口，进而形成空洞，要将所述第一字线沟槽结构G1的深宽比控制在合理的范围内。本实施例，所述第一字线沟槽结构G1的深度等于所述硅材料层110的厚度，一般在100～200nm，因此可将所述第一字线沟槽结构G1的宽度设置在10～25nm范围内，进而将其深宽比控制在4～20范围内，避免在所述第一牺牲层200中产生空洞。本实施中所述第一字线沟槽结构G1的宽度为21～23nm。
在其中一个实施例中，所述半导体器件还包括绝缘层(300，600)，其包括第一绝缘层300和第二绝缘层600。所述第二绝缘层600覆盖所述第一绝缘层300和所述埋入式字线结构500。
本实施例中，在所述第一绝缘层300上方，所述第二绝缘层600的厚度为20～50nm；在其他一些实施例中，所述第二绝缘层600的厚度为40nm、45nm或50nm。由于氮化硅材料具有良好的绝缘性能，因此除了通过增加绝缘层厚度防止漏电外，通常选择氮化硅材料制作所述第二绝缘层600。此外， 所述第二绝缘层600还可以采用氮氧化硅、氮碳化硅或其他适合的绝缘材料制作，但不以此为限。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种半导体器件的制作方法，包括：
    提供半导体基板，所述半导体基板中具有浅沟槽隔离结构和平行设置的多个有源区；
    在所述半导体基板中形成第一字线沟槽结构；
    在所述第一字线沟槽结构底部形成第一牺牲层；
    利用外延生长法填满位于所述有源区内的所述第一字线沟槽结构；
    形成第一绝缘层，所述第一绝缘层覆盖所述半导体基板的顶部和位于浅沟槽隔离结构中的所述第一字线沟槽结构，并将所述第一字线沟槽结构封口；
    在所述有源区内形成第二字线沟槽结构和鳍型结构，所述第二字线沟槽结构的深度小于所述第一字线沟槽结构的深度，且所述第二字线沟槽结构在竖直方向上的投影与所述第一牺牲层在竖直方向上的投影完全重叠；以及
    去除所述第一牺牲层，在所述半导体基板中形成字线隧道与所述第一字线沟槽结构连通；
    对所述第一字线沟槽结构、所述第二字线沟槽结构和所述字线隧道进行填充，以形成埋入式字线结构，所述埋入式字线结构环绕所述鳍型结构。
  2. 如权利要求1所述的制作方法，其中所述对所述第一字线沟槽结构、所述第二字线沟槽结构和所述字线隧道进行填充，以形成埋入式字线结构，包括：
    在所述第二字线沟槽结构的侧壁和底部以及所述字线隧道的侧壁和顶部形成栅氧化层；
    在形成所述栅氧化层的半导体基板上形成金属阻挡层，所述金属阻挡层覆盖所述栅氧化层、所述第一绝缘层和所述浅沟槽隔离结构；
    在所述第一字线沟槽结构、所述第二字线沟槽结构和所述字线隧道中填充金属导电材料，以形成金属导电层；以及
    对所述金属阻挡层以及所述第一字线沟槽结构和所述第二字线沟槽结构内的所述金属导电材料回刻蚀至预设高度，以形成所述埋入式字线结构。
  3. 如权利要求1所述的制作方法，其中利用湿法刻蚀工艺去除所述第一牺牲层。
  4. 如权利要求1所述的制作方法，其中所述第一牺牲层的高度为20～ 80nm。
  5. 如权利要求1所述的制作方法，其中所述半导体基板为SOI基板，包括硅材料层、背衬底以及夹设在所述硅材料层和所述背衬底之间的氧化材料层。
  6. 如权利要求5所述的制作方法，其中所述在所述半导体基板中形成第一字线沟槽结构，包括：
    在所述半导体基板上形成光刻胶层；
    在所述光刻胶层中形成与所述第一字线沟槽结构相匹配的目标图案；
    以图案化的所述光刻胶层为掩膜层，以所述氧化材料层为刻蚀停止层对所述硅材料层进行刻蚀，形成所述第一字线沟槽结构；以及
    去除剩余的所述光刻胶层。
  7. 如权利要求1～6任一项所述的制作方法，其中所述第一字线沟槽结构的宽度为10～25nm。
  8. 如权利要求6所述的制作方法，所述第一牺牲层由相对于所述硅材料层和所述氧化材料层具有刻蚀选择比大于1的材料形成。
  9. 如权利要求2所述的制作方法，其中所述在所述第一字线沟槽结构底部形成第一牺牲层，包括：
    在形成所述金属阻挡层的半导体基板上，利用原子层沉积技术沉积氮化硅材料以形成填充所述第一字线沟槽结构并覆盖所述半导体基板的氮化硅材料层；以及
    对所述氮化硅材料层进行回刻蚀，控制剩余的所述氮化硅材料层的厚度为20～80nm，形成所述第一牺牲层。
  10. 如权利要求1所述的制作方法，还包括：
    在形成所述埋入式字线结构的半导体基板上形成绝缘层，所述绝缘层覆盖所述埋入式字线结构。
  11. 如权利要求10所述的制作方法，所述第二绝缘层的厚度为40nm、45nm或50nm。
  12. 一种半导体器件，包括：
    半导体基板，具有浅沟槽隔离结构和平行设置的多个有源区；
    埋入式字线结构，位于所述半导体基板内，沿第一方向延伸，跨过多个 所述浅沟槽隔离结构和所述有源区；以及
    鳍型结构，位于所述有源区与所述埋入式字线结构相交的区域中，且所述埋入式字线结构环绕包覆所述鳍型结构。
  13. 如权利要求12所述的半导体器件，其中所述半导体基板为SOI基板，包括硅材料层、背衬底以及夹设在所述硅材料层和所述背衬底之间的氧化材料层。
  14. 如权利要求12所述的半导体器件，其中位于所述鳍型结构下方的所述埋入式字线结构的高度为20～80nm。
  15. 如权利要求12所述的半导体器件，其中位于所述鳍型结构上方的所述埋入式字线结构的高度为10～100nm。
  16. 如权利要求13所述的半导体器件，其中所述埋入式字线结构包括金属导电层，所述金属导电层与所述鳍型结构绝缘设置，且环绕包覆所述鳍型结构。
  17. 如权利要求16所述的半导体器件，其中所述埋入式字线结构还包括：
    栅氧化层，设置于所述衬底基板面向所述金属导电层的表面上，包覆所埋入式字线结构；和
    金属阻挡层，设置于所述栅氧化层与所述金属导电层之间。
  18. 如权利要求16所述的半导体器件，其中所述金属导电层的制作材料为铝、钨、铜或钛铝合金。
  19. 如权利要求13所述的半导体器件，其中所述埋入式字线结构的宽度为10～25nm。
  20. 如权利要求13所述的半导体器件，其中还包括绝缘层，所述绝缘层覆盖所述埋入式字线结构。
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