WO2019087784A1 - 薄膜トランジスタ及びその製造方法 - Google Patents

薄膜トランジスタ及びその製造方法 Download PDF

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WO2019087784A1
WO2019087784A1 PCT/JP2018/038616 JP2018038616W WO2019087784A1 WO 2019087784 A1 WO2019087784 A1 WO 2019087784A1 JP 2018038616 W JP2018038616 W JP 2018038616W WO 2019087784 A1 WO2019087784 A1 WO 2019087784A1
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metal oxide
oxide layer
layer
thin film
film transistor
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PCT/JP2018/038616
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English (en)
French (fr)
Japanese (ja)
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亨 菊池
大園　修司
太田　淳
秀昭 座間
伸 浅利
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株式会社アルバック
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Priority to CN201880058156.1A priority Critical patent/CN111052397B/zh
Priority to JP2019509580A priority patent/JP6703186B2/ja
Priority to KR1020207009025A priority patent/KR102317441B1/ko
Publication of WO2019087784A1 publication Critical patent/WO2019087784A1/ja

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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
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    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • the present invention relates to a thin film transistor having a multi-layered gate insulating film and a method of manufacturing the same.
  • the LTPS thin film transistor (Low Temperature Poly Silicon TFT) has high mobility and is used for an organic EL display device or a liquid crystal display device.
  • Patent Document 1 discloses a thin film transistor using LTPS as an active layer.
  • a thin film transistor using polysilicon is formed on a polysilicon in the order of a gate insulating film and a gate electrode.
  • the gate insulating film is not uniformly deposited on the uneven polysilicon. Therefore, a leak current flows between the gate electrode and the polysilicon, which causes a problem on the display device such as unevenness in the image.
  • the manufacturing method of the thin film transistor concerning one form of the present invention is: Forming an active layer on the substrate. Source and drain regions are formed to be electrically connectable to the active layer. A first metal oxide layer composed of silicon oxide is formed on the surface of the active layer by plasma CVD. A second metal oxide layer composed of aluminum oxide is formed by ALD on the surface of the first metal oxide layer. A gate electrode is formed on the surface of the second metal oxide layer.
  • first and second metal oxide layers are sequentially formed as the gate insulating film. Since the second metal oxide layer is formed of an aluminum oxide film formed by ALD, a high coverage can be obtained as compared to a gate insulating film of a silicon oxide single film formed by plasma CVD. Thereby, it is possible to effectively prevent the leak current between the gate electrode and the active layer, and it is possible to manufacture a thin film transistor capable of excellent threshold voltage control.
  • the gate insulating film in multiple layers in this manner, the apparent dielectric constant is higher than that of the gate insulating film made of a silicon oxide single film. This improves the charge mobility of the active layer.
  • the method may further include the steps of forming a hydrogen-rich intermediate layer between the first metal oxide layer and the second metal oxide layer, and annealing the intermediate layer.
  • a large amount of hydrogen atoms contained in the hydrogen-rich intermediate layer are transferred to the interface between the active layer and the first metal oxide layer by annealing.
  • a large amount of hydrogen atoms terminate dangling bonds present at the interface to lower the interface state density. This makes it possible to prevent a leak current between the gate electrode and the active layer, and to manufacture a thin film transistor having good switching characteristics.
  • the second metal oxide layer functions as a barrier layer, and hydrogen atoms contained in the first metal oxide layer and the intermediate layer are annealed to form the active layer and the first metal oxide. It becomes easy to move to the interface with the object layer. This makes it possible to enhance the defect repair effect of the interface.
  • the intermediate layer may be formed by hydrogen plasma treatment of the first metal oxide layer.
  • the intermediate layer may be formed by forming a layer of silicon nitride or silicon oxynitride between the first and second metal oxide layers.
  • the step of forming the first metal oxide layer and the step of forming the layer of silicon nitride or silicon oxynitride may be performed in the same chamber.
  • the step of forming the first metal oxide layer and the step of forming the layer of silicon nitride or silicon oxynitride may be performed in the same chamber.
  • the step of forming the first metal oxide layer and the step of forming the second metal oxide layer may be performed continuously in a vacuum atmosphere. As described above, by making the substrate processing vacuum consistent, it is possible to prevent contamination of the substrate surface by gas or air.
  • a thin film transistor includes a gate electrode, an active layer, a source region and a drain region, and a gate insulating film.
  • the active layer is composed of polysilicon.
  • the source region and the drain region are electrically connected to the active layer.
  • the gate insulating film includes a first metal oxide layer and a second metal oxide layer.
  • the first metal oxide layer is made of silicon oxide and disposed between the gate electrode and the active layer.
  • the second metal oxide layer is made of aluminum oxide and is disposed between the first metal oxide layer and the gate electrode.
  • the gate insulating film may further include an intermediate layer containing silicon nitride between the first metal oxide layer and the second metal oxide layer.
  • the gate insulating film may further include an intermediate layer containing silicon oxynitride between the first metal oxide layer and the second metal oxide layer.
  • the thickness of the intermediate layer may be 3 nm or more and 10 nm or less. Since the intermediate layer functions only as a source of hydrogen atoms, it becomes possible to supply a sufficient amount of hydrogen to the interface with a thickness of 3 nm or more and 10 nm or less.
  • the present invention it is possible to provide a thin film transistor having a gate insulating film with high coverage and excellent transistor characteristics, and a method of manufacturing the same.
  • FIG. 1 is a schematic view of an ALD apparatus used for manufacturing a thin film transistor according to an aspect of the present invention. It is process sectional drawing explaining the manufacturing method of the said thin-film transistor. It is process sectional drawing explaining the manufacturing method of the said thin-film transistor. It is process sectional drawing explaining the manufacturing method of the said thin-film transistor. It is process sectional drawing explaining the manufacturing method of the said thin-film transistor. It is process sectional drawing explaining the manufacturing method of the said thin-film transistor.
  • TEOS-SiO X is used for the gate insulating film used for LTPS.
  • the gate insulating film used for TEOS-SiO x is superior in thin film transistor characteristics to the gate insulating film made of SiH 4 -SiO.
  • the flat band voltage is close to the ideal value, the threshold voltage control of the thin film transistor is relatively easy, the long-term stability of the thin film transistor characteristics is excellent, the defect state density of the interface is small, etc. It is characterized by
  • the TEOS-SiO X film has a problem that it is difficult to obtain a good coverage for the device pattern.
  • a gate insulating film and a gate electrode are sequentially formed on polysilicon as an active layer. If the coverage of the gate insulating film formed on the uneven polysilicon is poor, the gate insulating film is not uniformly deposited, and a leak current flows between the gate electrode and the polysilicon, causing an image to appear on the image. It becomes a problem on the display device that unevenness occurs. In order to increase the aperture ratio of the pixel portion of the display device and to reduce the power consumption of peripheral circuits other than the pixel, it is necessary to lower the operating voltage.
  • Atomic layer deposition is known as an insulating film deposition technique excellent in coverage with respect to asperities. This is a method of forming a thin film of which atomic layer control is performed by sequentially supplying two or more kinds of source gases to the substrate surface.
  • ALD uses the function of self-terminating adsorption and reaction in a single molecular layer when the raw material is supplied to the surface of the substrate, which makes it extremely suitable for the unevenness of the substrate, and the coverage is approximately 100% It is a formation method of the insulating film which is.
  • the flat band voltage tends to be largely shifted to the positive side, as described later. If hysteresis occurs, which causes a difference in flat band voltage depending on whether the start voltage at the time of CV curve measurement is positive or negative, the threshold voltage of the transistor characteristics becomes unstable. It can not be used.
  • the coverage of polysilicon is increased while the hysteresis characteristics of the CV curve are suppressed, and good transistor characteristics are obtained. I am trying to get it.
  • FIG. 1 is a schematic cross-sectional view of a thin film transistor 1 according to an embodiment of the present invention.
  • the thin film transistor 1 includes an active layer 11, a source region 14S and a drain region 14D, a gate insulating film 12, and a gate electrode 13.
  • the gate insulating film 12 is formed to cover the active layer 11, the source region 14 S, and the drain region 14 D formed on the substrate 10, and the gate electrode 13 is formed on the gate insulating film 12. It is composed of a gated thin film transistor.
  • the active layer 11 is made of polysilicon formed on the insulating film (for example, silicon oxide film) 10 a on the substrate 10 and functions as a channel layer of the thin film transistor 1.
  • the substrate 10 is typically a transparent glass substrate, but may be a semiconductor substrate such as a silicon substrate or a resin substrate such as a plastic film.
  • the active layer 11 is formed by crystallizing amorphous silicon formed on the substrate 10 by annealing, as described later.
  • the thickness of the active layer 11 is not particularly limited, and is, for example, 40 nm to 50 nm.
  • the source region 14S and the drain region 14D are formed apart from each other so as to sandwich the active layer 11.
  • the source region 14S and the drain region 14D are formed, for example, by implanting impurity ions into a polysilicon film forming the active layer 11, as described later.
  • the gate insulating film 12 is disposed between the active layer 11 and the gate electrode 13 and electrically insulates between these, and the charge is inverted in the active layer 11 by the voltage applied to the gate electrode 12. It has a function of forming a layer (inversion layer).
  • the gate insulating film 12 has a first metal oxide layer 12A and a second metal oxide layer 12B.
  • the first metal oxide layer 12A is formed on the substrate 10 so as to cover the active layer 11, and the source region 14S and the drain region 14D.
  • the first metal oxide layer 12A is made of silicon oxide (SiO x ), and in this embodiment, is made of silicon oxide formed using silane (SiH 4 ) or TEOS as a film forming material. Accordingly, the thin film transistor 1 can relatively easily control the threshold voltage, and can obtain excellent characteristics such as excellent long-term stability of transistor characteristics and small interface state density.
  • the thickness of the first metal oxide layer 12A can be, for example, 10 nm to 120 nm.
  • plasma-enhanced chemical vapor deposition is used as described later.
  • silicon compounds such as silane (SiH 4 ) and tetraethoxysilane (TEOS) can be used as source gases for plasma CVD.
  • TEOS and oxygen (O 2 ) are used as source gases for plasma CVD.
  • the second metal oxide layer 12B is formed on the first metal oxide layer 12A.
  • the second metal oxide layer 12B is made of aluminum oxide (Al 2 O 3 ).
  • ALD Atomic Layer Deposition
  • various aluminum compounds can be used, and in the present embodiment, trimethylaluminum (TMA) is used.
  • TMA trimethylaluminum
  • an oxidizing gas such as oxygen or ozone (O 3 ) can be used, and in the present embodiment, water vapor (H 2 O) is used.
  • the purge gas for ALD is not particularly limited, and in the present embodiment, nitrogen (N 2 ) is used.
  • ALD is excellent in step coverage and film thickness controllability, and the Al 2 O 3 layer produced by ALD has excellent coverage and can effectively prevent leak current.
  • the gate insulating film is formed of a single layer of Al 2 O 3 thin film, the flat band voltage tends to shift in the positive direction, which causes hysteresis characteristics, and depending on the magnitude of the hysteresis characteristics, The threshold voltage of the thin film transistor may be unstable.
  • the gate insulating film 12 is formed by sequentially laminating a first metal oxide layer 12A composed of TEOS-SiO x and a second metal oxide layer 12B composed of Al 2 O 3 . It has a two-layer structure. This structure makes it possible to suppress the hysteresis characteristics attributed to the Al 2 O 3 layer and obtain an excellent coverage. Thereby, the thin film transistor 1 can perform good threshold voltage control while preventing a leak current.
  • the thickness of the second metal oxide layer 12B can be, for example, 10 nm to 120 nm. This makes it possible to obtain excellent coverage while suppressing hysteresis characteristics.
  • the thickness of the gate insulating film 12 (the sum of the thickness of the first metal oxide layer 12A and the thickness of the second metal oxide layer 12B) within 130 nm in total, the miniaturization of the thin film transistor 1 can be achieved. It is possible to obtain each of the above effects.
  • the gate electrode 13 is formed of a conductive film formed on the gate insulating film 12.
  • the gate electrode 13 is typically formed of a metal single layer film or a metal multilayer film of Al, Mo, Cu, Ti or the like, and is formed by, for example, a sputtering method.
  • the thickness of the gate electrode 13 is not particularly limited, and is, for example, 200 nm to 300 nm.
  • An interlayer insulating film 15 is formed on the gate insulating film 12 and the gate electrode 13.
  • the interlayer insulating film 15 is for maintaining the insulation between the electrodes.
  • the interlayer insulating film 15 is made of an electrically insulating material, and typically made of silicon oxide, silicon nitride or the like.
  • the thickness of the interlayer insulating film 15 is not particularly limited, and is, for example, 200 nm to 500 nm.
  • the thin film transistor 1 further includes a source electrode 16S and a drain electrode 16D.
  • the source electrode 16S and the drain electrode 16D penetrate the interlayer insulating film 15 and the gate insulating film 12, and are electrically connected to the source region 14S and the drain region 14D, respectively.
  • the source electrode 16S and the drain electrode 16D are configured as lead electrodes for connecting the source region 14S and the drain region 14D to peripheral circuits (not shown).
  • the insulating film 10 a and the amorphous silicon film A are formed on the substrate 10.
  • the insulating film 10a is typically formed of a silicon oxide film, but may of course be formed of another material and may be omitted if necessary.
  • the raw material of the amorphous silicon film A is not particularly limited. For example, if it is formed by plasma CVD, silicon compounds such as silane (SiH 4 ) and disilane (Si 2 H 6 ) can be used as a raw material gas.
  • a gate insulating film 12 is formed on the substrate 10 so as to cover the surface of the active layer 11.
  • the step of forming the gate insulating film 12 includes the steps of forming a first metal oxide layer 12A and forming a second metal oxide layer 12B.
  • the first metal oxide layer 12A is formed on the substrate 10 so as to cover the surface of the active layer 11.
  • the first metal oxide layer 12A is formed by plasma CVD.
  • the plasma CVD apparatus is not particularly limited, and in the present embodiment, a plasma CVD apparatus 100 schematically shown in FIG. 4 is used.
  • the plasma CVD apparatus 100 includes a vacuum chamber 110 and a stage 111 for supporting a substrate provided inside the vacuum chamber 110.
  • the stage 111 has a heater 112 inside.
  • a high frequency electrode 113 is disposed at a position facing the heater stage 111.
  • the high frequency electrode 113 has a shower head 114, and the shower head 114 is provided with a gas diffusion plate 115 for uniformly diffusing the gas introduced from the gas introduction system and a plurality of ejection holes 116 for ejecting the gas.
  • a vacuum evacuation system 120 Connected to the vacuum chamber 110 are a vacuum evacuation system 120, a power supply system 130 having a high frequency power source, a controller 140, and a gas introduction system (not shown).
  • the controller 140 controls the heater 112, the power supply system 130, the vacuum exhaust system 120, and the gas introduction system, respectively.
  • TEOS and O 2 are used as a source gas (CVD gas) for plasma CVD.
  • the film formation conditions are not particularly limited, and for example, when the glass substrate size is 730 mm ⁇ 920 mm, the following conditions are implemented.
  • TEOS flow rate 360 [sccm] O 2 flow rate: 16000 [sccm]
  • Process pressure 175 [Pa]
  • RF frequency 27.12 [MHz]
  • RF power 4000 [W]
  • Heater temperature 350 [° C]
  • the second metal oxide layer 12B is formed to cover the first metal oxide layer 12A.
  • the second metal oxide layer 12B is formed by ALD.
  • the ALD apparatus is not particularly limited, and in the present embodiment, the ALD apparatus 200 schematically shown in FIG. 5 is used.
  • the ALD apparatus 200 includes a vacuum chamber 210 and a stage 211 for supporting a substrate provided inside the vacuum chamber 210.
  • the stage 211 has a heater 212 inside.
  • a controller 220 controls the heater 212, the gas introduction system and the vacuum exhaust system, respectively.
  • the gas introduction system is configured to be capable of introducing the source gas, the reaction gas, and the purge gas independently or mixed into the vacuum chamber 210.
  • TMA gas is used as the source gas
  • water vapor is used as the reaction gas
  • N 2 gas is used as the purge gas.
  • a TMA gas is introduced into the vacuum chamber 210 as a source gas from the gas introduction system. Molecules of TMA gas introduced into the vacuum chamber 210 are adsorbed (chemisorbed) on the surface of the substrate 10. After the molecules of the TMA gas are adsorbed on the surface of the substrate 10, the introduction of the TMA gas from the gas introduction system is stopped.
  • the temperature of the substrate 10 can be 250 ° C.
  • the pressure in the vacuum chamber 210 can be 100 Pa
  • the amount of TMA gas introduced can be 3 cc / cycle.
  • the temperature of the substrate 10 is set to 250 ° C. also in the subsequent processing.
  • N 2 gas is introduced as a purge gas from the gas introduction system.
  • the pressure in the vacuum chamber 210 is increased by the purge gas, and the source gas is pushed out.
  • the source gas diffused in the vacuum chamber 210 is evacuated by the exhaust pump.
  • the purge conditions were such that the introduction time of the N 2 gas was 1 second, the pressure in the vacuum chamber 210 was 100 Pa, and the flow rate of the N 2 gas was 1000 sccm.
  • water vapor is introduced as a reaction gas from the gas introduction system.
  • the water vapor introduced into the vacuum chamber 210 reacts with the molecules of the TMA gas adhering to the surface of the substrate 10 to oxidize the TMA, and a thin film of aluminum oxide (Al 2 O 3 ) is formed on the surface of the substrate 10 .
  • the introduction of the reaction gas from the gas introduction system is stopped.
  • the oxidation conditions were such that the pressure in the vacuum chamber 210 was 100 Pa, and the amount of water vapor introduced was 3 cc / cycle.
  • N 2 gas is introduced as a purge gas from the gas introduction system.
  • the pressure in the vacuum chamber 210 is increased by the purge gas and the water vapor is pushed out.
  • the water vapor diffused in the vacuum chamber 210 is evacuated by an exhaust pump.
  • the purge conditions were such that the introduction time of the N 2 gas was 1 second, the pressure in the vacuum chamber 210 was 100 Pa, and the flow rate of the N 2 gas was 1000 sccm.
  • the first to fourth steps are sequentially repeated a plurality of cycles until the thin film has a desired thickness, whereby the second metal oxide layer 12B made of an Al 2 O 3 thin film is formed.
  • Step of forming gate electrode Next, as shown in FIG. 6, the gate electrode 13 is formed on the second metal oxide layer 12B.
  • the gate electrode 13 is typically formed of a metal single layer film or metal multilayer film of aluminum, molybdenum, copper, titanium or the like, and is formed by, for example, a sputtering method.
  • the gate electrode 13 is formed by patterning the metal film into a predetermined shape.
  • Step of forming source region and drain region Subsequently, as shown in FIG. 7, a source region 14S and a drain region 14D are respectively formed.
  • the method of forming the source region 14S and the drain region 14D is not particularly limited, and in this embodiment, the source region 14S and the source region 14S are formed in predetermined regions of the polysilicon film forming the active layer 11 by ion implantation technology using the gate electrode 13 as a mask. Drain regions 14D are respectively formed.
  • the impurity ions (dopant) to be implanted are appropriately selected according to the conductivity type (N type, P type) of the active layer 11, and typically, boron (B) or phosphorus (P) is used.
  • Step of forming interlayer insulating film and source / drain electrode Next, as shown in FIG. 8, an interlayer insulating film 15 is formed to cover the gate electrode 13 and the second metal oxide layer 12B.
  • the interlayer insulating film 15 is made of an electrically insulating material. Typically, it is composed of an oxide film or nitride film such as a silicon oxide film or a silicon nitride film, and a laminated film of these.
  • the interlayer insulating film 15 is formed by, for example, a CVD method or a sputtering method.
  • openings D1 and D2 reaching the source region 14S and the drain region 14D are formed to penetrate the interlayer insulating film 15 and the gate insulating film 12.
  • the method for forming the openings D1 and D2 is not particularly limited, and, for example, a laser processing technique, an etching method, or the like is used.
  • a metal film filling the openings D1 and D2 is formed on the interlayer insulating film 15, and the metal film is patterned into a predetermined shape to form the source electrode 16S and the drain electrode 16D. As described above, the thin film transistor 1 shown in FIG. 1 is manufactured.
  • the gate insulating film 12 is formed of a laminated film of a first metal oxide layer 12A and a second metal oxide layer 12B. Since the second metal oxide layer 12B is formed of an aluminum oxide layer formed by ALD, the coverage with respect to the active layer 11 is higher than that of a gate insulating film made of a silicon oxide single film formed by plasma CVD. Is obtained.
  • the gate insulating film when the gate insulating film is formed of a single layer of Al 2 O 3 thin film, the flat band voltage tends to shift in the positive direction. In addition, hysteresis characteristics are likely to occur. When a gate insulating film having hysteresis characteristics is applied to a thin film transistor, the threshold voltage of the thin film transistor may be unstable.
  • the inventors fabricated a plurality of samples having different gate insulating film configurations on a silicon wafer, and evaluated their flat band voltage and hysteresis characteristics.
  • Sample 1 having a gate insulating film consisting of a single layer of Al 2 O 3 thin film deposited by ALD, and Sample having a gate insulating film consisting of a single layer of TEOS-SiO x thin film deposited by plasma CVD 2 were produced.
  • the plasma CVD apparatus 100 and the ALD apparatus 200 shown in FIG. 4 and FIG. 5 were used as the film forming apparatus.
  • FIG. 9 and Table 1 show measurement results showing the relationship between the film thickness of the gate insulating film and the flat band voltage (Vfb) in Samples 1 and 2.
  • Vfb flat band voltage
  • FIG. 9 open diamonds indicate Al 2 O 3 thin films and black squares indicate TEOS-SiO x thin films.
  • sample 1 in which the gate insulating film is formed of an Al 2 O 3 thin film has a flat band voltage of +3 V or more And a large shift in the positive direction.
  • the flat band voltage is shifted to the positive as described above.
  • the flat band voltage is different between when the start voltage at the time of CV curve measurement is plus and minus when there is a hysteresis characteristic.
  • the generation of the hysteresis characteristic in the CV curve means that the threshold voltage of the transistor characteristic is unstable, which is not preferable as a gate insulating film.
  • the gate insulating film is an Al 2 O 3 thin film formed on the TEOS-SiO x thin film
  • the hysteresis characteristic like the above-mentioned sample of only Al 2 O 3 thin film is not generated. Is confirmed. As described above, it has been confirmed that the hysteresis characteristic of the CV curve hardly occurs in the thin film of the two-layer structure in which the TEOS-SiO x thin film and the Al 2 O 3 thin film are sequentially formed on the silicon substrate.
  • the gate insulating film 12 is formed of the first metal oxide layer 12A composed of TEOS-SiO x and Al 2 O 3 on the active layer 11. Since the structured second metal oxide layer 12B and the second metal oxide layer 12B are sequentially formed, the occurrence of hysteresis characteristics can be suppressed. Thereby, the thin film transistor 1 can perform good threshold voltage control.
  • the band voltage Vfb (V), the hysteresis (V), and the interface state density Dit (eV -1 ⁇ cm -2 ) were measured, respectively. The above measurements were performed immediately after film formation and after annealing (500 ° C.).
  • the interface state density after the annealing treatment is greatly reduced when the film thickness of the first metal oxide layer 12A (TEOS-SiO x ) is 20 nm or more and 80 nm or less. Ru.
  • the first metal oxide layer 12A is formed by plasma CVD, hydrogen atoms are contained in the first metal oxide layer 12A. The hydrogen atoms are transferred to the interface between the active layer 11 and the first metal oxide layer 12A by annealing, and the interface state density is lowered by terminating dangling bonds present at the interface. it is conceivable that.
  • the gate insulating film 12 includes the first metal oxide layer 12A formed of the TEOS-SiO x thin film and the second metal oxide layer 12B formed of the Al 2 O 3 thin film.
  • the above-described laminated structure ensures excellent threshold voltage control without generating hysteresis characteristics of Al 2 O 3 .
  • the gate insulating film 12 can be formed with a very high coverage to the active layer 11, leak current between the gate electrode 13 and the active layer 11 can be prevented, and good switching characteristics can be obtained. .
  • the thin film transistor can be miniaturized and thinned, and the aperture ratio of the pixel portion of the display device can be increased.
  • the operating voltage of the thin film transistor can be reduced, power consumption of the display device can be reduced.
  • FIG. 15 is a schematic cross-sectional view of a thin film transistor 2 according to a second embodiment of the present invention.
  • the configuration different from the first embodiment will be mainly described, and the same configuration as that of the above-described embodiment will be denoted by the same reference numeral, and the description thereof will be omitted or simplified.
  • the thin film transistor 2 of the present embodiment differs from that of the first embodiment in the configuration of the gate insulating film 22.
  • the gate insulating film 22 further includes an intermediate layer 12C disposed between the first metal oxide layer 12A and the second metal oxide layer 12B.
  • the intermediate layer 12C is a hydrogen-rich layer containing a large amount of hydrogen atoms, and is made of, for example, silicon nitride (SiN x ) or silicon oxynitride (SiO x N y ) formed by plasma CVD.
  • the intermediate layer 12C a large amount of hydrogen atoms contained in the intermediate layer 12C move to the interface between the active layer 11 and the first metal oxide layer 12A by the annealing process described later. A large amount of hydrogen atoms terminate dangling bonds present at the interface and an effect of reducing interface state density is obtained.
  • the thickness of the intermediate layer 12C is not particularly limited as long as it has a function of supplying hydrogen atoms to dangling bonds as described above, and is, for example, 3 nm or more and 30 nm or less.
  • the step of forming an intermediate layer is included after the step of forming the first metal oxide layer.
  • the process of forming the active layer, the process of forming the source and drain regions, the process of forming the gate electrode, the process of forming the interlayer insulating film, and the process of forming the source and drain electrodes are the same as in the first embodiment. , I omit the explanation here.
  • the intermediate layer 12C is formed on the first metal oxide layer 12A.
  • the method for forming the intermediate layer 12C is not particularly limited as long as it is a method in which a hydrogen atom is contained in the intermediate layer 12C.
  • plasma CVD is used.
  • SiH 4 , NH 3 and N 2 are used as source gases for plasma CVD, and an intermediate layer 12 C composed of SiN x is formed.
  • the intermediate layer 12C is annealed at a predetermined temperature (for example, 500 ° C.). The annealing may be performed before or after the formation of the second metal oxide layer 12B.
  • annealing treatment is performed after the second metal oxide layer 12B is formed. It is desirable to
  • the plasma CVD apparatus for forming the intermediate layer 12C is not particularly limited.
  • the plasma CVD apparatus 100 described with reference to FIG. 4 can be employed.
  • the film forming conditions for the intermediate layer 12C are not particularly limited. For example, when the glass substrate size is 730 mm ⁇ 920 mm, the following conditions are implemented. SiH 4 flow rate: 500 [sccm] NH 3 flow rate: 5000 [sccm] N 2 flow rate: 7000 [sccm] Process pressure: 200 [Pa] RF frequency: 27.12 [MHz] RF power: 4000 [W] Heater temperature: 350 [° C]
  • the same operation and effect as those of the above-described first embodiment can be obtained.
  • a large amount of hydrogen atoms contained in the hydrogen-rich intermediate layer 12C move to the interface between the active layer 11 and the first metal oxide layer 12A by annealing.
  • a large amount of hydrogen atoms terminate dangling bonds present at the interface to lower the interface state density.
  • the second metal oxide layer 12B functions as a hydrogen barrier layer, and the hydrogen atoms contained in the intermediate layer 12C are annealed to form the active layer 11 and the first metal oxide layer 12A. It is easy to move to the interface with This makes it possible to enhance the defect repair effect of the interface.
  • the step of forming the first metal oxide layer 12A and the step of forming the intermediate layer 12C may be performed in the same chamber. This makes it possible to prevent the contamination of the surface of the first metal oxide layer 12A accompanying the replacement of the processing target substrate. Moreover, it becomes possible to reduce the effort of board
  • the interface state density Dit (eV ⁇ 1 ⁇ cm ⁇ 2 ) was measured by changing the structure of the gate insulating film as follows.
  • the structure of the gate insulating film of each thin film transistor used in the experiment is the structure of only the first metal oxide layer 12A (film thickness 80 nm), the structure of only the second metal oxide layer 12B (film thickness 80 nm), the first Layer structure of the metal oxide layer 12A (film thickness 50 nm) and the second metal oxide layer 12B (film thickness 50 nm), and the first metal oxide layer 12A (film thickness 50 nm) and the second metal An intermediate layer 12C (film thickness 3 nm) is disposed between the oxide layer 12B (film thickness 50 nm) and the three-layer structure.
  • the interface state density was measured immediately after film formation and after annealing (500 ° C.).
  • Table 3 shows the interface state density obtained by the above measurement.
  • the interface state density after annealing is lower in the two-layer structure and the three-layer structure compared to when the gate insulating film is a single film, which is a preferable value for the thin film transistor characteristics. That is confirmed. It is confirmed that the interface state density when the gate insulating film has the above three-layer structure is lower than that of the above two-layer structure, which is a more preferable value. This is because the large amount of hydrogen atoms contained in the intermediate layer 12C is transferred to the interface between the active layer 11 and the first metal oxide layer 12A by the annealing process, and the dangling bond is terminated, so that the interface is further improved. It is considered that the rank density is lowered. Thereby, the thin film transistor 2 can obtain more excellent switching characteristics.
  • the second metal oxide layer 12B was involved as a hydrogen barrier layer in this result. Specifically, the second metal oxide layer 12B functions as a hydrogen barrier layer, and hydrogen atoms contained in the intermediate layer 12C are annealed at the interface between the active layer 11 and the first metal oxide layer 12A. It becomes easy to move. This makes it possible to enhance the defect repair effect of the interface.
  • the film thickness of the intermediate layer 12C will be considered.
  • the film thicknesses of the first metal oxide layer 12A and the second metal oxide layer 12B are fixed to 50 nm and the film thickness of the intermediate layer 12C is 0 nm to 30 nm.
  • the interface state density Dit (eV -1 ⁇ cm -2 ) was measured.
  • the interface state density decreases even if the intermediate layer 12C is 3 nm.
  • the interface state density is further decreased, and it is confirmed that the interface state density becomes the minimum value at the film thickness of 10 nm in Example 3-3.
  • the intermediate layer 12C exceeds 10 nm, the interface state density does not decrease. Therefore, it is understood that the intermediate layer 12C has a function of supplying hydrogen atoms sufficiently with an extremely thin film thickness of 3 nm to 10 nm.
  • the structure of the gate insulating film of each thin film transistor is the structure of only the first metal oxide layer 12A (film thickness 100 nm), the first metal oxide layer 12A (film thickness 50 nm) and the second metal oxide layer 12B (film thickness A two-layer structure (thin film transistor 1) having a film thickness of 50 nm, and an intermediate layer 12C (a film thickness of 50 nm) between the first metal oxide layer 12A (film thickness 50 nm) and the second metal oxide layer 12B (film thickness 50 nm)
  • TFT characteristic value mobility (cm 2 / Vs) and subthreshold swing value (S value) (V / dec) were measured.
  • S value subthreshold swing value
  • Table 5 shows the mobility and the S value obtained by the above measurement.
  • the hydrogen in the film terminates defects not only at the interface but also in the film, eliminating unnecessary charges in the TEOS-SiO X film. It is also considered to generate more carriers at the same voltage as well.
  • the second metal oxide layer 12B functions as a hydrogen barrier layer, and the hydrogen atoms in the first metal oxide layer 12A become the active layer-gate. This is because the interface state density is lowered by effectively repairing the defect at the insulating film interface. In particular, when the gate insulating film has a three-layer structure, the interface state density is further reduced by the large amount of hydrogen atoms in the intermediate layer 12C because the intermediate layer 12C is provided, and the S value is particularly preferable There is.
  • FIG. 17 is a schematic cross-sectional view of a thin film transistor 3 according to a third embodiment of the present invention.
  • the configuration different from the first embodiment will be mainly described, and the same configuration as that of the above-described embodiment will be denoted by the same reference numeral, and the description thereof will be omitted or simplified.
  • the gate insulating film 32 further includes an intermediate layer 12D disposed between the first metal oxide layer 12A and the second metal oxide layer 12B. It differs from the embodiment.
  • the intermediate layer 12D is a hydrogen-rich layer containing a large amount of hydrogen atoms, and is formed by hydrogen plasma treatment of the first metal oxide layer 12A.
  • the middle layer 12D has the same effect as the middle layer 12C of the second embodiment.
  • the thickness of the intermediate layer 12D is not particularly limited, and is, for example, 3 nm or more and 10 nm or less.
  • the step of forming an intermediate layer is included after the step of forming the first metal oxide layer.
  • the process of forming the active layer, the process of forming the source and drain regions, the process of forming the gate electrode, the process of forming the interlayer insulating film, and the process of forming the source and drain electrodes are the same as in the first embodiment. , I omit the explanation here.
  • the intermediate layer 12D is formed by hydrogen plasma treatment of the surface of the first metal oxide layer 12A. After the formation of the intermediate layer 12D, annealing is performed at a predetermined temperature (for example, 500 ° C.). The annealing may be performed before or after the formation of the second metal oxide layer 12B. However, in order to efficiently supply the hydrogen atoms contained in the intermediate layer 12D to the interface between the active layer 11 and the first metal oxide layer 12A, annealing treatment is performed after the second metal oxide layer 12B is formed. It is desirable to After the annealing process, the intermediate layer 12D may disappear by being diffused to the first metal oxide layer 12A.
  • a predetermined temperature for example, 500 ° C.
  • the apparatus for performing hydrogen plasma processing is not particularly limited as long as it is a plasma apparatus capable of performing hydrogen plasma processing on the surface of the first metal oxide layer 12A.
  • the plasma apparatus may be configured to be capable of applying a bias potential to the electrode on the side of the target substrate at the time of hydrogen plasma processing.
  • the film formation conditions are not particularly limited, and for example, when the glass substrate size is 730 mm ⁇ 920 mm, the following conditions are implemented.
  • H 2 flow rate 1000 [sccm]
  • Process pressure 200 [Pa]
  • RF frequency 27.12 [MHz]
  • RF power 500 [W]
  • Heater temperature 350 [° C]
  • the plasma CVD apparatus and the ALD apparatus used in the above embodiments are not limited to the above-described apparatuses, and other apparatuses may be used.
  • the step of forming the first metal oxide layer and the step of forming the second metal oxide layer may be performed by a single wafer type multi-chamber system or an in-line system.
  • a plasma CVD chamber is formed after the formation of the first metal oxide layer in the first chamber (plasma CVD chamber for forming the first metal oxide layer)
  • the substrate to be processed is taken out from the chamber and transferred to the next second chamber (ALD chamber for forming a second metal oxide layer) to perform substrate processing one by one.
  • the first processing chamber first metal partitioned in the transport direction while transporting the substrate to be processed by transport means such as a walking beam or various conveyors.
  • Substrate processing is performed in the following second processing chamber (having an ALD apparatus for forming a second metal oxide layer) and the next second processing chamber (having a plasma CVD apparatus for forming an oxide layer).
  • the step of forming the first metal oxide layer and the step of forming the second metal oxide layer may be performed continuously in a vacuum atmosphere.
  • the substrate processing process vacuum consistent, it is possible to prevent the contamination of the substrate surface by gas or air.
  • the present invention has been described by taking a thin film transistor of top gate type (stagger type) structure as an example, but the gate electrode is disposed on the substrate and activated with the gate insulating film interposed on the gate electrode.
  • the present invention is applicable even to a thin film transistor having a bottom gate (inverted staggered) structure in which layers are disposed.
  • the thin film transistor described above can be used as a TFT for an active matrix display panel such as a liquid crystal display or an organic EL display.
  • the transistor can be used as a transistor element of various semiconductor devices or electronic devices.

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02228042A (ja) * 1989-02-28 1990-09-11 Seiko Epson Corp 薄膜半導体装置の製造方法
JPH05251701A (ja) * 1992-03-04 1993-09-28 Fujitsu Ltd 薄膜トランジスタの形成方法
JP2001284600A (ja) * 2000-04-04 2001-10-12 Matsushita Electric Ind Co Ltd 薄膜トランジスタ及びその製造方法
WO2007086163A1 (ja) * 2006-01-25 2007-08-02 Sharp Kabushiki Kaisha 半導体装置の製造方法、及び、半導体装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW502450B (en) * 2001-08-10 2002-09-11 Ind Tech Res Inst Method for fabricating a low temperature polysilicon thin film transistor incorporating channel passivation step
TW200537573A (en) * 2004-04-23 2005-11-16 Ulvac Inc Thin-film transistor and production method thereof
CN101501820B (zh) * 2006-08-10 2012-11-28 株式会社爱发科 导电膜形成方法、薄膜晶体管、带薄膜晶体管的面板、及薄膜晶体管的制造方法
JP2010098149A (ja) 2008-10-17 2010-04-30 Hitachi Displays Ltd 表示装置およびその製造方法
JP4752925B2 (ja) * 2009-02-04 2011-08-17 ソニー株式会社 薄膜トランジスタおよび表示装置
JP5506036B2 (ja) * 2010-03-02 2014-05-28 古河電気工業株式会社 半導体トランジスタ
JP5668917B2 (ja) * 2010-11-05 2015-02-12 ソニー株式会社 薄膜トランジスタおよびその製造方法
US9653614B2 (en) * 2012-01-23 2017-05-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN102956713B (zh) * 2012-10-19 2016-03-09 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示装置
CN104716193A (zh) * 2013-12-11 2015-06-17 昆山工研院新型平板显示技术中心有限公司 一种薄膜晶体管及其制备方法和应用
TWI548100B (zh) * 2015-01-08 2016-09-01 友達光電股份有限公司 薄膜電晶體、顯示面板以及其製造方法
TWI611463B (zh) * 2016-06-29 2018-01-11 友達光電股份有限公司 金屬氧化物半導體層的結晶方法及半導體結構

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02228042A (ja) * 1989-02-28 1990-09-11 Seiko Epson Corp 薄膜半導体装置の製造方法
JPH05251701A (ja) * 1992-03-04 1993-09-28 Fujitsu Ltd 薄膜トランジスタの形成方法
JP2001284600A (ja) * 2000-04-04 2001-10-12 Matsushita Electric Ind Co Ltd 薄膜トランジスタ及びその製造方法
WO2007086163A1 (ja) * 2006-01-25 2007-08-02 Sharp Kabushiki Kaisha 半導体装置の製造方法、及び、半導体装置

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