WO2019051978A1 - 一种tft器件及液晶显示面板的静电保护电路 - Google Patents

一种tft器件及液晶显示面板的静电保护电路 Download PDF

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Publication number
WO2019051978A1
WO2019051978A1 PCT/CN2017/110312 CN2017110312W WO2019051978A1 WO 2019051978 A1 WO2019051978 A1 WO 2019051978A1 CN 2017110312 W CN2017110312 W CN 2017110312W WO 2019051978 A1 WO2019051978 A1 WO 2019051978A1
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Prior art keywords
metal
igzo layer
diffractive
prepared
igzo
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PCT/CN2017/110312
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English (en)
French (fr)
Inventor
赵阳
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深圳市华星光电半导体显示技术有限公司
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Priority to EP17925505.4A priority Critical patent/EP3683828A4/en
Priority to KR1020207010939A priority patent/KR102323902B1/ko
Priority to US15/576,858 priority patent/US10158025B1/en
Priority to JP2020509522A priority patent/JP7012826B2/ja
Publication of WO2019051978A1 publication Critical patent/WO2019051978A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/22—Antistatic materials or arrangements

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT device and an electrostatic protection circuit for a liquid crystal display panel.
  • TFT Thin Film Transistor, thin film transistor
  • ESD Electro-Static Discharge, electrostatic discharge circuit / electrostatic protection circuit
  • the drain generates a large voltage; therefore, before the current enters the pixel array, a protection circuit generated by a plurality of TFTs in series and parallel is designed to directly flow into the ESD when an instantaneous large current is generated to protect the pixel array.
  • IGZO indium gallium zinc Oxide, indium gallium zinc oxide (TFT), which means that a layer of metal oxide (IGZO) is applied to the active layer of the TFT device, so that the channel carrier mobility of the TFT device is greatly improved, thereby improving the response speed of the pixel. .
  • IGZO 4 MASK IGZO TFT
  • the source and drain electrodes are the same mask as the IGZO layer, and after three wet etchings, the wet etching of the IGZO layer causes the IGZO layer to be over-etched. Affect the performance of TFT devices.
  • the prior art IGZO layer may cause over-etching after repeated etching, which may affect the performance of the TFT device, thereby affecting the pixel reaction speed of the liquid crystal display panel.
  • the invention provides a TFT device capable of reducing the degree of over-etching of the IGZO layer after multiple etchings in the etching process of the IGZO layer, thereby protecting the integrity of the IGZO layer, and solving the existing IGZO The technical problem of over-etching caused by the IGZO layer after multiple etching in the TFT preparation process.
  • the invention provides a TFT device comprising:
  • a gate insulating layer is prepared on the surface of the glass substrate and covers the gate metal;
  • An IGZO layer is prepared on the surface of the gate insulating layer
  • a source metal and a drain metal are formed on a surface of the IGZO layer, and a channel region is formed between the source metal and the drain metal;
  • a diffractive metal prepared on the surface of the IGZO layer and located in the channel region;
  • the diffractive metal is located at an intermediate position of the channel region.
  • the diffractive metal covers at least a portion of the surface of the IGZO layer.
  • the IGZO layer is rectangular, the IGZO layer includes a first dimension parallel to a short side of the IGZO layer, and a second dimension parallel to a long side of the IGZO layer.
  • the diffractive metal covers the IGZO layer in a first dimension of the IGZO layer.
  • the diffractive metal is a rectangle, and the diffractive metal includes a long side and a short side, and a long side of the diffractive metal is parallel to a first dimension of the IGZO layer.
  • At least one of the diffractive metals is prepared on the surface of the IGZO layer.
  • the surface of the IGZO layer is prepared with a first diffractive metal and a second diffractive metal disposed at intervals, the first diffractive metal is disposed adjacent to the source metal, and the second diffractive metal is adjacent to the The drain metal arrangement, wherein a length of the first diffractive metal and the source metal is equal to a length of the second diffractive metal and the drain metal.
  • the length of the diffractive metal is 7 um to 9 um, and the width of the diffractive metal is 4 um to 6 um.
  • the invention also provides a TFT device comprising:
  • a gate insulating layer is prepared on the surface of the glass substrate and covers the gate metal;
  • An IGZO layer is prepared on the surface of the gate insulating layer
  • a source metal and a drain metal are formed on a surface of the IGZO layer, and a channel region is formed between the source metal and the drain metal;
  • a diffractive metal is prepared on the surface of the IGZO layer and located in the channel region.
  • the diffractive metal covers at least a portion of the surface of the IGZO layer.
  • the IGZO layer is rectangular, the IGZO layer includes a first dimension parallel to a short side of the IGZO layer, and a second dimension parallel to a long side of the IGZO layer.
  • the diffractive metal covers the IGZO layer in a first dimension of the IGZO layer.
  • the diffractive metal is a rectangle, and the diffractive metal includes a long side and a short side, and a long side of the diffractive metal is parallel to a first dimension of the IGZO layer.
  • At least one of the diffractive metals is prepared on the surface of the IGZO layer.
  • the surface of the IGZO layer is prepared with a first diffractive metal and a second diffractive metal disposed at intervals, the first diffractive metal is disposed adjacent to the source metal, and the second diffractive metal is adjacent to the The drain metal arrangement, wherein a length of the first diffractive metal and the source metal is equal to a length of the second diffractive metal and the drain metal.
  • the length of the diffractive metal is 7 um to 9 um, and the width of the diffractive metal is 4 um to 6 um.
  • an electrostatic protection circuit for a liquid crystal display panel is provided, the electrostatic protection circuit is disposed at an input end of a pixel driving circuit of the liquid crystal display panel, the electrostatic protection circuit includes a metal trace, and at least Two TFT devices connected in series or in parallel; wherein
  • the TFT device includes:
  • a gate insulating layer is prepared on the surface of the glass substrate and covers the gate metal;
  • An IGZO layer is prepared on the surface of the gate insulating layer
  • a source metal and a drain metal are formed on a surface of the IGZO layer, and a channel region is formed between the source metal and the drain metal;
  • a diffractive metal is prepared on the surface of the IGZO layer and located in the channel region.
  • the diffractive metal covers at least a portion of the surface of the IGZO layer.
  • the beneficial effects of the present invention are: IGZO provided by the present invention compared to the prior art IGZO TFT device TFT device, providing a protective layer on the surface of the IGZO layer to avoid over-etching of IGZO by multiple etching processes; solving the prior art IGZO In the preparation process of the TFT, the IGZO layer may cause over-etching after repeated etching, which may affect the performance of the TFT device, thereby affecting the technical problem of the pixel reaction speed of the liquid crystal display panel.
  • FIG. 1 is a schematic structural view of a TFT device film layer provided by the present invention.
  • FIG. 2 is a schematic top plan view of a TFT device provided by the present invention.
  • the present invention is directed to the prior art IGZO
  • the IGZO layer may cause over-etching after being etched many times, which may affect the performance of the TFT device, thereby affecting the pixel reaction speed of the liquid crystal display panel. This embodiment can solve the defect.
  • the TFT device comprises: a glass substrate 101; a gate metal 102 prepared on the surface of the glass substrate 101; and a gate insulating layer 103 prepared on the surface of the glass substrate 101, and covered by a gate metal 102; an IGZO layer 104 is formed on the surface of the gate insulating layer 103; a source metal 105 and a drain metal 106 are prepared on the surface of the IGZO layer 104, the source metal 105 and the drain A channel region is formed between the metals 106; and a diffractive metal 107 is formed on the surface of the IGZO layer 104 and located in the channel region.
  • the source metal 105 and the drain metal 106 are electrically connected to the IGZO layer 104.
  • the IGZO layer 104 is used to realize electron transfer between the source metal 105 and the drain metal 106.
  • the length of the IGZO layer 104 is The width affects the electron migration rate; when the IGZO layer 104 is over-etched, the surface of the IGZO layer 104 is damaged, the IGZO layer 104 is etched from the regular pattern into a profile, and the width of the partial region of the IGZO layer 104 is reduced.
  • the migration path changes, which in turn leads to a decrease in the rate of electron migration.
  • the surface of the IGZO layer 104 is coated with a photoresist layer after passing through a mask process. After developing on the surface of the photoresist layer, the photoresist layer on the surface of the IGZO layer 104 is wet-etched three times; due to material limitation, the IGZO layer 104 is more susceptible to wet etching than the metal layer, and therefore, exposure is performed using a photomask.
  • the IGZO layer 104 is exposed to an excessive depth, which is caused by the subsequent wet etching. The shape of the IGZO layer 104 is damaged.
  • the diffractive metal 107 is prepared by using the same photomask as the source metal 105 and the drain metal 106, and is required to be added on the surface of the photomask to form the diffractive metal 107.
  • a light-shielding pattern when exposed using the photomask, a surface of the exposed region corresponding to the IGZO layer 104 has a diffractive metal 107 capable of diffracting the reference light upon exposure, thereby changing the original illumination
  • the direction of the photoresist of the IGZO surface is turned around to reduce the amount of light of the photoresist irradiated on the surface of the IGZO.
  • the diffractive metal 107 is not connected to any potential and is only used to diffract light in the exposure process.
  • the diffractive metal 107 covers at least a portion of the surface of the IGZO layer 104.
  • the diffractive metal 107 covers 1/5 of the area of the IGZO layer 104, and the diffractive metal is avoided under the demand of diffracted illumination.
  • the coverage area of 107 is too large to affect the film thickness of the IGZO layer 104.
  • the TFT device comprises a glass substrate, a gate metal 201 prepared on the surface of the glass substrate, a gate insulating layer prepared on the surface of the gate metal 201 and the glass substrate, and preparation.
  • the IGZO layer 202 is rectangular, and the IGZO layer 202 includes a first dimension parallel to a short side of the IGZO layer 202 and a second dimension parallel to a long side of the IGZO layer 202, the diffraction metal being
  • the IGZO layer 202 covers the IGZO layer 202 in a first dimension; the source metal 203 is adjacent to one end of the IGZO layer 202, and the drain metal 204 is adjacent to the opposite end of the IGZO layer 202.
  • the diffractive metal is disposed at an intermediate position of the channel region such that the illumination diffraction distribution is uniform, and if the diffractive metal is offset to either side of the channel region, away from the channel region of the diffractive metal The amount of exposure will increase, eventually resulting in a non-uniform thickness of the surface layer of the IGZO layer 202.
  • the surface of the IGZO layer 202 is prepared with at least one of the diffractive metals; for example, the surface of the IGZO layer 202 is prepared with two of the diffractive metals; and a first diffraction interval is prepared on the surface of the IGZO layer 202.
  • a metal 2051 and a second diffractive metal 2052 disposed adjacent to the source metal 203, the second diffractive metal 2052 being disposed adjacent to the drain metal 204, wherein the first diffractive metal 2051
  • the length of the interval from the source metal 203 is equal to the length of the interval between the second diffractive metal 2052 and the drain metal 204.
  • the first diffractive metal 2051 and the second diffractive metal 2052 which are spaced apart from each other can repeatedly diffract light, thereby further reducing the light intensity and protecting the IGZO layer 202.
  • an electrostatic protection circuit for a liquid crystal display panel is provided, the electrostatic protection circuit is disposed at an input end of a pixel driving circuit of the liquid crystal display panel, the electrostatic protection circuit includes a metal trace, and at least Two TFT devices connected in series or in parallel; wherein the TFT device comprises: a glass substrate; a gate metal is prepared on the surface of the glass substrate; a gate insulating layer is prepared on the surface of the glass substrate and covers the gate a metal; an IGZO layer prepared on a surface of the gate insulating layer; a source metal and a drain metal formed on a surface of the IGZO layer, wherein a channel region is formed between the source metal and the drain metal; A diffractive metal is prepared on the surface of the IGZO layer and located in the channel region.
  • the working principle of the electrostatic protection circuit of the preferred embodiment is the same as that of the TFT device of the preferred embodiment.
  • the beneficial effects of the present invention are: IGZO provided by the present invention compared to the prior art IGZO TFT device
  • a protective layer is disposed on the surface of the IGZO layer 202 to avoid over-etching of the IGZO by multiple etching processes; and the prior art IGZO is solved.
  • the IGZO layer 202 may cause over-etching after repeated etching, which may affect the performance of the TFT device, thereby affecting the technical problem of the pixel reaction speed of the liquid crystal display panel.

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Abstract

一种TFT器件，包括：玻璃基板(101)；栅极金属(102,201)，制备于玻璃基板(101)表面；栅绝缘层(103)，制备于玻璃基板(101)表面，且覆盖栅极金属(102,201)；IGZO层(104,202)，制备于栅绝缘层(103)表面；源极金属(105,203)、漏极金属(106,204)，制备于IGZO层(104,202)表面，源极金属(105,203)与漏极金属(106,204)之间形成有沟道区域；以及，衍射金属(107)，制备于IGZO层(104,202)表面，且位于沟道区域内。

Description

一种TFT器件及液晶显示面板的静电保护电路 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT器件及液晶显示面板的静电保护电路。
 背景技术
在TFT（Thin Film Transistor，薄膜晶体管）液晶显示面板中，存在较多静电破坏，而ESD（Electro-Static discharge，静电释放电路/静电保护电路），能够让瞬时放电的电流，不会流入液晶显示面板的像素阵列而破坏像素内的TFT器件，即使流入像素阵列，也能避免TFT器件的栅极或源漏极产生很大的电压；因此，在电流进入像素阵列前，会设计由多个TFT串并联产生的防护电路，当有瞬时大电流产生时，会直接流入ESD，以保护像素阵列。
IGZO（indium gallium zinc oxide，铟镓锌氧化物）TFT，是指在TFT器件的主动层上，打上一层金属氧化物（IGZO），使得TFT器件的沟道载流子迁移率大幅提高，进而提高像素的响应速度。
在IGZO 4 MASK（IGZO TFT 4道光罩工序制程）中，由于TFT的沟道较大，源、漏极金属与IGZO层为同一道光罩，并经过3次湿刻，多次湿刻会导致IGZO层被过刻蚀，从而影响TFT器件的性能。
综上所述，现有技术的IGZO TFT的制备工艺中，IGZO层经多次刻蚀后会导致过刻蚀，会影响TFT器件的性能，进而影响液晶显示面板的像素反应速度。
 技术问题
本发明提供一种TFT器件，能够在IGZO层的刻蚀制程中，减少IGZO层经多次刻蚀后的过刻蚀程度，进而保护IGZO层的完整度；以解决现有的IGZO TFT制备工艺中，IGZO层经多次刻蚀后导致的过刻蚀的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种TFT器件，包括：
玻璃基板；
栅极金属，制备于所述玻璃基板表面；
栅绝缘层，制备于所述玻璃基板表面，且覆盖所述栅极金属；
IGZO层，制备于所述栅绝缘层表面；
源极金属、漏极金属，制备于所述IGZO层表面，所述源极金属与所述漏极金属之间形成有沟道区域；以及，
衍射金属，制备于所述IGZO层表面，且位于所述沟道区域内；
所述衍射金属位于所述沟道区域的中间位置。
根据本发明一优选实施例，所述衍射金属覆盖所述IGZO层表面的至少一部分。
根据本发明一优选实施例，所述IGZO层为长方形，所述IGZO层包括平行于所述IGZO层的短边的第一维度，以及平行于所述IGZO层的长边的第二维度，所述衍射金属在所述IGZO层的第一维度上覆盖所述IGZO层。
根据本发明一优选实施例，所述衍射金属为长方形，所述衍射金属包括长边以及短边，所述衍射金属的长边平行于所述IGZO层的第一维度。
根据本发明一优选实施例，所述IGZO层表面制备有至少一个所述衍射金属。
根据本发明一优选实施例，所述IGZO层表面制备有间隔设置的第一衍射金属与第二衍射金属，所述第一衍射金属靠近所述源极金属设置，所述第二衍射金属靠近所述漏极金属设置，其中，所述第一衍射金属与所述源极金属的间隔长度，等于所述第二衍射金属与所述漏极金属的间隔长度。
根据本发明一优选实施例，所述衍射金属的长度为7um～9um，所述衍射金属的宽度为4um～6um。
本发明还提供一种TFT器件，包括：
玻璃基板；
栅极金属，制备于所述玻璃基板表面；
栅绝缘层，制备于所述玻璃基板表面，且覆盖所述栅极金属；
IGZO层，制备于所述栅绝缘层表面；
源极金属、漏极金属，制备于所述IGZO层表面，所述源极金属与所述漏极金属之间形成有沟道区域；以及，
衍射金属，制备于所述IGZO层表面，且位于所述沟道区域内。
根据本发明一优选实施例，所述衍射金属覆盖所述IGZO层表面的至少一部分。
根据本发明一优选实施例，所述IGZO层为长方形，所述IGZO层包括平行于所述IGZO层的短边的第一维度，以及平行于所述IGZO层的长边的第二维度，所述衍射金属在所述IGZO层的第一维度上覆盖所述IGZO层。
根据本发明一优选实施例，所述衍射金属为长方形，所述衍射金属包括长边以及短边，所述衍射金属的长边平行于所述IGZO层的第一维度。
根据本发明一优选实施例，所述IGZO层表面制备有至少一个所述衍射金属。
根据本发明一优选实施例，所述IGZO层表面制备有间隔设置的第一衍射金属与第二衍射金属，所述第一衍射金属靠近所述源极金属设置，所述第二衍射金属靠近所述漏极金属设置，其中，所述第一衍射金属与所述源极金属的间隔长度，等于所述第二衍射金属与所述漏极金属的间隔长度。
根据本发明一优选实施例，所述衍射金属的长度为7um～9um，所述衍射金属的宽度为4um～6um。
根据本发明的上述目的，提供一种液晶显示面板的静电保护电路，所述静电保护电路设置于所述液晶显示面板的像素驱动电路的输入端，所述静电保护电路包括金属走线、以及至少两个串联或者并联的TFT器件；其中，
所述TFT器件包括：
玻璃基板；
栅极金属，制备于所述玻璃基板表面；
栅绝缘层，制备于所述玻璃基板表面，且覆盖所述栅极金属；
IGZO层，制备于所述栅绝缘层表面；
源极金属、漏极金属，制备于所述IGZO层表面，所述源极金属与所述漏极金属之间形成有沟道区域；以及，
衍射金属，制备于所述IGZO层表面，且位于所述沟道区域内。
根据本发明一优选实施例，所述衍射金属覆盖所述IGZO层表面的至少一部分。
 有益效果
本发明的有益效果为：相较于现有技术的IGZO TFT器件，本发明提供的IGZO TFT器件，在IGZO层表面设置保护层，避免多次刻蚀工序对IGZO造成过刻蚀；解决了现有技术的IGZO TFT的制备工艺中，IGZO层经多次刻蚀后会导致过刻蚀，会影响TFT器件的性能，进而影响液晶显示面板的像素反应速度的技术问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明提供的TFT器件膜层结构示意图；
图2为本发明提供的TFT器件俯视结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有技术的IGZO TFT的制备工艺中，IGZO层经多次刻蚀后会导致过刻蚀，会影响TFT器件的性能，进而影响液晶显示面板的像素反应速度，本实施例能够解决该缺陷。
如图1所示，本发明提供的TFT器件；包括：玻璃基板101；栅极金属102，制备于所述玻璃基板101表面；栅绝缘层103，制备于所述玻璃基板101表面，且覆盖所述栅极金属102；IGZO层104，制备于所述栅绝缘层103表面；源极金属105、漏极金属106，制备于所述IGZO层104表面，所述源极金属105与所述漏极金属106之间形成有沟道区域；以及，衍射金属107，制备于所述IGZO层104表面，且位于所述沟道区域内。
所述源极金属105与漏极金属106电性连接所述IGZO层104，所述IGZO层104用以实现源极金属105与漏极金属106间的电子迁移；所述IGZO层104的长度与宽度影响着电子迁移速率；当所述IGZO层104被过刻蚀后，所述IGZO层104表面会出现破损，IGZO层104从规则图形蚀刻为异形，IGZO层104部分区域的宽度减小，电子迁移路径发生变化，进而导致电子迁移速率降低。
IGZO TFT制备工艺中，在形成所述源极金属105、所述漏极金属106以及所述IGZO层104的图案的工序时，IGZO层104表面涂布有光刻胶层，经过一道光罩工序后，在光刻胶层表面显影，之后对IGZO层104表面的光刻胶层进行3次湿刻；受材料限制，IGZO层104相对金属层更易受湿刻影响，因此，在使用光罩进行曝光时，光照量小，会导致所述源极金属105、漏极金属106的曝光深度不足，光照量大时，则会导致IGZO层104曝光过深，在后续湿刻的过程中，导致所述IGZO层104形状受损。
在制备所述衍射金属107时，所述衍射金属107与所述源极金属105以及所述漏极金属106采用同一道光罩制备，需要在所述光罩表面增加用以形成所述衍射金属107的遮光图案；在使用所述光罩进行曝光时，对应所述IGZO层104的曝光区域表面具有衍射金属107，所述衍射金属107能够在曝光时，实现对照光的衍射，从而改变原本照射在所述IGZO表面的光刻胶的方向转向周围，以减弱照射在所述IGZO表面的光刻胶的光量。
所述衍射金属107不接任何电位，仅用以实现曝光制程中对光照进行衍射。
所述衍射金属107覆盖所述IGZO层104表面的至少一部分，例如，所述衍射金属107覆盖所述IGZO层104的面积的1/5，在起到衍射光照的需求下，避免所述衍射金属107覆盖面积过大而影响所述IGZO层104的膜层厚度。
如图2所示，本发明提供的TFT器件，包括玻璃基板、制备于所述玻璃基板表面的栅极金属201、制备于所述栅极金属201以及所述玻璃基板表面的栅绝缘层、制备于所述栅绝缘层表面的IGZO层202、制备于所述IGZO层202表面的源极金属203和漏极金属204、形成于所述源极金属203和所述漏极金属204之间的沟道区域、以及制备于所述IGZO层202表面且位于所述沟道区域内的衍射金属205。
所述IGZO层202为长方形，所述IGZO层202包括平行于所述IGZO层202的短边的第一维度，以及平行于所述IGZO层202的长边的第二维度，所述衍射金属在所述IGZO层202的第一维度上覆盖所述IGZO层202；所述源极金属203靠近所述IGZO层202的一端，所述漏极金属204靠近所述IGZO层202的相对另一端。
所述衍射金属设置于所述沟道区域的中间位置，使得光照衍射分布均匀，如果所述衍射金属向所述沟道区域的任意一侧偏移，则远离所述衍射金属的沟道区域的曝光量将增强，最终导致所述IGZO层202表面膜层厚度不均匀。
例如，所述IGZO层202表面制备有至少一个所述衍射金属；又如，所述IGZO层202表面制备有两个所述衍射金属；在所述IGZO层202表面制备有间隔设置的第一衍射金属2051与第二衍射金属2052，所述第一衍射金属2051靠近所述源极金属203设置，所述第二衍射金属2052靠近所述漏极金属204设置，其中，所述第一衍射金属2051与所述源极金属203的间隔长度，等于所述第二衍射金属2052与所述漏极金属204的间隔长度。
间隔设置的所述第一衍射金属2051与所述第二衍射金属2052，相互之间能够对光照进行重复衍射，从而进一步削减光照强度，保护IGZO层202。
根据本发明的上述目的，提供一种液晶显示面板的静电保护电路，所述静电保护电路设置于所述液晶显示面板的像素驱动电路的输入端，所述静电保护电路包括金属走线、以及至少两个串联或者并联的TFT器件；其中，所述TFT器件包括：玻璃基板；栅极金属，制备于所述玻璃基板表面；栅绝缘层，制备于所述玻璃基板表面，且覆盖所述栅极金属；IGZO层，制备于所述栅绝缘层表面；源极金属、漏极金属，制备于所述IGZO层表面，所述源极金属与所述漏极金属之间形成有沟道区域；以及，衍射金属，制备于所述IGZO层表面，且位于所述沟道区域内。
本优选实施例的静电保护电路的工作原理跟上述优选实施例的TFT器件的工作原理一致，具体可参考上述优选实施例的TFT器件的工作原理，此处不再做赘述。
本发明的有益效果为：相较于现有技术的IGZO TFT器件，本发明提供的IGZO TFT器件，在IGZO层202表面设置保护层，避免多次刻蚀工序对IGZO造成过刻蚀；解决了现有技术的IGZO TFT的制备工艺中，IGZO层202经多次刻蚀后会导致过刻蚀，会影响TFT器件的性能，进而影响液晶显示面板的像素反应速度的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种TFT器件，其包括：
    玻璃基板；
    栅极金属，制备于所述玻璃基板表面；
    栅绝缘层，制备于所述玻璃基板表面，且覆盖所述栅极金属；
    IGZO层，制备于所述栅绝缘层表面；
    源极金属、漏极金属，制备于所述IGZO层表面，所述源极金属与所述漏极金属之间形成有沟道区域；以及，
    衍射金属，制备于所述IGZO层表面，且位于所述沟道区域内；
    所述衍射金属位于所述沟道区域的中间位置。
  2. 根据权利要求1所述的TFT器件，其中，所述衍射金属覆盖所述IGZO层表面的至少一部分。
  3. 根据权利要求2所述的TFT器件，其中，所述IGZO层为长方形，所述IGZO层包括平行于所述IGZO层的短边的第一维度，以及平行于所述IGZO层的长边的第二维度，所述衍射金属在所述IGZO层的第一维度上覆盖所述IGZO层。
  4. 根据权利要求3所述的TFT器件，其中，所述衍射金属为长方形，所述衍射金属包括长边以及短边，所述衍射金属的长边平行于所述IGZO层的第一维度。
  5. 根据权利要求1所述的TFT器件，其中，所述IGZO层表面制备有至少一个所述衍射金属。
  6. 根据权利要求5所述的TFT器件，其中，所述IGZO层表面制备有间隔设置的第一衍射金属与第二衍射金属，所述第一衍射金属靠近所述源极金属设置，所述第二衍射金属靠近所述漏极金属设置，其中，所述第一衍射金属与所述源极金属的间隔长度，等于所述第二衍射金属与所述漏极金属的间隔长度。
  7. 根据权利要求1所述的TFT器件，其中，所述衍射金属的长度为7um～9um，所述衍射金属的宽度为4um～6um。
  8. 一种TFT器件，其包括：
    玻璃基板；
    栅极金属，制备于所述玻璃基板表面；
    栅绝缘层，制备于所述玻璃基板表面，且覆盖所述栅极金属；
    IGZO层，制备于所述栅绝缘层表面；
    源极金属、漏极金属，制备于所述IGZO层表面，所述源极金属与所述漏极金属之间形成有沟道区域；以及，
    衍射金属，制备于所述IGZO层表面，且位于所述沟道区域内。
  9. 根据权利要求8所述的TFT器件，其中，所述衍射金属覆盖所述IGZO层表面的至少一部分。
  10. 根据权利要求9所述的TFT器件，其中，所述IGZO层为长方形，所述IGZO层包括平行于所述IGZO层的短边的第一维度，以及平行于所述IGZO层的长边的第二维度，所述衍射金属在所述IGZO层的第一维度上覆盖所述IGZO层。
  11. 根据权利要求10所述的TFT器件，其中，所述衍射金属为长方形，所述衍射金属包括长边以及短边，所述衍射金属的长边平行于所述IGZO层的第一维度。
  12. 根据权利要求8所述的TFT器件，其中，所述IGZO层表面制备有至少一个所述衍射金属。
  13. 根据权利要求12所述的TFT器件，其中，所述IGZO层表面制备有间隔设置的第一衍射金属与第二衍射金属，所述第一衍射金属靠近所述源极金属设置，所述第二衍射金属靠近所述漏极金属设置，其中，所述第一衍射金属与所述源极金属的间隔长度，等于所述第二衍射金属与所述漏极金属的间隔长度。
  14. 根据权利要求8所述的TFT器件，其中，所述衍射金属的长度为7um～9um，所述衍射金属的宽度为4um～6um。
  15. 一种液晶显示面板的静电保护电路，设置于所述液晶显示面板的像素驱动电路的输入端，其特征在于，所述静电保护电路包括金属走线、以及至少两个串联或者并联的TFT器件；其中，
    所述TFT器件包括：
    玻璃基板；
    栅极金属，制备于所述玻璃基板表面；
    栅绝缘层，制备于所述玻璃基板表面，且覆盖所述栅极金属；
    IGZO层，制备于所述栅绝缘层表面；
    源极金属、漏极金属，制备于所述IGZO层表面，所述源极金属与所述漏极金属之间形成有沟道区域；以及，
    衍射金属，制备于所述IGZO层表面，且位于所述沟道区域内。
  16. 根据权利要求15所述的静电保护电路，其中，所述衍射金属覆盖所述IGZO层表面的至少一部分。
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