WO2019015270A1 - 显示基板及其制备方法和显示装置 - Google Patents

显示基板及其制备方法和显示装置 Download PDF

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Publication number
WO2019015270A1
WO2019015270A1 PCT/CN2018/072071 CN2018072071W WO2019015270A1 WO 2019015270 A1 WO2019015270 A1 WO 2019015270A1 CN 2018072071 W CN2018072071 W CN 2018072071W WO 2019015270 A1 WO2019015270 A1 WO 2019015270A1
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Prior art keywords
layer
metal
display
conductive material
pad
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Ceased
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PCT/CN2018/072071
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English (en)
French (fr)
Chinese (zh)
Inventor
黄炜赟
青海刚
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US16/092,721 priority Critical patent/US10756034B2/en
Priority to JP2018552877A priority patent/JP7113757B2/ja
Priority to EP18780011.5A priority patent/EP3457438A4/en
Publication of WO2019015270A1 publication Critical patent/WO2019015270A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/173—Passive-matrix OLED displays comprising banks or shadow masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01908—Manufacture or treatment of bond pads using permanent auxiliary members, e.g. using alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01951—Changing the shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/325—Die-attach connectors having a filler embedded in a matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/953—Materials of bond pads not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present disclosure relates to the field of organic light emitting display technology, and more particularly to a display substrate, a method of fabricating the same, and a display device.
  • the pad for the display device includes a metal sub-layer having a weaker corrosion resistance which is exposed at the edge of the pad and may cause damage to the exposed metal sub-layer when performing an electrode etching process on the electrode in the display region , thereby damaging the pads and the display device.
  • the edges of the pads are usually covered with a pixel defining layer material such as polyimide or acrylic.
  • a pixel defining layer material such as polyimide or acrylic.
  • the pixel defining layer is generally thick, in order not to affect the soldering quality, it is necessary to thin the pixel defining layer covering the pad region. Such thinning requires a halftone mask, and then a layer of a conductive material is deposited and an etching of the layer of the conductive material is performed, so that the cost increases and the process becomes complicated.
  • a display substrate including:
  • the pad region includes at least one pad, the pad comprising:
  • a metal layer comprising a first metal sub-layer and a second metal sub-layer laminated on the first metal sub-layer, wherein the second metal sub-layer is more resistant to corrosion than the first metal Sub-layer corrosion resistance;
  • the display area includes a display electrode, wherein the conductive material layer of the pad is disposed in the same layer as the display electrode of the display area.
  • the display electrode includes an anode, wherein the conductive material layer of the pad is disposed in the same layer as the anode.
  • the display region includes a transistor including a source and a drain, wherein the metal layer of the pad is the same as the source and drain of the display region Layer settings.
  • the first metal sublayer comprises aluminum and the second metal sublayer comprises titanium.
  • the metal layer further includes a third metal sublayer, wherein the first metal sublayer is laminated on the third metal sublayer, and the third metal sublayer is resistant to corrosion It is stronger than the corrosion resistance of the first metal sublayer.
  • the first metal sublayer comprises aluminum, and the second metal sublayer and the third metal sublayer each comprise titanium.
  • the conductive material layer is a multilayer structure including a first transparent conductive oxide layer, a metal material layer, and a second transparent conductive oxide layer.
  • the first or second transparent conductive oxide layer comprises any one of the group consisting of indium oxide, tin oxide, indium tin oxide, and any two or A mixture of more species.
  • the metal material layer contains silver.
  • the first or second transparent conductive oxide layer comprises indium tin oxide
  • the metal material layer comprises silver
  • the pad further includes an anisotropic conductive paste including a gold ball, wherein the second metal sublayer is in contact with the anisotropic conductive paste containing a gold ball.
  • a display device comprising the display substrate of any of the above.
  • a method for preparing a display substrate including a display area and a pad area outside the display area comprising the steps of:
  • the metal layer comprising a first metal sub-layer and a second metal sub-layer laminated on the first metal sub-layer, wherein the second metal sub-layer is more resistant to corrosion than Corrosion resistance of the first metal sublayer;
  • a layer of conductive material is formed, the layer of conductive material covering a side surface of the metal layer.
  • forming the conductive material layer includes:
  • the remaining photoresist is removed.
  • the method further includes the step of, after the developing, further retaining a photoresist covering a portion of the pre-formed conductive material layer in the display region, thereby removing remaining light After engraving, a portion of the layer of pre-formed conductive material in the display region forms a display electrode.
  • the display electrode includes an anode, and the conductive material layer of the pad region is formed simultaneously with the anode of the display region.
  • the display region further includes a source and a drain, and the metal layer of the pad region and the source and drain of the display region are simultaneously formed.
  • the method further includes forming an anisotropic conductive paste comprising a gold ball on the second metal sub-layer after etching the exposed portion of the pre-formed conductive material layer.
  • FIG. 1 is a cross-sectional view schematically showing an etched metal layer of a pad of a display substrate without protection.
  • FIG. 2 is a cross-sectional view schematically showing a display substrate when a periphery of a pad is covered with a pixel defining layer material such as polyimide or acryl.
  • FIG. 3A to 3E are cross-sectional views schematically showing a display substrate after respective process steps of a method for preparing a display substrate according to an embodiment of the present disclosure, wherein FIG. 3A is a cross-sectional view after the step of applying a photoresist; 3B is a cross-sectional view showing a step of masking a photoresist using a mask; FIG. 3C is a cross-sectional view showing a step of exposing a portion of the pre-formed conductive material layer after exposure and development; FIG. 3D is a cross-sectional view of etching the pre-formed conductive material layer; and FIG. A cross-sectional view of the glue step.
  • FIG. 4 is a cross-sectional view schematically showing a display substrate according to an embodiment of the present disclosure.
  • first”, “second” and “third” are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining “first”, “second” or “third” may include one or more of the features either explicitly or implicitly.
  • Pads for display devices typically include a metal layer.
  • the metal layer generally includes a first metal sub-layer and a second metal sub-layer laminated on the first metal sub-layer, wherein the first metal sub-layer is less resistant to corrosion than the second metal sub-layer Corrosion resistance.
  • the metal layer is a first conductive metal sublayer including a weak corrosion resistance, a second metal sublayer having a strong corrosion resistance for corrosion resistance thereon, and a substrate for reinforcement thereto
  • the combined corrosion-resistant multilayer structure of the third metal sub-layer such as a multilayer structure of a titanium layer, an aluminum layer, and a titanium layer.
  • the first metal sub-layer such as the aluminum layer having weak corrosion resistance in the pad in the pad region may be undercut, which makes the multilayer structure unstable.
  • a second metal sub-layer such as a titanium layer, which is more resistant to corrosion, collapses in subsequent processes and becomes a moving conductive particle, which causes a short circuit between different signal lines.
  • the present disclosure provides a display substrate, a method of fabricating the same, and a display device, which can avoid undercutting a first metal sub-layer such as an aluminum layer having weak corrosion resistance, thereby It is avoided that the corrosion-resistant second metal sub-layer such as the titanium layer collapses into a moving conductive particle in a subsequent process, causing a short circuit between different signal lines.
  • the method of making the display substrate of the present disclosure does not increase process steps and costs.
  • a display substrate can be provided.
  • the display substrate includes: a display area; and a pad area outside the display area.
  • the pad region includes at least one pad.
  • the pad includes a metal layer and a layer of conductive material.
  • the metal layer includes a first metal sub-layer and a second metal sub-layer laminated on the first metal sub-layer. The corrosion resistance of the second metal sublayer is stronger than the corrosion resistance of the first metal sublayer.
  • the layer of conductive material covers a side surface of the metal layer.
  • the display area may include a display electrode.
  • the conductive material layer of the pad is disposed in the same layer as the display electrode of the display area.
  • the display electrode includes an anode, wherein the conductive material layer of the pad is disposed in the same layer as the anode.
  • the display region further includes a source and a drain, wherein the metal layer of the pad is disposed in the same layer as the source and drain of the display region.
  • the metal layer is a layer formed in the same layer as the source and drain of the transistor in the display substrate and is included a three-layer structure of a titanium layer, an aluminum layer and a titanium layer;
  • the display electrode is an anode;
  • the conductive material layer is an anode material layer formed in the same layer and in the same patterning process as the anode;
  • the conductive material layer and the anode are composed of an ITO layer, a silver layer and ITO
  • the transistor can be, for example, a thin film transistor (TFT).
  • the metal layer can be a two-layer structure comprising an aluminum layer and a titanium layer overlying the aluminum layer.
  • the display electrode can also be a cathode, and the layer of conductive material can also be selected from the same material as the cathode to be formed in the same layer and in the same patterning process.
  • metal layers are sometimes also referred to as source and drain metal layers
  • conductive material layers are sometimes referred to as anode material layers
  • display electrodes are sometimes referred to as anodes.
  • FIG. 1 is a cross-sectional view schematically showing a process in which a metal layer of a pad 100 of a display substrate is etched through an anode in a display region without protection.
  • the display substrate may include a pad region 1000, and a display region 2000 outside the pad region 1000.
  • Pad area 1000 can include at least one pad 100.
  • the pad 100 may include a base substrate 10, an insulating layer 20 formed on the base substrate 10, and a metal layer 30 on the insulating layer 20 (three-layer structure, which may correspond to a source in the display area 2000 described below) And the drain metal layers 94, 96, the same sub-layer is represented by the same legend).
  • the display region 2000 may include a thin film transistor (TFT) 90 on the insulating layer 20 and a display electrode 80 such as an anode 80.
  • the display electrode can be, for example, a pixel electrode.
  • the TFT 90 may include a gate electrode 91, an interlayer dielectric layer 92, an active layer 93, a source electrode 94, and a drain electrode 96.
  • Source 94 or drain 96 may be coupled to display electrode 80, such as anode 80.
  • the drain 96 can be connected to the anode 80.
  • the metal layer 30 may be a multilayer structure including a third metal sublayer 32 which is more resistant to corrosion, a first metal sublayer 34 which is less resistant to corrosion, and a second metal sublayer 36 which is more resistant to corrosion, such as The multilayer structure of the first titanium layer 32, the aluminum layer 34, and the second titanium layer 36.
  • the first metal sub-layer 34 is between the third metal sub-layer 32 and the second metal sub-layer 36.
  • the pad 100 after passing through the etching process on the anode of the display device, causes an undercut of the intermediate first metal sub-layer such as the aluminum layer 34, making the multilayer structure unstable.
  • the second metal sub-layer 36 of the upper layer, such as the second titanium layer 36 may collapse during subsequent processes, becoming moving conductive particles, which may cause short circuits between different signal lines.
  • FIG. 2 is a cross-sectional view schematically showing a display substrate when an edge of the pad 100 is covered with a pixel defining layer material such as polyimide or acryl.
  • a pixel defining layer material such as polyimide or acryl.
  • the edges of the pads 100 are covered with a pixel defining layer material such as polyimide or acryl.
  • a pixel defining layer material such as polyimide or acryl.
  • the pixel defining layer 70 is generally thick, in order not to affect the soldering quality, the pixel defining layer covering the pad region 1000 needs to be thinned to form a thinned pixel defining layer 75.
  • Such thinning requires, for example, a halftone mask, so the cost increases and the process becomes complicated.
  • 150, 65, 60 in the figure respectively represent pads, gold balls, and anisotropic conductive paste of another circuit board such as a flexible printed circuit board (FPC).
  • FIGS. 3A to 3E are cross-sectional views schematically showing a display substrate after respective process steps of a method for preparing a display substrate, in which FIG. 3A is a cross-sectional view after the step of coating the photoresist 50, according to an embodiment of the present disclosure.
  • Figure 3B is a cross-sectional view showing a step of masking a photoresist using a mask
  • Figure 3C is a cross-sectional view showing a step of exposing a portion of the pre-formed conductive material layer after exposure and development
  • Figure 3D is a cross-sectional view of etching a layer of a pre-formed conductive material
  • Figure 3E is a view of removing light A cross-sectional view of the 50 step of engraving.
  • the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals; and detailed description thereof will not be repeated.
  • the method of the present disclosure for preparing a display substrate includes the following steps:
  • a metal layer 30 is formed in the pad region 1000; the metal layer 30 includes a first metal sub-layer 34 and a second metal sub-layer 36 laminated on the first metal sub-layer 34, wherein the second metal sub-layer 36 is highly resistant to corrosion Corrosion resistance to the first metal sub-layer 34;
  • a photoresist 50 is coated on the pre-formed conductive material layer 40.
  • the photoresist 50 is then masked by a mask M.
  • the occluded portion is the portion of the layer of pre-formed conductive material that is not desired to be etched away. In the figure, it is above the side surface of the metal layer 30, that is, the conductive material layer 40 that is intended to remain on the side of the metal layer 30.
  • a portion of the pre-formed conductive material layer 40 is subsequently exposed, developed, and exposed, wherein at least a photoresist that covers the pre-formed conductive material layer 40 on the side surface of the metal layer 30 remains after the development. 50, and at least removing the photoresist covering the pre-formed conductive material layer on a portion of the top surface of the metal layer.
  • the pre-formed conductive material layer 40 is subsequently etched.
  • the conductive material of the portion covered by the photoresist is retained and the other portions are etched away.
  • Figures 3A-3E also schematically illustrate one embodiment of a method of preparation including other components.
  • Display area 2000 can include display electrode 80.
  • the conductive material layer 40 of the pad region 1000 may be formed simultaneously with the display electrode 80 of the display region 2000, that is, formed in the same layer and formed using the same patterning process.
  • the pre-formed conductive material layer 40 extends to a portion of the display region 2000 where the display electrode 80 is to be formed.
  • the pad region 1000 and the prefabricated conductive material layer in the display region 2000 are continuous, they may be discontinuous. They may be formed in the same layer in one step such as a deposition step, but may also be formed separately.
  • a mask is also disposed over the photoresist 50 at a portion of the display electrode. As shown in FIG.
  • the display electrode can include an anode 80.
  • the conductive material layer 40 of the pad region 1000 and the anode 80 of the display region 2000 may be formed simultaneously, that is, formed in the same layer and formed using the same patterning process.
  • the pre-formed conductive material layer 40 extends to the portion of the display region 2000 where the anode 80 is to be formed.
  • the pad region 1000 and the prefabricated conductive material layer in the display region 2000 are continuous, they may be discontinuous. They may be formed in the same layer in one step such as a deposition step, but may also be formed separately.
  • a portion of the anode 80 is also provided with a mask over the photoresist 50. As shown in FIG.
  • the metal layer 30 of the pad region 1000 may be formed simultaneously with the source and drain electrodes in the transistor of the display region 2000, that is, formed in the same layer and formed using the same patterning process.
  • the anode material layer 40 covering the side surface of the metal layer 30 also belongs to the conductive contact region, and the conductivity of the metal layer 30 can be further improved.
  • FIG. 4 is a cross-sectional view schematically showing a display substrate according to an embodiment of the present disclosure.
  • the display substrate of the present disclosure may include a pad region 1000, and a display region 2000 outside the pad region 1000.
  • Pad area 1000 can include at least one pad 100.
  • the pad 100 may include a base substrate 10, an insulating layer 20 formed on the base substrate 10, and a metal layer 30 on the insulating layer 20.
  • the display area 2000 may include a TFT 90 on the insulating layer 20 and a display electrode 80 such as an anode 80.
  • the TFT 90 may include a gate electrode 91, an interlayer dielectric layer 92, an active layer 93, a source electrode 94, and a drain electrode 96. Source 94 or drain 96 may be coupled to display electrode 80, such as anode 80.
  • the drain 96 can be connected to the anode 80.
  • the metal layer 30 may be a multilayer structure including a third metal sublayer 32 which is more resistant to corrosion, a first metal sublayer 34 which is less resistant to corrosion, and a second metal sublayer 36 which is more resistant to corrosion, such as The multilayer structure of the first titanium layer 32, the aluminum layer 34, and the second titanium layer 36.
  • the first metal sub-layer 34 is between the third metal sub-layer 32 and the second metal sub-layer 36.
  • the metal layer 30 may also include only weak corrosion resistance.
  • the two-layer structure of the first metal sub-layer 34 and the second metal sub-layer 36 which is more resistant to corrosion.
  • the second metal sub-layer 36 covers the first metal sub-layer 34.
  • the metal layer 30 may be a two-layer structure of the aluminum layer 34 and the titanium layer 36. Titanium layer 36 covers aluminum layer 34.
  • the side surface of the metal layer 30 is covered by the anode material layer 40.
  • the anode material layer 40 covering the side surface of the metal layer 30 also belongs to the conductive contact region, and the conductivity of the metal layer 30 can be further improved.
  • the metal layer 30 may be a multilayer structure including the first titanium layer 32, the aluminum layer 34, and the second titanium layer 36.
  • Aluminum layer 34 is between first titanium layer 32 and second titanium layer 36.
  • the first titanium layer 32 may have a thickness of 400 to
  • the aluminum layer 34 may have a thickness of 4000
  • the thickness of the second titanium layer may be 400 to
  • the thicknesses of the first titanium layer 32 and the second titanium layer 36 may be the same or different.
  • the thickness of the titanium layer 36 may be 400 to And the thickness of the aluminum layer 34 can be 4000 to
  • the anode material layer 40 may be a multilayer structure including a first transparent conductive oxide layer, a metal material layer, and a second transparent conductive oxide layer.
  • the metal material layer is between the first transparent conductive oxide layer and the second transparent conductive oxide layer.
  • the thickness of the first transparent conductive oxide layer may be 50 to
  • the thickness of the metal material layer can be 800 to
  • the thickness of the second transparent conductive oxide layer may be 50 to
  • the thicknesses of the first transparent conductive oxide layer and the second transparent conductive oxide layer may be the same or different.
  • the transparent conductive oxides in the first and second transparent conductive oxide layers may be the same or different, and the first and second transparent conductive oxide layers may include a group consisting of the following Any of: indium oxide, tin oxide, indium tin oxide, and a mixture of any two or more thereof.
  • the metal material layer may include silver, such as silver.
  • the anode material layer may include a first indium tin oxide (ITO) layer, a silver layer, and a second indium tin oxide (ITO) layer.
  • the silver layer is between the first ITO layer and the second ITO layer.
  • the display substrate may be an active matrix light emitting substrate or a passive matrix light emitting substrate.
  • the pad 100 may also be bonded to the pad 150 of another circuit board by the anisotropic conductive paste 60 including the gold ball 65 on the second metal sub-layer 36.
  • the second metal sub-layer 36 is in contact with the anisotropic conductive paste 60 containing the gold balls 65.
  • the pads of the present disclosure can be used to connect an integrated circuit board or a flexible printed circuit board, such as electrically connected to pads 150 of an integrated circuit board or flexible printed circuit board.
  • the display area includes the display electrode 80.
  • the conductive material layer 40 of the pad 100 is disposed in the same layer as the display electrode 80 of the display region and formed by the same patterning process. As such, the conductive material layer 40 of the pad 100 can be formed without increasing process steps and costs.
  • the display electrode includes an anode 80.
  • the anode material layer 40 of the pad is disposed in the same layer as the anode 80 and formed by the same patterning process. As such, the anode material layer 40 of the pad 100 can be formed without increasing process steps and costs.
  • the display region further includes a transistor such as a TFT, and the transistor includes a source 94/drain 96.
  • the metal layer 30 of the pad 100 is disposed in the same layer as the source 94/drain 96 of the display region and formed by the same patterning process. As such, the metal layer 30 of the pad 100 can be formed without increasing process steps and costs.
  • the method for preparing a display substrate may further include forming a gold ball 65 on the second metal sub-layer 36 after removing the photoresist on the side surface of the metal layer 30.
  • Anisotropic conductive paste 60 may be formed on the second metal sub-layer 36 after removing the photoresist on the side surface of the metal layer 30.
  • the pad 100 of the present disclosure may be connected to an integrated circuit board or a flexible printed circuit board by an anisotropic conductive paste 60, such as electrically connected to pads 150 of an integrated circuit board or a flexible printed circuit board.
  • the display device of the present disclosure may include the display substrate of the present disclosure.
  • the display substrate of the present disclosure may include an active matrix light emitting substrate or a passive matrix light emitting substrate.
  • the display device of the present disclosure may include an active matrix light emitting display device and a passive matrix light emitting display device.
  • the display substrate of the present disclosure its preparation method and display device, undercutting of the intermediate first metal sub-layer such as the aluminum layer 34 can be avoided without increasing the number of process steps and costs.
  • the problem that the second metal sub-layer of the upper layer, such as the second titanium layer 36, collapses into moving conductive particles in the subsequent process, causing a short circuit between the different signal lines is avoided.
  • the intermediate aluminum layer 34 can be avoided by the display substrate of the present disclosure, the method of manufacturing the same, and the display device. An undercut appears. Thereby, the problem that the second titanium layer 36 is collapsed into a moving conductive particle in the subsequent process to cause a short circuit between the different signal lines is avoided.
  • the conductive material layer 40 covering the side surface of the metal layer 30, such as the anode conductive material 40 also belongs to the conductive contact region, and the conductivity of the metal layer 30 can be further improved.
  • the display substrate, the preparation method thereof and the display device of the present disclosure can avoid undercutting the first metal sub-layer such as the aluminum layer with weak corrosion resistance, thereby avoiding the second metal sub-layer with strong corrosion resistance. For example, in the subsequent process, the titanium layer collapses into a moving conductive particle, causing a short circuit between different signal lines.
  • the display substrate fabrication method of the present disclosure does not increase process steps and costs.
  • the metal layer is a multilayer structure including a titanium layer, an aluminum layer, and a titanium layer
  • the preparation method thereof, and the display device can avoid the undercut of the intermediate aluminum layer, thereby It is avoided that the upper titanium layer collapses into a moving conductive particle in a subsequent process, causing a short circuit between different signal lines.
  • the conductive material layer covering the side surface of the metal layer also belongs to the conductive contact region, and the conductivity of the metal layer can be further improved.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
PCT/CN2018/072071 2017-07-17 2018-01-10 显示基板及其制备方法和显示装置 Ceased WO2019015270A1 (zh)

Priority Applications (3)

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US16/092,721 US10756034B2 (en) 2017-07-17 2018-01-10 Display substrate, production method thereof, and display apparatus
JP2018552877A JP7113757B2 (ja) 2017-07-17 2018-01-10 表示基板、表示基板の製造方法、および表示装置
EP18780011.5A EP3457438A4 (en) 2017-07-17 2018-01-10 DISPLAY SUBSTRATE, PRODUCTION METHOD THEREFOR, AND DISPLAY DEVICE

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CN201710584603.4A CN109273483B (zh) 2017-07-17 2017-07-17 显示基板及其制备方法和显示装置
CN201710584603.4 2017-07-17

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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020191623A1 (zh) * 2019-03-26 2020-10-01 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN113809095B (zh) * 2020-05-27 2024-12-31 京东方科技集团股份有限公司 阵列基板及其制备方法
CN111682050B (zh) * 2020-06-22 2022-04-01 武汉华星光电半导体显示技术有限公司 触控显示装置及其制造方法
CN111708465B (zh) * 2020-07-08 2023-07-25 武汉华星光电半导体显示技术有限公司 触控显示装置及其制造方法
CN112002251B (zh) * 2020-08-06 2022-05-31 Tcl华星光电技术有限公司 显示面板及其制备方法
CN111916463B (zh) * 2020-08-20 2023-03-24 武汉华星光电技术有限公司 阵列基板、其制备方法及显示面板
WO2022048538A1 (zh) 2020-09-07 2022-03-10 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板和背光模组
CN120152481A (zh) * 2020-09-10 2025-06-13 京东方科技集团股份有限公司 一种发光基板、显示装置及制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101645456A (zh) * 2008-08-06 2010-02-10 奇美电子股份有限公司 电子装置、薄膜晶体管、显示装置及导体接触工艺
CN102496616A (zh) * 2011-11-28 2012-06-13 日月光半导体制造股份有限公司 具有整合被动元件的半导体元件及其制造方法
US20140184937A1 (en) * 2012-12-27 2014-07-03 Lg Display Co., Ltd. Organic light emitting diode display device including touch panel
CN104218058A (zh) * 2013-05-30 2014-12-17 三星显示有限公司 有机发光显示装置
CN105742324A (zh) * 2014-12-29 2016-07-06 乐金显示有限公司 有机发光显示装置及其制造方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2988159B2 (ja) * 1992-11-13 1999-12-06 日本電気株式会社 液晶表示装置
JP2000267595A (ja) 1999-03-15 2000-09-29 Toshiba Corp 表示装置用アレイ基板の製造方法
US6639265B2 (en) * 2000-01-26 2003-10-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the semiconductor device
KR20020083249A (ko) 2001-04-26 2002-11-02 삼성전자 주식회사 배선의 접촉 구조 및 그의 제조 방법과 이를 포함하는박막 트랜지스터 기판 및 그 제조 방법
JP4036154B2 (ja) * 2002-09-12 2008-01-23 セイコーエプソン株式会社 配線構造の製造方法、電気光学装置の製造方法、電気光学装置および電子機器
JP2006047827A (ja) * 2004-08-06 2006-02-16 Mitsubishi Electric Corp 液晶表示装置およびその製造方法
KR101232549B1 (ko) * 2005-12-29 2013-02-12 엘지디스플레이 주식회사 유기 전계 발광 표시 장치 및 이의 제조 방법
US8780310B2 (en) * 2008-11-26 2014-07-15 Sharp Kabushiki Kaisha Display device having higher-layer wiring that does not overlap connection portion
KR20110134444A (ko) * 2009-03-05 2011-12-14 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 직렬 연결된 ｏｌｅｄ
KR101073552B1 (ko) 2009-10-09 2011-10-17 삼성모바일디스플레이주식회사 유기 발광 표시 장치 및 그 제조 방법
KR101407814B1 (ko) * 2011-07-19 2014-06-17 파나소닉 주식회사 표시 장치 및 표시 장치의 제조 방법
JP2014145857A (ja) 2013-01-28 2014-08-14 Sony Corp 表示装置およびその製造方法、並びに電子機器
US10181573B2 (en) 2014-07-11 2019-01-15 Lg Display Co., Ltd. Organic light-emitting diode display device and method of fabricating the same
US9553156B2 (en) 2014-07-16 2017-01-24 Lg Display Co., Ltd. Organic light emitting display device and method of manufacturing the same
KR102230692B1 (ko) 2014-07-29 2021-03-19 엘지디스플레이 주식회사 유기 발광 표시 장치 및 유기 발광 표시 장치 제조 방법
EP3220410A4 (en) 2014-11-13 2018-07-18 Renesas Electronics Corporation Semiconductor device and manufacturing method for same
KR102377531B1 (ko) 2015-01-23 2022-03-22 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
KR101879180B1 (ko) 2015-11-16 2018-07-17 엘지디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
CN106338866B (zh) * 2016-10-18 2019-08-02 武汉华星光电技术有限公司 一种液晶面板的焊盘区域结构
KR102854033B1 (ko) * 2016-11-30 2025-09-02 엘지디스플레이 주식회사 유기 발광 표시 장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101645456A (zh) * 2008-08-06 2010-02-10 奇美电子股份有限公司 电子装置、薄膜晶体管、显示装置及导体接触工艺
CN102496616A (zh) * 2011-11-28 2012-06-13 日月光半导体制造股份有限公司 具有整合被动元件的半导体元件及其制造方法
US20140184937A1 (en) * 2012-12-27 2014-07-03 Lg Display Co., Ltd. Organic light emitting diode display device including touch panel
CN104218058A (zh) * 2013-05-30 2014-12-17 三星显示有限公司 有机发光显示装置
CN105742324A (zh) * 2014-12-29 2016-07-06 乐金显示有限公司 有机发光显示装置及其制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3457438A4 *

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CN109273483A (zh) 2019-01-25
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EP3457438A4 (en) 2020-03-11
CN109273483B (zh) 2021-04-02
US10756034B2 (en) 2020-08-25
EP3457438A1 (en) 2019-03-20
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