WO2018221340A1 - Grille de connexion, procédé de production de grille de connexion et procédé de production de dispositif semi-conducteur - Google Patents

Grille de connexion, procédé de production de grille de connexion et procédé de production de dispositif semi-conducteur Download PDF

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Publication number
WO2018221340A1
WO2018221340A1 PCT/JP2018/019792 JP2018019792W WO2018221340A1 WO 2018221340 A1 WO2018221340 A1 WO 2018221340A1 JP 2018019792 W JP2018019792 W JP 2018019792W WO 2018221340 A1 WO2018221340 A1 WO 2018221340A1
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WO
WIPO (PCT)
Prior art keywords
lead frame
back surface
front surface
manufacturing
mold
Prior art date
Application number
PCT/JP2018/019792
Other languages
English (en)
Japanese (ja)
Inventor
石橋　貴弘
Original Assignee
株式会社三井ハイテック
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社三井ハイテック filed Critical 株式会社三井ハイテック
Priority to KR1020197035872A priority Critical patent/KR102346708B1/ko
Priority to CN201880032553.1A priority patent/CN110622304B/zh
Publication of WO2018221340A1 publication Critical patent/WO2018221340A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure

Definitions

  • FIG. 1A is a plan view of the front surface of the lead frame according to the embodiment.
  • FIG. 1B is a plan view of the back surface of the lead frame according to the embodiment.
  • FIG. 2A is a diagram for explaining the roughening treatment apparatus according to the embodiment.
  • FIG. 2B is an enlarged cross-sectional view of the lead frame after the surface roughening process according to the embodiment.
  • FIG. 3A is an enlarged cross-sectional view for explaining a molding process according to the embodiment.
  • FIG. 3B is a plan view for explaining the molding process according to the embodiment.
  • FIG. 4 is a cross-sectional view of the semiconductor device according to the embodiment.
  • FIG. 5A is a diagram for describing an outline of a roughening apparatus according to a modification of the embodiment.
  • FIG. 5B is an enlarged cross-sectional view of the lead frame after the surface roughening process according to the modification of the embodiment.
  • the plurality of leads 12 are arranged side by side around the die pad 11. Each leading end portion of the lead 12 extends from the outer edge portion of the unit lead frame 10 toward the die pad 11.
  • the lead 12 is electrically connected to the electrode of the semiconductor chip 101 disposed on the die pad 11 by a bonding wire or the like. Thereby, the lead 12 functions as an external terminal of the semiconductor device 100.
  • the lead frame 1 has a first part 3a and a second part 3b on the back surface 3.
  • the first part 3 a is a part of the back surface 3 where the unit lead frame 10 is disposed.
  • the second part 3 b is a part other than the first part 3 a on the back surface 3.
  • the roughening treatment apparatus 30 includes, for example, a treatment tank 31, an anode 32, a cathode 33, and DC power supplies 34 and 35.
  • the anode 32 and the cathode 33 are both flat.
  • a predetermined electrolytic solution 36 is filled into the processing tank 31.
  • the anode 32 and the cathode 33 are disposed so as to face each other so as to be immersed in the electrolytic solution 36.
  • FIG. 3A is an enlarged cross-sectional view for explaining a molding process according to the embodiment.
  • illustration of the bonding wire mentioned above is abbreviate
  • the lead frame 1 is sandwiched between an upper mold 41 and a lower mold 42. Then, the mold resin 102 is formed in the space 42 a formed in the lower mold 42, the through hole 14, and the space 41 a formed in the upper mold 41 via the mold runner 43 from the outside of the mold. (See FIG. 4) is injected. In this way, a mold having a predetermined shape corresponding to the space 41a and the space 42a is formed.
  • the mold resin 102 remaining on the mold runner 43 after the molding step comes into contact with the second portion 3b of the back surface 3 having a small surface roughness R1. Therefore, according to the embodiment, the mold resin 102 remaining in the mold runner 43 can be easily peeled from the lead frame 1 after the molding process.
  • the lead 12 is disposed on the front surface 2 on which the mold runner 43 is disposed.
  • the adhesion between the front surface 2 and the mold resin 102 can be suppressed.
  • the roughening apparatus 30A according to the modification has basically the same configuration as the roughening apparatus 30 shown in FIG. 2A. For this reason, the same portions may be denoted by the same numbers and description thereof may be omitted.
  • FIG. 5B is an enlarged cross-sectional view of the lead frame 1 after the surface roughening process according to a modification of the embodiment.
  • the formed plating film 7 has a large particle size. Therefore, the plating film 7 is a film having a large surface roughness.
  • the plating film 7 is also formed around the through hole 14 on the back surface 3.
  • the desired portions (the second portion 3b of the back surface 3, the first portion 3a of the back surface 3, and the front surface 2) have the desired surface roughnesses R1, R2, and R3.
  • the lead frame 1 having it can be formed efficiently.
  • the above-described electrolytic treatment conditions are merely examples. As long as the desired effect is obtained, the electrolytic treatment may be performed under different conditions.
  • the tip of the lead 12 on which the copper plating film 7 is formed is plated (for example, Ag plating) to bond the electrode of the semiconductor chip 101 and the tip of the lead 12. Can be connected with a wire.
  • a plating film other than the copper plating film 7 may be formed on the lead frame 1.
  • a matte Ni plating film having a large surface roughness is formed on the first portion 3a of the front surface 2 and the back surface 3, and Pd, A noble metal film such as Au or Ru may be formed.
  • the method for manufacturing the semiconductor device 100 according to the embodiment includes a molding process in which the lead frame 1 is sealed with the mold resin 102. And the mold runner 43 which distribute

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

Dans la présente invention, la résine de moulage restant dans un canal d'alimentation de moule est facilement séparée d'une grille de connexion. Une grille de connexion a une surface avers sur laquelle est montée une puce semi-conductrice, et une surface revers sur le côté opposé à la surface avers, plusieurs grilles de connexion unitaires comprenant des pastilles de puce et plusieurs fils étant disposés de sorte à être alignés. La surface revers comprend une première zone dans laquelle sont disposées les grilles de connexion unitaires, et une seconde zone qui est une zone différente de la première zone. La première zone présente une rugosité de surface inférieure à celle de la surface avers, et la seconde zone présente une rugosité de surface inférieure à celle de la première zone.
PCT/JP2018/019792 2017-06-02 2018-05-23 Grille de connexion, procédé de production de grille de connexion et procédé de production de dispositif semi-conducteur WO2018221340A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020197035872A KR102346708B1 (ko) 2017-06-02 2018-05-23 리드 프레임, 리드 프레임의 제조 방법, 및 반도체 장치의 제조 방법
CN201880032553.1A CN110622304B (zh) 2017-06-02 2018-05-23 引线框架、引线框架的制造方法和半导体装置的制造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017110200A JP6850202B2 (ja) 2017-06-02 2017-06-02 リードフレーム、リードフレームの製造方法および半導体装置の製造方法
JP2017-110200 2017-06-02

Publications (1)

Publication Number Publication Date
WO2018221340A1 true WO2018221340A1 (fr) 2018-12-06

Family

ID=64456131

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2018/019792 WO2018221340A1 (fr) 2017-06-02 2018-05-23 Grille de connexion, procédé de production de grille de connexion et procédé de production de dispositif semi-conducteur

Country Status (5)

Country Link
JP (1) JP6850202B2 (fr)
KR (1) KR102346708B1 (fr)
CN (1) CN110622304B (fr)
TW (1) TWI711129B (fr)
WO (1) WO2018221340A1 (fr)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03295262A (ja) * 1990-04-13 1991-12-26 Mitsubishi Electric Corp リードフレームおよびその製造方法
JP2004158513A (ja) * 2002-11-01 2004-06-03 Mitsui High Tec Inc リードフレーム及びその製造方法
JP2006093559A (ja) * 2004-09-27 2006-04-06 Sumitomo Metal Mining Package Materials Co Ltd リードフレームおよびその製造方法
JP2009010407A (ja) * 2008-08-19 2009-01-15 Shinko Electric Ind Co Ltd パッケージ部品及びその製造方法ならびに半導体パッケージ
JP2013105849A (ja) * 2011-11-11 2013-05-30 Shindengen Electric Mfg Co Ltd 半導体装置
JP2014007363A (ja) * 2012-06-27 2014-01-16 Renesas Electronics Corp 半導体装置の製造方法および半導体装置
JP2017076764A (ja) * 2015-10-16 2017-04-20 新光電気工業株式会社 リードフレーム及びその製造方法、半導体装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013225595A (ja) * 2012-04-20 2013-10-31 Shinko Electric Ind Co Ltd リードフレーム及び半導体パッケージ並びにそれらの製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03295262A (ja) * 1990-04-13 1991-12-26 Mitsubishi Electric Corp リードフレームおよびその製造方法
JP2004158513A (ja) * 2002-11-01 2004-06-03 Mitsui High Tec Inc リードフレーム及びその製造方法
JP2006093559A (ja) * 2004-09-27 2006-04-06 Sumitomo Metal Mining Package Materials Co Ltd リードフレームおよびその製造方法
JP2009010407A (ja) * 2008-08-19 2009-01-15 Shinko Electric Ind Co Ltd パッケージ部品及びその製造方法ならびに半導体パッケージ
JP2013105849A (ja) * 2011-11-11 2013-05-30 Shindengen Electric Mfg Co Ltd 半導体装置
JP2014007363A (ja) * 2012-06-27 2014-01-16 Renesas Electronics Corp 半導体装置の製造方法および半導体装置
JP2017076764A (ja) * 2015-10-16 2017-04-20 新光電気工業株式会社 リードフレーム及びその製造方法、半導体装置

Also Published As

Publication number Publication date
JP2018206920A (ja) 2018-12-27
KR102346708B1 (ko) 2021-12-31
TWI711129B (zh) 2020-11-21
CN110622304A (zh) 2019-12-27
KR20200003884A (ko) 2020-01-10
TW201911493A (zh) 2019-03-16
JP6850202B2 (ja) 2021-03-31
CN110622304B (zh) 2023-07-14

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