JP2013105849A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2013105849A JP2013105849A JP2011247799A JP2011247799A JP2013105849A JP 2013105849 A JP2013105849 A JP 2013105849A JP 2011247799 A JP2011247799 A JP 2011247799A JP 2011247799 A JP2011247799 A JP 2011247799A JP 2013105849 A JP2013105849 A JP 2013105849A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
- H01L2924/13033—TRIAC - Triode for Alternating Current - A bidirectional switching device containing two thyristor structures with common gate contact
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Lead Frames For Integrated Circuits (AREA)
Abstract
【解決手段】半導体チップ110と、半導体チップ110を搭載するための第1リードフレーム120と、ボンディング面132を有する第2リードフレーム130,140とを備え、第2リードフレーム130,140におけるボンディング面132,142は、接続部材150を介して半導体チップ110と電気的に接続され、半導体チップ110、第1リードフレーム120及び第2リードフレーム130,140が樹脂封止により一体化された半導体装置であって、ボンディング面132,142は、第1の粗化処理が施された第1の粗化面であり、めっきを介することなく接続部材150と接続されていることを特徴とする半導体装置。
【選択図】図1
Description
1.実施形態に係る半導体装置100の構成
まず、実施形態に係る半導体装置100の構成を説明する。
図1は、実施形態に係る半導体装置100を説明するために示す図である。図1(a)は実施形態に係る半導体装置100の平面図であり、図1(b)は実施形態に係る半導体装置100の側断面図である。
以下、実施形態に係る半導体装置100の効果を記載する。
Claims (8)
- 半導体チップと、
前記半導体チップを搭載するためのダイパッドを有する第1リードフレームと、
ボンディング面を有し、前記第1リードフレームとは離間して配置された第2リードフレームとを備え、
前記第2リードフレームにおける前記ボンディング面は、接続部材を介して前記半導体チップと電気的に接続され、
前記半導体チップ、前記第1リードフレーム及び前記第2リードフレームが樹脂封止により一体化された半導体装置であって、
前記ボンディング面は、第1の粗化処理が施された第1の粗化面であり、めっきを介することなく前記接続部材と接続されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記ダイパッドにおける前記半導体チップを搭載する側の面は、第2の粗化処理が施された第2の粗化面であることを特徴とする半導体装置。 - 請求項1又は2に記載の半導体装置において、
前記第1の粗化面の平均粗さは、前記第2の粗化面の平均粗さよりも小さいことを特徴とする半導体装置。 - 請求項1〜3のいずれかに記載の半導体装置において、
前記接続部材は、ボンディングワイヤーであることを特徴とする半導体装置。 - 請求項4のいずれかに記載の半導体装置において、
前記ボンディング面と前記ボンディングワイヤーとは、超音波振動を加えながら熱圧着された構造を有することを特徴とする半導体装置。 - 請求項1〜5のいずれかに記載の半導体装置において、
前記第1の粗化処理は、エッチングによる粗化処理であることを特徴とする半導体装置。 - 請求項1〜5のいずれかに記載の半導体装置において、
前記第1の粗化処理は、研磨剤を用いた粗化処理であることを特徴とする半導体装置。 - 請求項1〜5のいずれかに記載の半導体装置において、
前記第1の粗化処理は、銅及び酸化銅からなる粒子を前記ボンディング面に電着させる粗化処理であることを特徴とする半導体装置。
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JP2011247799A JP2013105849A (ja) | 2011-11-11 | 2011-11-11 | 半導体装置 |
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JP2011247799A JP2013105849A (ja) | 2011-11-11 | 2011-11-11 | 半導体装置 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018221340A1 (ja) * | 2017-06-02 | 2018-12-06 | 株式会社三井ハイテック | リードフレーム、リードフレームの製造方法、および半導体装置の製造方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6139556A (ja) * | 1984-07-31 | 1986-02-25 | Toshiba Corp | リ−ドフレ−ム |
JPS6179542U (ja) * | 1984-10-29 | 1986-05-27 | ||
JPH01266729A (ja) * | 1988-04-18 | 1989-10-24 | Hitachi Ltd | 半導体装置 |
JPH08321577A (ja) * | 1995-05-26 | 1996-12-03 | Hitachi Cable Ltd | 多層リードフレームおよびその製造方法 |
JP2006140265A (ja) * | 2004-11-11 | 2006-06-01 | Denso Corp | 半導体装置および半導体装置に用いるリードフレームの製造方法 |
JP2010245417A (ja) * | 2009-04-09 | 2010-10-28 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
-
2011
- 2011-11-11 JP JP2011247799A patent/JP2013105849A/ja active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6139556A (ja) * | 1984-07-31 | 1986-02-25 | Toshiba Corp | リ−ドフレ−ム |
JPS6179542U (ja) * | 1984-10-29 | 1986-05-27 | ||
JPH01266729A (ja) * | 1988-04-18 | 1989-10-24 | Hitachi Ltd | 半導体装置 |
JPH08321577A (ja) * | 1995-05-26 | 1996-12-03 | Hitachi Cable Ltd | 多層リードフレームおよびその製造方法 |
JP2006140265A (ja) * | 2004-11-11 | 2006-06-01 | Denso Corp | 半導体装置および半導体装置に用いるリードフレームの製造方法 |
JP2010245417A (ja) * | 2009-04-09 | 2010-10-28 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018221340A1 (ja) * | 2017-06-02 | 2018-12-06 | 株式会社三井ハイテック | リードフレーム、リードフレームの製造方法、および半導体装置の製造方法 |
JP2018206920A (ja) * | 2017-06-02 | 2018-12-27 | 株式会社三井ハイテック | リードフレーム、リードフレームの製造方法および半導体装置の製造方法 |
CN110622304A (zh) * | 2017-06-02 | 2019-12-27 | 株式会社三井高科技 | 引线框架、引线框架的制造方法和半导体装置的制造方法 |
KR20200003884A (ko) * | 2017-06-02 | 2020-01-10 | 가부시키가이샤 미츠이하이테크 | 리드 프레임, 리드 프레임의 제조 방법, 및 반도체 장치의 제조 방법 |
TWI711129B (zh) * | 2017-06-02 | 2020-11-21 | 日商三井高科技股份有限公司 | 引線框架、引線框架的製造方法和半導體裝置的製造方法 |
KR102346708B1 (ko) * | 2017-06-02 | 2021-12-31 | 가부시키가이샤 미츠이하이테크 | 리드 프레임, 리드 프레임의 제조 방법, 및 반도체 장치의 제조 방법 |
CN110622304B (zh) * | 2017-06-02 | 2023-07-14 | 株式会社三井高科技 | 引线框架、引线框架的制造方法和半导体装置的制造方法 |
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