WO2018188332A1 - 一种氧化物半导体薄膜及由其制备的薄膜晶体管 - Google Patents

一种氧化物半导体薄膜及由其制备的薄膜晶体管 Download PDF

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WO2018188332A1
WO2018188332A1 PCT/CN2017/111109 CN2017111109W WO2018188332A1 WO 2018188332 A1 WO2018188332 A1 WO 2018188332A1 CN 2017111109 W CN2017111109 W CN 2017111109W WO 2018188332 A1 WO2018188332 A1 WO 2018188332A1
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thin film
oxide semiconductor
semiconductor thin
oxide
channel layer
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French (fr)
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徐苗
徐华
吴为敬
陈为峰
王磊
彭俊彪
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South China University of Technology SCUT
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South China University of Technology SCUT
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Priority to US17/105,655 priority patent/US11545580B2/en
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Definitions

  • the invention belongs to the technical field of semiconductor materials and devices, and in particular relates to an oxide semiconductor film and a thin film transistor prepared therefrom.
  • the core technology of the new Flat Panel Display (FPD) industry is Thin Film Transistor (TFT) backplane technology.
  • the metal oxide TFT (MO-TFT, Metal Oxide-TFT) not only has a high mobility (about 1 to 100 cm 2 /(V ⁇ s)), but also has a relatively simple fabrication process and can be combined with the current a-Si process. Compatible, low manufacturing cost, and excellent large area uniformity. Therefore, MO-TFT technology has attracted much attention from the industry since its inception.
  • the concentration of oxygen vacancies in the semiconductor film is reduced, which can improve the illumination stability of the device to some extent, but also reduce the device. Mobility; and, for its practical application, there are still huge challenges.
  • the active layer of the thin film transistor may be light-shielded by adding a black matrix similar to the silicon-based process.
  • this method can only improve the light response characteristics of the device to some extent, for long-term light.
  • the limited improvement in stability under the conditions has severely limited its application.
  • the increase in the shading process that is, the complexity of the preparation, increases the manufacturing cost. Therefore, it is of great practical significance to improve the illumination stability of an oxide thin film transistor.
  • Another object of the present invention is to provide a thin film transistor which is prepared from the above oxide semiconductor film as a channel layer material.
  • An oxide semiconductor thin film in which a metal oxide (Metal Oxide, MO) semiconductor film is doped with a small amount of rare earth oxide (Rare-earth Oxides, RO) as a light stabilizer to form (MO ) x (RO) y semiconductor material, where 0 ⁇ x ⁇ 1, 0.0001 ⁇ y ⁇ 0.2, x + y 1.
  • MO Metal Oxide
  • RO rare earth oxide
  • M is one element of In, Zn, Ga, Sn, Si, Al, Mg, Zr, Hf, Ta, or any combination of two or more.
  • the rare earth oxide RO material comprises one of cerium oxide, cerium oxide, cerium oxide, cerium oxide or a combination of any two or more materials.
  • the oxide semiconductor film has a thickness of 5 to 100 nm.
  • the oxide semiconductor film has a carrier concentration of less than 5 ⁇ 10 19 cm -3 .
  • the oxide semiconductor film is prepared by a single target sputtering method or by any one of solution method, atomic layer deposition, or pulsed laser deposition.
  • a thin film transistor including a gate, a channel layer, a gate insulating layer between the gate and the channel layer, and a source and a drain respectively connected across the channel layer; the channel Layer material It is the above oxide semiconductor film.
  • the present invention has the following advantages and beneficial effects:
  • the oxide semiconductor thin film and the thin film transistor of the present invention have excellent light stability. This is because the rare earth oxide is doped into the metal oxide semiconductor, and the rare earth metal atom replaces the original metal atom, which causes the original MM interaction to weaken, causing the valence band to be displaced, so that the original metal oxide semiconductor material band structure is directly
  • the gap changes to an indirect band gap.
  • the valence band electrons need to interact with the phonons to transition to the conduction band, contributing to the transport properties. Therefore, the incorporation of the rare earth metal oxide can greatly reduce the photo-generated carriers when the thin film transistor operates. That is, when the incident light is irradiated, the threshold voltage of the device and the unexposed light are hardly shifted, and other performance parameters are not affected by the light;
  • the content of the rare earth metal oxide is relatively small, and the influence on the mobility of the base material (the material which is the main component of the compound) is small, and the device is not substantially caused. Degradation of performance;
  • the oxide semiconductor thin film material of the present invention has very excellent light stability, and has the characteristics of simple preparation process and strong applicability, and the improvement of the matrix material of different systems is also obvious.
  • FIG. 1 is a schematic structural view of a thin film transistor in Embodiment 5 of the present invention.
  • FIG. 2 is a view showing a device light response characteristic of a thin film transistor in Embodiment 5 of the present invention
  • FIG. 3 is a schematic structural view of a thin film transistor in Embodiment 6 of the present invention.
  • Embodiment 6 is a view showing a device light response characteristic of a thin film transistor in Embodiment 6 of the present invention.
  • FIG. 5 is a schematic structural view of a thin film transistor in Embodiment 7 of the present invention.
  • Figure 6 is a schematic view showing the structure of a thin film transistor in Embodiment 8 of the present invention.
  • the oxide semiconductor thin film is formed by doping a small amount of cerium oxide as a light stabilizer in an indium zinc oxide semiconductor film by a ceramic target magnetron sputtering method to form a cerium oxide doped oxidation.
  • the Pr:IZO semiconductor film has a thickness of 20 nm and a carrier concentration of less than 5 ⁇ 10 19 cm -3 .
  • Tb: The IGZO semiconductor film has a thickness of 40 nm and a carrier concentration of less than 5 ⁇ 10 19 cm -3 .
  • An oxide semiconductor thin film of the present embodiment wherein the oxide semiconductor thin film is formed by doping a small amount of cerium oxide as a light stabilizer in an indium tin zinc-semiconductor thin film by an atomic layer deposition method to form yttrium oxide doped indium tin oxide.
  • a zinc (Dy:ITZO) semiconductor thin film material in which Dy:In:Sn:Zn 0.11:1:1:1 mol.
  • Dy: The thickness of the ITZO semiconductor film is 30 nm, and the carrier concentration is less than 5 ⁇ 10 19 cm -3 .
  • the Yb:ZTO semiconductor film has a thickness of 30 nm and a carrier concentration of less than 5 ⁇ 10 19 cm -3 .
  • a thin film transistor of the present embodiment is an etch barrier structure, and its structure is as shown in FIG. 1 , and is provided with a substrate 01 , a gate electrode 02 on the substrate 01 , and a substrate 01 and a gate electrode 02 .
  • the insulating layer 03, the channel layer 04 covering the upper surface of the insulating layer 03 and corresponding to the gate electrode 02, the etch barrier layer 05, and the source electrode 06-1 which are spaced apart from each other and electrically connected to both ends of the channel layer 04 And drain 06-2, and passivation layer 07.
  • the substrate 01 is a glass substrate covered with a buffer layer of silicon oxide.
  • the material of the gate electrode 02 is a molybdenum aluminum molybdenum (Mo/Al/Mo) laminated structure prepared by metal magnetron sputtering, and has a thickness of 50/200/50 nm.
  • the insulating layer 03 is a laminate of silicon nitride (Si 3 N 4 ) and silicon oxide (SiO 2 ) prepared by chemical vapor deposition, and has a thickness of 250/50 nm.
  • the material of the channel layer 04 is yttria-doped indium zinc oxide (Pr:IZO) and yttria-doped indium gallium zinc oxide (Tb: IGZO) of Examples 1 and 2, respectively.
  • the material of the etch barrier layer 05 and the passivation layer 07 is silicon oxide (SiO 2 ) prepared by chemical vapor deposition, and the thickness is 300 nm.
  • the material of the source 06-1 and the drain 06-2 is a metal molybdenum aluminum molybdenum (Mo/Al/Mo) laminated structure having a thickness of 50/200/50 nm.
  • the thin film transistor of this embodiment may be a closed structure including only a substrate, a gate, an insulating layer, a channel layer, an etch barrier layer, a source and a drain, and a passivation layer, and may further include a pixel defining layer and the like. Can be integrated with other devices.
  • the patterning of the film is performed by photolithography and etching in combination with wet or dry etching.
  • the photoreaction characteristics of the devices prepared by using the two channel layer materials Pr: IZO and Tb: IGZO in the present embodiment are respectively shown in (a) and (b) of FIG. 2 . It can be seen from Fig. 2 that by incorporating a certain amount of yttrium oxide or ytterbium oxide, the threshold voltage is hardly changed under the irradiation of different wavelengths of light and the dark condition (Dark), and excellent light is exhibited. stability.
  • the experimental results show that the incorporation of a certain amount of rare earth oxide in the base oxide material of the present invention can effectively improve the light stability of the material.
  • a thin film transistor of the present embodiment is a back channel etch type structure, and its structure is shown in FIG. 3, and is provided with a substrate 01, a gate electrode 02 located above the substrate 01, and a substrate 01 and a gate electrode 02.
  • the upper insulating layer 03, the channel layer 04 covering the upper surface of the insulating layer 03 and corresponding to the gate electrode 02, and the source electrode 05-1 and the drain electrode 50 which are spaced apart from each other and electrically connected to both ends of the channel layer 04 -2, and passivation layer 06.
  • the substrate 01 is a flexible polyimide (PI) substrate covered with a buffer layer of silicon oxide.
  • the material of the gate electrode 02 is a molybdenum aluminum molybdenum (Mo/Al/Mo) laminated structure prepared by metal magnetron sputtering, and has a thickness of 50/200/50 nm.
  • the insulating layer 03 is a laminate of silicon nitride (Si 3 N 4 ) and silicon oxide (SiO 2 ) prepared by chemical vapor deposition, and has a thickness of 250/50 nm.
  • the material of the channel layer 04 is yttria-doped indium tin zinc oxide (Dy:ITZO) and yttria-doped zinc tin oxide (Yb:ZTO) of Examples 3 and 4, respectively.
  • the material of source 05-1 and drain 05-2 is a metal molybdenum aluminum molybdenum (Mo/Al/Mo) laminated structure with a thickness of 50/200/50 nm, which is carried out using a commercial phosphoric acid molybdenum aluminum molybdenum etching solution. Patterned.
  • the material of the passivation layer 06 is silicon oxide (SiO 2 ) prepared by chemical vapor deposition and has a thickness of 300 nm.
  • the thin film transistor of this embodiment may be a closed structure including only a substrate, a gate, an insulating layer, a channel layer, a source and a drain, and a passivation layer, and may further include a pixel defining layer and the like, and may also be integrated with other devices. Wait.
  • the patterning of the film is performed by photolithography and etching in combination with wet or dry etching.
  • the photo response characteristics of the devices prepared by using the two channel layer materials Dy: ITZO and Yb: ZTO, respectively, in this embodiment are shown in (a) and (b) of FIG. 4, respectively. It can be seen from the results in Fig. 4 that by incorporating a certain amount of cerium oxide or cerium oxide, the threshold voltage is hardly changed with the incident light of different wavelengths and the dark condition (Dark), showing excellent performance. Light stability.
  • the experimental results show that the incorporation of a certain amount of rare earth oxide in the base oxide material of the present invention can effectively improve the light stability of the material.
  • a thin film transistor of the present embodiment is a back channel etch type structure, and a schematic structural view thereof is shown in FIG. 5, and is provided with a substrate 01, a gate electrode 02 located above the substrate 01, and a substrate 01 and a gate electrode 02.
  • the substrate 01 is a flexible polyimide (PI) substrate covered with a buffer layer of silicon oxide.
  • the material of the gate electrode 02 is a molybdenum aluminum molybdenum (Mo/Al/Mo) laminated structure prepared by metal magnetron sputtering, and has a thickness of 50/200/50 nm.
  • the insulating layer 03 is a laminate of silicon nitride (Si 3 N 4 ) and silicon oxide (SiO 2 ) prepared by chemical vapor deposition, and has a thickness of 250/50 nm.
  • the material of the channel layer 04 was yttria-doped indium zinc oxide (Pr: IZO) in Example 1, and the thickness was 20 nm.
  • the material of the channel protective layer 05 is a tin oxide doped oxide or carbon film prepared by magnetron sputtering, and has a thickness of 10 nm.
  • the material of source 06-1 and drain 06-2 is a metal molybdenum aluminum molybdenum (Mo/Al/Mo) laminated structure with a thickness of 50/200/50 nm, which is carried out using a commercial phosphoric acid molybdenum aluminum molybdenum etching solution. Patterned.
  • the material of the passivation layer 07 is silicon oxide (SiO 2 ) prepared by chemical vapor deposition and has a thickness of 300 nm.
  • the thin film transistor of this embodiment may be a closed structure including only a substrate, a gate, an insulating layer, a channel layer, a channel protective layer, a source and a drain, and a passivation layer, and may further include a pixel defining layer and the like. Can be integrated with other devices.
  • the patterning of the film is performed by photolithography and etching in combination with wet or dry etching.
  • the corresponding photo-response characteristics of the prepared device show that the threshold voltage is hardly changed with the incident light of different wavelengths, showing excellent light stability.
  • a thin film transistor of the present embodiment is a self-aligned structure, and its structure is shown in FIG. 6.
  • the substrate 01, the buffer layer 02, the channel layer 03, and the insulating layer above the channel layer 03 are provided. 04 and a gate electrode 05, a spacer layer 06 covering the upper surface of the channel layer 03, and a source electrode 07-1 and a drain electrode 07-2 which are spaced apart from each other and electrically connected to both ends of the channel layer.
  • the substrate 01 is a hard glass substrate.
  • the buffer layer 02 is a plasma enhanced chemical vapor deposition method for preparing silicon oxide.
  • the material of the channel layer 03 was yttria-doped indium gallium zinc oxide (Tb: IGZO) in Example 2 and had a thickness of 40 nm.
  • the gate insulating layer 04 is silicon oxide and has a thickness of 300 nm; the gate electrode 05 is a molybdenum aluminum molybdenum (Mo/Al/Mo) laminated structure prepared by magnetron sputtering, and has a thickness of 50/200/50 nm.
  • Mo/Al/Mo molybdenum aluminum molybdenum
  • the spacer layer 06 is silicon nitride and has a thickness of 200 nm.
  • the material of the source 07-1 and the drain 07-2 is a metal molybdenum aluminum molybdenum (Mo/Al/Mo) laminated structure having a thickness of 50/200/50 nm.
  • the thin film transistor of this embodiment may be a closed structure including only a substrate, a channel layer, an insulating layer, a gate, a spacer layer, a source and a drain, and may further include a passivation layer, a pixel defining layer, and the like. Integration with other devices, etc.
  • the patterning of the film is performed by photolithography and etching in combination with wet or dry etching.
  • the corresponding photo-response characteristics of the prepared device show that the threshold voltage is hardly changed with the incident light of different wavelengths, showing excellent light stability.

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Abstract

一种氧化物半导体薄膜及由其制备的薄膜晶体管。该氧化物半导体薄膜由金属氧化物半导体薄膜中掺入少量稀土氧化物得到。该薄膜晶体管包括栅极（02）、氧化物半导体薄膜制备的沟道层（04）、位于栅极和沟道层之间的栅绝缘层、以及分别连接在沟道层两端的源极（06-1）和漏极（06-2）。该氧化物半导体薄膜材料及由其制备的薄膜晶体管具有优异的光照稳定性，而且制备工艺简单、适用性强。

Description

一种氧化物半导体薄膜及由其制备的薄膜晶体管 技术领域
本发明属于半导体材料与器件技术领域，具体涉及一种氧化物半导体薄膜及由其制备的薄膜晶体管。
背景技术
新型平板显示(FPD,Flat Panel Display)产业的核心技术是薄膜晶体管(TFT,Thin Film Transistor)背板技术。金属氧化物TFT(MO-TFT,Metal Oxide-TFT)不仅具有较高的迁移率(在1～100cm2/(V·s)左右)，而且制作工艺相对简单，可以和目前的a-Si工艺兼容，制造成本较低，还具有优异的大面积均匀性。因此，MO-TFT技术自诞生以来便备受业界瞩目。
众所周知，作为显示器件核心部件的薄膜晶体管，在显示领域的应用中，其不可避免地会受到光的照射；而目前所开发的氧化物半导体薄膜由于氧空位的存在，使得禁带中产生相应的带隙态。该带隙态受到特定能量的光照射后，会激发出相应的电子空穴对，其在栅场的作用下导致器件阈值电压的偏移，从而引起显示画面的劣化。因此，如何实现优异的光照稳定性(在受到光照射时，器件的阈值电压几乎不发生偏移)是氧化物薄膜晶体管器件在实际应用中必须克服的难题。
现有技术，一方面，通过掺入一定量高断键能的氧化物，用以降低半导体薄膜中氧空位的浓度，这能一定程度上改善器件的光照稳定性，但同时也会降低器件的迁移率；而且，对于其在实际应用中而言，还存在巨大的挑战。另外一种方式，通过增加类似硅基工艺中的黑矩阵，对薄膜晶体管的有源层进行遮光处理。但是，该方式仅能一定程度上改善器件的光响应特性，对于长时间光 照条件下的稳定性改善有限，使其应用领域受到了严重的限制。而且，增加遮光工艺，也即增加了制备的复杂程度，造成制造成本的提高。因此，提高氧化物薄膜晶体管的光照稳定性具有非常重大的现实意义。
因此，开发一种具有优异的光照稳定性的氧化物半导体材料，对于氧化物薄膜晶体管的产业化应用具有非同寻常的意义。
发明内容
为了解决以上现有技术的缺点和不足之处，本发明的首要目的在于提供一种氧化物半导体薄膜。
本发明的另一目的在于提供一种由上述氧化物半导体薄膜作为沟道层材料制备的薄膜晶体管。
本发明目的通过以下技术方案实现：
一种氧化物半导体薄膜，所述氧化物半导体薄膜为：在金属氧化物(Metal Oxide,MO)半导体薄膜中掺入少量稀土氧化物(Rare-earth Oxides,RO)作为光稳定剂，形成(MO)x(RO)y半导体材料，其中0<x<1，0.0001≤y≤0.2，x+y＝1。
所述金属氧化物MO中，M为In、Zn、Ga、Sn、Si、Al、Mg、Zr、Hf、Ta中的一种元素或两种以上的任意组合。
所述稀土氧化物RO材料包含：氧化镨、氧化铽、氧化镝、氧化镱中的一种或任意两种以上材料组合。
优选地，0.001≤y≤0.1；更优选为0.001≤y≤0.05。
优选地，所述氧化物半导体薄膜的厚度为5～100nm。
优选地，所述氧化物半导体薄膜的载流子浓度小于5×1019cm-3。
优选地，所述氧化物半导体薄膜采用单靶溅射的方法制备，或者采用溶液法、原子层沉积或脉冲激光沉积中的任意一种方式制备。
一种薄膜晶体管，所述薄膜晶体管包括栅极、沟道层、位于栅极和沟道层之间的栅绝缘层、以及分别连接在沟道层两端的源极和漏极；所述沟道层材料 为上述氧化物半导体薄膜。
相对于现有技术，本发明具有如下优点及有益效果：
(1)本发明的氧化物半导体薄膜及薄膜晶体管，具有优异的光照稳定性。这是因为稀土氧化物掺入金属氧化物半导体中，稀土金属原子替代了原金属原子而导致原来的M-M相互作用减弱，致使价带顶位移，使原金属氧化物半导体材料能带结构由直接带隙向间接带隙转变。在入射光照射时，价带电子需要与声子相互作用才能跃迁到导带，对输运特性产生贡献。因此，稀土金属氧化物的掺入可以大大减少薄膜晶体管工作时的光生载流子。也即，在入射光照射时，器件的阈值电压和未受光照时几乎不发生偏移，同时其他性能参数亦不受光照影响；
(2)本发明的氧化物半导体薄膜材料中，稀土金属氧化物的含量相对较少，其对基体材料(化合物中占主要成分的材料)的迁移率等性能影响较小，不会造成器件基本性能的退化；
(3)本发明的氧化物半导体薄膜材料具有非常优异的光照稳定性，而且具有制备工艺简单、适用性强的特点，其对不同体系基体材料的改善同样明显。
附图说明
图1是本发明实施例5中薄膜晶体管的结构示意图；
图2是本发明实施例5中薄膜晶体管的器件光响应特性图；
图3是本发明实施例6中薄膜晶体管的结构示意图；
图4是本发明实施例6中薄膜晶体管的器件光响应特性图；
图5是本发明实施例7中薄膜晶体管的结构示意图；
图6是本发明实施例8中薄膜晶体管的结构示意图。
具体实施方式
下面结合实施例及附图对本发明作进一步详细的描述，但本发明的实施方 式不限于此。
实施例1
本实施例的一种氧化物半导体薄膜，所述氧化物半导体薄膜为：通过陶瓷靶磁控溅射方式在氧化铟锌半导体薄膜中掺入少量氧化镨作为光稳定剂，形成氧化镨掺杂氧化铟锌(Pr:IZO)半导体薄膜材料，其中，Pr:In:Zn＝0.2:5:1mol。Pr:IZO半导体薄膜的厚度为20nm，载流子浓度小于5×1019cm-3。
实施例2
本实施例的一种氧化物半导体薄膜，所述氧化物半导体薄膜为：通过陶瓷靶磁控溅射方式在氧化铟镓锌半导体薄膜中掺入少量氧化铽作为光稳定剂，形成氧化铽掺杂氧化铟镓锌(Tb:IGZO)半导体薄膜材料，其中，Tb:In:Ga:Zn＝0.1:1:1:0.5mol。Tb:IGZO半导体薄膜的厚度为40nm，载流子浓度小于5×1019cm-3。
实施例3
本实施例的一种氧化物半导体薄膜，所述氧化物半导体薄膜为：通过原子层沉积法在氧化铟锡锌半导体薄膜中掺入少量氧化铥作为光稳定剂，形成氧化铥掺杂氧化铟锡锌(Dy:ITZO)半导体薄膜材料，其中，Dy:In:Sn:Zn＝0.1:1:1:1mol。Dy:ITZO半导体薄膜的厚度为30nm，载流子浓度小于5×1019cm-3。
实施例4
本实施例的一种氧化物半导体薄膜，所述氧化物半导体薄膜为：通过原子层沉积法在氧化锌锡半导体薄膜中掺入少量氧化镱作为光稳定剂，形成氧化镱掺杂氧化锌锡(Yb:ZTO)半导体薄膜材料，其中，Yb:Sn:Zn＝0.2:1:1mol。Yb:ZTO半导体薄膜的厚度为30nm，载流子浓度小于5×1019cm-3。
实施例5
本实施例的一种薄膜晶体管，为刻蚀阻挡型结构，其结构示意图如图1所示，设置有：基板01、位于基板01之上的栅极02、位于基板01和栅极02之上的绝缘层03、覆盖在绝缘层03上表面并与栅极02对应的沟道层04、刻蚀阻挡层05、相互间隔并与沟道层04的两端电性相连的源极06-1和漏极06-2、以及钝化层07。
基板01为玻璃衬底，其上覆盖有缓冲层氧化硅。
栅极02的材料为金属磁控溅射方式制备的钼铝钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm。
绝缘层03为化学气相沉积方式制备的氮化硅(Si3N4)和氧化硅(SiO2)的叠层，厚度为250/50nm。
沟道层04的材料分别为实施例1和实施例2的氧化镨掺杂氧化铟锌(Pr:IZO)和氧化铽掺杂氧化铟镓锌(Tb:IGZO)两种材料。
刻蚀阻挡层05和钝化层07的材料为化学气相沉积方式制备的氧化硅(SiO2)，厚度都为300nm。
源极06-1以及漏极06-2的材料为金属钼铝钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm。
本实施例的薄膜晶体管可以为仅包括基板、栅极、绝缘层、沟道层、刻蚀阻挡层、源极和漏极、钝化层的封闭结构，也可以进一步包括像素定义层等，还可以与其它器件集成等。
其中薄膜的图案化采用光刻、并结合湿法或干法的刻蚀方式进行。
本实施例分别采用两种沟道层材料Pr:IZO和Tb:IGZO所制备的器件对应的光响应特性分别如图2中的(a)和(b)所示。由图2可以看出，通过掺入一定含量的氧化镨或氧化铥，器件随着不同波长的入射光照射及避光条件(Dark)下，阈值电压几乎不发生变化，表现出了优异的光稳定性。实验结果表明，本发明在基体氧化物材料中，掺入一定量的稀土氧化物能有效提高材料的光稳定性。
实施例6
本实施例的一种薄膜晶体管，为背沟道刻蚀型结构，其结构示意图如图3所示，设置有：基板01、位于基板01之上的栅极02、位于基板01和栅极02之上的绝缘层03、覆盖在绝缘层03上表面并与栅极02对应的沟道层04、相互间隔并与沟道层04的两端电性相连的源极05-1和漏极05-2、以及钝化层06。
基板01为柔性聚酰亚胺(PI)衬底，其上覆盖有缓冲层氧化硅。
栅极02的材料为金属磁控溅射方式制备的钼铝钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm。
绝缘层03为化学气相沉积方式制备的氮化硅(Si3N4)和氧化硅(SiO2)的叠层，厚度为250/50nm。
沟道层04的材料分别为实施例3和实施例4的氧化铥掺杂氧化铟锡锌(Dy:ITZO)和氧化镱掺杂氧化锌锡(Yb:ZTO)两种材料。
源极05-1以及漏极05-2的材料为金属钼铝钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm，其采用商用的磷酸基钼铝钼刻蚀液进行图案化。
钝化层06的材料为化学气相沉积方式制备的氧化硅(SiO2)，厚度为300nm。
本实施例的薄膜晶体管可以为仅包括基板、栅极、绝缘层、沟道层、源极和漏极、钝化层的封闭结构，也可以进一步包括像素定义层等，还可以与其它器件集成等。
其中薄膜的图案化采用光刻、并结合湿法或干法的刻蚀方式进行。
本实施例分别采用两种沟道层材料Dy:ITZO和Yb:ZTO所制备的器件对应的光响应特性分别如图4中的(a)和(b)所示。由图4结果可以看出，通过掺入一定含量的氧化铥或氧化镱，器件随着不同波长的入射光照射及避光条件(Dark)下，阈值电压几乎不发生变化，表现出了优异的光稳定性。实验结果表明，本发明在基体氧化物材料中，掺入一定量的稀土氧化物能有效提高材料的光稳定性。
实施例7
本实施例的一种薄膜晶体管，为背沟道刻蚀型结构，其结构示意图如图5所示，设置有：基板01、位于基板01之上的栅极02、位于基板01和栅极02之上的绝缘层03、覆盖在绝缘层03上表面并与栅极02对应的沟道层04、沟道保护层05、相互间隔并与沟道层的两端电性相连的源极06-1和漏极06-2、以及钝化层07。
基板01为柔性聚酰亚胺(PI)衬底，其上覆盖有缓冲层氧化硅。
栅极02的材料为金属磁控溅射方式制备的钼铝钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm。
绝缘层03为化学气相沉积方式制备的氮化硅(Si3N4)和氧化硅(SiO2)的叠层，厚度为250/50nm。
沟道层04的材料为实施例1中的氧化镨掺杂氧化铟锌(Pr:IZO)，厚度为20nm。
沟道保护层05的材料为磁控溅射方式制备的氧化锡掺杂氧化物或碳膜，厚度为10nm。
源极06-1以及漏极06-2的材料为金属钼铝钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm，其采用商用的磷酸基钼铝钼刻蚀液进行图案化。
钝化层07的材料为化学气相沉积方式制备的氧化硅(SiO2)，厚度为300nm。
本实施例的薄膜晶体管可以为仅包括基板、栅极、绝缘层、沟道层、沟道保护层、源极和漏极、钝化层的封闭结构，也可以进一步包括像素定义层等，还可以与其它器件集成等。
其中薄膜的图案化采用光刻、并结合湿法或干法的刻蚀方式进行。
所制备的器件对应的光响应特性结果表明：器件随着不同波长的入射光照射，阈值电压几乎不发生变化，表现出了优异的光稳定性。
实施例8
本实施例的一种薄膜晶体管，为自对准型结构，其结构示意图如图6所示，设置有：基板01、缓冲层02、沟道层03、位于沟道层03之上的绝缘层04以及栅极05、覆盖在沟道层03上表面的间隔层06、相互间隔并与沟道层的两端电性相连的源极07-1和漏极07-2。
基板01为硬质玻璃衬底。
缓冲层02为等离子增强化学气相沉积方式制备氧化硅。
沟道层03的材料为实施例2中的氧化铽掺杂氧化铟镓锌(Tb:IGZO)，厚度为40nm。
栅绝缘层04为氧化硅，厚度为300nm；栅极05为磁控溅射方式制备的钼铝钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm。
间隔层06为的氮化硅，厚度为200nm。
源极07-1以及漏极07-2的材料为金属钼铝钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm。
本实施例的薄膜晶体管可以为仅包括基板、沟道层、绝缘层、栅极、间隔层、源极和漏极的封闭结构，也可以进一步包括钝化层、以及像素定义层等，还可以与其它器件集成等。
其中薄膜的图案化采用光刻、并结合湿法或干法的刻蚀方式进行。
所制备的器件对应的光响应特性结果表明：器件随着不同波长的入射光照射，阈值电压几乎不发生变化，表现出了优异的光稳定性。
上述实施例为本发明较佳的实施方式，但本发明的实施方式并不受上述实施例的限制，其它的任何未背离本发明的精神实质与原理下所作的改变、修饰、替代、组合、简化，均应为等效的置换方式，都包含在本发明的保护范围之内。

Claims (9)

  1. 一种氧化物半导体薄膜，其特征在于所述氧化物半导体薄膜为：在金属氧化物MO半导体薄膜中掺入少量稀土氧化物RO作为光稳定剂，形成(MO)x(RO)y半导体材料，其中0<x<1，0.0001≤y≤0.2，x+y＝1。
  2. 根据权利要求1所述的一种氧化物半导体薄膜，其特征在于：所述金属氧化物MO中，M为In、Zn、Ga、Sn、Si、Al、Mg、Zr、Hf、Ta中的一种元素或两种以上的任意组合。
  3. 根据权利要求1所述的一种氧化物半导体薄膜，其特征在于：所述稀土氧化物RO材料包含：氧化镨、氧化铽、氧化镝、氧化镱中的一种或任意两种以上材料组合。
  4. 根据权利要求1所述的一种氧化物半导体薄膜，其特征在于：0.001≤y≤0.1。
  5. 根据权利要求4所述的一种氧化物半导体薄膜，其特征在于：0.001≤y≤0.05。
  6. 根据权利要求1所述的一种氧化物半导体薄膜，其特征在于：所述氧化物半导体薄膜的厚度为5～100nm。
  7. 根据权利要求1所述的一种氧化物半导体薄膜，其特征在于：所述氧化物半导体薄膜的载流子浓度小于5×1019cm-3。
  8. 根据权利要求1所述的一种氧化物半导体薄膜，其特征在于：所述氧化物半导体薄膜采用单靶溅射的方法制备，或者采用溶液法、原子层沉积或脉冲激光沉积中的任意一种方式制备。
  9. 一种薄膜晶体管，所述薄膜晶体管包括栅极、沟道层、位于栅极和沟道层之间的栅绝缘层、以及分别连接在沟道层两端的源极和漏极；其特征在于：所述沟道层材料为权利要求1～8任一项所述的氧化物半导体薄膜。
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