WO2022160149A1 - 薄膜晶体管及其制作方法、阵列基板和显示装置 - Google Patents

薄膜晶体管及其制作方法、阵列基板和显示装置 Download PDF

Info

Publication number
WO2022160149A1
WO2022160149A1 PCT/CN2021/074058 CN2021074058W WO2022160149A1 WO 2022160149 A1 WO2022160149 A1 WO 2022160149A1 CN 2021074058 W CN2021074058 W CN 2021074058W WO 2022160149 A1 WO2022160149 A1 WO 2022160149A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
atoms
thin film
protective layer
film transistor
Prior art date
Application number
PCT/CN2021/074058
Other languages
English (en)
French (fr)
Inventor
黄杰
贺家煜
宁策
李正亮
胡合合
刘凤娟
姚念琦
赵坤
周天民
王久石
田忠朋
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2022572769A priority Critical patent/JP2024504530A/ja
Priority to CN202180000087.0A priority patent/CN115152035A/zh
Priority to US17/611,156 priority patent/US20230091604A1/en
Priority to PCT/CN2021/074058 priority patent/WO2022160149A1/zh
Priority to EP21921769.2A priority patent/EP4141959A4/en
Publication of WO2022160149A1 publication Critical patent/WO2022160149A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a thin film transistor and a manufacturing method thereof, an array substrate and a display device.
  • a thin film transistor (Thin Film Transistor, TFT) is the core device of a display device, and each pixel in a display device relies on a thin film transistor for switching and driving.
  • thin film transistors mainly include oxide thin film transistors and amorphous silicon thin film transistors. Oxide thin film transistors have high mobility, can improve the resolution of display devices, and are more and more widely used in display devices.
  • the active layer of the oxide thin film transistor is respectively connected to the source and drain of the oxide thin film transistor.
  • the oxide thin film transistor works, carriers are generated in the active layer, and the source and drain connected to the active layer are turned on. , so that the oxide thin film transistor is turned on and starts to work.
  • the active layer of the oxide thin film transistor is an oxide semiconductor, but the oxide semiconductor is sensitive to light, the active layer is easily affected by light, and photogenerated carriers are generated when the active layer is irradiated by light. , so that the originally non-working oxide thin film transistor is turned on, which affects the stability of the oxide thin film transistor.
  • Embodiments of the present disclosure provide a thin film transistor and a method for fabricating the same, an array substrate and a display device, which improve the stability of the oxide thin film transistor.
  • the technical solution is as follows:
  • the present disclosure provides a thin film transistor including an active layer including at least two stacked metal oxide semiconductor layers, the at least two oxide semiconductor layers including a channel layer and a first protective layer, the metal element in the metal oxide semiconductor layer in the channel layer contains tin element, and contains at least one of indium element, gallium element and zinc element; the first protective layer contains The praseodymium element, the praseodymium element in the first protective layer is used for absorbing photo-generated electrons in the metal oxide semiconductor and reducing the photo-generated current caused by illumination.
  • the metal elements in the metal oxide semiconductor layer in the channel layer include tin element, indium element and gallium element; the number of indium atoms in the channel layer accounts for The ratio of the total number of indium atoms, gallium atoms and tin atoms in the channel layer is between 65% and 75%; the number of gallium atoms in the channel layer accounts for the indium atoms, The proportion of the total number of gallium atoms and tin atoms is between 24% and 30%; the proportion of the number of tin atoms in the channel layer to the total number of indium atoms, gallium atoms and tin atoms in the channel layer is Between 1% and 5%.
  • the content of praseodymium atoms in the first protective layer at different thickness positions of the first protective layer is not completely the same, and the first protective layer is far away from the channel
  • the content of praseodymium atoms on one side of the layer is smaller than the content of praseodymium atoms on the side of the first protective layer close to the channel layer.
  • the channel layer is doped with praseodymium element, and in the channel layer, a direction from close to the first protective layer to away from the first protective layer , the content of praseodymium atoms in the channel layer decreases monotonically.
  • the metal element in the first protective layer further includes at least one of tin element, indium element, gallium element, and zinc element, and praseodymium in the first protective layer
  • the number of atoms accounts for between 1% and 50% of the total number of atoms of metal elements in the first protective layer.
  • the metal element in the first protective layer further includes the indium element, the gallium element and the zinc element; the indium atoms in the first protective layer have The ratio of the number to the total number of indium atoms, gallium atoms and zinc atoms in the first protective layer is between 45% and 55%; the number of gallium atoms in the first protective layer accounts for the first protective layer.
  • the proportion of the total number of indium atoms, gallium atoms and zinc atoms in the first protective layer is between 25% and 35%; the number of zinc atoms in the first protective layer
  • the proportion of the total number of zinc atoms is between 15% and 25%.
  • the first protective layer is located on a surface of the channel layer that is away from the base substrate.
  • the at least two metal oxide semiconductor layers further include: a second protective layer, located on a surface of the channel layer close to the base substrate, and the second protective layer contains praseodymium element.
  • the second protective layer is an indium gallium zinc oxide layer containing praseodymium element, and the number of praseodymium atoms in the second protective layer accounts for the proportion of praseodymium atoms in the second protective layer.
  • the proportion of the total atomic number of metal elements is between 1% and 50%.
  • the at least two metal oxide semiconductor layers further include: a source and drain layer, located on a surface of the first protective layer away from the base substrate; a cover layer, located on the Between the first protective layer and the source and drain layers, the capping layer is a crystalline oxide layer that is not doped with praseodymium element.
  • the cover layer is a metal crystalline oxide layer
  • the metal in the metal crystalline oxide layer includes at least one of indium, gallium, zinc, and tin.
  • the thin film transistor further includes: a diffusion layer, the diffusion layer is located on a side of the first protective layer away from the base substrate, and the diffusion layer is a praseodymium metal layer or a praseodymium metal oxide layer.
  • the first protective layer is located on a surface of the channel layer close to the base substrate.
  • the thin film transistor further includes: a source electrode and a drain electrode, the source electrode and the drain electrode are located on the active layer, the source electrode and the drain electrode The electrodes respectively wrap the sidewalls of the active layer, the source electrodes and the drain electrodes are respectively connected to the sidewalls of the channel layer, and the source electrodes and the drain electrodes contain praseodymium element.
  • the present disclosure provides a method for fabricating a thin film transistor, the method comprising:
  • a base substrate is provided; at least two metal oxide semiconductor layers are sequentially formed on the base substrate to form an active layer of a thin film transistor, the at least two oxide semiconductor layers include a channel layer and a first protection layer layer, the metal element in the metal oxide semiconductor layer in the channel layer includes tin element, and includes at least one of indium element, gallium element, and zinc element; the first protective layer includes praseodymium element, the The praseodymium element in the first protective layer is used to absorb photo-generated electrons in the metal oxide semiconductor and reduce the photo-generated current caused by illumination.
  • sequentially forming at least two metal oxide semiconductor layers on the base substrate includes: forming an indium gallium tin oxide film layer on the base substrate; A diffusion film layer is formed on the side of the indium gallium tin oxide film layer away from the base substrate, and the diffusion film layer is a praseodymium metal film layer or a praseodymium metal oxide film layer; for the indium gallium tin oxide film layer and the diffusion film layer are annealed, so that the praseodymium element in the diffusion film layer is diffused into the indium gallium tin oxide film layer, so as to obtain the channel including the channels stacked in sequence on the base substrate layer and the active layer of the first protective layer; patterning the diffusion film layer to obtain a diffusion layer on the active layer, the diffusion layer is located on the first protective layer away from the On one side of the base substrate, the diffusion layer is a praseodymium metal layer or a praseodymium metal oxide layer.
  • the method further includes: forming a source-drain metal layer on the diffusion layer, the source-drain metal layer containing praseodymium element; patterning the source-drain metal layer processing to form the source and drain.
  • the present disclosure provides an array substrate, the array substrate includes a base substrate and a plurality of thin film transistors on the base substrate, where the thin film transistors are the thin film transistors described in any one of the foregoing aspects.
  • the array substrate further includes: a first insulating layer covering the first protective layer, the source electrode and the drain electrode; a first electrode layer including a plurality of first electrodes, the plurality of first electrodes are located on the side of the first insulating layer away from the base substrate; a second insulating layer covers the plurality of first electrodes; a second electrode layer, On the side of the second insulating layer away from the base substrate, the second electrode layer is electrically connected to the source or drain of the corresponding thin film transistor.
  • the present disclosure provides a display device including the array substrate according to any one of the above aspects.
  • the channel layer is the main channel region.
  • the first protective layer protects the channel layer.
  • the first protective layer When light shines on the channel layer from the side where the first protective layer is located, the light will first irradiate on the first protective layer, and the first protective layer will block the light and weaken the light.
  • the influence of light on the channel layer improves the stability of the thin film transistor.
  • the first protective layer When the first protective layer is irradiated by light, photogenerated carriers will also be generated. Since the first protective layer contains praseodymium element, the praseodymium element will introduce an intermediate energy level state in the internal band gap of the first protective layer, also known as trap state.
  • the photo-generated carriers When the first protective layer is irradiated with light to generate photo-generated carriers, the photo-generated carriers will be captured by trap states inside the first protective layer, so that the photo-generated carriers are digested inside the first protective layer and will not affect the actual channel. area function.
  • the channel layer contains tin element, which can improve the mobility of the thin film transistor, thereby improving the reaction speed of the thin film transistor.
  • FIG. 1 is a schematic cross-sectional structure diagram of a thin film transistor provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional structure diagram of a thin film transistor provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional structure diagram of a thin film transistor provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic cross-sectional structure diagram of a thin film transistor provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic cross-sectional structure diagram of a thin film transistor provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic cross-sectional structure diagram of a thin film transistor provided by an embodiment of the present disclosure.
  • FIG. 7 is a flowchart of a method for fabricating a thin film transistor provided by an embodiment of the present disclosure
  • FIG. 8 is a flowchart of a method for fabricating a thin film transistor provided by an embodiment of the present disclosure
  • FIG. 9 is a process diagram of a method for fabricating a thin film transistor provided by a disclosed embodiment
  • FIG. 10 is a process diagram of a method for fabricating a thin film transistor provided by a disclosed embodiment
  • FIG. 11 is a process diagram of a method for fabricating a thin film transistor provided by a disclosed embodiment
  • FIG. 12 is a process diagram of a method for fabricating a thin film transistor provided by a disclosed embodiment
  • FIG. 13 is a process diagram of a method for fabricating a thin film transistor provided by a disclosed embodiment
  • FIG. 14 is a flowchart of a method for fabricating a thin film transistor provided by an embodiment of the present disclosure
  • FIG. 15 is a process diagram of a method for fabricating a thin film transistor provided by an embodiment of the present disclosure.
  • 16 is a process diagram of a method for fabricating a thin film transistor provided by an embodiment of the present disclosure
  • 17 is a process diagram of a method for fabricating a thin film transistor provided by an embodiment of the present disclosure.
  • FIG. 18 is a process diagram of a method for fabricating a thin film transistor provided by an embodiment of the present disclosure
  • FIG. 19 is a process diagram of a method for fabricating a thin film transistor provided by an embodiment of the present disclosure.
  • FIG. 20 is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic cross-sectional structure diagram of a thin film transistor provided by an embodiment of the present disclosure.
  • the active layer 10 of the thin film transistor includes at least two stacked metal oxide semiconductor layers, and the at least two oxide semiconductor layers at least include a channel layer 101 and a first protective layer 102, wherein the channel layer 101
  • the metal in the metal oxide semiconductor layer contains tin (Sn) element, and contains at least one of indium (In) element, gallium (Ga) element, and zinc (Zn) element.
  • the first protective layer 102 contains praseodymium element, and the praseodymium element in the first protective layer 102 is used to absorb photo-generated electrons in the metal oxide semiconductor, thereby reducing the photo-generated current caused by illumination.
  • the thin film transistor has a top gate, bottom gate or double gate structure.
  • the top gate structure means that the gate is located on the side of the active layer away from the base substrate
  • the bottom gate structure means that the gate is located on the side of the active layer close to the base substrate
  • the double gate structure means that the thin film transistor includes Two gates located on different layers, separated by a gate insulating layer, both located on the side of the active layer away from the base substrate, or both located on the active layer The side of the layer close to the base substrate.
  • the channel layer 101 is the actual channel region.
  • the first protective layer 102 protects the channel layer 101.
  • the light When the light irradiates the channel layer 101 from the side where the first protective layer 102 is located, the light will first irradiate on the first protective layer 102, and the first protective layer 102 The light is shielded, the influence of the light on the channel layer 101 is weakened, and the stability of the thin film transistor is improved.
  • the first protective layer 102 is irradiated by light, photogenerated carriers will also be generated.
  • the praseodymium element will introduce an intermediate energy level state into the internal band gap of the first protective layer 102 , also called trap state.
  • the photo-generated carriers will be captured by trap states inside the first protective layer 102, so that the photo-generated carriers are digested inside the first protective layer 102 without affecting the function of the actual channel region.
  • the channel layer 101 contains tin element, which can improve the mobility of the thin film transistor, thereby improving the reaction speed of the thin film transistor.
  • the thin film transistor Since the active layer of the thin film transistor provided by the embodiment of the present disclosure is made of oxide, the thin film transistor is called an oxide thin film transistor.
  • the metal elements in the metal oxide semiconductor layer in the channel layer 101 include tin element, indium element and gallium element.
  • the ratio of the number of indium atoms in the channel layer 101 to the total number of indium atoms, gallium atoms and tin atoms in the channel layer 101 is between 65% and 75%.
  • the ratio of the number of gallium atoms in the channel layer 101 to the total number of indium atoms, gallium atoms and tin atoms in the channel layer 101 is between 24% and 30%.
  • the ratio of the number of tin atoms in the channel layer 101 to the total number of indium atoms, gallium atoms and tin atoms in the channel layer 101 is between 1% and 5%.
  • the number ratio of indium atoms, gallium atoms, and tin atoms in the channel layer 101 is between 90:20:1 and 20:10:1.
  • the ratio is determined according to the ratio of the above-mentioned indium atoms, gallium atoms, and tin atoms.
  • the ratio of each element in the channel layer 101 is different, and the mobility of the channel layer 101 is different.
  • the mobility of the thin film transistor can reach between 30 cm 2 /(V ⁇ S) and 50 cm 2 /V ⁇ s, and further Improve the mobility of thin film transistors.
  • the channel layer 101 configured with the above atomic number ratio is in a crystalline state.
  • the number ratio of indium atoms, gallium atoms, and tin atoms in the channel layer 101 is 57:21:2. In other examples, in the channel layer 101 , the number ratio of indium atoms, gallium atoms, and tin atoms is 29:11:1.
  • the number proportion of each atom in the channel layer 101 fluctuates, and the number proportion of each atom fluctuates within a range of ⁇ 10%.
  • the number ratio of indium atoms, gallium atoms, and tin atoms in the channel layer 101 is between 27.55:11:1 and 30.45:11:1.
  • the number ratio of indium atoms, gallium atoms, and tin atoms is 30:11:1.
  • the thickness of the channel layer 101 is less than 30 nanometers (nm). For example, 25 nanometers.
  • the thickness of the first protective layer 102 is less than 20 nanometers (nm). For example, 20 nanometers.
  • the metal element of the first protective layer 102 further includes at least one of tin element, indium element, gallium element, and zinc element.
  • the first protective layer 102 is an indium gallium zinc oxide (IGZO) layer doped with praseodymium element.
  • IGZO indium gallium zinc oxide
  • Indium gallium zinc oxide is easy to obtain, and doping praseodymium element in indium gallium zinc oxide can enable the first protective layer 102 to protect the channel layer 101 when light is irradiated.
  • the ratio of the number of indium atoms in the first protective layer 102 to the total number of indium atoms, gallium atoms, and zinc atoms in the first protective layer 102 is between 45% and 55%. time; the number of gallium atoms in the first protective layer 102 accounts for 25% to 35% of the total number of indium atoms, gallium atoms, and zinc atoms in the first protective layer 102; the zinc in the first protective layer 102
  • the ratio of the number of atoms to the total number of indium atoms, gallium atoms and zinc atoms in the first protective layer 102 is between 15% and 25%.
  • the number ratio of indium atoms, gallium atoms, and zinc atoms in the first protective layer 102 is between 6:3:1 and 3:3:1.
  • the ratio is determined according to the ratio of the above-mentioned indium atoms, gallium atoms, and zinc atoms.
  • the number ratio of indium atoms, gallium atoms, and zinc atoms of the first protective layer 102 is 46:29:21. In some other examples, in the first protective layer 102 , the number ratio of indium atoms, gallium atoms, and zinc atoms is 23:14:10.
  • the number of praseodymium atoms in the first protective layer 102 accounts for between 1% and 50% of the total number of metal element atoms in the first protective layer 102 .
  • Praseodymium is readily available and inexpensive, reducing production costs. After the praseodymium element is doped into the indium gallium zinc oxide, it will have an intermediate energy level state inside the indium gallium zinc oxide, which will accelerate the recombination of photogenerated carriers. This intermediate energy level state is called trivalent praseodymium. (Pr3 + ) trap state. The trap state can provide an electronic recombination ladder.
  • the photo-generated carriers When the indium gallium zinc oxide is irradiated by light to generate photo-generated carriers (that is, photo-generated charges), the photo-generated carriers will be quickly captured by the trivalent praseodymium trap state, and the photo-generated current
  • the recombination of electrons and electronic recombination ladders reduces the lifetime of photogenerated carriers, reduces the concentration of photogenerated carriers, and makes the photogenerated carriers internally digested, which will not affect the channel layer, thereby improving the light stability of thin-film transistors. mobility.
  • the content ratio of the doped praseodymium element is controlled to ensure that the first protective layer 102 achieves the best protective effect, protects the channel layer 101, and further improves the light stability of the thin film transistor.
  • the number of praseodymium atoms in the first protective layer 102 accounts for 5% of the total number of indium atoms, gallium atoms and zinc atoms in the first protective layer 102 .
  • the number ratio of indium atoms, gallium atoms, zinc atoms, and praseodymium atoms of the first protective layer 102 is 46:29:21:4. In other examples, in the first protective layer 102, the number ratio of indium atoms, gallium atoms, zinc atoms and praseodymium atoms is 23:14:10:2.
  • the number proportion of each atom in the first protective layer 102 also fluctuates, and the number proportion of each atom also fluctuates within a range of ⁇ 10%.
  • the content ratio of praseodymium element refers to the ratio of the number of praseodymium atoms to the atomic number of all metal elements in the first protective layer 102 .
  • the content of praseodymium atoms in the first protective layer 102 at different thickness positions of the first protective layer 102 is not completely the same, and the content of praseodymium atoms on the side of the first protective layer 102 away from the channel layer 101
  • the content of praseodymium atoms on the side of the first protective layer 102 close to the channel layer 101 is smaller than that of the first protective layer 102 .
  • the first protective layer 102 is a praseodymium oxide (Pr-Oxide) layer, eg, a praseodymium trioxide (Pr 2 O 3 ) layer.
  • Pr-Oxide praseodymium oxide
  • Pr 2 O 3 praseodymium trioxide
  • the channel layer 101 contains praseodymium element, and the percentage of the atomic number of praseodymium element in the channel layer 101 to the atomic number of all metal elements in the channel layer 101 is smaller than that of the praseodymium element in the first protective layer 102
  • the atomic number is a percentage of the atomic number of all metal elements in the first protective layer 102 .
  • the praseodymium element in the first protective layer 102 may be doped into the channel layer 101 during the annealing process, so that the channel layer 101 also contains praseodymium element.
  • the praseodymium element is doped into the channel layer 101 from the first protective layer 102 , the content ratio of the praseodymium element in the channel layer 101 is smaller than the content ratio of the praseodymium element in the first protective layer 102 .
  • the content ratio of the praseodymium element contained in the channel layer 101 decreases sequentially.
  • the number of praseodymium atoms in the channel layer 101 accounts for 2% of the total number of indium atoms, gallium atoms and tin atoms in the channel layer 101 .
  • the active layer 10 is located on the base substrate 30 .
  • the first protective layer 102 is located on the surface of the channel layer 101 away from the base substrate 30 .
  • the first protective layer 102 is disposed on the surface of the channel layer 101 away from the base substrate 30 , so that the first protective layer 102 shields the ambient light irradiated to the channel layer 101 from the side away from the surface of the base substrate 30 , reducing the influence of light on the channel layer 101 .
  • the praseodymium element in the first protective layer 102 diffuses into the channel layer 101, the praseodymium element in the side of the channel layer 101 close to the base substrate 30 is less, so as to avoid reducing the stability of the thin film transistor.
  • the thin film transistor further includes a source drain (Source Drain, SD) layer 50 .
  • the source-drain layer 50 includes a source electrode 501 and a drain electrode 502, the source electrode 501 and the drain electrode 502 are located on the active layer 10, the source electrode 501 and the drain electrode 502 respectively wrap the sidewall of the active layer 10, and the source electrode 501 and the drain electrode 502
  • the drain electrodes 502 are respectively connected to the sidewalls of the channel layer 101 .
  • the source electrode 501 and the drain electrode 502 in the source and drain layer 50 need to be connected to the channel layer 101 respectively.
  • the source electrode 501 and the drain electrode 502 are conducted through the channel layer 101 .
  • the channel layer 101 is located under the first protective layer 102 , the source electrode 501 and the drain electrode 502 cannot be connected to the channel layer 101 from above the channel layer 101 , and the source electrode 501 and the drain electrode 502 are respectively
  • the sidewalls of the wrapped active layer 10 that is, the source electrode 501 and the drain electrode 502 are connected to the channel layer 101 through the sidewalls of the channel layer 101 .
  • the source and drain layers 50 are metal layers or indium tin oxide (ITO) layers to ensure the conductivity of the source and drain layers 50 .
  • ITO indium tin oxide
  • the thin film transistor further includes a gate (Gate) 60 and a gate insulating (Gate Insulator, GI) layer 70 .
  • the gate 60 is located on the side of the active layer 10 close to the base substrate 30 .
  • the gate insulating layer 70 is located between the active layer 10 and the gate electrode 60 to separate the active layer 10 and the gate electrode 60 .
  • the gate 60 is made of metal, such as copper, etc.; or the gate 60 is made of a transparent conductive material, such as indium tin oxide.
  • the gate 60 and the first protective layer 102 are located on two sides of the channel layer 101 respectively, and the gate 60 and the first protective layer 102 can shield the channel layer 101 from light from both sides.
  • the gate insulating layer 70 is a silicon oxide, a silicon nitride layer or an epoxy resin.
  • the thin film transistor further includes a first insulating layer (PVX) 80 .
  • the first insulating layer 80 covers the first protective layer 102 and the source and drain layers 50 .
  • the first insulating layer 80 is arranged to separate the source-drain layer 50 from the film layer above the source-drain layer 50 to avoid affecting the transmission of electrical signals of the source-drain layer 50 .
  • the first insulating layer 80 is a silicon oxide layer.
  • the first insulating layer 80 is generally a silicon oxide layer
  • the first insulating layer 80 contains silicon elements
  • the channel layer 101 is an indium gallium tin oxide layer, and there is no silicon element in the channel layer 101 If the channel layer 101 is in direct contact with the first insulating layer 80, an interface state will be generated at the contact surface between the channel layer 101 and the first insulating layer 80, which affects the mobility of the thin film transistor.
  • the first insulating layer 80 and the channel layer 101 are separated by the first protective layer 102 that does not contain silicon-based elements, so that the influence of the interface state on the mobility of the thin film transistor can be avoided.
  • the thin film transistor shown in FIG. 1 is a thin film transistor with a bottom gate structure. In other implementation manners, the thin film transistor may also be a thin film transistor with a top gate structure. For a specific structure, see FIG. 2 .
  • FIG. 2 is a schematic cross-sectional structure diagram of a thin film transistor provided by an embodiment of the present disclosure.
  • the gate insulating layer 70 is located on the side of the first protective layer 102 away from the base substrate 30
  • the gate 60 is located on the side of the gate insulating layer 70 away from the base substrate 30
  • the gate 60 is located on the active layer 10
  • a thin film transistor with a top-gate structure is a thin film transistor with a top-gate structure.
  • the first protective layer 102 separates the gate insulating layer 70 from the channel layer 101 to prevent the channel layer 101 from directly contacting the gate insulating layer 70.
  • An interface state is generated between the layer 70 and the channel layer 101, which affects the mobility of the thin film transistor.
  • the thin film transistor further includes an interlayer dielectric (ILD) layer 120, the interlayer dielectric layer 120 wraps the gate 60 and the active layer 10, and the source and drain layers 50 are located on the interlayer dielectric layer 120, and also That is, the gate electrode 60 is separated from the source-drain layer 50 by the interlayer dielectric layer 120 .
  • ILD interlayer dielectric
  • the interlayer dielectric layer 120 is a silicon oxide layer, a silicon nitride layer or an epoxy resin layer.
  • the thin film transistor further includes a shield layer 130 and a buffer layer 140. Both the shield layer 130 and the buffer layer 140 are located on the base substrate, and the shield layer 130 is opposite to the channel layer 101.
  • the buffer layer 140 between the light shielding layer 130 and the channel layer 101 .
  • arranging the light shielding layer 130 can shield the light irradiated to the channel layer 101 from the light shielding layer 130 side, and reduce the influence of the light on the channel layer 101 .
  • the channel layer 101 is arranged on the buffer layer 140 to reduce the influence of impurities on the base substrate 30 on the channel layer 101 .
  • FIG. 3 is a schematic cross-sectional structure diagram of a thin film transistor provided by an embodiment of the present disclosure.
  • the at least two metal oxide semiconductor layers further include a second protective layer 103 .
  • the second protective layer 103 is located on the surface of the channel layer 101 close to the base substrate 30 , and the second protective layer 103 contains praseodymium element.
  • both sides of the channel layer 101 are irradiated by light, for example, ambient light, light from a light-emitting unit or light from a backlight.
  • a first protective layer is arranged on both surfaces of the channel layer 101
  • the second protective layer 103 is also doped with praseodymium element, and the second protective layer 103 has the same function as the first protective layer 102 .
  • both the first protective layer 102 and the second protective layer 103 can protect the channel layer 101 and improve the stability of the thin film transistor.
  • the first protective layer 102 and the second protective layer 103 are respectively disposed on the opposite two surfaces of the channel layer 101 , the first protective layer 102 separates the channel layer 101 and the first insulating layer 80 . Separated, the second protective layer 103 separates the channel layer 101 from the gate insulating layer 70 , which can simultaneously avoid the formation of interface states on the two surfaces of the channel layer 101 and avoid affecting the stability of the thin film transistor.
  • the second protective layer 103 is an indium gallium zinc oxide layer containing praseodymium element.
  • the number of praseodymium atoms in the second protective layer 103 is between 1% and 50% of the total number of indium atoms, gallium atoms and zinc atoms in the second protective layer 103 .
  • the proportions of indium atoms, gallium atoms, and zinc atoms in the second protective layer 103 are the same as the proportions of indium atoms, gallium atoms, and zinc atoms in the first protective layer 102 .
  • the number ratio of indium atoms, gallium atoms, and zinc atoms of the second protective layer 103 is between 6:3:1 and 3:3:1.
  • the number ratio of indium atoms, gallium atoms, and zinc atoms in the second protective layer 103 is 4:3:2.
  • the number of praseodymium atoms in the second protective layer 103 accounts for 20% of the total number of indium atoms, gallium atoms and zinc atoms in the second protective layer 103 .
  • the number proportion of each atom in the second protective layer 103 also fluctuates, and the number proportion of each atom also fluctuates within a range of ⁇ 10%.
  • the second protective layer 103 is a praseodymium oxide layer, eg, a praseodymium trioxide layer.
  • FIG. 4 is a schematic cross-sectional structure diagram of a thin film transistor provided by an embodiment of the present disclosure.
  • the at least two metal oxide semiconductor layers further include a capping layer 104 .
  • the capping layer 104 is located on the side of the first protective layer 102 away from the base substrate 30 , and the capping layer 104 is a crystalline oxide layer that is not doped with praseodymium element.
  • the capping layer 104 is located between the source and drain layers 50 and the first protective layer 102 .
  • a cover layer 104 is arranged on the first protective layer 102, and the cover layer 104 can improve the stability of the thin film transistor under high temperature and high voltage.
  • the crystalline oxide layer can reduce the influence on the active layer 10 during the etching, and improve the stability of the thin film transistor.
  • the capping layer 104 is a metal crystalline oxide layer, and the metal in the metal crystalline oxide layer includes at least one of indium, gallium, zinc and tin.
  • the capping layer 104 is an indium gallium zinc oxide (IGZO) layer, an indium gallium oxide (IGZ) layer, an indium gallium zinc tin oxide (IGZTO) layer, an indium tin oxide (ITO) layer, and an indium zinc oxide (IZO) layer any of the .
  • IGZO indium gallium zinc oxide
  • IGZTO indium gallium zinc tin oxide
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • Indium gallium zinc oxide, indium gallium oxide, indium gallium zinc tin oxide, indium tin oxide and indium zinc oxide are commonly used materials for making thin film transistors, which are easy to obtain and reduce the cost of fabrication.
  • FIG. 5 is a schematic cross-sectional structure diagram of a thin film transistor provided by an embodiment of the present disclosure.
  • the thin film transistor further includes a diffusion layer 40 .
  • the diffusion layer 40 is located on the side of the first protective layer 102 away from the base substrate 30 , and the diffusion layer 40 is a praseodymium metal layer or a praseodymium metal oxide layer.
  • the diffusion layer 40 is a product of fabricating the first protective layer 102 , the diffusion layer 40 is arranged on the untreated carrier transport film layer, and then the untreated carrier transport film layer is disposed on the untreated carrier transport film layer.
  • the praseodymium element in the diffusion layer 40 will be doped into the untreated active layer during the annealing treatment, so that the untreated carrier transport film layer is close to the diffusion layer 40.
  • a first protective layer 102 containing praseodymium element is formed on one side, and a channel layer 101 serving as a channel region is formed on the side away from the diffusion layer 40 .
  • the diffusion layer 40 wraps the sidewall of the active layer 10 , and the diffusion layer 40 can protect the active layer 10 when the source and drain layers 50 are etched.
  • the diffusion layer 40 includes two parts that are disconnected from each other.
  • the diffusion layer 40 is located between the source and drain layers 50 and the active layer 10. Since the two parts of the diffusion layer 40 are disconnected from each other, diffusion is avoided.
  • Layer 40 connects source 501 and drain 502 in source-drain layer 50 .
  • the diffusion layer 40 is a praseodymium metal layer or a praseodymium metal oxide layer.
  • the diffusion layer 40 may also be an integral structure, that is, cover the first protective layer 102 , in this case, the diffusion layer is a praseodymium metal oxide layer.
  • the diffusion layer 40 may also be removed on the basis of FIG. 5 , but praseodymium element is included in the source electrode 501 and the drain electrode 502 .
  • the praseodymium element in the source electrode 501 and the drain electrode 502 is caused to diffuse into the active layer 10 .
  • the source and drain layers are a praseodymium metal doped metal compound, or a praseodymium metal thin film stacked with other metal film layers, such as a praseodymium metal layer and a copper metal layer stacked together.
  • the diffusion layer 40 may not wrap the sidewall of the active layer 10 , the diffusion layer 40 is stacked with the active layer 10 , and the diffusion layer 40 is located at a position where the active layer 10 is far from the base substrate 30 . one side.
  • the source electrode 501 and the drain electrode 502 wrap the sidewalls of the active layer 10 and the diffusion layer 40, respectively.
  • FIG. 6 is a schematic cross-sectional structure diagram of a thin film transistor provided by an embodiment of the present disclosure. The difference from the structure shown in FIG. 1 is that in FIG. 6 , the first protective layer 102 is located on the surface of the channel layer 101 close to the base substrate 30 .
  • FIG. 7 is a flowchart of a method for fabricating a thin film transistor according to an embodiment of the present disclosure. Referring to Figure 7, the method includes:
  • step S11 a base substrate is provided.
  • step S12 at least two metal oxide semiconductor layers are sequentially formed on the base substrate to form the active layer of the thin film transistor, the at least two oxide semiconductor layers include a channel layer and a first protective layer, the channel layer
  • the metal in the metal oxide semiconductor layer contains tin element, and contains at least one of indium element, gallium element, and zinc element;
  • the first protective layer contains praseodymium element, and the praseodymium element in the first protective layer is used to absorb metal Photogenerated electrons in oxide semiconductors reduce the photogenerated current caused by illumination.
  • FIG. 8 is a flowchart of a method for fabricating a thin film transistor provided by an embodiment of the present disclosure. Referring to Figure 8, the method includes:
  • step S21 a base substrate is provided.
  • FIGS. 9 to 13 are process diagrams of a method for fabricating a thin film transistor provided by the disclosed embodiments. The manufacturing process of the base substrate will be described below with reference to FIGS. 9 to 13 .
  • a base substrate 30 is provided.
  • step S22 a gate is formed on the base substrate.
  • the gate electrode 60 is fabricated on the base substrate 30 .
  • the gate 60 is a metal electrode.
  • a gate film layer can be fabricated on the base substrate 30 by a deposition method, and then the gate film layer is patterned to obtain the gate electrode 60 .
  • step S23 a gate insulating layer is formed on the gate.
  • a gate insulating layer 70 is formed on the gate electrode 60 , and the gate insulating layer 70 wraps the gate electrode 60 .
  • the gate insulating layer 70 is a silicon oxide layer.
  • the gate insulating layer 70 may be fabricated on the gate electrode 60 by a deposition method.
  • step S24 an active layer is formed on the gate insulating layer.
  • an active layer 10 is formed on the gate insulating layer 70 .
  • the active layer 10 includes a channel layer 101 and a first protective layer 102, the channel layer 101 is made of indium gallium tin oxide, and the first protective layer 102 is indium gallium zinc oxide containing praseodymium element material made.
  • an indium gallium tin oxide film layer may be sputtered on the gate insulating layer 70 first, and then an indium gallium tin oxide film layer containing praseodymium element may be formed on the indium gallium tin oxide film layer. . Then, the indium gallium tin oxide film layer and the indium gallium zinc oxide film layer containing praseodymium element are patterned to obtain the channel layer 101 and the first protective layer 102 as shown in FIG. 12 .
  • step S25 source and drain layers are formed on the active layer.
  • a source and drain layer 50 is fabricated on the active layer 10.
  • the source and drain layers 50 include a source electrode 501 and a drain electrode 502.
  • the source electrode 501 and the drain electrode 502 are located on the active layer 10.
  • the source electrode 501 and the drain electrode The electrodes 502 wrap the sidewalls of the active layer 10 respectively, and the source electrodes 501 and the drain electrodes 502 are respectively connected to the sidewalls of the channel layer 101 .
  • the source and drain layers 50 are metal layers, and a metal film layer can be formed on the active layer 10 by sputtering, and then the metal film layer is patterned to obtain the result as shown in FIG. 13 .
  • Source 501 and drain 502 are shown.
  • step S26 a first insulating layer is formed on the source and drain layers.
  • a first insulating layer 80 is sequentially formed on the source and drain layers 50 to obtain the base substrate as shown in FIG. 1 .
  • FIG. 14 is a flowchart of a method for fabricating a thin film transistor provided by an embodiment of the present disclosure. Referring to Figure 14, the method includes:
  • step S31 a base substrate is provided.
  • step S32 a gate is formed on the base substrate.
  • step S33 a gate insulating layer is formed on the gate.
  • step S34 an indium gallium tin oxide film layer is formed on the gate insulating layer.
  • FIGS. 15 to 19 are process diagrams of a method for fabricating a thin film transistor provided by an embodiment of the present disclosure. The fabrication process of the thin film transistor will be described below with reference to FIGS. 15 to 19 .
  • an indium gallium tin oxide film layer 170 is formed on the gate insulating layer 70 .
  • a diffusion film layer is formed on the side of the indium gallium tin oxide film layer away from the base substrate.
  • the diffusion film layer is a praseodymium metal film layer or a praseodymium metal oxide film layer.
  • a diffusion film layer 180 is formed on the indium gallium tin oxide film layer 170 .
  • step S36 annealing is performed on the indium gallium tin oxide film layer and the diffusion film layer, so that the praseodymium element in the diffusion film layer is diffused into the indium gallium tin oxide film layer, to obtain an The channel layer and the active layer of the first protective layer.
  • the indium gallium tin oxide film layer 170 and the diffusion film layer 180 are annealed at the same time, so that the praseodymium element in the diffusion film layer 180 is diffused into the indium gallium tin oxide film layer 170, and the indium gallium tin oxide film layer 170 is An active layer including the channel layer 101 and the first protective layer 102 is formed in the film layer 170 .
  • step S37 patterning is performed on the diffusion film layer to obtain a diffusion layer on the active layer.
  • the diffusion film layer is patterned to obtain the diffusion layer 40 on the active layer.
  • the diffusion layer 40 is located on the side of the first protective layer 102 away from the base substrate 30 , the diffusion layer 40 wraps the sidewall of the active layer 10 , and the diffusion layer 40 is a praseodymium metal layer or a praseodymium metal oxide layer.
  • the indium gallium tin oxide film layer 170 and the diffusion film layer 180 may be etched at the same time, which simplifies the manufacturing process. That is, a diffusion film layer 180 is formed directly on the indium gallium tin oxide film layer 170, and then the indium gallium tin oxide film layer 170 and the diffusion film layer 180 are patterned at the same time to form the active layer 10 and the diffusion film layer 180. Layer 40. At this time, the diffusion layer 40 does not wrap the sidewall of the active layer 10 , the diffusion layer 40 is stacked with the active layer 10 , and the diffusion layer 40 is located on the side of the active layer 10 away from the base substrate 30 .
  • step S38 a source-drain metal layer is formed on the diffusion film layer.
  • step S39 the source and drain metal layers are patterned to form source and drain electrodes.
  • the source/drain metal layer is patterned to obtain the source/drain layer 50 shown in FIG. 19 .
  • step S40 a first insulating layer is formed on the source and drain layers.
  • a first insulating layer 80 is formed on the source and drain layers 50 to obtain the base substrate as shown in FIG. 5 .
  • steps S35 to S37 may also be omitted, and a source-drain metal layer may be directly formed on the indium gallium tin oxide film layer, the source-drain metal layer contains praseodymium element, and then the source-drain metal layer The layer is patterned, the praseodymium element in the source and drain metal layers diffuses into the indium gallium tin oxide film layer, and an active layer including a channel layer and a first protective layer is formed in the indium gallium tin oxide film layer.
  • An embodiment of the present disclosure further provides an array substrate, the array substrate includes a stacked substrate 30 and a plurality of thin film transistors, and the thin film transistors are the thin film transistors shown in any one of FIGS. 1 to 7 .
  • FIG. 20 is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the present disclosure.
  • the array substrate further includes: a first electrode layer 90 , a second insulating layer 100 and a second electrode layer 110 .
  • the first electrode layer 90 includes a plurality of first electrodes, and the plurality of first electrodes are located on the side of the first insulating layer 80 away from the base substrate 30 .
  • the second insulating layer 100 covers the plurality of first electrodes.
  • the second electrode layer 110 is located on the side of the second insulating layer 100 away from the base substrate 30 , and the second electrode layer 110 is electrically connected to the source electrode 501 or the drain electrode 502 of the corresponding thin film transistor.
  • the array substrate provided by the embodiment of the present disclosure can be used in a liquid crystal display (Liquid Crystal Display, LCD) device.
  • one of the first electrode layer 90 and the second electrode layer 110 is a pixel electrode layer, and the other is a common electrode layer.
  • the second insulating layer 100 separates the first electrode layer 90 from the second electrode layer 110 .
  • the first electrode layer 90 and the second electrode layer 110 are indium tin oxide layers to ensure the conductivity and transparency of the first electrode layer 90 and the second electrode layer 110 .
  • the array substrate further includes a planarization layer 150 located between the first insulating layer 80 and the first electrode layer 90 .
  • the planarization layer 150 can make the surface on which the first insulating layer 80 is arranged more flat, which facilitates the fabrication of the first electrode layer 90 .
  • the planarization layer 150 is a resin (Resin) layer.
  • the first insulating layer 80 , the planarization layer 150 and the second insulating layer 100 have via holes 160 , and the second electrode layer 110 communicates with the source electrode 501 or the drain electrode in the source and drain layers 50 through the via hole 160 502 Electrical connection.
  • An embodiment of the present disclosure also provides a display device, which includes the array substrate shown in FIG. 20 .
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.

Abstract

本公开是关于一种薄膜晶体管及其制作方法、阵列基板和显示装置，属于显示技术领域。薄膜晶体管的有源层包括层叠的至少两层金属氧化物半导体层，至少两层氧化物半导体层包括沟道层和第一保护层，沟道层中的金属氧化物半导体层中的金属包含锡元素，以及包含铟元素、镓元素、锌元素中的至少一种。第一保护层包含镨元素，第一保护层中的镨元素用于吸收金属氧化物半导体中的光生电子，降低光照引起的光生电流。该薄膜晶体管的稳定性高且迁移率高。

Description

薄膜晶体管及其制作方法、阵列基板和显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种薄膜晶体管及其制作方法、阵列基板和显示装置。
背景技术
薄膜晶体管(Thin Film Transistor，TFT)是显示装置的核心器件，显示装置中的每一个像素均依赖薄膜晶体管进行开关和驱动。根据薄膜晶体管的有源层的半导体材料的不同，薄膜晶体管主要包括氧化物薄膜晶体管和非晶硅薄膜晶体管。氧化物薄膜晶体管具有较高的迁移率，可以提高显示装置的分辨率，在显示装置中的应用越来越广泛。
氧化物薄膜晶体管的有源层分别连接氧化物薄膜晶体管的源极和漏极，在氧化物薄膜晶体管工作时，有源层中产生载流子，有源层连接的源极和漏极导通，使得该氧化物薄膜晶体管导通开始工作。
相关技术中，氧化物薄膜晶体管的有源层为氧化物半导体，但氧化物半导体对光线比较敏感，有源层容易受到光的影响，有源层受到光线照射的情况下会产生光生载流子，使得原本不工作的氧化物薄膜晶体管导通，影响氧化物薄膜晶体管的稳定性。
发明内容
本公开实施例提供了一种薄膜晶体管及其制作方法、阵列基板和显示装置，提高氧化物薄膜晶体管的稳定性。所述技术方案如下：
一方面，本公开提供了一种薄膜晶体管，所述薄膜晶体管包括有源层，所述有源层包括层叠的至少两层金属氧化物半导体层，所述至少两层氧化物半导体层包括沟道层和第一保护层，所述沟道层中的金属氧化物半导体层中的金属元素包含锡元素，以及包含铟元素、镓元素、锌元素中的至少一种；所述第一保护层包含镨元素，所述第一保护层中的镨元素用于吸收金属氧化物半导体中的光生电子，降低光照引起的光生电流。
在本公开实施例的一种实现方式中，所述沟道层中的金属氧化物半导体层中的金属元素包含锡元素、铟元素和镓元素；所述沟道层中的铟原子的数量占所述沟道层中的铟原子、镓原子、锡原子总数量的比例在65％至75％之间；所述沟道层中的镓原子的数量占所述沟道层中的铟原子、镓原子、锡原子总数量的比例在24％至30％之间；所述沟道层中的锡原子的数量占所述沟道层中的铟原子、镓原子、锡原子总数量的比例在1％至5％之间。
在本公开实施例的一种实现方式中，所述第一保护层中的镨原子在所述第一保护层的不同厚度位置的含量不完全相同，所述第一保护层远离所述沟道层的一侧的镨原子的含量小于所述第一保护层靠近所述沟道层的一侧的镨原子的含量。
在本公开实施例的一种实现方式中，所述沟道层中掺杂有镨元素，在所述沟道层中，从靠近所述第一保护层到远离所述第一保护层的方向上，所述沟道层中镨原子的含量单调递减。
在本公开实施例的一种实现方式中，所述第一保护层中的金属元素还包括锡元素、铟元素、镓元素、锌元素中的至少一种，所述第一保护层中的镨原子的数量占所述第一保护层中金属元素原子总数量的比例1％至50％之间。
在本公开实施例的一种实现方式中，所述第一保护层中的金属元素还包括所述铟元素、所述镓元素和所述锌元素；所述第一保护层中的铟原子的数量占所述第一保护层中的铟原子、镓原子、锌原子总数量的比例在45％至55％之间；所述第一保护层中的镓原子的数量占所述第一保护层中的铟原子、镓原子、锌原子总数量的比例在25％至35％之间；所述第一保护层中的锌原子的数量占所述第一保护层中的铟原子、镓原子、锌原子总数量的比例在15％至25％之间。
在本公开实施例的一种实现方式中，所述第一保护层位于所述沟道层的远离衬底基板的表面。
在本公开实施例的一种实现方式中，所述至少两层金属氧化物半导体层还包括：第二保护层，位于沟道层靠近衬底基板的表面，第二保护层中包含镨元素。
在本公开实施例的一种实现方式中，所述第二保护层为包含镨元素的铟镓锌氧化物层，所述第二保护层中的镨原子的数量占所述第二保护层中金属元素的原子总数量的比例在1％至50％之间。
在本公开实施例的一种实现方式中，所述至少两层金属氧化物半导体层还 包括：源漏极层，位于所述第一保护层远离衬底基板的表面；覆盖层，位于所述第一保护层和所述源漏极层之间，所述覆盖层为未掺杂镨元素的结晶氧化物层。
在本公开实施例的一种实现方式中，所述覆盖层为金属结晶氧化物层，所述金属结晶氧化物层中的金属包括铟、镓、锌和锡中至少一种。
在本公开实施例的一种实现方式中，所述薄膜晶体管还包括：扩散层，所述扩散层位于所述第一保护层远离所述衬底基板的一面，所述扩散层为镨金属层或镨金属氧化物层。
在本公开实施例的一种实现方式中，所述第一保护层位于所述沟道层的靠近衬底基板的表面。
在本公开实施例的一种实现方式中，所述薄膜晶体管还包括：源极和漏极，所述源极和所述漏极位于所述有源层上，所述源极和所述漏极分别包裹所述有源层的侧壁，且所述源极和所述漏极分别与所述沟道层的侧壁连接，所述源极和所述漏极中包含镨元素。
另一方面，本公开提供了一种薄膜晶体管的制作方法，所述方法包括：
提供一衬底基板；在所述衬底基板上依次形成至少两层金属氧化物半导体层，以形成薄膜晶体管的有源层，所述至少两层氧化物半导体层包括沟道层和第一保护层，所述沟道层中的金属氧化物半导体层中的金属元素包含锡元素，以及包含铟元素、镓元素、锌元素中的至少一种；所述第一保护层包含镨元素，所述第一保护层中的镨元素用于吸收金属氧化物半导体中的光生电子，降低光照引起的光生电流。
在本公开实施例的一种实现方式中，在所述衬底基板上依次形成至少两层金属氧化物半导体层，包括：在所述衬底基板上形成一层铟镓锡氧化物膜层；在所述铟镓锡氧化物膜层远离衬底基板的一面形成一层扩散膜层，所述扩散膜层为镨金属膜层或镨金属氧化物膜层；对所述铟镓锡氧化物膜层和所述扩散膜层进行退火处理，使所述扩散膜层中的镨元素扩散至所述铟镓锡氧化物膜层中，得到包含依次层叠在所述衬底基板上的所述沟道层和所述第一保护层的有源层；对所述扩散膜层进行图形化处理，得到位于所述有源层上的扩散层，所述扩散层位于所述第一保护层远离所述衬底基板的一面，所述扩散层为镨金属层或镨金属氧化物层。
在本公开实施例的一种实现方式中，所述方法还包括：在所述扩散层上形成源漏金属层，所述源漏金属层包含镨元素；对所述源漏金属层进行图形化处理，以形成源极和漏极。
另一方面，本公开提供了一种阵列基板，所述阵列基板包括衬底基板和在所述衬底基板上的多个薄膜晶体管，所述薄膜晶体管为上述任一方面所述的薄膜晶体管。
在本公开实施例的一种实现方式中，所述阵列基板还包括：第一绝缘层，覆盖在所述第一保护层、所述源极和所述漏极上；第一电极层，包括多个第一电极，所述多个第一电极位于所述第一绝缘层远离所述衬底基板的一面；第二绝缘层，覆盖在所述多个第一电极上；第二电极层，位于所述第二绝缘层远离所述衬底基板的一面，所述第二电极层与对应的薄膜晶体管中的源极或漏极电连接。
另一方面，本公开提供了一种显示装置，所述显示装置包括上述任一方面所述的阵列基板。
本公开实施例提供的技术方案带来的有益效果至少包括：
在本公开实施例中，在薄膜晶体管工作的过程中，沟道层为主要的沟道区。第一保护层对沟道层进行保护，当光线从第一保护层所在的一侧照向沟道层时，光线会先照射到第一保护层上，第一保护层对光线进行遮挡，减弱光线对沟道层的影响，提高薄膜晶体管的稳定性。第一保护层受到光线照射时，也会产生光生载流子，由于第一保护层中包含有镨元素，镨元素会在第一保护层的内部带隙中引入一个中间能级态，也称陷阱态。在第一保护层受到光线照射产生光生载流子时，光生载流子会在第一保护层内部被陷阱态捕获，使得光生载流子在第一保护层内部消化，不会影响实际沟道区的功能。并且，沟道层中包含锡元素，可以提高薄膜晶体管的迁移率，从而提高薄膜晶体管的反应速度。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开 的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种薄膜晶体管的截面结构示意图；
图2是本公开实施例提供的一种薄膜晶体管的截面结构示意图；
图3是本公开实施例提供的一种薄膜晶体管的截面结构示意图；
图4是本公开实施例提供的一种薄膜晶体管的截面结构示意图；
图5是本公开实施例提供的一种薄膜晶体管的截面结构示意图；
图6是本公开实施例提供的一种薄膜晶体管的截面结构示意图；
图7是本公开实施例提供的一种薄膜晶体管的制作方法的流程图；
图8是本公开实施例提供的一种薄膜晶体管的制作方法的流程图；
图9是公开实施例提供的一种薄膜晶体管的制作方法的过程图；
图10是公开实施例提供的一种薄膜晶体管的制作方法的过程图；
图11是公开实施例提供的一种薄膜晶体管的制作方法的过程图；
图12是公开实施例提供的一种薄膜晶体管的制作方法的过程图；
图13是公开实施例提供的一种薄膜晶体管的制作方法的过程图；
图14是本公开实施例提供的一种薄膜晶体管的制作方法的流程图；
图15是本公开实施例提供的一种薄膜晶体管的制作方法的过程图；
图16是本公开实施例提供的一种薄膜晶体管的制作方法的过程图；
图17是本公开实施例提供的一种薄膜晶体管的制作方法的过程图；
图18是本公开实施例提供的一种薄膜晶体管的制作方法的过程图；
图19是本公开实施例提供的一种薄膜晶体管的制作方法的过程图；
图20是本公开实施例提供的一种阵列基板的截面结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
本公开实施例提供了一种薄膜晶体管，图1是本公开实施例提供的一种薄膜晶体管的截面结构示意图。参见图1，该薄膜晶体管的有源层10包括层叠的至少两层金属氧化物半导体层，至少两层氧化物半导体层至少包括沟道层101和第一保护层102，其中，沟道层101中的金属氧化物半导体层中的金属包含锡 (Sn)元素，以及包含铟(In)元素、镓(Ga)元素、锌(Zn)元素中的至少一种。第一保护层102包含镨元素，第一保护层102中的镨元素用于吸收金属氧化物半导体中的光生电子，降低光照引起的光生电流。
可选地，该薄膜晶体管为顶栅、底栅或双栅结构。其中，顶栅结构是指栅极位于有源层的远离衬底基板的一侧，底栅结构是指栅极位于有源层的靠近衬底基板的一侧，双栅结构是指薄膜晶体管包括位于不同层的两个栅极，两个栅极之间通过栅极绝缘层隔开，两个栅极均位于有源层的远离衬底基板的一侧或者，两个栅极均位于有源层的靠近衬底基板的一侧。
在本公开实施例中，在薄膜晶体管工作的过程中，沟道层101为实际的沟道区。第一保护层102对沟道层101进行保护，当光线从第一保护层102所在的一侧照向沟道层101时，光线会先照射到第一保护层102上，第一保护层102对光线进行遮挡，减弱光线对沟道层101的影响，提高薄膜晶体管的稳定性。第一保护层102受到光线照射时，也会产生光生载流子，由于第一保护层102中包含有镨元素，镨元素会在第一保护层102的内部带隙中引入一个中间能级态，也称陷阱态。在第一保护层102受到光线照射产生光生载流子时，光生载流子会在第一保护层102内部被陷阱态捕获，使得光生载流子在第一保护层102内部消化，不会影响实际沟道区的功能。并且，沟道层101中包含锡元素，可以提高薄膜晶体管的迁移率，从而提高薄膜晶体管的反应速度。
由于本公开实施例提供的薄膜晶体管的有源层采用氧化物制作，该薄膜晶体管称为氧化物薄膜晶体管。
在本公开实施例的一种实现方式中，沟道层101中的金属氧化物半导体层中的金属元素包含锡元素、铟元素和镓元素。沟道层101中的铟原子的数量占沟道层101中的铟原子、镓原子、锡原子总数量的比例在65％至75％之间。沟道层101中的镓原子的数量占沟道层101中的铟原子、镓原子、锡原子总数量的比例在24％至30％之间。沟道层101中的锡原子的数量占沟道层101中的铟原子、镓原子、锡原子总数量的比例在1％至5％之间。
在本公开实施例的一种实现方式中，沟道层101中的铟原子、镓原子、锡原子的数量比在90:20:1至20:10:1之间。该比例是根据上述铟原子、镓原子、锡原子的占比确定出来的。
沟道层101中各个元素的配比不同，沟道层101的迁移率不同。按照上述比例配置沟道层101中的各种元素，薄膜晶体管的迁移率可以达到30平方厘米 /伏·秒(cm 2/(V·S))到50平方厘米/伏·秒之间，进一步提高薄膜晶体管的迁移率。且采用上述原子数量比例配置的沟道层101为结晶态。
在一些示例中，沟道层101中，铟原子、镓原子、锡原子的数量比为57:21:2。在另一些示例中，沟道层101中，铟原子、镓原子、锡原子的数量比为29:11:1。
需要说明的是，由于制备工艺中存在误差，沟道层101中的各个原子的数量占比存在波动，每个原子的数量占比在±10％的范围内波动。
以沟道层101中，铟原子、镓原子、锡原子的数量比为29:11:1，沟道层101中的铟原子的数量占比的浮动范围为±5％为例，则此时沟道层101中，铟原子、镓原子、锡原子的数量比在27.55：11：1至30.45：11：1之间。例如，铟原子、镓原子、锡原子的数量比为30：11：1。
在本公开实施例中，沟道层101的厚度小于30纳米(nm)。例如，25纳米。
在本公开实施例中，第一保护层102的厚度小于20纳米(nm)。例如，20纳米。
在本公开实施例的一种实现方式中，第一保护层102的金属元素还包括锡元素、铟元素、镓元素、锌元素中的至少一种。
示例性地，第一保护层102为掺杂有镨元素的铟镓锌氧化物(IGZO)层。
铟镓锌氧化物容易获得，且在铟镓锌氧化物中掺杂镨元素可以使得第一保护层102能够在光线照射时对沟道层101进行保护。
在本公开实施例的一种实现方式中，第一保护层102中的铟原子的数量占第一保护层102中的铟原子、镓原子、锌原子总数量的比例在45％至55％之间；第一保护层102中的镓原子的数量占第一保护层102中的铟原子、镓原子、锌原子总数量的比例在25％至35％之间；第一保护层102中的锌原子的数量占第一保护层102中的铟原子、镓原子、锌原子总数量的比例在15％至25％之间。
在本公开实施例的中，第一保护层102的铟原子、镓原子、锌原子数量比在6:3:1至3:3:1之间。该比例是根据上述铟原子、镓原子、锌原子的占比确定出来的。
在一些示例中，第一保护层102的铟原子、镓原子、锌原子数量比为46:29:21。在另一些示例中，第一保护层102中，铟原子、镓原子、锌原子的数量比为23:14:10。
在本公开实施例的一种实现方式中，第一保护层102中的镨原子的数量占第一保护层102中金属元素原子总数量的比例1％至50％之间。
镨容易获得，价格便宜，降低制作成本。镨元素掺杂至铟镓锌氧化物后，会在铟镓锌氧化物的内部一个中间能级态，对光生载流子的复合起着加速的作用，该中间能级态称为三价镨(Pr3 +)陷阱态。陷阱态可以提供一个电子复合阶梯，当铟镓锌氧化物受光线照射产生光生载流子(也即光生电荷)时，该光生载流子会被迅速被三价镨陷阱态捕获，光生载流子与电子复合阶梯进行复合，使得光生载流子寿命降低，降低了光生载流子浓度，并使得光生载流子在内部消化，进而不会影响沟道层，从而提高薄膜晶体管光照稳定性和迁移率。
同时控制掺杂的镨元素的含量占比，保证第一保护层102达到最佳的保护效果，对沟道层101进行保护，进一步提高薄膜晶体管的光稳定性。
示例性地，第一保护层102中的镨原子的数量占第一保护层102中的铟原子、镓原子和锌原子总数量的5％。
在一些示例中，第一保护层102的铟原子、镓原子、锌原子和镨原子的数量比为46:29:21:4。在另一些示例中，第一保护层102中，铟原子、镓原子、锌原子和镨原子的数量比为23:14:10:2。
同样地，第一保护层102中的各个原子的数量占比同样存在波动，每个原子的数量占比同样在±10％的范围内波动。
在本公开实施例中，镨元素的含量占比指镨原子的数量占第一保护层102中的所有金属元素的原子数量的比值。
在本公开实施例中，第一保护层102中的镨原子在第一保护层102的不同厚度位置的含量不完全相同，第一保护层102远离沟道层101的一侧的镨原子的含量小于第一保护层102靠近沟道层101的一侧的镨原子的含量。
可替代地，在其他实现方式中，第一保护层102为镨氧化物(Pr-Oxide)层，例如，三氧化二镨(Pr 2O 3)层。
在本公开实施例的中，沟道层101中包含镨元素，沟道层101中镨元素的原子数量占沟道层101所有金属元素的原子数量的百分比小于第一保护层102中镨元素的原子数量占第一保护层102中所有金属元素的原子数量的百分比。
在制作有源层10的过程中，需要进行退火处理，第一保护层102中镨元素在退火的过程中可能会掺杂至沟道层101中，使得沟道层101中同样包含镨元素。但由于镨元素是从第一保护层102中掺杂至沟道层101中的，所以沟道层101中镨元素的含量占比小于第一保护层102中镨元素的含量占比。
同时，在沟道层101中，从靠近第一保护层102到远离第一保护层102的 方向上，沟道层101中包含的镨元素的含量占比依次减小。
示例性地，沟道层101中的镨原子的数量占沟道层101中的铟原子、镓原子和锡原子总数量的2％。
再次参见图1，有源层10位于衬底基板30上。第一保护层102位于沟道层101的远离衬底基板30的表面。
薄膜晶体管工作的过程中，从远离衬底基板30的表面的一侧照射向沟道层101的光线较多。将第一保护层102设置在沟道层101的远离衬底基板30的表面，使得第一保护层102对从远离衬底基板30的表面的一侧照射向沟道层101的环境光进行遮挡，减小光线对沟道层101的影响。同时当第一保护层102中的镨元素扩散中沟道层101中时，使得沟道层101靠近衬底基板30一侧中的镨元素较少，避免降低薄膜晶体管的稳定性。
再次参见图1，薄膜晶体管还包括源漏极(Source Drain，SD)层50。源漏极层50包括源极501和漏极502，源极501和漏极502位于有源层10上，源极501和漏极502分别包裹有源层10的侧壁，且源极501和漏极502分别与沟道层101的侧壁连接。
对于一个薄膜晶体管而言，源漏极层50中的源极501和漏极502需要分别与沟道层101连接，在薄膜晶体管工作时，源极501和漏极502通过沟道层101导通。而在图1中，由于沟道层101位于第一保护层102的下方，源极501和漏极502无法从沟道层101的上方与沟道层101连接，源极501和漏极502分别包裹有源层10的侧壁，也即源极501和漏极502通过沟道层101的侧壁与沟道层101连接。
在本公开实施例中，源漏极层50为金属层或氧化铟锡(ITO)层，保证源漏极层50的导电性。
再次参见图1，薄膜晶体管还包括栅极(Gate)60和栅极绝缘(Gate Insulator，GI)层70。栅极60位于有源层10靠近衬底基板30的一侧。栅极绝缘层70位于有源层10和栅极60之间，将有源层10和栅极60隔开。
示例性地，栅极60采用金属制成，例如铜等；或者栅极60采用透明导电材料制成，氧化铟锡等。
在本公开实施例中，栅极60和第一保护层102分别位于沟道层101的两侧，栅极60和第一保护层102可以从两个侧面对沟道层101进行遮光。
示例性地，栅极绝缘层70为氧化硅、氮化硅层或环氧树脂。
如图1所示，薄膜晶体管还包括第一绝缘层(PVX)80。第一绝缘层80覆盖第一保护层102和源漏极层50上。
布置第一绝缘层80，将源漏极层50与位于源漏极层50上方的膜层隔开，避免影响源漏极层50电信号的传输。
示例性地，第一绝缘层80为氧化硅层。
在本公开实施例中，由于第一绝缘层80一般为氧化硅层，第一绝缘层80中包含硅类元素，沟道层101为铟镓锡氧化物层，沟道层101中无硅类元素，沟道层101直接与第一绝缘层80接触的话，在沟道层101与第一绝缘层80的接触面会上产生界面态，影响薄膜晶体管的迁移率。通过不含硅类元素的第一保护层102将第一绝缘层80和沟道层101隔开，能够避免由于界面态对薄膜晶体管的迁移率的影响。
图1所示的薄膜晶体管为底栅结构的薄膜晶体管，在其他实现方式中，薄膜晶体管还可以为顶栅结构的薄膜晶体管，具体结构参见图2。
图2是本公开实施例提供的一种薄膜晶体管的截面结构示意图。参见图2，栅极绝缘层70位于第一保护层102远离衬底基板30的一面，栅极60位于栅极绝缘层70远离衬底基板30的一面，也即栅极60位于有源层10的上方，为顶栅结构的薄膜晶体管。
再次参见图2，对于顶栅结构的薄膜晶体管，第一保护层102将栅极绝缘层70与沟道层101隔开，避免沟道层101直接与栅极绝缘层70接触，在栅极绝缘层70和沟道层101之间产生界面态，影响薄膜晶体管的迁移率。
再次参见图2，薄膜晶体管还包括层间电介质(Interlayer Dielectric，ILD)层120，层间电介质层120包裹栅极60和有源层10，源漏极层50位于层间电介质层120上，也即通过层间电介质层120将栅极60和源漏极层50隔开。
示例性地，层间电介质层120为氧化硅层、氮化硅层或环氧树脂层。
再次参见图2，薄膜晶体管还包括遮光(Shield)层130和缓冲(Buffer)层140，遮光层130和缓冲层140均位于衬底基板上，遮光层130与沟道层101相对，缓冲层140位于遮光层130和沟道层101之间。
在本公开实施例中，布置遮光层130可以遮挡从遮光层130一侧向沟道层101照射的光线，减小光线对沟道层101的影响。
将沟道层101布置在缓冲层140上，减小衬底基板30上的杂质对沟道层101的影响。
图3是本公开实施例提供的一种薄膜晶体管的截面结构示意图。参见图3，至少两层金属氧化物半导体层还包括第二保护层103。第二保护层103位于沟道层101的靠近衬底基板30的表面，第二保护层103中包含镨元素。
薄膜晶体管工作的过程中，沟道层101的两侧均会受到光线的照射，例如，环境光，发光单元光线或者背光发出的光线。在沟道层101的两个表面均布置第一保护层，第二保护层103中同样掺杂有镨元素，第二保护层103与第一保护层102的作用相同。当光线从沟道层101的相对的两个表面对沟道层101进行照射时，第一保护层102和第二保护层103均可以对沟道层101进行保护，提高薄膜晶体管的稳定性。
在本公开实施例中，当沟道层101的相对的两个表面均分别布置第一保护层102和第二保护层103时，第一保护层102将沟道层101和第一绝缘层80隔开，第二保护层103将沟道层101和栅极绝缘层70隔开，可同时避免在沟道层101的两个表面形成界面态，避免影响薄膜晶体管的稳定性。
在本公开实施例的一种实现方式中，第二保护层103为包含镨元素的铟镓锌氧化物层。第二保护层103中的镨原子的数量占第二保护层103中的铟原子、镓原子和锌原子总数量的1％至50％之间。
在本公开实施例中，第二保护层103的铟原子、镓原子、锌原子的占比与第一保护层102的铟原子、镓原子、锌原子的占比相同。
示例性地，第二保护层103的铟原子、镓原子、锌原子数量比在6:3:1至3:3:1之间。
例如，第二保护层103的铟原子、镓原子、锌原子数量比为4:3:2。第二保护层103中的镨原子的数量占第二保护层103中的铟原子、镓原子和锌原子总数量的20％。
同样地，第二保护层103中的各个原子的数量占比同样存在波动，每个原子的数量占比同样在±10％的范围内波动。
可替代地，第二保护层103为镨氧化物层，例如，三氧化二镨层。
图4是本公开实施例提供的一种薄膜晶体管的截面结构示意图。参见图4，至少两层金属氧化物半导体层还包括覆盖层104。覆盖层104位于第一保护层102远离衬底基板30的一面，覆盖层104为未掺杂镨元素的结晶氧化物层。覆盖层104位于源漏极层50和第一保护层102之间。
在本公开实施例中，在第一保护层102上布置覆盖层104，覆盖层104可以 提高薄膜晶体管在高温高电压下的稳定性。同时源漏极刻蚀时，结晶氧化物层可以减小刻蚀时对有源层10的影响，提高薄膜晶体管的稳定性。
在本公开实施例中，覆盖层104为金属结晶氧化物层，金属结晶氧化物层中的金属包括铟、镓、锌和锡中至少一种。
示例性地，覆盖层104为氧化铟镓锌(IGZO)层、氧化铟镓(IGZ)层、氧化铟镓锌锡(IGZTO)层、氧化铟锡(ITO)层和氧化铟锌(IZO)层中的任意一种。
氧化铟镓锌、氧化铟镓、氧化铟镓锌锡、氧化铟锡和氧化铟锌均为制作薄膜晶体管常用的材料，容易获取，降低制作的成本。
图5是本公开实施例提供的一种薄膜晶体管的截面结构示意图。参见图5，薄膜晶体管还包括扩散层40。扩散层40位于第一保护层102远离衬底基板30的一面，扩散层40为镨金属层或镨金属氧化物层。
在本公开实施例中，扩散层40是在制作第一保护层102的产物，在未经处理的载流子传输膜层上布置扩散层40，再对未经处理的载流子传输膜层进行高温退火处理时，在退火处理的过程中，扩散层40中的镨元素会掺杂至未经处理的有源层中，使得未经处理的载流子传输膜层在靠近扩散层40的一侧形成包含镨元素的第一保护层102，在远离扩散层40的一侧形成作为沟道区的沟道层101。
再次参见图5，且扩散层40包裹有源层10的侧壁，在对源漏极层50进行刻蚀时，扩散层40可对有源层10进行保护。
再次参见图5，扩散层40包括相互断开的两个部分，扩散层40位于源漏极层50和有源层10之间，由于扩散层40的两个部分之间相互断开，避免扩散层40将源漏极层50中的源极501和漏极502连接。在这种情况下，扩散层40为镨金属层或镨金属氧化物层。
可替代地，在其他实现中，扩散层40也可以是一体结构，即覆盖第一保护层102，这种情况下，扩散层为镨金属氧化物层。
需要说明的是，在其他实施例中，也可以在图5的基础上去除该扩散层40，而是在源极501和漏极502中包含镨元素。使得源极501和漏极502中的镨元素扩散到有源层10中。示例性地，源漏极层为一种镨金属掺杂的金属化合物，或者，为镨金属薄膜叠加其他金属膜层，如镨金属层和铜金属层叠加等。
需要说明的是，在其他实施例中，扩散层40可以不包裹有源层10的侧壁， 扩散层40与有源层10层叠，且扩散层40位于有源层10远离衬底基板30的一面。源极501和漏极502分别包裹有源层10和扩散层40的侧壁。
图6是本公开实施例提供的一种薄膜晶体管的截面结构示意图。与图1所示结构的不同之处在于，图6中第一保护层102位于沟道层101的靠近衬底基板30的表面。
本公开实施例还提供了一种薄膜晶体管的制作方法，图7是本公开实施例提供的一种薄膜晶体管的制作方法的流程图。参见图7，该方法包括：
在步骤S11中，提供一衬底基板。
在步骤S12中，在衬底基板上依次形成至少两层金属氧化物半导体层，以形成薄膜晶体管的有源层，至少两层氧化物半导体层包括沟道层和第一保护层，沟道层中的金属氧化物半导体层中的金属包含锡元素，以及包含铟元素、镓元素、锌元素中的至少一种；第一保护层包含镨元素，第一保护层中的镨元素用于吸收金属氧化物半导体中的光生电子，降低光照引起的光生电流。
图8是本公开实施例提供的一种薄膜晶体管的制作方法的流程图。参见图8，该方法包括：
在步骤S21中，提供一衬底基板。
图9至图13是公开实施例提供的一种薄膜晶体管的制作方法的过程图。下面结合图9至图13对衬底基板的制作过程进行介绍。
参见图9，提供一衬底基板30。
在步骤S22中，在衬底基板上形成栅极。
参见图10，在衬底基板30上制作栅极60。
在本公开实施例中，栅极60为金属电极。
示例性地，可以通过沉积的方法在衬底基板30上制作一层栅极膜层，然后对栅极膜层进行图形化处理得到栅极60。
在步骤S23中，在栅极上形成栅极绝缘层。
参见图11，在栅极60上制作栅极绝缘层70，栅极绝缘层70包裹栅极60。
在本公开实施例中，栅极绝缘层70为氧化硅层。
示例性地，可以通过沉积的方法在栅极60上制作栅极绝缘层70。
在步骤S24中，在栅极绝缘层上形成有源层。
参见图12，在栅极绝缘层70上制作一层有源层10。
在本公开实施例中，有源层10包括沟道层101和第一保护层102，沟道层101采用铟镓锡氧化物制成，第一保护层102为包含镨元素的铟镓锌氧化物制成。
示例性地，可以先在栅极绝缘层70上溅射(Sputter)一层铟镓锡氧化物膜层，然后在铟镓锡氧化物薄膜层上形成包含镨元素的铟镓锌氧化物膜层。然后对铟镓锡氧化物膜层和包含镨元素的铟镓锌氧化物膜层进行图形化处理得到如图12所示的沟道层101和第一保护层102。
在步骤S25中，在有源层上形成源漏极层。
参见图13，在有源层10上制作源漏极层50，源漏极层50包括源极501和漏极502，源极501和漏极502位于有源层10上，源极501和漏极502分别包裹有源层10的侧壁，且源极501和漏极502分别与沟道层101的侧壁连接。
在本公开实施例中，源漏极层50为金属层，可以通过溅射的方法在有源层10上形成一层金属膜层，然后对金属膜层进行图形化处理，得到如图13所示的源极501和漏极502。
在步骤S26中，在源漏极层上形成第一绝缘层。
在源漏极层50上依次形成第一绝缘层80，得到如图1所示的衬底基板。
图14是本公开实施例提供的一种薄膜晶体管的制作方法的流程图。参见图14，该方法包括：
在步骤S31中，提供一衬底基板。
在步骤S32中，在衬底基板上形成栅极。
在步骤S33中，在栅极上形成栅极绝缘层。
在步骤S34中，在栅极绝缘层上形成一层铟镓锡氧化物膜层。
图15至图19是本公开实施例提供的一种薄膜晶体管的制作方法的过程图。下面结合图15至图19对薄膜晶体管的制作过程进行介绍。参见图15，在栅极绝缘层70上形成铟镓锡氧化物膜层170。
在步骤S35中，在铟镓锡氧化物膜层远离衬底基板的一面形成一层扩散膜层。扩散膜层为镨金属膜层或镨金属氧化物膜层。
参见图16，在铟镓锡氧化物膜层170上形成一层扩散膜层180。
在步骤S36中，对铟镓锡氧化物膜层和扩散膜层进行退火处理，使扩散膜层中的镨元素扩散至铟镓锡氧化物膜层中，得到包含依次层叠在衬底基板上的沟道层和第一保护层的有源层。
参见图17，对铟镓锡氧化物膜层170和扩散膜层180同时进行退火处理， 使扩散膜层180中的镨元素扩散至铟镓锡氧化物膜层170中，在铟镓锡氧化物膜层170中形成包含沟道层101和第一保护层102的有源层。
在步骤S37中，对扩散膜层进行图形化处理，得到位于有源层上的扩散层。
参见图18，对扩散膜层进行图形化处理，得到位于有源层上的扩散层40。扩散层40位于第一保护层102远离衬底基板30的一面，扩散层40包裹有源层10的侧壁，扩散层40为镨金属层或镨金属氧化物层。
需要说明的是，在其他实施例中，铟镓锡氧化物膜层170和扩散膜层180可以同时进行刻蚀，简化制作流程。也即直接在铟镓锡氧化物膜层170上形成一层扩散膜层180，然后对铟镓锡氧化物膜层170和扩散膜层180同时进行图形化处理，以形成有源层10和扩散层40。此时扩散层40未包裹有源层10的侧壁，扩散层40与有源层10层叠，且扩散层40位于有源层10远离衬底基板30的一面。
在步骤S38中，在扩散膜层上形成源漏金属层。
在步骤S39中，对源漏金属层进行图形化处理，以形成源极和漏极。
参见图19，在扩散膜层180上制作源漏金属层后，对源漏金属层进行图形化处理就可以得到如图19所示的源漏极层50。
在步骤S40中，在源漏极层上形成第一绝缘层。
在源漏极层50上形成第一绝缘层80，得到如图5所示的衬底基板。
需要说明的是，在其他实施例中，也可以省略步骤S35至步骤S37，而直接在铟镓锡氧化物膜层上形成源漏金属层，源漏金属层包含镨元素，然后对源漏金属层进行图形化处理，源漏金属层中的镨元素扩散至铟镓锡氧化物膜层中，在铟镓锡氧化物膜层中形成包含沟道层和第一保护层的有源层。
本公开实施例还提供了一种阵列基板，该阵列基板包括叠层设置的衬底基板30和多个薄膜晶体管，薄膜晶体管为图1至图7任一幅图所示的薄膜晶体管。
图20是本公开实施例提供的一种阵列基板的截面结构示意图。参见图20，阵列基板还包括：第一电极层90、第二绝缘层100和第二电极层110。第一电极层90包括多个第一电极，多个第一电极位于第一绝缘层80远离衬底基板30的一面。第二绝缘层100覆盖在多个第一电极上。第二电极层110位于第二绝缘层100远离衬底基板30的一面，第二电极层110与对应的薄膜晶体管中的源极501或漏极502电连接。
本公开实施例提供的阵列基板可用于液晶显示(Liquid Crystal Display，LCD)装置，此时，第一电极层90和第二电极层110中的一个为像素电极层，另一个为公共电极层，第二绝缘层100将第一电极层90和第二电极层110隔开。
在本公开实施例中，第一电极层90和第二电极层110为氧化铟锡层，保证第一电极层90和第二电极层110的导电性和透明性。
再次参见图20，阵列基板还包括平坦化层150，平坦化层150位于第一绝缘层80和第一电极层90之间。平坦化层150可以使布置了第一绝缘层80的表面更加平坦，方便制作第一电极层90。
在本公开实施例中，平坦化层150为树脂(Resin)层。
再次参见图20，第一绝缘层80、平坦化层150和第二绝缘层100中具有过孔160，第二电极层110通过过孔160与源漏极层50中的源极501或漏极502电连接。
本公开实施例还提供了一种显示装置，该显示装置包括图20所示的阵列基板。
在具体实施时，本公开实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅为本公开的较佳实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种薄膜晶体管，其特征在于，所述薄膜晶体管包括有源层(10)，所述有源层包括层叠的至少两层金属氧化物半导体层，所述至少两层金属氧化物半导体层包括沟道层(101)和第一保护层(102)，所述沟道层(101)中的金属氧化物半导体层中的金属元素包含锡元素，以及包含铟元素、镓元素、锌元素中的至少一种；所述第一保护层(102)包含镨元素，所述第一保护层(102)中的镨元素用于吸收金属氧化物半导体中的光生电子，降低光照引起的光生电流。
  2. 根据权利要求1所述的薄膜晶体管，其特征在于，所述沟道层(101)中的金属氧化物半导体层中的金属元素包含锡元素、铟元素和镓元素；
    所述沟道层(101)中的铟原子的数量占所述沟道层(101)中的铟原子、镓原子、锡原子总数量的比例在65％至75％之间；
    所述沟道层(101)中的镓原子的数量占所述沟道层(101)中的铟原子、镓原子、锡原子总数量的比例在24％至30％之间；
    所述沟道层(101)中的锡原子的数量占所述沟道层(101)中的铟原子、镓原子、锡原子总数量的比例在1％至5％之间。
  3. 根据权利要求1或2所述的薄膜晶体管，其特征在于，所述第一保护层(102)中的镨原子在所述第一保护层(102)的不同厚度位置的含量不完全相同，所述第一保护层(102)远离所述沟道层(101)的一侧的镨原子的含量小于所述第一保护层(102)靠近所述沟道层(101)的一侧的镨原子的含量。
  4. 根据权利要求1至3任一项所述的薄膜晶体管，其特征在于，所述沟道层(101)中掺杂有镨元素，在所述沟道层(101)中，从靠近所述第一保护层(102)到远离所述第一保护层(102)的方向上，所述沟道层(101)中镨原子的含量单调递减。
  5. 根据权利要求1至4任一项所述的薄膜晶体管，其特征在于，所述第一保护层(102)中的金属元素还包括锡元素、铟元素、镓元素、锌元素中的至少一种，所述第一保护层(102)中的镨原子的数量占所述第一保护层(102)中金属元素原子总数量的比例1％至50％之间。
  6. 根据权利要求5所述的薄膜晶体管，其特征在于，所述第一保护层(102)中的金属元素还包括所述铟元素、所述镓元素和所述锌元素；
    所述第一保护层(102)中的铟原子的数量占所述第一保护层(102)中的铟原子、镓原子、锌原子总数量的比例在45％至55％之间；
    所述第一保护层(102)中的镓原子的数量占所述第一保护层(102)中的铟原子、镓原子、锌原子总数量的比例在25％至35％之间；
    所述第一保护层(102)中的锌原子的数量占所述第一保护层(102)中的铟原子、镓原子、锌原子总数量的比例在15％至25％之间。
  7. 根据权利要求1至6任一项所述的薄膜晶体管，其特征在于，所述第一保护层(102)位于所述沟道层(101)的远离衬底基板(30)的表面。
  8. 根据权利要求7所述的薄膜晶体管，其特征在于，所述至少两层金属氧化物半导体层还包括：
    第二保护层(103)，位于所述沟道层(101)靠近所述衬底基板(30)的表面，所述第二保护层(103)中包含镨元素。
  9. 根据权利要求8所述的薄膜晶体管，其特征在于，所述第二保护层(103)为包含镨元素的铟镓锌氧化物层；
    所述第二保护层(103)中的镨原子的数量占所述第二保护层(103)中金属元素的原子总数量的比例在1％至50％之间。
  10. 根据权利要求7所述的薄膜晶体管，其特征在于，所述至少两层金属氧化物半导体层还包括：
    源漏极层(50)，位于所述第一保护层(102)远离衬底基板(30)的表面；
    覆盖层(104)，位于所述第一保护层(102)和所述源漏极层(50)之间，所述覆盖层(104)为未掺杂镨元素的结晶氧化物层。
  11. 根据权利要求10所述的薄膜晶体管，其特征在于，所述覆盖层(104)为金属结晶氧化物层，所述金属结晶氧化物层中的金属包括铟、镓、锌和锡中至少一种。
  12. 根据权利要求7至9任一项所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括：
    扩散层(40)，所述扩散层(40)位于所述第一保护层(102)远离所述衬底基板(30)的一面，所述扩散层(40)为镨金属层或镨金属氧化物层。
  13. 根据权利要求1至6任一项所述的薄膜晶体管，其特征在于，所述第一保护层(102)位于所述沟道层(101)的靠近衬底基板(30)的表面。
  14. 根据权利要求7至9任一项或权利要求13所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括：
    源极(501)和漏极(502)，所述源极(501)和所述漏极(502)位于所述有源层(10)上，所述源极(501)和所述漏极(502)分别包裹所述有源层(10)的侧壁，且所述源极(501)和所述漏极(502)分别与所述沟道层(101)的侧壁连接，所述源极(501)和所述漏极(502)中包含镨元素。
  15. 一种薄膜晶体管的制作方法，其特征在于，所述方法包括：
    提供一衬底基板；
    在所述衬底基板上依次形成至少两层金属氧化物半导体层，以形成薄膜晶体管的有源层，所述至少两层氧化物半导体层包括沟道层和第一保护层，所述沟道层中的金属氧化物半导体层中的金属元素包含锡元素，以及包含铟元素、镓元素、锌元素中的至少一种；所述第一保护层包含镨元素，所述第一保护层中的镨元素用于吸收金属氧化物半导体中的光生电子，降低光照引起的光生电流。
  16. 根据权利要求15所述的方法，其特征在于，在所述衬底基板上依次形成至少两层金属氧化物半导体层，包括：
    在所述衬底基板上形成一层铟镓锡氧化物膜层；
    在所述铟镓锡氧化物膜层远离衬底基板的一面形成一层扩散膜层，所述扩散膜层为镨金属膜层或镨金属氧化物膜层；
    对所述铟镓锡氧化物膜层和所述扩散膜层进行退火处理，使所述扩散膜层中的镨元素扩散至所述铟镓锡氧化物膜层中，得到包含依次层叠在所述衬底基板上的所述沟道层和所述第一保护层的有源层；
    对所述扩散膜层进行图形化处理，得到位于所述有源层上的扩散层，所述扩散层位于所述第一保护层远离所述衬底基板的一面，所述扩散层为镨金属层或镨金属氧化物层。
  17. 根据权利要求16所述的方法，其特征在于，所述方法还包括：
    在所述扩散层上形成源漏金属层，所述源漏金属层包含镨元素；
    对所述源漏金属层进行图形化处理，以形成源极和漏极。
  18. 一种阵列基板，其特征在于，所述阵列基板包括衬底基板(30)和在所述衬底基板上的多个薄膜晶体管，所述薄膜晶体管为权利要求1至14任一项所述的薄膜晶体管。
  19. 根据权利要求18所述的阵列基板，其特征在于，所述阵列基板还包括：
    第一绝缘层(80)，覆盖在所述第一保护层(102)、源极(501)和漏极(502)上；
    第一电极层(90)，包括多个第一电极，所述多个第一电极位于所述第一绝缘层(80)远离所述衬底基板(30)的一面；
    第二绝缘层(100)，覆盖在所述多个第一电极上；
    第二电极层(110)，位于所述第二绝缘层(100)远离所述衬底基板(30)的一面，所述第二电极层(110)与对应的薄膜晶体管中的源极(501)或漏极(502)电连接。
  20. 一种显示装置，其特征在于，所述显示装置包括如权利要求18或19所述的阵列基板。
PCT/CN2021/074058 2021-01-28 2021-01-28 薄膜晶体管及其制作方法、阵列基板和显示装置 WO2022160149A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2022572769A JP2024504530A (ja) 2021-01-28 2021-01-28 薄膜トランジスタ及びその製造方法、アレイ基板、表示装置
CN202180000087.0A CN115152035A (zh) 2021-01-28 2021-01-28 薄膜晶体管及其制作方法、阵列基板和显示装置
US17/611,156 US20230091604A1 (en) 2021-01-28 2021-01-28 Thin film transistor and method for manufacturing the same, array substrate and display device
PCT/CN2021/074058 WO2022160149A1 (zh) 2021-01-28 2021-01-28 薄膜晶体管及其制作方法、阵列基板和显示装置
EP21921769.2A EP4141959A4 (en) 2021-01-28 2021-01-28 THIN FILM TRANSISTOR AND METHOD OF MANUFACTURE THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/074058 WO2022160149A1 (zh) 2021-01-28 2021-01-28 薄膜晶体管及其制作方法、阵列基板和显示装置

Publications (1)

Publication Number Publication Date
WO2022160149A1 true WO2022160149A1 (zh) 2022-08-04

Family

ID=82654014

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/074058 WO2022160149A1 (zh) 2021-01-28 2021-01-28 薄膜晶体管及其制作方法、阵列基板和显示装置

Country Status (5)

Country Link
US (1) US20230091604A1 (zh)
EP (1) EP4141959A4 (zh)
JP (1) JP2024504530A (zh)
CN (1) CN115152035A (zh)
WO (1) WO2022160149A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115347005A (zh) * 2022-10-18 2022-11-15 广州华星光电半导体显示技术有限公司 显示面板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140061631A1 (en) * 2012-09-05 2014-03-06 Samsung Display Co., Ltd. Thin film transistor and manufacturing method thereof
JP2015144175A (ja) * 2014-01-31 2015-08-06 国立研究開発法人物質・材料研究機構 薄膜トランジスタおよびその製造方法
CN110767745A (zh) * 2019-09-18 2020-02-07 华南理工大学 复合金属氧化物半导体及薄膜晶体管与应用

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8142862B2 (en) * 2009-01-21 2012-03-27 Asm Japan K.K. Method of forming conformal dielectric film having Si-N bonds by PECVD
JP2012103683A (ja) * 2010-10-14 2012-05-31 Semiconductor Energy Lab Co Ltd 表示装置及び表示装置の駆動方法
US9911762B2 (en) * 2015-12-03 2018-03-06 Innolux Corporation Display device
CN107146816B (zh) * 2017-04-10 2020-05-15 华南理工大学 一种氧化物半导体薄膜及由其制备的薄膜晶体管
CN211957649U (zh) * 2020-06-24 2020-11-17 京东方科技集团股份有限公司 薄膜晶体管、阵列基板以及电子装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140061631A1 (en) * 2012-09-05 2014-03-06 Samsung Display Co., Ltd. Thin film transistor and manufacturing method thereof
JP2015144175A (ja) * 2014-01-31 2015-08-06 国立研究開発法人物質・材料研究機構 薄膜トランジスタおよびその製造方法
CN110767745A (zh) * 2019-09-18 2020-02-07 华南理工大学 复合金属氧化物半导体及薄膜晶体管与应用

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4141959A4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115347005A (zh) * 2022-10-18 2022-11-15 广州华星光电半导体显示技术有限公司 显示面板

Also Published As

Publication number Publication date
EP4141959A1 (en) 2023-03-01
EP4141959A4 (en) 2023-08-09
US20230091604A1 (en) 2023-03-23
JP2024504530A (ja) 2024-02-01
CN115152035A (zh) 2022-10-04

Similar Documents

Publication Publication Date Title
USRE48290E1 (en) Thin film transistor array panel
KR101675114B1 (ko) 박막 트랜지스터 및 그 제조방법
US20170256569A1 (en) Semiconductor device and display device and manufacturing method thereof
US10615193B2 (en) Array substrate, method for manufacturing the same, display panel, and display device
US9449991B2 (en) Semiconductor device having circular light-blocking layer
US10707236B2 (en) Array substrate, manufacturing method therefor and display device
CN101621076B (zh) 薄膜晶体管及其制造方法和平板显示装置
US9502436B2 (en) Thin film transistor, array substrate and method for fabricating the same, and display device
US20160343836A1 (en) Method for manufacturing semiconductor device
US20150187948A1 (en) Semiconductor device and method for producing same
US20150129865A1 (en) Semiconductor device and method for manufacturing same
US20120181533A1 (en) Thin film transistor array panel
US20110233542A1 (en) Method for manufacturing semiconductor device
KR20090079686A (ko) 박막 트랜지스터 기판 및 이의 제조 방법
KR20130098906A (ko) 트랜지스터, 트랜지스터 제조 방법, 반도체 장치 및 반도체 장치 제조 방법, 표시 장치, 및 전자 기기
KR20100027377A (ko) 박막 트랜지스터 기판 및 이의 제조 방법
US10411039B2 (en) Semiconductor device, display device, and method for manufacturing the same
WO2019238026A1 (zh) 光学传感器件及其制作方法、显示器件
US11342431B2 (en) Thin film transistor and manufacturing method thereof, array substrate and display device
WO2022160149A1 (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
JP2019036615A (ja) 表示装置および表示装置の製造方法
KR20120014748A (ko) 박막 트랜지스터 및 그 제조 방법
WO2022236868A1 (zh) 阵列基板
US10283533B2 (en) Transistor array panel including transistor with top electrode being electrically connected to source electrode and manufacturing method thereof
US20220254933A1 (en) Active device substrate and fabrication method of active device substrate

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21921769

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2022572769

Country of ref document: JP

ENP Entry into the national phase

Ref document number: 2021921769

Country of ref document: EP

Effective date: 20221122

NENP Non-entry into the national phase

Ref country code: DE