WO2019238026A1 - 光学传感器件及其制作方法、显示器件 - Google Patents

光学传感器件及其制作方法、显示器件 Download PDF

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WO2019238026A1
WO2019238026A1 PCT/CN2019/090651 CN2019090651W WO2019238026A1 WO 2019238026 A1 WO2019238026 A1 WO 2019238026A1 CN 2019090651 W CN2019090651 W CN 2019090651W WO 2019238026 A1 WO2019238026 A1 WO 2019238026A1
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layer
sensor device
display area
optical sensor
gate
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PCT/CN2019/090651
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English (en)
French (fr)
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王国英
宋振
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京东方科技集团股份有限公司
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Priority to US16/759,832 priority Critical patent/US11489020B2/en
Publication of WO2019238026A1 publication Critical patent/WO2019238026A1/zh

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    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
    • H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
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    • H01L31/14—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the light source or sources being controlled by the semiconductor device sensitive to radiation, e.g. image converters, image amplifiers or image storage devices
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    • H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
    • H01L31/16—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources
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    • H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
    • H01L31/16—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources
    • H01L31/167—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources the light sources and the devices sensitive to radiation all being semiconductor devices characterised by at least one potential or surface barrier
    • H01L31/173—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources the light sources and the devices sensitive to radiation all being semiconductor devices characterised by at least one potential or surface barrier formed in, or on, a common substrate
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    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]

Definitions

  • the present disclosure relates generally to display technology, and in particular, to an optical sensor device, a method of manufacturing the same, and a display device.
  • the current circuit compensation scheme is electrical compensation, which can only compensate for the display Mura (uneven brightness of the display, which causes various traces) caused by changes in the threshold voltage and mobility of the Thin Film Transistor (TFT), but Cannot cope with the compensation of brightness changes caused by OLED device aging. Although the entire panel can be optically compensated once it is shipped from the factory, it cannot resolve the Mura caused by the attenuation of EL (electroluminescence, cold light film) efficiency, that is, real-time optical compensation cannot be achieved.
  • a PD photodiode / photodiode, such as a PIN-type photodiode
  • OLED Organic Light-Emitting Diode
  • a common practice is to make a photosensitive sensor device such as PD during the TFT process. After the PD is manufactured, the wet-etching process in the subsequent preparation of the TFT will damage the sidewalls of the PD, cause an increase in PD leakage current, and affect the performance of the display device.
  • an embodiment of the present disclosure provides an optical sensor device including a display area and a non-display area.
  • the optical sensor device includes a thin film transistor including an active layer, a gate insulating layer, a gate layer, a source-drain layer, and an interlayer dielectric layer, and the gate insulating layer is configured To insulate the active layer and the gate layer, and the interlayer dielectric layer is configured to insulate the gate layer and the source-drain layer.
  • the optical sensor device includes a first insulating layer, a conductive layer, and a second insulating layer that are sequentially stacked, and the conductive layer is disposed on the same layer as the source and drain layers or the gate layer.
  • the first insulating layer is provided with a first opening
  • the optical sensor device further includes a photosensitive sensor device, and the photosensitive sensor device is located in the first opening hole.
  • the conductive layer covers the bottom and sidewalls of the first opening
  • the second insulating layer covers at least the conductive layer covering the sidewalls of the first opening.
  • the photosensitive sensor device is disposed in the groove.
  • the depth of the groove is less than or equal to the thickness of the photosensitive sensor device.
  • the optical sensor device further includes a buffer layer on the substrate in the display area and the non-display area, and the first opening penetrates all of the first insulating layer. Thickness and at least a portion of the thickness of the buffer layer.
  • the optical sensor device is a PIN-type photodiode and includes an N-type layer, an I-type layer, and a P-type layer of a semiconductor material that are sequentially stacked.
  • the N-type layer of the semiconductor material is electrically connected to the conductive layer.
  • the conductive layer is disposed on the same layer as the source-drain layer, and the first insulating layer is disposed on the same layer as the interlayer dielectric layer.
  • the optical sensor device further includes a first passivation layer covering the source and drain layers in the display area, and the second insulation layer and the first passivation layer Same level setting.
  • one of the conductive layer and the source-drain layer is an integrated component.
  • the conductive layer is disposed on the same layer as the gate layer, the first insulating layer is disposed on the same layer as the gate insulating layer, and the second insulating layer is disposed on the same layer as the gate insulating layer.
  • the interlayer dielectric layer is set at the same layer.
  • an embodiment of the present disclosure provides a display device including the optical sensor device as described above.
  • the display device further includes:
  • a black matrix located on the optical sensor device and defining the display area
  • a color film layer which is located in the display area, covers the photosensitive sensor device and partially covers the black matrix
  • a cover layer which is located on the black matrix and the color film layer
  • a spacer layer which is located on the non-display area and on the cover layer
  • an embodiment of the present disclosure provides a method for manufacturing an optical sensor device.
  • the optical sensor device includes a display area and a non-display area.
  • the method includes:
  • an active layer, a gate insulating layer, a gate layer, a source-drain layer, and an interlayer dielectric layer are sequentially formed to form a thin film transistor, and the gate insulating layer is configured to combine the active layer and The gate layer is insulated, and the interlayer dielectric layer is configured to insulate the gate layer and the source-drain layer, and
  • first insulating layer in the non-display area, forming a first opening in the first insulating layer, forming a conductive layer and a second insulating layer, and forming a photosensitive sensor device in the first opening,
  • the conductive layer is disposed on the same layer as the source and drain layers or the gate layer.
  • forming the conductive layer includes forming the conductive layer to cover a bottom and a sidewall of the first opening,
  • Forming the second insulating layer includes forming the second insulating layer to cover at least a portion of the conductive layer covering a side wall of the first opening to form a groove, and
  • Forming the photosensitive sensor device includes forming the photosensitive sensor device in the groove.
  • the method further includes: forming a buffer layer on the substrate in the display area and the non-display area before forming the active layer, and
  • Forming the first opening includes forming the first opening to penetrate the entire thickness of the first insulating layer and at least a portion of the thickness of the buffer layer.
  • the conductive layer is disposed on the same layer as the source-drain layer, and the first insulating layer is disposed on the same layer as the interlayer dielectric layer.
  • the source-drain layer is formed after the photosensitive sensor device is formed.
  • the conductive layer is disposed on the same layer as the gate layer, the first insulating layer is disposed on the same layer as the gate insulating layer, and the second insulating layer is disposed on the same layer as the gate insulating layer.
  • the interlayer dielectric layer is set at the same layer.
  • the depth of the groove is less than or equal to the thickness of the photosensitive sensor device.
  • forming the photosensitive sensor device includes:
  • the display device is a top emission display device or a bottom emission display device.
  • FIG. 1 is a schematic structural diagram of an optical sensor device according to an embodiment of the present disclosure
  • FIG. 2 is a flowchart of a method for manufacturing an optical sensor device according to an embodiment of the present disclosure
  • FIG. 3 is a flowchart of a method for manufacturing an optical sensor device in a specific embodiment provided by an embodiment of the present disclosure
  • 4a, 4b, 4c, 4d, and 4e are schematic structural diagrams of optical sensor devices in a manufacturing process according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of an optical sensor device according to an embodiment of the present disclosure. as well as
  • FIG. 6 is a flowchart of a method for manufacturing an optical sensor device according to an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides an optical sensor device including a display area AA and a non-display area DA.
  • the optical sensor device includes a substrate 1 such as glass or resin.
  • the optical sensor device includes a TFT formed on the substrate 1.
  • the TFT includes an active layer 4, a gate layer 6, and a source-drain layer 8.
  • the optical sensor device includes a light shielding layer 2 disposed between the substrate 1 and the TFT.
  • the orthographic projection of the active layer 4 of the TFT on the substrate 1 falls into the orthographic projection of the light-shielding layer 2 on the substrate 1, thereby reducing or preventing light from illuminating the active layer, thereby reducing the off-state current (i.e., leakage Current) to improve display quality.
  • off-state current i.e., leakage Current
  • the optical sensor device includes a buffer layer 3 provided on a substrate 1. As shown in FIG. 1, the buffer layer 3 covers the light shielding layer 2 and the substrate 1.
  • the buffer layer 3 includes an insulating material such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the active layer 4 includes an ohmic contact region for contacting the source-drain layer 8, that is, the source contact region 4S and the drain contact. District 4D.
  • the TFT further includes a gate insulating layer 5 and an interlayer dielectric layer 7.
  • the gate insulating layer 5 is located above the active layer 4, the gate layer 6 is located above the gate insulating layer 5, and the interlayer dielectric layer 7 is located above the gate layer 6.
  • the source-drain layer 8 is located above the interlayer dielectric layer 7 and is electrically connected to the active layer 4 through the second opening 7B, that is, it is electrically connected to the source contact region 4S and the drain contact region 4D, respectively.
  • the second opening 7B penetrates the interlayer dielectric layer 7.
  • the TFT further includes a first passivation layer 9 and a second passivation layer 12.
  • the first passivation layer 9 covers the surface of the source-drain layer 8.
  • the second passivation layer 12 covers the first passivation layer 9 and provides a substantially flat surface.
  • the optical sensor device includes a photosensitive sensor device 10.
  • the optical sensor device includes a buffer layer 3, an interlayer dielectric layer 7, and a first opening 7A penetrating the buffer layer 3 and the interlayer dielectric layer 7 in this order.
  • the source-drain layer 8 covers the bottom and sidewalls of the first opening 7A.
  • the first passivation layer 9 covers at least a portion of the source-drain layer 8 that covers the side wall of the first opening 7A, thereby forming a groove for accommodating the photosensitive sensor device 10.
  • the photosensitive sensor device 10 fills the groove. That is, the photosensitive sensor device 10 is disposed on the source-drain layer 8 in the groove, and a first passivation layer 9 is provided between the photosensitive sensor device 10 and the source-drain layer 8 covering the side wall of the first opening 7A.
  • the photosensitive sensor device 10 Since the photosensitive sensor device 10 is disposed in the groove formed by the first opening 7A, the photosensitive sensor device 10 is protected by the metal of the source-drain layer 8 to avoid the influence of ambient light on the off-state current of the photosensitive sensor device. Since the first passivation layer 9 protects the sidewall of the photosensitive sensor device 10, the sidewall of the photosensitive sensor device 10 will not be damaged during the subsequent TFT manufacturing process, thereby improving the performance of the display device. Adding the optical sensor device with a photosensitive sensor device and an optical compensation control TFT to the display device can realize real-time optical compensation, effectively solve the display Mura caused by the brightness change of the EL device, and improve the display effect.
  • the photosensitive sensor device 10 further includes a first transparent conductive layer 19 and a second transparent conductive layer 11.
  • the second transparent conductive layer 11 is electrically connected to the first transparent conductive layer 19 through a via hole penetrating the second passivation layer 12 and serves as a lead of the first transparent conductive layer 19.
  • the depth of the groove is less than or equal to the thickness of the photosensitive sensor device.
  • the groove can better protect the sidewall of the photosensitive sensor device.
  • the depth of the groove is greater than the thickness of the photosensitive sensor device, the first transparent conductive layer 19 and the source-drain layer 8 on the photosensitive sensor device are easily short-circuited.
  • the depth of the groove may be slightly smaller than the thickness of the photosensitive sensor device.
  • the entire or part of the thickness of the buffer layer 3 can be further removed on the basis of removing the interlayer dielectric layer 7 of the entire thickness, thereby increasing the depth of the first opening 7A. , Thereby increasing the depth of the groove. That is, the first opening 7A may penetrate a part of the thickness of the interlayer dielectric layer 7, the entire thickness of the interlayer dielectric layer 7, the entire thickness of the interlayer dielectric layer 7, and the partial thickness of the buffer layer 3, or the layer.
  • the total thickness of both the interlayer dielectric layer 7 and the buffer layer 3 that is, the case shown in FIG. 1).
  • the optical sensor device further includes a black matrix (BM) 13 located above the TFT.
  • the black matrix 13 defines a non-display area DA and surrounds the display area AA.
  • the black matrix 13 defines the display area AA.
  • the optical sensor device further includes a color film layer 14 located above the photosensitive sensor device 10 in the display area AA.
  • the color film layer 14 includes three or more color film units, such as R, G, and B color film units, so as to provide corresponding primary colors to achieve color display.
  • the optical sensor device further includes an overcoating 15.
  • the cover layer 15 includes a planarizing material such as resin, SOG (Silicon On Glass) and BCB (benzocyclobutene), and covers the black matrix 13 and the color film layer 14 to provide a substantially flat upper surface. surface.
  • the optical sensor device further includes, for example, an auxiliary electrode 16 provided in the non-display area DA, a spacer 17 provided above the auxiliary electrode 16, and a cathode 18.
  • the cathode 18 covers the stack of the auxiliary electrode 16 and the spacer 17, and covers the remaining surface of the cover layer 15.
  • the auxiliary electrode 16 includes commonly used metals such as Mo, Al, Ti, Au, Cu, Hf, Ta, or alloys thereof such as AlNd, MoNb, etc., and may also be multilayer metals such as MoNb / Cu / MoNb, AlNd / Mo / AlNd, and the like.
  • the auxiliary electrode 16 is electrically connected to the cathode 18.
  • the arrangement of the auxiliary electrode can reduce the voltage drop of the display device due to the thin cathode and too large resistance, so that the display device has good display uniformity.
  • An embodiment of the present disclosure also provides a method for manufacturing an optical sensor device.
  • the optical sensor device includes a display area and a non-display area, and the method includes: sequentially forming an active layer and a gate insulating layer in the display area. , A gate layer, a source-drain layer, and an interlayer dielectric layer to form a thin film transistor, the gate insulating layer is configured to insulate the active layer and the gate layer, and the interlayer dielectric layer is configured to The gate layer and the source-drain layer are insulated.
  • the method further includes: forming a first insulating layer in the non-display area, forming a first opening in the first insulating layer, forming a conductive layer and a second insulating layer, and forming a first opening in the first opening.
  • a photosensitive sensor device is formed inside, wherein the conductive layer is disposed on the same layer as the source-drain layer or the gate layer.
  • the method includes:
  • Step S201 Remove the interlayer dielectric material layer at a position corresponding to the photosensitive sensor device to form a first opening
  • Step S202 depositing a source-drain material layer, the source-drain material layer covering a bottom and a sidewall of the first opening;
  • Step S203 a first passivation layer is formed on the source-drain material layer, and the first passivation layer covers at least a portion of the source-drain material layer that covers a sidewall of the first opening to form a groove;
  • Step S204 making a photosensitive sensor device on the source-drain material layer in the groove.
  • Step S205 pattern the source and drain material layers to form a source and drain layer.
  • the photosensitive sensor device is disposed in the groove and has a passivation layer to protect its sidewall, the sidewall of the photosensitive sensor device will not be damaged during the subsequent TFT manufacturing process. This improves the performance of the display device and the display effect.
  • a photosensitive sensor device is a PIN-type PD.
  • PD usually includes (same) a P-type layer of a semiconductor material (layer that uses holes as carriers to conduct charge), an I-type layer (intrinsic layer), and an N-type layer (layer that uses electrons as carriers to conduct charge) .
  • the P-type layer and N-type layer of PD are usually formed by doping amorphous silicon. In this process, a large amount of H (hydrogen) is introduced, and H is easily diffused to the TFT, which seriously affects the characteristics of the TFT.
  • H hydrogen
  • a photosensitive sensor device is made after the source-drain material layer is formed, but before the source-drain material layer is patterned to form the source-drain layer. Due to the shielding of the source-drain material layer, H diffusion to the TFT is avoided, thereby Improve the performance of display devices and display effects.
  • the depth of the groove is equal to the thickness of the photosensitive sensor device.
  • the groove has a better protection effect on the photosensitive sensor device. If it is difficult to achieve the same, the depth of the groove can be slightly smaller than the thickness of the photosensitive sensor device, thereby preventing the first transparency.
  • the conductive layer is short-circuited with the source-drain layer.
  • removing all or part of the thickness of the interlayer dielectric material layer at the position corresponding to the photosensitive sensor device to form a groove includes:
  • the grooves are formed by removing the interlayer dielectric material layer of the full thickness and the buffer layer material of all or part of the thickness at the position corresponding to the photosensitive sensor device.
  • fabricating a photosensitive sensor device on the source and drain layers in the groove includes:
  • the N-type layer, the I-type layer and the P-type layer and the first transparent conductive layer are patterned to form a photosensitive sensor device.
  • the N-type layer, I-type layer, P-type layer and the first transparent conductive layer of the photosensitive sensor device are continuously deposited, the patterning is completed in one etching process, the process steps are simple, and the cost is saved.
  • Step S301 As shown in FIG. 4a, a metal material is deposited on the substrate 1, and then a photoresist is applied and patterned by etching to form a metal light shielding layer 2.
  • the metal material may be a common metal such as Mo, Al, Ti, Au, Cu, Hf, Ta, or an alloy such as AlNd, MoNb.
  • Step S302 As shown in FIG. 4a, a buffer layer 3 and an active material layer are sequentially deposited, and then the active material layer is patterned by wet etching to form the active layer 4.
  • the buffer layer 3 includes, for example, an insulating material such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the active layer 4 includes, for example, a metal oxide material such as an IGZO material.
  • Step S303 As shown in FIG. 4a, a gate insulating material layer and a gate material layer are sequentially deposited, and a photoresist is applied. A gate material layer is first wet-etched using a mask to form the gate layer 6. Next, using the gate layer 6 as a reticle, the gate insulating material layer is dry-etched to form the gate insulating layer 5, thereby forming a stack of the gate insulating layer 5 and the gate layer 6.
  • the material of the gate insulating layer 5 may be an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the material of the gate layer 6 may be commonly used metals such as Mo, Al, Ti, Au, Cu, Hf, Ta, etc., or may be a Cu process, such as MoNd / Cu / MoNd.
  • step S303 further includes using the gate layer 6 or the stack of the gate insulating layer 5 and the gate layer 6 as a reticle to perform ion implantation on the exposed area of the active layer 4 to form an active layer.
  • Step S304 As shown in FIG. 4a, an interlayer dielectric layer 7 is deposited and patterned by photolithography to form a first opening 7A and a second opening 7B.
  • the first opening 7A is located in the display area AA and is located in the interlayer dielectric layer 7.
  • the first opening 7A penetrates the interlayer dielectric layer 7 and the buffer layer 3 to expose the surface of the substrate 1.
  • the second opening 7B is located in the non-display area DA, penetrates the interlayer dielectric layer 7 and exposes the ohmic contact area of the active layer 4, that is, the source contact area 4S and the drain contact area 4D.
  • Step S305 As shown in FIG. 4b, a source and drain material layer 8 'and a first passivation material layer are sequentially deposited, and the first passivation material layer is patterned to form a first passivation layer 9.
  • the source / drain material layer 8 ' covers the bottom and sidewalls of the first opening 7A.
  • the first passivation layer 9 covers at least a portion of the source and drain material layer 8 ′ that covers the side wall of the first opening 7A, thereby forming a groove for accommodating the photosensitive sensor device 10.
  • Step S306 As shown in FIG. 4c, the N-type semiconductor layer, the I-type semiconductor layer, and the P-type semiconductor layer of the PIN-type photosensitive sensor device 10 are sequentially deposited by PECVD (Plasma Enhanced Chemical Deposition).
  • the semiconductor layer may be an inorganic semiconductor or an organic semiconductor.
  • the I-type semiconductor layer is an intrinsic semiconductor layer
  • the N-type semiconductor layer is a phosphorus or arsenic-doped semiconductor layer
  • the P-type semiconductor layer is a boron-doped semiconductor.
  • a first layer of transparent conductive material is then deposited.
  • Only one mask is used to perform the patterning of the wet and dry engraving to form the patterned N-type semiconductor layer, the I-type semiconductor layer, and the P-type semiconductor layer of the photosensitive sensor device 10 and the photosensitive sensor device 10
  • the first transparent conductive layer 19 functions as an electrode of the photosensitive sensor device 10.
  • the source / drain material layer 8 ' is patterned by wet etching to form the source / drain material layer 8.
  • the source / drain layer 8 includes, for example, commonly used metals such as Mo, Al, Ti, Au, Cu, Hf, Ta, etc., and Cu process can also be adopted, such as MoNd / Cu / MoNd.
  • Step S308 As shown in FIG. 4e, a second passivation layer 12 is deposited, and vias are formed by patterning. A second transparent conductive material layer is deposited to fill the vias, and the second transparent conductive material layer is patterned to form a second transparent conductive layer 11. The second transparent conductive layer 11 is used as a lead of the first transparent conductive layer 19.
  • the subsequent process includes the following steps S309-S313.
  • Step S309 As shown in FIG. 1, a black matrix material layer is deposited and patterned to form a black matrix 13 above the TFT in the non-display area DA.
  • Step S310 As shown in FIG. 1, a color filter layer 14 is formed in the display area AA. Forming the color film layer 14 includes sequentially depositing R, G, and B color film units. Each color film unit adjacent to the black matrix 13 partially covers the black matrix 13 to prevent light leakage and crosstalk.
  • a cover layer 15 is deposited, and an auxiliary electrode 16 is formed by deposition and patterning.
  • the material of the cover layer 15 includes, but is not limited to, a planarizing material such as resin, SOG (Silicon On Glass, silicon-glass bonding structure material), and BCB (benzocyclobutene).
  • the material of the auxiliary electrode 16 may be commonly used metals such as Mo, Al, Ti, Au, Cu, Hf, Ta, or alloys thereof such as AlNd, MoNb, etc., or multilayer metals such as MoNb / Cu / MoNb, AlNd / Mo / AlNd et al.
  • Step S312 As shown in FIG. 1, in the non-display area DA, a spacer material layer is deposited on the auxiliary electrode 16 and patterned to form the spacer 17.
  • a transparent conductive oxide (TCO) film is deposited as the transparent cathode 18.
  • the material of the cathode 18 includes, but is not limited to, a transparent conductive oxide, such as AZO, IZO, AZTO, or a combination thereof.
  • the material of the cathode 18 may also be a thin metal material, such as a composite material such as Mg / Ag, Ca / Ag, Sm / Ag, Al / Ag, Ba / Ag.
  • the above embodiment designs a control TFT with a top-gate self-aligned structure.
  • This technical solution is also applicable to an ESL (etch stop layer) TFT, a BCE (back channel etch) TFT, and the like.
  • the active layer material is an oxide semiconductor such as IGZO, and may also be a-Si or the like.
  • the embodiments of the present disclosure also provide a display device, which includes the optical sensor device provided by the above embodiments of the present disclosure.
  • the display device may further include:
  • a black matrix provided on the optical sensor device
  • Color film layer covering the photosensitive sensor device and partially covering the black matrix
  • a septum layer provided on the cover layer
  • An auxiliary electrode provided on the septum layer
  • the display device is a top emission display device or a bottom emission display device.
  • the first opening 7A is located in the interlayer dielectric layer 7 and penetrates at least a part of the thickness of the interlayer dielectric layer 7.
  • the first opening 7A penetrates the interlayer dielectric layer 7 and the buffer layer 3.
  • the photosensitive sensor device 10 is disposed in a groove formed by the first opening 7A.
  • FIG. 5 shows a modification of the optical sensor device. This modification is different from the embodiment shown in FIG. 1 only in the manner in which the first opening 7A and the groove are arranged in the display area AA. As shown in FIG.
  • the optical sensor device includes a buffer layer 3, a gate insulating material layer 5 ′, and a first insulating layer 5 ′ which are stacked on the substrate 1 in this order.
  • the gate insulating material layer 5 ′ is provided in the same layer as the gate insulating layer 5.
  • the gate material layer 6 ' is disposed in the same layer as the gate layer 6, and covers the bottom and the side wall of the first opening 7A.
  • the interlayer dielectric layer 7 covers at least a portion of the gate material layer 6 ′ that covers the side wall of the first opening 7A, thereby forming a groove for accommodating the photosensitive sensor device 10.
  • the photosensitive sensor device 10 fills the groove. That is, the photosensitive sensor device 10 is disposed on the gate material layer 6 ′ in the groove, and an interlayer dielectric layer 7 is provided between the photosensitive sensor device 10 and the gate material layer 6 ′ covering the sidewall of the first opening 7A. .
  • the arrangement of the first component and the second component in the same layer means that the materials of the first component and the second component are the same and are formed by the same patterning process.
  • the photosensitive sensor device 10 Since the photosensitive sensor device 10 is disposed in the groove formed by the first opening 7A, the photosensitive sensor device 10 is protected by the metal of the gate material layer 6 ′, and the influence of ambient light on the off-state current of the photosensitive sensor device is avoided. Since the interlayer dielectric layer 7 protects the sidewall of the photosensitive sensor device 10, the sidewall of the photosensitive sensor device 10 will not be damaged during the subsequent TFT manufacturing process, thereby improving the performance of the display device.
  • the first opening 7A may penetrate a part of the thickness of the gate insulating material layer 5 ′, the entire thickness of the gate insulating material layer 5 ′, and the entire thickness of the gate insulating material layer 5 ′ and the buffer. Part of the thickness of the layer 3, or the entire thickness of both the gate insulating material layer 5 'and the buffer layer 3 (that is, the situation shown in FIG. 5).
  • the method includes, for example:
  • Step S601 removing the gate insulating material layer at a position corresponding to the photosensitive sensor device to form a first opening
  • Step S602 depositing a gate material layer, the gate material layer covering a bottom and a sidewall of the first opening;
  • Step S603 An interlayer dielectric layer is formed on the gate material layer, and the interlayer dielectric layer covers at least a portion of the gate material layer that covers a sidewall of the first opening to form a groove;
  • Step S604 a photosensitive sensor device is fabricated on the gate material layer in the groove.
  • Embodiments of the present disclosure provide an optical sensor device, a manufacturing method thereof, and a display device. Since the photosensitive sensor device is disposed in the first opening, the photosensitive sensor device is protected by the metal of the source-drain layer or the gate layer, which prevents the influence of ambient light on the off-state current of the photosensitive sensor device. The side walls are protected, so during the subsequent TFT manufacturing process, the side walls of the photosensitive sensor device will not be damaged, thereby improving the performance of the display device and improving the display effect.
  • Adding the optical sensor device with a photosensitive sensor device, that is, a photosensitive sensor device and an optical compensation control TFT, to the display device can realize real-time optical compensation, effectively solve the display Mura caused by the brightness change of the EL device, and improve the display effect.

Abstract

公开了一种光学传感器件及其制作方法、显示器件。该光学传感器包括显示区（AA）和非显示区（DA）。在非显示区（DA），光学传感器件包括薄膜晶体管，薄膜晶体管包括有源层（4）、栅极绝缘层（5）、栅极层（6）、源漏极层（8）和层间介质层（7）。在显示区（AA），光学传感器件包括依次堆叠的第一绝缘层（7）、导电层（8）和第二绝缘层（9）。导电层（8）与所述源漏极层（8）或者栅极层（6）同层设置。在显示区（AA），第一绝缘层（7）设有第一开孔（7A），光学传感器件还包括光敏传感器件，并且光敏传感器件位于第一开孔（7A）内。由于光敏传感器件设置在第一开孔（7A）中，光敏传感器件被源漏极层（8）或栅极层（6）的金属保护，避免了环境光对光敏传感器件关态电流的影响。

Description

光学传感器件及其制作方法、显示器件
相关申请的交叉引用
本公开主张于2018年6月11日提交的中国专利申请No.201810594582.9的优先权，其全部内容通过引用结合于此。
技术领域
本公开一般涉及显示技术，尤其涉及一种光学传感器件及其制作方法、显示器件。
背景技术
现有的电路补偿方案是电学补偿，它只能对TFT(Thin Film Transistor，薄膜晶体管)阈值电压和迁移率变化造成的显示Mura(显示器亮度不均匀，造成各种痕迹的现象)进行补偿，但是无法应对OLED器件老化引起的亮度变化的补偿。虽然可以在面板出厂时对面板整体进行一次光学补偿，但无法解决伴随EL(electroluminescence，冷光片)效率衰减造成的Mura，即无法实现光学实时补偿。因此需要引入光学传感器内置补偿，即在OLED(Organic Light-Emitting Diode，有机发光二极管)显示器件添加PD(photo diode/光敏二极管，例如PIN型光敏二极管)，用于实时监控EL亮度变化，并且通过外围IC(integrated circuit，集成电路)计算对面板进行实时光学补偿。
通常做法是在做TFT过程中制作光敏传感器件，例如PD。在PD制作完成后，TFT的后续制备过程中的湿刻工艺会对使PD的侧壁受损，造成PD的漏电流增大，影响显示器件的性能。
发明内容
第一方面，本公开实施例提供一种光学传感器件，包括显示区和非显示区。在所述显示区，所述光学传感器件包括薄膜晶体管，所述薄膜晶体管包括有源层、栅极绝缘层、栅极层、源漏极层和层间介质层，所述栅极绝缘层配置成将所述有源层和所述栅极层绝缘，并且所述层间介质层配置成将所述栅极层和所述源漏极层绝缘。在所述非显示区，所述光学传感器件包括依次堆叠的第一绝缘层、导电层和第二 绝缘层，并且所述导电层与所述源漏极层或者所述栅极层同层设置。在所述非显示区，所述第一绝缘层设有第一开孔，所述光学传感器件还包括光敏传感器件，并且所述光敏传感器件位于所述第一开孔内。
在一个或多个实施例中，所述导电层覆盖所述第一开孔的底部和侧壁，所述第二绝缘层至少覆盖所述导电层的覆盖所述第一开孔的侧壁的部分以形成凹槽，并且所述光敏传感器件设置在所述凹槽内。
在一个或多个实施例中，所述凹槽的深度小于或等于所述光敏传感器件的厚度。
在一个或多个实施例中，所述光学传感器件还包括在所述显示区和所述非显示区位于基板上的缓冲层，并且所述第一开孔贯穿所述第一绝缘层的全部厚度和所述缓冲层的至少部分厚度。
在一个或多个实施例中，所述光学传感器件为PIN型光敏二极管，并且包括依次堆叠的半导体材料的N型层、I型层和P型层。
在一个或多个实施例中，所述半导体材料的N型层与所述导电层电连接。
在一个或多个实施例中，所述导电层与所述源漏极层同层设置，并且所述第一绝缘层与所述层间介质层同层设置。
在一个或多个实施例中，所述光学传感器件还包括在所述显示区覆盖所述源漏极层的第一钝化层，并且所述第二绝缘层与所述第一钝化层同层设置。
在一个或多个实施例中，所述导电层与所述源漏极层其中之一为一体部件。
在一个或多个实施例中，所述导电层与所述栅极层同层设置，所述第一绝缘层与所述栅极绝缘层同层设置，并且所述第二绝缘层与所述层间介质层同层设置。
第二方面，本公开实施例提供一种显示器件，包括如上所述的光学传感器件。
在一个或多个实施例中，该显示器件还包括：
黑矩阵，其位于所述光学传感器件上并且限定所述显示区；
彩膜层，其位于所述显示区，覆盖所述光敏传感器件并部分覆盖所述黑矩阵；
覆盖层，其位于所述黑矩阵和所述彩膜层上；
隔垫物层，其位于所述非显示区并且在所述覆盖层上；
辅助电极，其设置在所述隔垫物层上；以及
透明阴极，其覆盖所述辅助电极、所述隔垫物层和所述覆盖层，并且与所述辅助电极电连接。
第三方面，本公开实施例提供一种光学传感器件制作方法。所述光学传感器件包括显示区和非显示区。所述方法包括：
在所述显示区，依次形成有源层、栅极绝缘层、栅极层、源漏极层和层间介质层以形成薄膜晶体管，所述栅极绝缘层配置成将所述有源层和所述栅极层绝缘，并且所述层间介质层配置成将所述栅极层和所述源漏极层绝缘，并且
在所述非显示区，形成第一绝缘层，在所述第一绝缘层内形成第一开孔，形成导电层和第二绝缘层，以及在所述第一开孔内形成光敏传感器件，其中所述导电层与所述源漏极层或者所述栅极层同层设置。
在一个或多个实施例中，形成所述导电层包括，形成所述导电层以覆盖所述第一开孔的底部和侧壁，
形成所述第二绝缘层包括，形成所述第二绝缘层以至少覆盖所述导电层的覆盖所述第一开孔的侧壁的部分以形成凹槽，以及
形成所述光敏传感器件包括，在所述凹槽内形成所述光敏传感器件。
在一个或多个实施例中，该方法还包括：在形成所述有源层之前，在所述显示区和所述非显示区中，在基板上形成缓冲层，并且
其中形成所述第一开孔包括，形成所述第一开孔，以贯穿所述第一绝缘层的全部厚度和所述缓冲层的至少部分厚度。
在一个或多个实施例中，所述导电层与所述源漏极层同层设置，并且所述第一绝缘层与所述层间介质层同层设置。
在一个或多个实施例中，在形成所述光敏传感器件之后，形成所述源漏极层。
在一个或多个实施例中，所述导电层与所述栅极层同层设置，所述第一绝缘层与所述栅极绝缘层同层设置，并且所述第二绝缘层与所述层间介质层同层设置。
在一个或多个实施例中，所述凹槽的深度小于或等于光敏传感器件的厚度。
在一个或多个实施例中，形成所述光敏传感器件包括：
依次沉积半导体材料的N型层、I型层和P型层；
在所述P型层上沉积第一透明导电层；以及
图形化所述半导体材料的N型层、I型层和P型层以及所述第一透明导电层，以形成所述光敏传感器件。
该显示器件为顶发射显示器件或者底发射显示器件。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本公开的其它特征、目的和优点将会变得更明显：
图1为本公开实施例提供的光学传感器件结构示意图；
图2为本公开实施例提供的光学传感器件制作方法流程图；
图3为本公开实施例提供的具体实施例中光学传感器件制作方法流程图；
[根据细则91更正 12.06.2019]　
图4a、4b、4c、4d、4e为本公开实施例提供的在制作过程中的光学传感器件结构示意图；
[根据细则91更正 12.06.2019]　
图5为本公开实施例提供的光学传感器件结构示意图。以及
[根据细则91更正 12.06.2019]　
图6为本公开实施例提供的光学传感器件制作方法流程图。
具体实施方式
下面结合附图和实施例对本公开作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关发明，而非对该发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与发明相关的部分。
需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本公开。
请参考图1，本公开实施例提供一种光学传感器件，包括显示区AA和非显示区DA。该光学传感器件包括诸如玻璃或树脂的基板1。在非显示区DA，该光学传感器件包括形成于基板1上的TFT。该TFT包括有源层4、栅极层6和源漏极层8。
在示例性实施例中，该光学传感器件包括布置在基板1和TFT之间的遮光层2。TFT的有源层4在基板1上的正投影落入遮光层2在基 板1上的正投影，从而减少或避免光线对有源层的照烧，由此减少TFT的关态电流(即漏电流)，提升显示品质。
在示例性实施例中，该光学传感器件包括设置在基板1上的缓冲层3。如图1所示，缓冲层3覆盖遮光层2和基板1。例如，缓冲层3包括氧化硅、氮化硅、氮氧化硅等绝缘材料。
为了降低有源层2和源漏极层8的接触电阻，改善TFT的性能，有源层4包括用于与源漏极层8接触的欧姆接触区，即源极接触区4S和漏极接触区4D。
例如，TFT还包括栅极绝缘层5和层间介质层7。栅极绝缘层5位于有源层4上方，栅极层6位于栅极绝缘层5上方，并且层间介质层7位于栅极层6上方。源漏极层8位于层间介质层7上方，并通过第二开孔7B与有源层4电连接，即分别与上述的源极接触区4S和漏极接触区4D电连接。在图1所示的示例性实施例中，第二开孔7B贯穿层间介质层7。
例如，TFT还包括第一钝化层9和第二钝化层12。第一钝化层9覆盖源漏极层8的表面。第二钝化层12覆盖第一钝化层9，并且提供大致平坦的表面。
在显示区AA，该光学传感器件包括光敏传感器件10。在显示区AA，该光学传感器件包括依次堆叠在基板1上的缓冲层3，层间介质层7，以及贯穿缓冲层3和层间介质层7的第一开孔7A。源漏极层8覆盖第一开孔7A的底部和侧壁。第一钝化层9至少覆盖源漏极层8的覆盖第一开孔7A的侧壁的部分，由此形成用于容纳光敏传感器件10的凹槽。光敏传感器件10填充该凹槽。即，光敏传感器件10设置在凹槽中的源漏极层8上，并且光敏传感器件10与覆盖第一开孔7A侧壁的源漏极层8之间设置有第一钝化层9。
由于光敏传感器件10设置在由第一开孔7A形成的该凹槽中，光敏传感器件10被源漏极层8的金属保护，避免了环境光对光敏传感器件关态电流的影响。由于第一钝化层9对光敏传感器件10的侧壁进行保护，在后续TFT制作过程中，光敏传感器件10的侧壁不会受损，进而提高显示器件的性能。在显示器件中添加该具有光敏传感器件和光学补偿控制TFT的光学传感器件，可以实现光学实时补偿，有效解决了EL器件亮度变化造成的显示Mura，提高了显示效果。
光敏传感器件10还包括第一透明导电层19以及第二透明导电层11。第二透明导电层11通过贯穿第二钝化层12的过孔与第一透明导电层19电连接，并且充当第一透明导电层19的引线。
在本公开实施例中，该凹槽的深度小于或等于光敏传感器件的厚度。凹槽的深度大于或等于光敏传感器件的厚度时，凹槽能更好的保护光敏传感器件的侧壁。当凹槽的深度大于光敏传感器件的厚度时，光敏传感器件上面的第一透明导电层19与源漏极层8发生容易短路。当较难做到凹槽的深度等于光敏传感器件的厚度时，凹槽的深度可以略小于光敏传感器件的厚度。
若层间介质层7厚度小于光敏传感器件10的厚度，可以在去除全部厚度的层间介质层7的基础上，进一步去除全部或部分厚度的缓冲层3，从而增加第一开孔7A的深度，进而增加该凹槽的深度。也就是说，第一开孔7A可以贯穿层间介质层7的部分厚度，贯穿层间介质层7的全部厚度，贯穿层间介质层7的全部厚度和缓冲层3的部分厚度，或者贯穿层间介质层7和缓冲层3二者的全部厚度(即图1所示的情形)。
继续参考图1，该光学传感器件还包括位于TFT上方的黑矩阵(Black Matrix，BM)13。该黑矩阵13限定非显示区DA并且围绕显示区AA。换言之，黑矩阵13限定显示区AA。该光学传感器件还包括在显示区AA中位于光敏传感器件10上方的彩膜层14。彩膜层14包括三个或多个彩膜单元，例如R、G、B彩膜单元，从而提供相应基色以实现彩色显示。
该光学传感器件还包括覆盖层(overcoating)15。覆盖层15包含树脂、SOG(Silicon On Glass，硅-玻璃键合结构材料)和BCB(苯并环丁烯)等平坦化材料，并且覆盖黑矩阵13和彩膜层14以提供大致平坦的上表面。
该光学传感器件还包括例如设置于非显示区DA的辅助电极16，设置在辅助电极16上方的隔垫物(Photo Spacer)17，以及阴极18。阴极18覆盖辅助电极16和隔垫物17的叠层，并且覆盖该覆盖层15的其余表面。辅助电极16包括Mo、Al、Ti、Au、Cu、Hf、Ta等常用金属，或其合金如AlNd，MoNb等，也可为多层金属如MoNb/Cu/MoNb、AlNd/Mo/AlNd等。辅助电极16与阴极18电连接。辅助电极的设置可 以降低显示装置由于阴极太薄、电阻太大而产生的电压降，使得显示装置具有良好的显示均匀性。
本公开实施例还相应提供一种光学传感器件制作方法，所述光学传感器件包括显示区和非显示区，并且所述方法包括：在所述显示区，依次形成有源层、栅极绝缘层、栅极层、源漏极层和层间介质层以形成薄膜晶体管，所述栅极绝缘层配置成将所述有源层和所述栅极层绝缘，并且所述层间介质层配置成将所述栅极层和所述源漏极层绝缘。所述方法还包括：在所述非显示区，形成第一绝缘层，在所述第一绝缘层内形成第一开孔，形成导电层和第二绝缘层，以及在所述第一开孔内形成光敏传感器件，其中所述导电层与所述源漏极层或者所述栅极层同层设置。
结合图2，示例性描述如图1所示的光学传感器件的制作方法。例如，该方法包括：
步骤S201、在对应光敏传感器件的位置去除层间介质材料层形成第一开孔；
步骤S202、沉积源漏极材料层，该源漏极材料层覆盖第一开孔的底部和侧壁；
步骤S203、在该源漏极材料层上制作第一钝化层，该第一钝化层至少覆盖源漏极材料层的覆盖第一开孔的侧壁的部分以形成凹槽；
步骤S204、在该凹槽中的源漏极材料层上制作光敏传感器件；以及
步骤S205、图形化源漏极材料层以形成源漏极层。
由于光敏传感器件设置在凹槽中，且具有钝化层对其侧壁进行保护，所以，后续的TFT制作过程中，光敏传感器件的侧壁不会受损。这提高显示器件的性能，提高显示效果。
以PIN型PD作为光敏传感器件的例子。PD通常包括(同一)半导体材料的P型层(以空穴作为载流子传导电荷的层)、I型层(本征层)和N型层(以电子作为载流子传导电荷的层)。PD的P型层和N型层通常是采用对非晶硅掺杂而形成的，这个过程中会引入大量的H(氢)，H很容易扩散到TFT，从而严重影响TFT的特性。通过该方法，在形成源漏极材料层之后但是在图形化源漏极材料层以形成源漏极层之前制作光敏传感器件，由于源漏极材料层的遮挡，避免了H扩 散到TFT，从而提高显示器件的性能，提高显示效果。
进一步，凹槽的深度等于光敏传感器件的厚度。凹槽的深度等于光敏传感器件的厚度时，凹槽对光敏传感器件具有较好的保护作用，若较难做到等于，凹槽的深度可以略小于光敏传感器件的厚度，从而防止第一透明导电层与源漏极层发生短路。
进一步，当层间介质层厚度小于光敏传感器件的厚度时，在对应光敏传感器件的位置去除全部或部分厚度的层间介质材料层形成凹槽，包括：
在对应光敏传感器件的位置去除全部厚度的层间介质材料层和全部或部分厚度的缓冲层材料形成凹槽。
进一步，步骤S204中，在凹槽中的源漏极层上制作光敏传感器件，包括：
依次沉积半导体材料的N型层、I型层和P型层；
在P型层上沉积第一透明导电层；以及
图形化该N型层、I型层和P型层以及该第一透明导电层，以形成光敏传感器件。
由于连续沉积光敏传感器件的N型层、I型层、P型层和第一透明导电层，一次刻蚀工艺完成图形化，工艺步骤简单，节约成本。
下面对光学传感器件的制作工艺进行详细说明，如图3所示，包括下述步骤S301-S308。
步骤S301、如图4a所示，在基板1上沉积金属材料，之后涂覆光刻胶，通过刻蚀进行图形化以形成金属遮光层2。该金属材料可为Mo、Al、Ti、Au、Cu、Hf、Ta等常用金属，也可为AlNd、MoNb等合金。
步骤S302、如图4a所示，依次沉积缓冲层3和有源材料层，然后通过湿刻图形化该有源材料层以形成有源层4。缓冲层3例如包括氧化硅、氮化硅、氮氧化硅等绝缘材料。有源层4例如包括金属氧化物材料，如IGZO材料。
步骤S303、如图4a所示，依次沉积栅极绝缘材料层和栅极材料层，并且涂覆光刻胶。利用一块掩膜版先湿刻栅极材料层以形成栅极层6。接着利用栅极层6为掩模版，干刻栅极绝缘材料层以形成栅极绝缘层5，由此形成栅极绝缘层5和栅极层6的叠层。栅极绝缘层5材料可为氧化硅、氮化硅、氮氧化硅等绝缘材料。栅极层6材料可为Mo、Al、Ti、 Au、Cu、Hf、Ta等常用金属，也可为Cu工艺制程，如MoNd/Cu/MoNd。
可选地，步骤S303还包括以利用栅极层6，或者利用栅极绝缘层5和栅极层6的叠层为掩模版，对有源层4的露出区域进行离子注入，以形成有源层4的欧姆接触区，即源极接触区4S和漏极接触区4D。
步骤S304、如图4a所示，沉积层间介质层7，通过光刻进行图形化，以形成第一开孔7A和第二开孔7B。第一开孔7A位于显示区AA，并且位于层间介质层7中。例如，在图4a所示实施例中，第一开孔7A贯穿层间介质层7和缓冲层3以露出基板1的表面。第二开孔7B位于非显示区DA，贯穿层间介质层7并且露出有源层4的欧姆接触区，即源极接触区4S和漏极接触区4D。
步骤S305、如图4b所示，依次沉积源漏极材料层8′和第一钝化材料层，并图形化该第一钝化材料层以形成第一钝化层9。源漏极材料层8′覆盖第一开孔7A的底部和侧壁。第一钝化层9至少覆盖源漏极材料层8′的覆盖第一开孔7A的侧壁的部分，由此形成用于容纳光敏传感器件10的凹槽。
步骤S306、如图4c所示，通过PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)依次沉积PIN型光敏传感器件10的N型半导体层、I型半导体层和P型半导体层。该半导体层可以是无机半导体，也可以是有机半导体。I型半导体层为本征半导体层，N型半导体层为磷或砷掺杂的半导体层，P型半导体层为硼掺杂的半导体。然后沉积第一透明导电材料层。只用一块掩膜版先湿刻后干刻进行图形化，以形成光敏传感器件10的图形化的N型半导体层、I型半导体层和P型半导体层的叠层，以及位于光敏传感器件10上并且与其电连接的第一透明导电层19。第一透明导电层19充当光敏传感器件10的电极。
步骤S307、如图4d所示，通过湿刻图形化源漏极材料层8′以形成源漏极层8。源漏极层8例如包括Mo、Al、Ti、Au、Cu、Hf、Ta等常用金属，也可采用Cu工艺制程，例如包括MoNd/Cu/MoNd。
步骤S308、如图4e所示，沉积第二钝化层12，通过图形化以形成过孔(Via)。沉积第二透明导电材料层以填充该过孔，并且图形化该第二透明导电材料层，以形成第二透明导电层11。该第二透明导电层11作为第一透明导电层19的引线。
至此光学传感器件制作完成，如果是制作顶发射显示器件，后续工艺包括下述步骤S309-S313。
步骤S309、如图1所示，沉积黑矩阵材料层并图形化，以在非显示区DA中形成位于TFT上方的黑矩阵13。
步骤S310、如图1所示，在显示区AA中形成彩膜层14。形成彩膜层14包括依次沉积R、G、B彩膜单元。与黑矩阵13邻接的各彩膜单元部分地覆盖黑矩阵13，以防止漏光和串扰。
步骤S311、如图1所示，沉积覆盖层15，并且通过沉积和图形化以形成辅助电极16。覆盖层15的材料包含但不限于树脂、SOG(Silicon On Glass，硅-玻璃键合结构材料)和BCB(苯并环丁烯)等平坦化材料。辅助电极16的材料可为Mo、Al、Ti、Au、Cu、Hf、Ta等常用金属，或其合金如AlNd，MoNb等，也可为多层金属如MoNb/Cu/MoNb、AlNd/Mo/AlNd等。
步骤S312、如图1所示，在非显示区DA中，在辅助电极16上沉积隔垫物材料层，并且图形化以形成隔垫物17。
步骤S313、如图1所示，沉积透明导电氧化物(TCO)薄膜作为透明阴极18。阴极18的材料包含但不限于透明导电氧化物，如AZO、IZO、AZTO或其组合。例如阴极18的材料也可以是较薄的金属材料，如Mg/Ag、Ca/Ag、Sm/Ag、Al/Ag、Ba/Ag等复合材料。
通过以上步骤，TFT盖板部分制作完成。
上述实施方案设计了顶栅自对准结构的控制TFT，该技术方案同样适用于ESL(蚀刻阻挡层)型TFT、BCE(背沟道蚀刻)型TFT等。有源层材料为诸如IGZO的氧化物半导体，也可以是a-Si等材料。
应当注意，尽管在附图中以特定顺序描述了本公开方法的操作，但是，这并非要求或者暗示必须按照该特定顺序来执行这些操作，或是必须执行全部所示的操作才能实现期望的结果。相反，流程图中描绘的步骤可以改变执行顺序。附加地或备选地，可以省略某些步骤，将多个步骤合并为一个步骤执行，和/或将一个步骤分解为多个步骤执行。
本公开实施例还相应提供一种显示器件，包括本公开上述实施例提供的光学传感器件。
该显示器件还可以包括：
设置在光学传感器件上的黑矩阵；
覆盖光敏传感器件并部分覆盖黑矩阵的彩膜层；
设置在黑矩阵和彩膜层上的覆盖层；
设置在覆盖层上的隔垫物层；
设置在隔垫物层上的辅助电极；以及
覆盖覆盖层、隔垫物层和辅助电极的透明阴极。
该显示器件为顶发射显示器件或者底发射显示器件。
在图1所示的光学传感器件中，第一开孔7A位于层间介质层7内，至少贯穿层间介质层7的部分厚度。例如，第一开孔7A贯穿层间介质层7以及缓冲层3。光敏传感器件10设置在由第一开孔7A形成的凹槽内。图5示出了该光学传感器件的一种变型。该变型与图1所示实施例的不同之处仅在于显示区AA中第一开孔7A和凹槽的设置方式不同。如图5所示，在显示区AA，该光学传感器件包括依次堆叠在基板1上的缓冲层3，栅极绝缘材料层5′，以及贯穿缓冲层3和栅极绝缘材料层5′的第一开孔7A。栅极绝缘材料层5′与栅极绝缘层5同层设置。栅极材料层6′与栅极层6同层设置，并且覆盖第一开孔7A的底部和侧壁。层间介质层7至少覆盖栅极材料层6′的覆盖第一开孔7A的侧壁的部分，由此形成用于容纳光敏传感器件10的凹槽。光敏传感器件10填充该凹槽。即，光敏传感器件10设置在凹槽中的栅极材料层6′上，且光敏传感器件10与覆盖第一开孔7A侧壁的栅极材料层6′之间设置有层间介质层7。
应指出，在本公开的上下文中，第一部件和第二部件同层设置是指第一部件和第二部件的材料相同并且通过同一图形化工艺形成。
由于光敏传感器件10设置在由第一开孔7A形成的该凹槽中，光敏传感器件10被栅极材料层6′的金属保护，避免了环境光对光敏传感器件关态电流的影响。由于层间介质层7对光敏传感器件10的侧壁进行保护，在后续TFT制作过程中，光敏传感器件10的侧壁不会受损，进而提高显示器件的性能。
与图1实施例类似，第一开孔7A可以贯穿栅极绝缘材料层5′的部分厚度，贯穿栅极绝缘材料层5′的全部厚度，贯穿栅极绝缘材料层5′的全部厚度和缓冲层3的部分厚度，或者贯穿栅极绝缘材料层5′和缓冲层3二者的全部厚度(即图5所示的情形)。
[根据细则91更正 12.06.2019]　
下文简要描述图5所示的光学传感器件制作方法。如图6所示，该方法例如包括：
步骤S601、在对应光敏传感器件的位置去除栅极绝缘材料层形成第一开孔；
步骤S602、沉积栅极材料层，该栅极材料层覆盖第一开孔的底部和侧壁；
步骤S603、在该栅极材料层上制作层间介质层，该层间介质层至少覆盖栅极材料层的覆盖第一开孔的侧壁的部分以形成凹槽；以及
步骤S604、在该凹槽中的栅极材料层上制作光敏传感器件。
本公开实施例提供一种光学传感器件及其制作方法、显示器件。由于光敏传感器件设置在第一开孔中，光敏传感器件被源漏极层或栅极层的金属保护，避免了环境光对光敏传感器件关态电流的影响，此外，由于钝化层对其侧壁进行保护，所以，后续的TFT制作过程中，光敏传感器件的侧壁不会受损，进而提高显示器件的性能，提高显示效果。在显示器件中添加该具有光敏传感器件即光敏传感器件和光学补偿控制TFT的光学传感器件，可以实现光学实时补偿，有效解决了EL器件亮度变化造成的显示Mura，提高了显示效果。
以上描述仅为本公开的优选实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本公开中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本公开中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (20)

  1. 一种光学传感器件，包括显示区和非显示区，
    其中在所述显示区，所述光学传感器件包括薄膜晶体管，所述薄膜晶体管包括有源层、栅极绝缘层、栅极层、源漏极层和层间介质层，所述栅极绝缘层配置成将所述有源层和所述栅极层绝缘，并且所述层间介质层配置成将所述栅极层和所述源漏极层绝缘，
    其中在所述非显示区，所述光学传感器件包括依次堆叠的第一绝缘层、导电层和第二绝缘层，并且所述导电层与所述源漏极层或者所述栅极层同层设置，以及
    其中在所述非显示区，所述第一绝缘层设有第一开孔，所述光学传感器件还包括光敏传感器件，所述光敏传感器件位于所述第一开孔内。
  2. 如权利要求1所述的光学传感器件，其中所述导电层覆盖所述第一开孔的底部和侧壁，所述第二绝缘层至少覆盖所述导电层的覆盖所述第一开孔的侧壁的部分以形成凹槽，并且所述光敏传感器件设置在所述凹槽内。
  3. 如权利要求1所述的光学传感器件，其中所述凹槽的深度小于或等于所述光敏传感器件的厚度。
  4. 如权利要求2所述的光学传感器件，其中所述光学传感器件还包括在所述显示区和所述非显示区位于基板上的缓冲层，并且所述第一开孔贯穿所述第一绝缘层的全部厚度和所述缓冲层的至少部分厚度。
  5. 如权利要求2所述的光学传感器件，其中所述光学传感器件为PIN型光敏二极管，并且包括依次堆叠的半导体材料的N型层、I型层和P型层。
  6. 如权利要求5所述的光学传感器件，其中所述半导体材料的N型层与所述导电层电连接。
  7. 如权利要求1所述的光学传感器件，其中所述导电层与所述源漏极层同层设置，并且所述第一绝缘层与所述层间介质层同层设置。
  8. 如权利要求7所述的光学传感器件，其中所述光学传感器件还包括在所述显示区覆盖所述源漏极层的第一钝化层，并且所述第二绝 缘层与所述第一钝化层同层设置。
  9. 如权利要求7所述的光学传感器件，其中所述导电层与所述源漏极层其中之一为一体部件。
  10. 如权利要求1所述的光学传感器件，其中所述导电层与所述栅极层同层设置，所述第一绝缘层与所述栅极绝缘层同层设置，并且所述第二绝缘层与所述层间介质层同层设置。
  11. 一种显示器件，包括如权利要求1-10中任一所述的光学传感器件。
  12. 如权利要求11所述的显示器件，还包括：
    黑矩阵，其位于所述光学传感器件上并且限定所述显示区；
    彩膜层，其位于所述显示区，覆盖所述光敏传感器件并部分覆盖所述黑矩阵；
    覆盖层，其位于所述黑矩阵和所述彩膜层上；
    隔垫物层，其位于所述非显示区并且在所述覆盖层上；
    辅助电极，其设置在所述隔垫物层上；以及
    透明阴极，其覆盖所述辅助电极、所述隔垫物层和所述覆盖层，并且与所述辅助电极电连接。
  13. 一种光学传感器件制作方法，其中所述光学传感器件包括显示区和非显示区，并且所述方法包括：
    在所述显示区，依次形成有源层、栅极绝缘层、栅极层、源漏极层和层间介质层以形成薄膜晶体管，所述栅极绝缘层配置成将所述有源层和所述栅极层绝缘，并且所述层间介质层配置成将所述栅极层和所述源漏极层绝缘，并且
    在所述非显示区，形成第一绝缘层，在所述第一绝缘层内形成第一开孔，形成导电层和第二绝缘层，以及在所述第一开孔内形成光敏传感器件，其中所述导电层与所述源漏极层或者所述栅极层同层设置。
  14. 如权利要求13所述的方法，其中形成所述导电层包括，形成所述导电层以覆盖所述第一开孔的底部和侧壁，
    形成所述第二绝缘层包括，形成所述第二绝缘层以至少覆盖所述导电层的覆盖所述第一开孔的侧壁的部分以形成凹槽，以及
    形成所述光敏传感器件包括，在所述凹槽内形成所述光敏传感器件。
  15. 如权利要求14所述的方法，还包括：在形成所述有源层之前，在所述显示区和所述非显示区中，在基板上形成缓冲层，并且
    其中形成所述第一开孔包括，形成所述第一开孔，以贯穿所述第一绝缘层的全部厚度和所述缓冲层的至少部分厚度。
  16. 如权利要求13所述的方法，其中所述导电层与所述源漏极层同层设置，并且所述第一绝缘层与所述层间介质层同层设置。
  17. 如权利要求16所述的方法，其中在形成所述光敏传感器件之后，形成所述源漏极层。
  18. 如权利要求13所述的方法，其中所述导电层与所述栅极层同层设置，所述第一绝缘层与所述栅极绝缘层同层设置，并且所述第二绝缘层与所述层间介质层同层设置。
  19. 如权利要求14的方法，其中所述凹槽的深度小于或等于光敏传感器件的厚度。
  20. 如权利要求4所述的方法，其中形成所述光敏传感器件包括：
    依次沉积半导体材料的N型层、I型层和P型层；
    在所述P型层上沉积第一透明导电层；以及
    图形化所述半导体材料的N型层、I型层和P型层以及所述第一透明导电层，以形成所述光敏传感器件。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI812253B (zh) * 2022-01-19 2023-08-11 友達光電股份有限公司 感測裝置及其製造方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108807556B (zh) 2018-06-11 2021-01-29 京东方科技集团股份有限公司 一种光学传感器件及其制作方法、显示器件、显示设备
CN109616054B (zh) * 2019-02-27 2020-07-28 Oppo广东移动通信有限公司 亮度补偿方法、显示器及计算机存储介质
CN111430386B (zh) * 2020-04-01 2023-11-10 京东方科技集团股份有限公司 光电探测器、显示基板及光电探测器的制作方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104681655A (zh) * 2015-01-12 2015-06-03 京东方科技集团股份有限公司 一种探测基板及其制备方法、探测器
US20150349016A1 (en) * 2013-01-17 2015-12-03 Silicon Display Technology Image sensor for x-ray and method of manufacturing the same
CN105789226A (zh) * 2016-05-10 2016-07-20 京东方科技集团股份有限公司 指纹采集器件及其制作方法、指纹采集面板及显示面板
CN106684202A (zh) * 2017-01-04 2017-05-17 京东方科技集团股份有限公司 一种感光组件、指纹识别面板及装置
CN107611159A (zh) * 2017-08-28 2018-01-19 惠科股份有限公司 显示面板及其制造方法与显示装置
CN107978609A (zh) * 2017-11-23 2018-05-01 上海中航光电子有限公司 一种阵列基板及显示装置
CN108807556A (zh) * 2018-06-11 2018-11-13 京东方科技集团股份有限公司 一种光学传感器件及其制作方法、显示器件、显示设备

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030089929A1 (en) * 2001-02-14 2003-05-15 Rhodes Howard E. Trench photosensor for a CMOS imager
KR101333783B1 (ko) * 2009-11-10 2013-11-29 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
KR101881133B1 (ko) * 2011-06-29 2018-07-24 삼성디스플레이 주식회사 절연층의 경사 구조 형성 방법, 유기 발광 표시 장치 및 유기 발광 표시 장치의 제조 방법
JP5558446B2 (ja) * 2011-09-26 2014-07-23 株式会社東芝 光電変換装置及びその製造方法
CN103311265B (zh) * 2012-03-08 2016-05-18 群康科技(深圳)有限公司 有机发光二极管显示面板及其制造方法
US20150187830A1 (en) * 2013-12-31 2015-07-02 Shenzhen China Star Optoelectronics Technology Co., Ltd. Photosensitive unit, array substrate of display panel and manufacturing method thereof
CN104022181B (zh) * 2014-05-26 2016-05-18 武汉电信器件有限公司 一种光电二极管的制作方法
CN106941108B (zh) 2017-05-23 2019-09-17 深圳市华星光电技术有限公司 微发光二极管显示面板及其制作方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150349016A1 (en) * 2013-01-17 2015-12-03 Silicon Display Technology Image sensor for x-ray and method of manufacturing the same
CN104681655A (zh) * 2015-01-12 2015-06-03 京东方科技集团股份有限公司 一种探测基板及其制备方法、探测器
CN105789226A (zh) * 2016-05-10 2016-07-20 京东方科技集团股份有限公司 指纹采集器件及其制作方法、指纹采集面板及显示面板
CN106684202A (zh) * 2017-01-04 2017-05-17 京东方科技集团股份有限公司 一种感光组件、指纹识别面板及装置
CN107611159A (zh) * 2017-08-28 2018-01-19 惠科股份有限公司 显示面板及其制造方法与显示装置
CN107978609A (zh) * 2017-11-23 2018-05-01 上海中航光电子有限公司 一种阵列基板及显示装置
CN108807556A (zh) * 2018-06-11 2018-11-13 京东方科技集团股份有限公司 一种光学传感器件及其制作方法、显示器件、显示设备

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI812253B (zh) * 2022-01-19 2023-08-11 友達光電股份有限公司 感測裝置及其製造方法

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