CN108807556B - 一种光学传感器件及其制作方法、显示器件、显示设备 - Google Patents

一种光学传感器件及其制作方法、显示器件、显示设备 Download PDF

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CN108807556B
CN108807556B CN201810594582.9A CN201810594582A CN108807556B CN 108807556 B CN108807556 B CN 108807556B CN 201810594582 A CN201810594582 A CN 201810594582A CN 108807556 B CN108807556 B CN 108807556B
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CN108807556A (zh
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王国英
宋振
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BOE Technology Group Co Ltd
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Abstract

本申请公开了一种光学传感器件及其制作方法、显示器件、显示设备，涉及显示技术，在对应PIN器件的位置设置有去除全部或部分厚度的层间介质层所形成凹槽，源漏极层覆盖凹槽的底部和侧壁，PIN器件设置在凹槽中的源漏极层上，且PIN器件与覆盖凹槽侧壁的源漏极层之间设置有钝化层。由于PIN器件设置在凹槽中，凹槽中的PIN器件被源漏极层的金属保护，避免了环境光对PIN关态电流的影响，且具有钝化层对其侧壁进行保护，所以，后续的TFT制作过程中，不会使PIN器件的侧壁受损，进而提高显示器件的性能，提高显示效果；由于添加了光敏Sensor即PIN器件和光学补偿控制TFT，可以实现光学实时补偿，有效解决了EL器件亮度变化造成的显示Mura，提高了显示效果。

Description

一种光学传感器件及其制作方法、显示器件、显示设备
技术领域
本公开一般涉及显示技术，尤其涉及一种光学传感器件及其制作方法、显示器件、显示设备。
背景技术
现有的电路补偿方案是电学补偿，它只能对TFT(Thin Film Transistor，薄膜晶体管)阈值电压和迁移率变化造成的显示Mura(显示器亮度不均匀，造成各种痕迹的现象)进行补偿，但是无法应对OLED器件老化引起的亮度变化的补偿。虽然可以在panel(面板)出厂时对panel整体进行一次光学补偿，但无法解决伴随EL(electroluminescence，冷光片)效率衰减造成的Mura，即无法实现光学实时补偿。因此需要引入光学传感器内置补偿，即在OLED(Organic Light-Emitting Diode，有机发光二极管)显示器件添加了PIN(光敏二极管P-I-N)器件，用于实时监控EL亮度变化，通过外围IC(integratedcircuit，集成电路)计算对panel进行实时光学补偿。
通常做法是在做TFT过程中做光敏Sensor即PIN器件，在PIN制作完成后，TFT的后续制备过程中的湿刻工艺会对使PIN侧壁受损，造成PIN漏电流增大，影响显示器件的性能。
发明内容
鉴于现有技术中的上述缺陷或不足，期望提供涉及一种光学传感器件及其制作方法、显示器件、显示设备，以提高显示器件的性能，提高显示效果。
第一方面，本发明实施例提供一种光学传感器件，包括层间介质层、源漏极层和PIN器件，其中：
对应PIN器件的位置设置有去除全部或部分厚度的层间介质层所形成凹槽，所述源漏极层覆盖所述凹槽的底部和侧壁，所述PIN器件设置在所述凹槽中的源漏极层上，且所述PIN器件与覆盖凹槽侧壁的源漏极层之间设置有钝化层。
进一步，所述凹槽的深度小于或等于所述PIN器件的高度。
更进一步，还包括缓冲层，设置在所述层间介质层下面；
所述层间介质层厚度小于PIN器件的高度时，所述凹槽为去除全部厚度的层间介质层和全部或部分厚度的缓冲层形成的凹槽。
第二方面，本发明实施例提供一种光学传感器件制作方法，包括：
在对应PIN器件的位置去除全部或部分厚度的层间介质层材料形成凹槽；
沉积源漏极层，所述源漏极层覆盖所述凹槽的底部和侧壁；
在所述源漏极层上制作钝化层图形，所述钝化层图形覆盖所述凹槽的侧壁；
在所述凹槽中的源漏极层上制作PIN器件；
图形化所述源漏极层。
进一步，凹槽的深度小于或等于PIN器件的高度。
进一步，当所述层间介质层厚度小于PIN器件的高度时，在对应PIN器件的位置去除全部或部分厚度的层间介质层材料形成凹槽，具体包括：
在对应PIN器件的位置去除全部厚度的层间介质层材料和全部或部分厚度的缓冲层材料形成凹槽。
进一步，所述在所述凹槽中的源漏极层上制作PIN器件，具体包括：
依次沉积N区、I区、P区三种半导体材料；
在所述P区上沉积第一透明导电层；
图形化形成PIN器件。
第三方面，本发明实施例提供一种显示器件，包括如第一方面中所述的光学传感器件。
进一步，还包括：
设置在所述光学传感器件上的黑矩阵；
覆盖PIN器件并部分覆盖所述黑矩阵的彩膜；
设置在所述黑矩阵和所述彩膜上的有机覆盖层；
设置在所述有机覆盖层上的隔垫物层；
设置在所述隔垫物层上的辅助电极；以及
覆盖所述有机覆盖层、所述隔垫物层和所述辅助电极的透明阴极。
第四方面，本发明实施例提供一种显示设备，包括如第一方面中所述的光学传感器件。
进一步，该显示设备为顶发射显示设备或者底发射显示设备。
本发明实施例提供一种光学传感器件及其制作方法、显示器件、显示设备，在对应PIN器件的位置设置有去除全部或部分厚度的层间介质层所形成凹槽，源漏极层覆盖凹槽的底部和侧壁，PIN器件设置在凹槽中的源漏极层上，且PIN器件与覆盖凹槽侧壁的源漏极层之间设置有钝化层。由于PIN器件设置在凹槽中，凹槽中的PIN器件被源漏极层的金属保护，避免了环境光对PIN关态电流的影响，且具有钝化层对其侧壁进行保护，所以，后续的TFT制作过程中，不会使PIN器件的侧壁受损，进而提高显示器件的性能，提高显示效果。在显示器件中添加该具有光敏Sensor即PIN器件和光学补偿控制TFT的光学传感器件，可以实现光学实时补偿，有效解决了EL器件亮度变化造成的显示Mura，提高了显示效果。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显：
图1为本发明实施例提供的光学传感器件结构示意图；
图2为本发明实施例提供的光学传感器件制作方法流程图；
图3为本发明实施例提供的具体实施例中光学传感器件制作方法流程图；
图4-图8为本发明实施例提供的在制作过程中的光学传感器件结构示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关发明，而非对该发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与发明相关的部分。
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
请参考图1，本发明实施例提供一种光学传感器件，包括层间介质层7、源漏极层8和PIN器件10，其中：
对应PIN器件10的位置设置有去除全部或部分厚度的层间介质层7所形成凹槽，源漏极层8覆盖凹槽的底部和侧壁，PIN器件10设置在凹槽中的源漏极层8上，且PIN器件10与覆盖凹槽侧壁的源漏极层8之间设置有钝化层9。
由于PIN器件10设置在凹槽中，凹槽中的PIN器件10被源漏极层8的金属保护，避免了环境光对PIN关态电流的影响，且具有钝化层9对其侧壁进行保护，所以，后续的TFT制作过程中，不会使PIN器件10的侧壁受损，进而提高显示器件的性能，提高显示效果。在显示器件中添加该具有光敏Sensor即PIN器件和光学补偿控制TFT的光学传感器件，可以实现光学实时补偿，有效解决了EL器件亮度变化造成的显示Mura，提高了显示效果。
凹槽的深度小于或等于PIN器件的高度较佳，凹槽的深度大于或等于PIN器件的高度时，凹槽能更好的保护PIN器件10的侧壁，但凹槽的深度大于PIN器件的高度时，容易导致PIN器件10上面的第一透明导电层19与源漏极层8发生短路，所以，当较难做到凹槽的深度等于PIN器件的高度时，凹槽的深度可以略小于PIN器件的高度。
进一步，层间介质层7下面设置有缓冲层3，若层间介质层7厚度小于PIN器件的高度，可以在去除全部厚度的层间介质层7的基础上，进一步去除全部或部分厚度的缓冲层3，从而增加凹槽的深度。
本发明实施例还相应提供一种光学传感器件制作方法，如图2所示，包括：
步骤S201、在对应PIN器件的位置去除层间介质层材料形成凹槽；
步骤S202、沉积源漏极层，源漏极层覆盖凹槽的底部和侧壁；
步骤S203、在源漏极层上制作钝化层图形，钝化层图形覆盖凹槽的侧壁；
步骤S204、在凹槽中的源漏极层上制作PIN器件；
步骤S205、图形化源漏极层。
由于PIN器件设置在凹槽中，且具有钝化层对其侧壁进行保护，所以，后续的TFT制作过程中，不会对PIN器件的侧壁受损，进而提高显示器件的性能，提高显示效果。
同时，由于PIN器件材料采用是非晶硅参杂形成P区、I区、N区，但是在制备PIN器件的过程中会引入大量的H(氢)，H很容易扩散到其下部的TFT，从而严重影响TFT的特性，通过该方法，在图形化源漏极层之前制作PIN器件，由于源漏极层材料的遮挡，避免了H扩散到下部的TFT，从而提高显示器件的性能，提高显示效果。
进一步，凹槽的深度等于PIN器件的高度较佳，凹槽的深度等于PIN器件的高度时，凹槽对PIN器件具有较好的保护作用，若较难做到等于，凹槽的深度可以略小于PIN器件的高度，从而防止第一透明导电层与源漏极层发生短路。
进一步，当层间介质层厚度小于PIN器件的高度时，在对应PIN器件的位置去除全部或部分厚度的层间介质层材料形成凹槽，具体包括：
在对应PIN器件的位置去除全部厚度的层间介质层材料和全部或部分厚度的缓冲层材料形成凹槽。
进一步，步骤S204中，在凹槽中的源漏极层上制作PIN器件，具体包括：
依次沉积N区、I区、P区三种半导体材料；
在P区上沉积第一透明导电层；
图形化形成PIN器件。
由于连续沉积PIN器件的N区、I区、P区和第一透明导电层，一次刻蚀工艺完成图形化，工艺步骤简单，节约成本。
下面对光学传感器件的制作步骤进行详细说明，如图3所示，包括：
步骤S301、如图4所示，在玻璃盖板1上沉积金属，之后涂覆光刻胶，刻蚀图形化形成Shield(遮光)金属图形2，金属材料可为Mo、Al、Ti、Au、Cu、Hf、Ta等常用金属，也可为AlNd、MoNb等合金；
步骤S302、如图4所示，依次沉积Buffer(缓冲)层3、Act(有源)层4，然后湿刻图形化Act层4形成有源岛；其中Buffer层3材料可为氧化硅、氮化硅、氮氧化硅等绝缘材料，Act层4材料可为金属氧化物材料，如IGZO材料；
步骤S303、如图4所示，依次沉积(栅极绝缘)层5、Gate(栅极)层6，涂覆光刻胶，其中Gate、GI利用一块掩膜版先湿刻Gate层6，后干刻GI层5实现图形化；其中GI层5材料可为氧化硅、氮化硅、氮氧化硅等绝缘材料，Gate层6材料可为Mo、Al、Ti、Au、Cu、Hf、Ta等常用金属，也可为Cu工艺制程，如MoNd/Cu/MoNd；
步骤S304、如图4所示，沉积ILD(层间介质)层7，光刻图形化形成ILD孔和CNT孔，CNT孔使得ILD层7和Buffer层3被刻穿至下层玻璃盖板1；
步骤S305、如图5所示，淀积源漏极层8和第一PVX(钝化)层9并图形化第一PVX层9，形成凹槽结构；
步骤S306、如图6所示，通过PECVD(Plasma Enhanced Chemical VaporDeposition，等离子体增强化学气相沉积法)依次沉积N、I、P三种无机(或有机)半导体(I为本征半导体，N为磷或砷掺杂半导体，P为硼掺杂半导体)，然后沉积第一透明导电层19，只用一块掩膜版先湿刻后干刻图形化形成PIN器件10和PIN器件10上面的第一透明导电层19图案，第一透明导电层19是PIN器件10的电极；
步骤S307、如图7所示，湿刻并图形化源漏极层8，形成SD源漏电极；
步骤S308、如图8所示，沉积第二PVX(绝缘)层12，图形化形成过孔(Via)，沉积一层第二透明导电层11并图形化，该第二透明导电层11作为第一透明导电层19的引线；
至此光学传感器件制作完成，如果是制作顶发射玻璃盖板，后续工艺为：
步骤S309、如图1所示，沉积BM(Black Matrix，黑色矩阵)13并图形化，使得BM13覆盖有源矩阵TFT；
步骤S310、如图1所示，沉积CF(彩膜)，其中CF层14制备时先后沉积R、G、B各彩膜，并使彩膜对BM13有一定的覆盖；
步骤S311、如图1所示，沉积OC(有机覆盖)层15和辅助电极16并图形化，OC材料包含但不限于Resin(树脂)、SOG(Silicon On Glass，硅-玻璃键合结构材料)和BCB(苯并环丁烯)等平坦化材料，辅助电极15材料可为Mo、Al、Ti、Au、Cu、Hf、Ta等常用金属，或其合金如AlNd，MoNb等，也可为多层金属如MoNb/Cu/MoNb、AlNd/Mo/AlNd等；
步骤S312、如图1所示，沉积PS(Photo Spacer，隔垫物)17层材料并形成图形；
步骤S313、如图1所示，淀积一层TCO(透明导电氧化物)薄膜作为透明阴极18，TCO材料包含但不限于透明导电氧化物，如AZO、IZO、AZTO或其组合，也可以是较薄的金属材料，如Mg/Ag、Ca/Ag、Sm/Ag、Al/Ag、Ba/Ag等复合材料。
通过以上步骤，TFT盖板部分制作完成。
上述实施方案设计了顶栅自对准结构的控制TFT，该技术方案同样适用于ESL、BCE等结构TFT；其有源层材料为IGZO氧化物半导体，也可以是a-Si等材料。
应当注意，尽管在附图中以特定顺序描述了本发明方法的操作，但是，这并非要求或者暗示必须按照该特定顺序来执行这些操作，或是必须执行全部所示的操作才能实现期望的结果。相反，流程图中描绘的步骤可以改变执行顺序。附加地或备选地，可以省略某些步骤，将多个步骤合并为一个步骤执行，和/或将一个步骤分解为多个步骤执行。
本发明实施例还相应提供一种显示器件，包括本发明实施例提供的光学传感器件。
在该显示器件中，还可以包括：
设置在光学传感器件上的黑矩阵；
覆盖PIN器件并部分覆盖黑矩阵的彩膜；
设置在黑矩阵和彩膜上的有机覆盖层；
设置在有机覆盖层上的隔垫物层；
设置在隔垫物层上的辅助电极；以及
覆盖有机覆盖层、隔垫物层和辅助电极的透明阴极。
本发明实施例还相应提供一种显示设备，包括本发明实施例提供的光学传感器件。
进一步，该显示设备为顶发射显示设备或者底发射显示设备。
以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本申请中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (7)

1.一种光学传感器件，其特征在于，包括层间介质层、源漏极层和PIN器件，其中：
所述层间介质层位于所述源漏极层下方，对应PIN器件的位置设置有去除全部或部分厚度的层间介质层所形成凹槽，所述源漏极层覆盖所述凹槽的底部和侧壁，所述PIN器件设置在所述凹槽中的源漏极层上，且所述PIN器件与覆盖凹槽侧壁的源漏极层之间设置有钝化层，所述凹槽的深度小于或等于所述PIN器件的高度。
2.如权利要求1所述的光学传感器件，其特征在于，还包括缓冲层，设置在所述层间介质层下面；
所述层间介质层厚度小于PIN器件的高度时，所述凹槽为去除全部厚度的层间介质层和全部或部分厚度的缓冲层形成的凹槽。
3.一种光学传感器件制作方法，其特征在于，包括：
在对应PIN器件的位置去除全部或部分厚度的层间介质层材料形成凹槽；
沉积源漏极层，所述源漏极层覆盖所述凹槽的底部和侧壁；
在所述源漏极层上制作钝化层图形，所述钝化层图形覆盖所述凹槽的侧壁；
在所述凹槽中的源漏极层上制作PIN器件，凹槽的深度小于或等于PIN器件的高度；
图形化所述源漏极层。
4.如权利要求3所述的方法，其特征在于，当所述层间介质层厚度小于PIN器件的高度时，在对应PIN器件的位置去除全部或部分厚度的层间介质层材料形成凹槽，具体包括：
在对应PIN器件的位置去除全部厚度的层间介质层材料和全部或部分厚度的缓冲层材料形成凹槽。
5.如权利要求3所述的方法，其特征在于，所述在所述凹槽中的源漏极层上制作PIN器件，具体包括：
依次沉积N区、I区、P区三种半导体材料；
在所述P区上沉积第一透明导电层；
图形化形成PIN器件。
6.一种显示器件，其特征在于，包括如权利要求1或2所述的光学传感器件。
7.如权利要求6所述的显示器件，其特征在于，还包括：
设置在所述光学传感器件上的黑矩阵；
覆盖PIN器件并部分覆盖所述黑矩阵的彩膜；
设置在所述黑矩阵和所述彩膜上的有机覆盖层；
设置在所述有机覆盖层上的隔垫物层；
设置在所述隔垫物层上的辅助电极；以及
覆盖所述有机覆盖层、所述隔垫物层和所述辅助电极的透明阴极。
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