WO2018177073A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2018177073A1
WO2018177073A1 PCT/CN2018/077910 CN2018077910W WO2018177073A1 WO 2018177073 A1 WO2018177073 A1 WO 2018177073A1 CN 2018077910 W CN2018077910 W CN 2018077910W WO 2018177073 A1 WO2018177073 A1 WO 2018177073A1
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Prior art keywords
medium
gate
drain
semiconductor device
semiconductor layer
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PCT/CN2018/077910
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English (en)
French (fr)
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李元
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苏州捷芯威半导体有限公司
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Priority to JP2019520712A priority Critical patent/JP6790255B2/ja
Publication of WO2018177073A1 publication Critical patent/WO2018177073A1/zh
Priority to US16/199,055 priority patent/US10978564B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/118—Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

  • the present invention relates to the field of semiconductor and semiconductor manufacturing technologies, and in particular to a semiconductor device and a method of fabricating the same.
  • a common field effect semiconductor device operating at a high drain-source voltage has a high electric field peak formed near the drain side of the gate.
  • the high electric field of such localized regions can cause high leakage or even material breakdown, thereby reducing the breakdown voltage of the device.
  • the high electric field will also cause degradation and denaturation of the semiconductor material of the device, which will affect the reliability of the device and reduce the service life of the device. Therefore, in the structural design and process development of actual devices, it is necessary to reduce the strong electric field at the near-leak edge of the gate to improve the breakdown voltage of the device and obtain excellent reliability.
  • reducing the strong electric field near the gate is generally to place a field plate on the drain side of the gate.
  • the field plate is usually connected to the source or the gate, and an additional potential is generated in the gate-drain region, which can effectively suppress the gate near.
  • the electric field spike near the edge of the drain increases the device breakdown voltage and device reliability. Since the bottom of the field plate is parallel to the surface of the device semiconductor material, a new small electric field spike is formed near the termination of the field plate while reducing the electric field spike near the edge of the gate.
  • the peak of the newly appearing electric field will increase with the increase of the length of the field plate, which will easily cause the breakdown or failure of the device in the end region of the field plate, so that the device breakdown problem has not been fundamentally solved, but the contradiction is transferred from one place to another. local.
  • the excessive length of the field plate will also generate large parasitic capacitance, which affects the high frequency characteristics of the device.
  • an aspect of the invention provides a semiconductor device including: a semiconductor layer; a source and a drain on one side of the semiconductor layer; and a gate between the source and the drain; and a gate and a drain At least two media between the poles, at least two media having different dielectric coefficients; and a field plate located on one side of the at least two media away from the semiconductor layer.
  • one end of the field plate adjacent the drain is above the dielectric of the adjacent drain.
  • the dielectric of the medium near the gate is greater than the dielectric constant of the medium remote from the gate.
  • the dielectric constant of at least two of the dielectrics decreases sequentially in the direction from the gate to the drain.
  • the field plate has an end between the gate and the drain over a medium having a small dielectric constant.
  • the at least two mediums comprise a first medium and a second medium, the first medium is adjacent to the gate, the second medium is located between the first medium and the drain, and the end of the field plate is adjacent to the drain.
  • the first medium is connected to the second medium, and the dielectric constant of the first medium is greater than the dielectric constant of the second medium.
  • the junction of the first medium and the second medium is a plane having an angle between the plane and the surface of the semiconductor layer that is greater than 0° and less than 180°.
  • the junction of the first medium and the second medium is a curved surface.
  • the first medium has a first step at the junction with the second medium
  • the second medium has a second step that matches the first step at the junction with the first medium
  • the at least two mediums include a first medium, a second medium, and a third medium, the first medium is adjacent to the gate, the third medium is adjacent to the drain, and the second medium is connected to the first medium and the first medium Between the three media, the dielectric constant of the first medium is greater than the second medium, and the dielectric constant of the second medium is greater than the third medium.
  • the field plate is coupled to the source and extends through the drain on the gate to the drain and extends at least over the second medium.
  • the field plate is coupled to the gate and extends from the gate to the drain and extends at least over the second medium.
  • the semiconductor layer includes a semiconductor substrate and an epitaxial layer grown on the semiconductor substrate.
  • the semiconductor layer includes: a substrate, a buffer layer on one side of the substrate, a channel layer on a side of the buffer layer away from the substrate, and a side of the channel layer away from the buffer layer. Barrier layer.
  • Another aspect of the present invention provides a method of fabricating a semiconductor device, the method comprising: providing a semiconductor layer; forming a gate on the semiconductor layer; forming source and drain electrodes on both sides of the gate on the semiconductor layer; Forming at least two dielectrics between the gate and the drain on the semiconductor layer, the at least two dielectrics having different dielectric coefficients; and forming a field plate on a side of the at least two dielectrics away from the semiconductor layer.
  • the dielectric of the medium near the gate is greater than the dielectric constant of the medium remote from the gate.
  • the step of forming at least two dielectrics between the gate and the drain on the semiconductor layer includes: depositing a first dielectric on the semiconductor layer and the gate; engraving the first dielectric Etching, retaining a first medium near one side of the gate; depositing a second medium having a lower dielectric constant than the first medium on the semiconductor layer and the first medium; and polishing the second medium to surface and The surface of a medium is flush, wherein one end of the field plate near the drain is on the second medium.
  • the at least two mediums include a first medium and a second medium, the second medium having a dielectric constant smaller than a dielectric constant of the first medium, wherein the gate and the drain are formed on the semiconductor layer
  • the step of at least two dielectrics between the poles includes: depositing a second dielectric on the semiconductor layer and the gate; etching the second dielectric such that the second dielectric is between the gate and the drain and adjacent to the drain a side; depositing a first medium on the semiconductor layer and the second medium; and polishing the first medium such that a surface of the first medium is flush with a surface of the second medium, wherein the end of the field plate near the drain is located at the second On the media.
  • the method further includes forming a third medium between the second medium and the drain on one side of the semiconductor layer.
  • an equivalent step field plate or an equivalent slant field plate is formed when the bias voltage is applied to the drain of the semiconductor device by using at least two kinds of media having different dielectric coefficients. And while pulling down the electric field spike at the near-leak end of the gate, the electric field peak at the end of the field plate is flattened, so that the entire electric field distribution is more uniform, no obvious high peak electric field is generated, and the easy breakdown region is eliminated. The overall withstand voltage of the semiconductor device is improved.
  • FIG. 1 is a schematic structural diagram of a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural diagram of a semiconductor device according to Embodiment 2 of the present invention.
  • FIG. 3 is a schematic structural diagram of a semiconductor device according to Embodiment 3 of the present invention.
  • Embodiment 4 is a schematic structural view of a semiconductor device according to Embodiment 4 of the present invention.
  • FIG. 5 is a schematic structural diagram of a semiconductor device according to Embodiment 5 of the present invention.
  • FIG. 6 and FIG. 7 are schematic diagrams showing the structure of a semiconductor device according to Embodiment 6 of the present invention.
  • FIG. 8 is a flowchart of a method of fabricating a semiconductor device according to an embodiment of the present invention.
  • FIG. 9 is a flowchart of another method of fabricating a semiconductor device according to an embodiment of the present invention.
  • FIG. 10 is a flowchart of another method of fabricating a semiconductor device according to an embodiment of the present invention.
  • 11-a, 11-b, 11-c, 11-d, 11-e, and 11-f are schematic diagrams showing changes in the structure of the semiconductor device in the method of fabricating the semiconductor device shown in Fig. 10.
  • Reference numerals 100-semiconductor device; 1-semiconductor layer; 2-source; 3-drain; 4-gate; 5-media layer; 6-first medium; ; 61 - junction; 9 - third medium; 101 - substrate; 102 - buffer layer; 103 - channel layer; 104 - barrier layer; 105 - nucleation layer;
  • a gradient distribution field plate structure in which a plurality of layers (for example, three layers) are successively raised may be employed, or a single-layer slant field plate structure may be employed.
  • the gradient distribution field plate structure since it must be completed by a multi-step photolithography, dielectric deposition, metal deposition, etc., the manufacturing cost of the device is increased.
  • the single-layer slant field plate structure since it needs to increase the bevel manufacturing process, the process difficulty is increased; further, the surface of the device is uneven due to the existence of the slant surface, which is disadvantageous for process integration.
  • FIG. 1 is a schematic structural diagram of a semiconductor device 100 according to an embodiment of the present invention.
  • the semiconductor device 100 includes a semiconductor layer 1, a source 2, a drain 3, a gate 4, a first medium 6, a second medium 7, and a field plate 8.
  • the semiconductor layer 1 may be a single layer, a double layer or a multilayer structure composed of one or more semiconductor materials, and the present invention is not limited thereto.
  • the semiconductor layer 1 can be made of a semiconductor material silicon (Si).
  • the semiconductor layer 1 includes a semiconductor substrate and an epitaxial layer grown on the semiconductor substrate.
  • the semiconductor layer 1 can be any structure made of a semiconductor material in any semiconductor power device that requires the field plate 8.
  • the semiconductor layer 1 may be a semiconductor material suitable for a high voltage LDMOS power device, a gallium nitride high electron mobility radio frequency device, a power electronic device, a SiC power device, and a GaAs device.
  • the source 2, the drain 3 and the gate 4 are respectively located on the semiconductor layer 1, wherein the source 2 and the drain 3 are located on opposite sides of the semiconductor layer 1, and the gate 4 is located between the source 2 and the drain 3.
  • a dielectric layer 5 is further included between the gate electrode 4 and the semiconductor layer 1.
  • the dielectric layer 5 is inserted under the gate 4 to form a MISFET structure. This layer of dielectric serves as both a passivation layer for the device and an insulating layer for the gate electrode 4, which can effectively reduce the leakage current of the gate electrode 4 and adjust the turn-on voltage.
  • the dielectric layer 5 may be composed of silicon nitride (SiN), silicon dioxide (SiO 2 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium aluminum oxide (HfAlO x ). Made of at least one material.
  • the first medium 6 is located between the gate 4 and the drain 3 and may or may not extend to the source 2 (an embodiment of the extension to the source 2 is shown). That is to say, the first medium 6 may be disposed between the source 2 and the gate 4, and the first medium 6 may not be provided, and may be other mediums.
  • the second medium 7 is located between the first medium 6 and the drain 3, and the first medium 6 is connected to the second medium 7.
  • the second medium 7 may extend to the drain 3 and be connected to the drain 3 or may not extend to the drain 3.
  • the dielectric constant of the first medium 6 is different from the dielectric constant of the second medium 7, and sequentially decreases in the direction from the gate 4 to the drain 3.
  • the dielectric constant of the first medium 6 is greater than the dielectric constant of the second medium 7.
  • the junction 61 of the first medium 6 and the second medium 7 is a plane and perpendicular to the surface of the semiconductor layer 1.
  • the angle between the junction 61 and the surface of the semiconductor layer 1 is equal to 90°.
  • the first medium 6 and the second medium 7 have the same thickness and a thickness equal to or greater than the thickness of the gate 4. It should be noted that the thicknesses of the first medium 6 and the second medium 7 can also be adjusted according to a specific process and device design.
  • the field plate 8 may be made of a conductive material such as a metal element, an alloy or a composite metal, and the specific material is determined according to the process and device requirements, and the present invention is not limited thereto.
  • the structure of the field plate 8 may be a uniform field plate, a step field plate, a multi-layer field plate, and a double layer field plate.
  • the surface of the field plate 8 near the side of the semiconductor layer 1 is in contact with the source 2, the upper surfaces of the first medium 6 and the second medium 7.
  • the manner in which the field plates 8 are connected may include various types, for example, connected to the source 2, connected to the gate 4, individually connected to an independent potential, or not connected to any potential as a floating field plate.
  • the field plate 8 is connected to the source 2 and extends in the direction of the source 2 to the drain 3 and extends at least above the second medium 7.
  • the extension of the field plate 8 above the second medium 7 is related to the thickness of the second medium 7 and the distance of the second medium 7 from the grid 4 in order to make the overall electric field distribution more uniform, preferably the field plate 8 is in the second
  • the length of the medium 7 extending over the second medium 7 is between 0.1 ⁇ m and 3 ⁇ m. Further, one end of the field plate 8 near the drain 3 is located above the second medium 7 adjacent to the drain 3. Further, the end of the field plate 8 between the gate 4 and the drain 3 is located above the second medium 7 having a small dielectric constant.
  • an equivalent step field plate or an equivalent slant field plate is formed when the bias voltage is applied to the drain of the semiconductor device by using at least two kinds of media having different dielectric coefficients. And while pulling down the electric field spike at the near-leak end of the gate, the electric field peak at the end of the field plate is flattened, so that the entire electric field distribution is more uniform, no obvious high peak electric field is generated, and the easy breakdown region is eliminated. The overall withstand voltage of the semiconductor device is improved.
  • FIG. 2 is a schematic structural diagram of a semiconductor device 100 according to a second embodiment of the present invention.
  • the present embodiment is different from the first embodiment in that the junction 61 of the first medium 6 and the second medium 7 is a flat surface and is oblique to the surface of the semiconductor layer 1.
  • the angle between the plane and the surface of the semiconductor layer 1 is greater than 0° and less than 180°, and the optimum included angle is greater than 30° and less than 70° or greater than 120° and less than 160°.
  • the electric field distribution is adjusted by changing the angle between the plane and the surface of the semiconductor layer, so that the electric field in the semiconductor device is excessively smoothed over a larger range, thereby reducing the electric field peak. Achieve higher breakdown voltage, better dynamic performance and excellent long-term reliability.
  • FIG. 3 is a schematic structural diagram of a semiconductor device 100 according to Embodiment 3 of the present invention.
  • the present embodiment is different from the first embodiment in that the first medium 6 has a first step at the junction 61 with the second medium 7, and the second medium 7 is in the first medium 6.
  • the joint 61 has a second step that matches the first step, and the joint 61 of the first medium 6 and the second medium 7 is trapezoidal rather than planar.
  • the electric field distribution is adjusted by changing the step height and the number of the first medium and the second medium, so that the electric field in the semiconductor device is excessively smoothed over a larger range, thereby reducing the electric field peak. , achieving higher breakdown voltage, better dynamic performance and excellent long-term reliability.
  • junction 61 of the first medium 6 and the second medium 7 may also be a curved surface.
  • the surface may consist of a curved surface, or may be composed of multiple curved surfaces, or may be a mixture of planar and curved surfaces.
  • FIG. 4 is a schematic structural diagram of a semiconductor device 100 according to Embodiment 4 of the present invention. As shown in FIG. 4, the present embodiment is different from the first embodiment in that the field plate 8 is connected to the gate electrode 4 and extends in the direction of the gate electrode 4 toward the drain electrode 3, and extends at least to the second medium 7.
  • the electric field intensity distribution of the gate edge can be effectively adjusted, thereby improving the characteristics of the device.
  • the structure of the semiconductor device 100 provided by the fourth embodiment can also be modified in accordance with the second embodiment and the third embodiment.
  • the junction 61 of the first medium 6 and the second medium 7 and the surface of the semiconductor layer 1 can be made. Skewed, or having the first medium 6 at the junction 61 with the second medium 7 having a first step, the second medium 7 having a second step at the junction 61 with the first medium 6 that matches the first step
  • the junction 61 of the first medium 6 and the second medium 7 has a trapezoidal shape.
  • the first embodiment, the second embodiment, the third embodiment and the fourth embodiment of the present invention use two media having different dielectric coefficients, so that when the load is biased At the voltage, an equivalent step field plate or an equivalent slant field plate is formed in the semiconductor device, and the electric field peak at the terminal end of the field plate is flattened while the electric field peak at the near-drain end of the gate is pulled down, so that the entire electric field distribution is more uniform, A significant high peak electric field is generated again, and the easy breakdown region is eliminated, thereby improving the overall withstand voltage of the semiconductor device.
  • the dielectric constant of the second medium is smaller than the dielectric constant of the first medium, so that the parasitic capacitance effect is gradually weakened, thereby improving the influence of the field plate on the high frequency characteristics of the semiconductor device.
  • the present invention achieves the same or better results as a stepped field plate, a multilayer field plate or a slant field plate using a single layer flat plate field plate structure.
  • the embodiment of the present invention adopts a single-layer flat field plate structure, and has the advantages of simple manufacture, easy manufacture, and low manufacturing cost.
  • FIG. 5 is a schematic structural diagram of a semiconductor device 100 according to Embodiment 5 of the present invention. As shown in FIG. 5, the present embodiment is different from the first embodiment in that the semiconductor device 100 further includes a third medium 9 between the second medium 7 and the drain 3. Preferably, in the present embodiment, the dielectric constant of the third medium 9 is smaller than the dielectric constant of the second medium 7.
  • the electric field peak of the field plate terminal is better optimized while optimizing the electric field near the drain end of the gate, thereby increasing the electric field distribution.
  • the shape of the joint 61 of the first medium 6, the second medium 7, and the third medium 9 and the positional relationship with the surface of the semiconductor layer 1 are not limited to those shown in FIG.
  • the junction 61 of the first medium 6, the second medium 7, and the third medium 9 may be a plane perpendicular to the surface of the semiconductor layer 1, or may be a plane oblique to the surface of the semiconductor layer 1, or may be
  • the present invention is not limited in any way, it is stepped, or other structures known to those skilled in the art.
  • the semiconductor device 100 provided by the present invention is not limited to including only two or three media having different dielectric coefficients, and may also include a plurality of media having different dielectric coefficients.
  • a dielectric coefficient of the medium close to the gate 4 is greater than a dielectric coefficient of the medium remote from the gate 4.
  • the junction 61 between the plurality of dielectrics having different dielectric coefficients may be a plane which is perpendicular or oblique to the surface of the semiconductor layer 1, or the junction 61 of each medium with another medium has a trapezoidal portion, or each medium and
  • the joint 61 of the other medium is a curved surface, and there is no limitation here.
  • FIG. 6 is a schematic structural diagram of a semiconductor device 100 according to Embodiment 6 of the present invention. As shown in FIG. 6, the present embodiment is different from the first embodiment in that the semiconductor layer 1 includes a substrate 101, a buffer layer 102 on the side of the substrate 101, and a side of the buffer layer 102 away from the substrate 101. The channel layer 103 is located on the channel layer 103 on the side of the buffer layer 102 away from the buffer layer 102.
  • Substrate 101 may be made of sapphire, silicon carbide (SiC), gallium nitride (GaN), silicon (Si), rare earth oxides, or any other suitable compound for the growth of III-V compounds known to those skilled in the art. The material is made, and the invention is not limited thereto.
  • the buffer layer 102 includes gallium nitride (GaN), aluminum nitride (AlN) or other nitrides to function as a matching substrate 101 material and a high quality epitaxial gallium nitride (GaN) layer, affecting the upper layer by GaN/ The crystal quality, surface morphology and electrical properties of the heterojunction composed of aluminum gallium nitride.
  • GaN gallium nitride
  • AlN aluminum nitride
  • GaN epitaxial gallium nitride
  • the semiconductor layer 1 further includes a nucleation layer 105.
  • the nucleation layer 105 is located between the substrate 101 and the buffer layer 102 to reduce lattice mismatch between the substrate 101 and the buffer layer 102.
  • the nucleation layer 105 is made of aluminum nitride (AlN).
  • the channel layer 103 has a better lattice quality than the buffer layer 102 and has a higher carrier mobility than the buffer layer 102.
  • the channel layer 103 may be made of gallium nitride (GaN), indium aluminum gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), aluminum nitride (AlN), and other semiconductors known to those skilled in the art. Made of at least one of the materials.
  • the material of the channel layer 103 is gallium nitride (GaN).
  • the barrier layer 104 is a laminate of a plurality of layers of a semiconductor material that can form a heterojunction with the channel layer 103 or a plurality of layers of a semiconductor material and an insulating material that can form a heterojunction with the channel layer 103.
  • the semiconductor material may be, but not limited to, InGaAs, InGaN, AlGaN, InAlN, and AlN.
  • the channel layer 103 and the barrier layer 104 together constitute a semiconductor heterojunction structure, a high concentration two-dimensional electron gas is formed at the interface, and a conductive channel is generated at the heterojunction interface of the channel layer 103.
  • the dielectric layer 5 between the gate electrode 4 and the semiconductor layer 1 may also be omitted.
  • the semiconductor layer 1 may further include a cap layer on a side of the barrier layer 104 away from the channel layer 103.
  • the cap layer prevents oxidation of the surface of the barrier layer 104 and also suppresses current collapse.
  • the material of the cap layer may be a material well known to those skilled in the art such as aluminum gallium nitride (AlGaN) and gallium nitride (GaN).
  • FIG. 8 is a flowchart of a method of fabricating a semiconductor device 100 according to an embodiment of the present invention. As shown in FIG. 8, the manufacturing method of the semiconductor device 100 includes steps S101, S102, S103, S104, and S105.
  • Step S101 providing a semiconductor layer.
  • Step S102 forming a gate on the semiconductor layer.
  • Step S103 forming source and drain electrodes on both sides of the gate on the semiconductor layer.
  • Step S104 forming at least two media between the gate and the drain on the semiconductor layer, the at least two media having different dielectric coefficients.
  • the dielectric of the medium near the gate is greater than the dielectric constant of the medium remote from the gate.
  • Step S105 forming a field plate on a side of the at least two mediums away from the semiconductor layer.
  • the field plate is a metal field plate.
  • the metal field plate may be formed by a metal electron beam evaporation process, a metal sputtering process, or a metal chemical vapor deposition process, etc., and the specific manufacturing process may be determined according to process conditions or design.
  • FIG. 9 is a flowchart of another method of fabricating a semiconductor device according to an embodiment of the present invention. As shown in FIG. 9, after step S101 and before step S102, the method may further include: step S106, generating a dielectric layer on the semiconductor layer. Then, step S102 is to form a gate on the dielectric layer.
  • step S104 further includes sub-step S1041, sub-step S1042, sub-step S1043, sub-step S1044, and sub-step S1045.
  • FIG. 10 is a flowchart of another method of fabricating a semiconductor device according to an embodiment of the present invention.
  • 11-a, 11-b, 11-c, 11-d, 11-e, and 11-f are schematic diagrams showing changes in the structure of the semiconductor device in the method of fabricating the semiconductor device shown in Fig. 10.
  • the method of manufacturing the semiconductor device may include:
  • Step S101 providing a semiconductor layer.
  • Step S106 a dielectric layer is formed on the semiconductor layer.
  • step S102 a gate electrode is formed on one side of the semiconductor layer.
  • Sub-step S1041 depositing a first medium on the semiconductor layer and the gate.
  • Sub-step S1042 etching the first medium.
  • the photoresist 200 is deposited on the first medium 6 and exposed and developed; further, as shown in FIG. 11-b, the first medium 6 of the exposed region is removed by an etching process. .
  • Sub-step S1043 depositing a second medium on the semiconductor layer and the first medium.
  • the second medium 7 is formed on the semiconductor layer 1 and the first medium 6 by deposition.
  • the dielectric constant of the second medium 7 is smaller than the dielectric constant of the first medium 6.
  • Sub-step S1044 polishing the second medium such that the surface of the second medium is flush with the surface of the first medium.
  • the second medium 7 is polished to planarize the surface of the second medium 7, i.e., the surface of the second medium 7 is flush with the surface of the first medium 6.
  • Sub-step S1045 removing the excess second medium by a subsequent photolithography process and etching process.
  • the excess second medium 7 is removed by a subsequent photolithography process and etching process, and the positions of the source 2 and the drain 3 are reserved on the semiconductor layer 1.
  • Step S103 forming source and drain electrodes on both sides of the gate on the semiconductor layer.
  • the source 2 and the drain 3 are respectively formed at reserved positions on the semiconductor layer 1, and the source 2 and the drain 3 are respectively located on both sides of the gate 4.
  • Step S105 forming a field plate on a side of the first medium and the second medium away from the semiconductor layer.
  • a field plate 8 is formed on the first medium 6 and the second medium 7, wherein one end of the field plate 8 near the drain 3 is located on the second medium 7.
  • the second medium 7 may be formed first to form the first medium 6.
  • the specific steps are as follows:
  • Polishing the first medium causes the surface of the first medium to be flush with the surface of the second medium, wherein one end of the field plate adjacent the drain is on the second medium.
  • the method further includes forming a third medium between the second medium and the drain on one side of the semiconductor layer.
  • the semiconductor device provided by the present invention adopts at least two kinds of media having different dielectric coefficients, so that when a bias voltage is applied, an equivalent step field plate or an equivalent slant field plate is formed in the semiconductor device, and the gate is pulled low. At the same time as the electric field spike at the drain end, the electric field spike at the terminal of the field plate is flattened, so that the entire electric field distribution is more uniform, no obvious high peak electric field is generated, and the easy breakdown region is eliminated, thereby improving the overall withstand voltage of the semiconductor device. Sex.
  • the dielectric constant of the medium close to the gate is greater than the dielectric constant of the medium away from the gate, so that the parasitic capacitance effect is gradually weakened, thereby improving the influence of the field plate on the high frequency characteristics of the semiconductor device.
  • the present invention achieves the same or better results as a stepped field plate, a multilayer field plate or a slant field plate using a single layer flat plate field plate structure.
  • the embodiment of the present invention adopts a single-layer flat plate field plate structure, and has the advantages of simple manufacture, easy manufacture, and low manufacturing cost.
  • the semiconductor device of the present invention and the method of fabricating the same through at least two dielectrics having different dielectric coefficients, such that when a bias voltage is applied to the drain of the semiconductor device, an equivalent step field plate or an equivalent slant field plate is formed, And while pulling down the electric field spike at the near-leak end of the gate, the electric field peak at the end of the field plate is flattened, so that the entire electric field distribution is more uniform, no obvious high peak electric field is generated, and the easy breakdown region is eliminated, thereby improving The overall withstand voltage of the semiconductor device.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种半导体器件及其制造方法。该半导体器件包括：半导体层(1)，位于半导体层(1)一侧的源极(2)和漏极(3)以及位于源极(2)与漏极(3)之间的栅极(4)，位于栅极(4)与漏极(3)之间的至少两种介质，至少两种介质具有不同的介电系数，以及位于至少两种介质上远离半导体层(1)一侧的场板(8)。通过采用具有不同介电系数的至少两种介质，使得当加载偏置电压时，半导体器件内能形成等效阶梯场板或等效斜场板，并在拉低栅极近漏端的电场尖峰的同时，平抑场板终端的电场尖峰，从而使器件内电场分布更加均匀，因此，提高了半导体器件的整体耐压及可靠性。

Description

半导体器件及其制造方法
本发明是要求由申请人提出的，申请日为2017年3月29日，申请号为201710196548.1，名称为“半导体器件及其制造方法”的申请的优先权。以上申请的全部内容通过整体引用结合于此。
技术领域
本发明涉及半导体及半导体制造技术领域，具体而言，涉及一种半导体器件及其制造方法。
发明背景
工作在高漏源电压下的普通场效应半导体器件，其栅极靠近漏端一侧附近会形成一个高电场尖峰。这种局部区域的高电场可以引起高漏电甚至材料击穿，从而降低器件的击穿电压。同时，随着时间的增加，高电场也会引起器件的半导体材料退化、变性，进而影响器件的可靠性，降低器件使用寿命。所以，在实际器件的结构设计和工艺研发中，需降低栅极近漏边缘的强电场以提高器件的击穿电压并获得优良的可靠性。
目前，降低栅极附近的强电场一般是在栅极靠漏端一侧放置场板，场板通常与源极或栅极相连，在栅漏区域产生一个附加电势，可以有效地平抑栅极近漏端边沿附近的电场尖峰，从而提高器件击穿电压及器件可靠性。由于这种场板的底部与器件半导体材料表面是平行的，在减小靠近栅极边缘的电场尖峰同时，会在场板终端附近形成一个新的较小电场尖峰。这个新出现的电场尖峰峰值会随着场板长度的增加而增加，容易造成场板终端区域器件击穿或失效，使得器件击穿问题没有得到根本解决，只是将矛盾从一个地方转移到了另一个地方。此外，场板过长还会产生较大的寄生电容，影响器件高频特性。
发明内容
有鉴于此，本发明的目的在于提供一种半导体器件及其制造方法，以解决上述问题。
为实现上述目的，本发明的一个方面提供一种半导体器件，包括：半导体层；位于半导体层一侧的源极和漏极以及位于源极与漏极之间的栅极；位于栅极与漏极之间的至少两种介质，至少两种介质具有不同的介电系数；以及位于至少两种介质上远离半导体层一侧的场板。
在本发明的一个实施例中，场板靠近漏极的一端位于相邻漏极的介质上方。
在本发明的一个实施例中，至少两种介质中，靠近栅极的介质的介电系数大于远离栅极的介质的介电系数。
在本发明的一个实施例中，至少两种介质的介电系数在从栅极到漏极的方向上依次减小。
在本发明的一个实施例中，场板在栅极与漏极之间的一端位于介电系数小的介质上方。
在本发明的一个实施例中，至少两种介质包括第一介质和第二介质，第一介质靠近栅极，第二介质位于第一介质与漏极之间，场板靠近漏极的一端位于第二介质上，第一介质与第二介质相连，第一介质的介电系数大于第二介质的介电系数。
在本发明的一个实施例中，第一介质和第二介质的连接处为一平面，该平面与半导体层的表面之间的夹角大于0°且小于180°。
在本发明的一个实施例中，第一介质和第二介质的连接处为曲面。
在本发明的一个实施例中，第一介质在和第二介质的连接处具有第一阶梯部，第二介质在和第一介质的连接处具有与第一阶梯部匹配的第二阶梯部。
在本发明的一个实施例中，至少两种介质包括第一介质、第二介质和第三介质，第一介质靠近栅极，第三介质靠近漏极，第二介质连接于第一介质与第三介质之间，第一介质的介电系数大于第二介质，第二介质的介电系数大于第三介质。
在本发明的一个实施例中，场板与源极连接并经过栅极上方向漏极的方向延 伸，且至少延伸至第二介质上方。
在本发明的一个实施例中，场板与栅极连接并从栅极向漏极的方向延伸，且至少延伸至第二介质上方。
在本发明的一个实施例中，半导体层包括半导体衬底及在半导体衬底上生长的外延层。
在本发明的一个实施例中，半导体层包括：衬底、位于衬底一侧的缓冲层、位于缓冲层上远离衬底一侧的沟道层、位于沟道层上远离缓冲层一侧的势垒层。
本发明的另一个方面提供一种半导体器件的制造方法，该方法包括：提供一半导体层；在半导体层上形成栅极；在半导体层上分别形成位于栅极两侧的源极和漏极；在半导体层上形成位于栅极与漏极之间的至少两种介质，至少两种介质具有不同的介电系数；以及在至少两种介质上远离半导体层的一侧形成场板。
在本发明的一个实施例中，至少两种介质中，靠近栅极的介质的介电系数大于远离栅极的介质的介电系数。
在本发明的一个实施例中，在半导体层上形成位于栅极与漏极之间的至少两种介质的步骤包括：在半导体层和栅极上淀积第一介质；对第一介质进行刻蚀，保留靠近栅极一侧的第一介质；在半导体层和第一介质上淀积介电系数小于第一介质的第二介质；以及对第二介质进行抛光使第二介质的表面与第一介质的表面平齐，其中，场板靠近漏极的一端位于第二介质上。
在本发明的一个实施例中，至少两种介质包括第一介质和第二介质，第二介质的介电系数小于第一介质的介电系数，其中，在半导体层上形成位于栅极与漏极之间的至少两种介质的步骤包括：在半导体层和栅极上淀积第二介质；对第二介质进行刻蚀，使第二介质位于栅极与漏极之间且靠近漏极一侧；在半导体层和第二介质上淀积第一介质；以及对第一介质进行抛光使第一介质的表面与第二介质的表面平齐，其中，场板靠近漏极的一端位于第二介质上。
在本发明的一个实施例中，该方法还包括：在半导体层的一侧形成位于第二介质与漏极之间的第三介质。
根据本发明实施例提供的技术方案，通过采用具有不同介电系数的至少两种 介质，使得当偏置电压加载到半导体器件的漏极上时，形成等效阶梯场板或等效斜场板，并在拉低栅极近漏端的电场尖峰的同时，平抑场板终端的电场尖峰，从而使整个电场分布更加均匀，不再产生明显的高尖峰电场，以及易击穿区域被消除，因此，提高了半导体器件的整体耐压性。
附图简要说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍。应当理解，以下附图仅示出了本发明的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本发明实施例一提供的半导体器件的结构示意图。
图2为本发明实施例二提供的半导体器件的结构示意图。
图3为本发明实施例三提供的半导体器件的结构示意图。
图4为本发明实施例四提供的半导体器件的结构示意图。
图5为本发明实施例五提供的半导体器件的结构示意图。
图6和图7为本发明实施例六提供的半导体器件的结构示意图。
图8为本发明实施例提供的半导体器件的制造方法的流程图。
图9为本发明实施例提供的半导体器件的另一制造方法的流程图。
图10为本发明实施例提供的半导体器件的另一制造方法的流程图。
图11-a、图11-b、图11-c、图11-d、图11-e和图11-f为图10所示的半导体器件制造方法中的半导体器件的结构变化示意图。
附图标记：100-半导体器件；1-半导体层；2-源极；3-漏极；4-栅极；5-介质层；6-第一介质；7-第二介质；8-场板；61-连接处；9-第三介质；101-衬底；102-缓冲层；103-沟道层；104-势垒层；105-成核层；200-光刻胶。
实施本发明的方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、 完整地描述。显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本发明实施例的组件可以以各种不同的配置来布置和设计。
因此，以下对在附图中提供的本发明的实施例的详细描述并非旨在限制要求保护的本发明的范围，而是仅仅表示本发明的选定实施例。基于本发明的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。在本发明的描述中，术语“第一”、“第二”、“第三”、“第四”等仅用于区分描述，而不能理解为只是或暗示相对重要性。
为了在抑制栅极近漏端电场的同时不增加新的电场尖峰，可以采用多层(例如，三层)依次逐渐走高的梯度分布场板结构，或者采用单层斜场板结构。对于梯度分布场板结构，由于其必须由多步光刻、介质沉积、金属沉积等工艺配合完成，因此，增加了器件的制造成本。对于单层斜场板结构，由于其需要增加斜面制作工艺，因此，增加了工艺难度；进一步地，由于斜面的存在造成器件表面不平整，因此，不利于工艺集成。
实施例一
图1示出了本发明实施例提供的半导体器件100的结构示意图。如图1所示，半导体器件100包括：半导体层1、源极2、漏极3、栅极4、第一介质6、第二介质7和场板8。
半导体层1可以是由一种或多种半导体材料构成的单层、双层或多层结构，本发明对此没有任何限制。半导体层1可以由半导体材料硅(Si)制成。或者，半导体层1包括半导体衬底及在半导体衬底上生长的外延层。抑或，半导体层1可以是任何需要使用场板8的半导体功率器件中的由半导体材料制成的结构。例如，半导体层1可以是适用于高压LDMOS功率器件、氮化镓高电子迁移率射频器件、电力电子器件、SiC功率器件及GaAs器件等的半导体材料。
源极2、漏极3和栅极4分别位于半导体层1上，其中源极2和漏极3位于半导体层1上的相对两侧，栅极4位于源极2与漏极3之间。优选地，在本实施例中，在栅极4与半导体层1之间还包括介质层5。在栅极4下方插入介质层5，形成MISFET结构，这一层介质既作为器件的钝化层，又是栅极4的绝缘层，可以有效地降低栅极4的漏电电流，调节开启电压。介质层5可以由氮化硅(SiN)、二氧化硅(SiO 2)、氮氧化硅(SiON)、氧化铝(Al 2O 3)、氧化铪(HfO 2)、氧化铪铝(HfAlO x)中的至少一种材料制成。
第一介质6位于栅极4与漏极3之间，可以延伸至源极2也可以不延伸至源极2(图中示出了延伸至源极2的实施方式)。也就是说，在源极2与栅极4之间可以设置第一介质6也可以不设置第一介质6，还可以是其他介质。第二介质7位于第一介质6与漏极3之间，且第一介质6与第二介质7相连。第二介质7可以延伸到漏极3并与漏极3相连，也可以不延伸到漏极3。第一介质6的介电系数与第二介质7的介电系数不同，并且在从栅极4到漏极3的方向上依次减小。优选地，在本实施例中，第一介质6的介电系数大于第二介质7的介电系数。优选地，在本实施例中，第一介质6和第二介质7的连接处61为一平面且与半导体层1的表面垂直。当第一介质6和第二介质7的连接处61与半导体层1的表面垂直时，连接处61与半导体层1的表面之间的夹角等于90°。第一介质6和第二介质7的厚度相同，且其厚度大于等于栅极4的厚度。需要说明的是，第一介质6和第二介质7的厚度也可以根据具体工艺和器件设计进行调整。
场板8可以由金属单质、合金或复合金属等导电材料制成，具体材料根据工艺及器件要求而定，本发明对此没有任何限制。场板8的结构可以是均匀场板、台阶场板、多层场板以及双层场板等。场板8靠近半导体层1一侧的表面与源极2、第一介质6和第二介质7的上表面接触。场板8的连接方式可以包括多种类型，例如，与源极2相连，与栅极4相连，单独连接一个独立电位，或者不接任何电位而作为浮空场板。优选地，在本实施例中，场板8与源极2相连并沿源极2向漏极3的方向延伸，且至少延伸至第二介质7的上方。
场板8在第二介质7上方的延伸长度设置与第二介质7的厚度、第二介质7 距栅极4的距离相关，才能使整个电场分布更加均匀，优选地，场板8在第二介质7上方延伸至第二介质7上的长度介于0.1μm至3μm之间。进一步地，场板8靠近漏极3的一端位于与漏极3相邻的第二介质7的上方。此外，场板8在栅极4与漏极3之间的一端位于介电系数小的第二介质7的上方。
根据本发明实施例提供的技术方案，通过采用具有不同介电系数的至少两种介质，使得当偏置电压加载到半导体器件的漏极上时，形成等效阶梯场板或等效斜场板，并在拉低栅极近漏端的电场尖峰的同时，平抑场板终端的电场尖峰，从而使整个电场分布更加均匀，不再产生明显的高尖峰电场，以及易击穿区域被消除，因此，提高了半导体器件的整体耐压性。
实施例二
图2是本发明实施例二提供的半导体器件100的结构示意图。如图2所示，本实施例与实施例一的不同之处在于，第一介质6和第二介质7的连接处61为一平面且与半导体层1的表面斜交。该平面与半导体层1的表面之间的夹角大于0°且小于180°，最佳夹角范围为大于30°且小于70°或者大于120°且小于160°。
根据本发明实施例提供的技术方案，通过改变平面与半导体层的表面之间的夹角来调整电场分布，使得半导体器件中的电场在更大范围内平滑过度，因此，减小了电场峰值，实现了更高的击穿电压、更好的动态性能及优良的长期可靠性。
实施例三
图3是本发明实施例三提供的半导体器件100的结构示意图。如图3所示，本实施例与实施例一的不同之处在于，第一介质6在和第二介质7的连接处61具有第一阶梯部，第二介质7在和第一介质6的连接处61具有与第一阶梯部匹配的第二阶梯部，第一介质6和第二介质7的连接处61呈梯形而不是平面。
根据本发明实施例提供的技术方案，通过改变第一介质和第二介质的阶梯高低和数量来调整电场分布，使得半导体器件中的电场在更大范围内平滑过度，因此，减小了电场峰值，实现了更高的击穿电压、更好的动态性能及优良的长期可靠性。
应理解，第一介质6和第二介质7的连接处61还可以是曲面。该曲面可以由 一个弧面组成，或者可以由多个弧面组成，或者可以由平面和弧面混合而成。
实施例四
图4是本发明实施例四提供的半导体器件100的结构示意图。如图4所示，本实施例与实施例一的不同之处在于，场板8与栅极4连接并沿栅极4向漏极3的方向延伸，且至少延伸至第二介质7上方。
根据本发明实施例提供的技术方案，通过将场板与栅极相连，形成栅极斜场板器件结构，可以有效地调节栅极边缘的电场强度分布，因此，提高了器件的特性。
应理解，还可以仿照实施例二和实施例三对实施例四提供的半导体器件100的结构进行变形，例如，可以使第一介质6和第二介质7的连接处61与半导体层1的表面斜交，或者使第一介质6在和第二介质7的连接处61具有第一阶梯部，第二介质7在和第一介质6的连接处61具有与第一阶梯部匹配的第二阶梯部，第一介质6和第二介质7的连接处61呈梯形。
与台阶场板、多层场板或斜场板相比，本发明实施例一、实施例二、实施例三和实施例四采用了具有不同介电系数的两种介质，使得当加载偏置电压时，半导体器件内形成等效阶梯场板或等效斜场板，并在拉低栅极近漏端的电场尖峰的同时，平抑场板终端的电场尖峰，从而使整个电场分布更加均匀，不再产生明显的高尖峰电场，以及易击穿区域被消除，因此，提高了半导体器件的整体耐压性。并且，第二介质的介电系数比第一介质的介电系数小，使得寄生电容效应逐渐减弱，因此，改善了场板对半导体器件高频特性的影响。因而，本发明采用单层的平板形的场板结构就能跟采用台阶场板、多层场板或斜场板一样达到相同或更好的效果。此外，本发明实施例采用单层的平板的场板结构，具有制造简单、易于制造且制造成本低等优点。
实施例五
图5是本发明实施例五提供的半导体器件100的结构示意图。如图5所示，本实施例与实施例一的不同之处在于，半导体器件100还包括第三介质9，该第三介质9位于第二介质7与漏极3之间。优选地，在本实施例中，第三介质9的 介电系数小于第二介质7的介电系数。
根据本发明实施例提供的技术方案，通过在场板下增加第三介质，使得在优化栅极近漏端电场的同时，更好地优化场板终端的电场峰值，因此，增加了优化电场分布的方法，且更好地改善了器件特性。
应理解，第一介质6、第二介质7及第三介质9的连接处61的形状及与半导体层1表面的位置关系不限于图5所示。例如，第一介质6、第二介质7及第三介质9的连接处61既可以是与半导体层1的表面垂直的平面，也可以是与半导体层1的表面斜交的平面，还可以是阶梯状，或是本领域的技术人员公知的其他结构，本发明对此没有任何限制。
还应理解，本发明提供的半导体器件100不限于只包括两种或三种介电系数不同的介质，还可以包括多种介电系数不同的介质。优选地，多种介电系数不同的介质中，靠近栅极4的介质的介电系数大于远离栅极4的介质的介电系数。多种介电系数不同的介质之间的连接处61可以是一平面，平面与半导体层1的表面垂直或斜交，或者各介质与另一介质的连接处61具有梯形部，或者各介质与另一介质的连接处61是曲面，在此不作任何限制。
实施例六
图6是本发明实施例六提供的半导体器件100的结构示意图。如图6所示，本实施例与实施例一的不同之处在于，半导体层1包括：衬底101、位于衬底101一侧的缓冲层102、位于缓冲层102上远离衬底101一侧的沟道层103、位于沟道层103上远离缓冲层102一侧的势垒层104。
衬底101可以是由蓝宝石(Sapphire)、碳化硅(SiC)、氮化镓(GaN)、硅(Si)、稀土氧化物或者本领域的技术人员公知的任何其它适合生长III-V族化合物的材料所制成，本发明对此没有任何限制。
缓冲层102包括氮化镓(GaN)、氮化铝(AlN)或其他氮化物，起到匹配衬底101材料和高质量外延氮化镓(GaN)层的作用，影响上方由氮化镓/铝镓氮构成的异质结的晶体质量、表面形貌以及电学性质等参数。
如果衬底101材料与缓冲层102材料晶格失配较大，优选地，在本实施例中， 半导体层1还包括成核层105。成核层105位于衬底101与缓冲层102之间，以减小衬底101与缓冲层102之间的晶格失配。优选地，在本实施例中，成核层105由铝氮(AlN)制成。
沟道层103晶格质量优于缓冲层102，且载流子迁移率高于缓冲层102。沟道层103可以由氮化镓(GaN)、铟铝镓氮(InAlGaN)、铝镓氮(AlGaN)、铟铝氮(InAlN)、铝氮(AlN)和本领域的技术人员公知的其它半导体材料中的至少一种材料制成。优选地，在本实施例中，沟道层103的材料是氮化镓(GaN)。
势垒层104是若干层可以与沟道层103形成异质结的半导体材料或若干层可以与沟道层103形成异质结的半导体材料和绝缘材料的叠层。半导体材料可以是，但不限于，铟铝镓氮(InAlGaN)、铝镓氮(AlGaN)、铟铝氮(InAlN)和铝氮(AlN)等。沟道层103和势垒层104一起组成半导体异质结结构，在界面处形成高浓度二维电子气，并在沟道层103的异质结界面处产生导电沟道。
本实施例六的另一种实施方式中，如图7所示，在栅极4与半导体层1之间的介质层5还可以省略。
优选地，在其它实施例中，半导体层1还可以包括帽层，帽层位于势垒层104上远离沟道层103的一侧。帽层可以防止势垒层104表面氧化，还可以抑制电流崩塌。帽层的材料可以是铝镓氮(AlGaN)和氮化镓(GaN)等本领域技术人员公知的材料。
图8为本发明实施例提供的半导体器件100的制造方法的流程图。如图8所示，该半导体器件100的制造方法包括：步骤S101、步骤S102、步骤S103、步骤S104和步骤S105。
步骤S101，提供一半导体层。
步骤S102，在半导体层上形成栅极。
步骤S103，在半导体层上分别形成位于栅极两侧的源极和漏极。
步骤S104，在半导体层上形成位于栅极与漏极之间的至少两种介质，至少两种介质具有不同的介电系数。优选地，靠近栅极的介质的介电系数大于远离栅极的介质的介电系数。
步骤S105，在至少两种介质上远离半导体层的一侧形成场板。优选地，场板为金属场板。金属场板可以由金属电子束蒸发工艺、金属溅射工艺、或金属化学气相淀积工艺等形成，具体制造工艺可根据工艺条件或设计而定。
图9为本发明实施例提供的半导体器件的另一制造方法的流程图。如图9所示，在步骤S101之后、步骤S102之前，该方法还可以包括：步骤S106，在半导体层上生成介质层。则步骤S102即为在介质层上形成栅极。
在半导体器件的制造方法中，上述步骤的实施顺序不做限定，可以根据情况灵活设计。例如，步骤S103和步骤S104的实施顺序可以互换。半导体器件的制造方法应用于制造包括两种介质的半导体器件时，步骤S104还包括子步骤S1041、子步骤S1042、子步骤S1043、子步骤S1044和子步骤S1045。
图10为本发明实施例提供的半导体器件的另一制造方法的流程图。图11-a、图11-b、图11-c、图11-d、图11-e和图11-f为图10所示的半导体器件制造方法中的半导体器件的结构变化示意图。
如图10所示，该半导体器件的制造方法可以包括：
步骤S101，提供一半导体层。
步骤S106，在半导体层上生成介质层。
步骤S102，在半导体层一侧形成栅极。
子步骤S1041，在半导体层及栅极上淀积第一介质。
子步骤S1042，对第一介质进行刻蚀。
具体地，如图11-a所示，在第一介质6上淀积光刻胶200并曝光显影；进一步地，如图11-b所示，通过刻蚀工艺去除暴露区域的第一介质6。
子步骤S1043，在半导体层及第一介质上淀积第二介质。
具体地，如图11-c所示，通过淀积，使第二介质7形成在半导体层1和第一介质6上。优选地，第二介质7的介电系数小于第一介质6的介电系数。
子步骤S1044，对第二介质进行抛光，使第二介质的表面与第一介质的表面平齐。
具体地，如图11-d所示，对第二介质7进行抛光，使第二介质7的表面平整 化，即，使第二介质7的表面与第一介质6的表面平齐。
子步骤S1045，通过后继的光刻工艺和刻蚀工艺去除多余的第二介质。
具体地，如图11-e所示，通过后继的光刻工艺和刻蚀工艺去除多余的第二介质7，并在半导体层1上预留生长源极2和漏极3的位置。
步骤S103，在半导体层上分别形成位于栅极两侧的源极和漏极。
具体地，如图11-f所示，在半导体层1上的预留位置处分别形成源极2和漏极3，源极2和漏极3分别位于栅极4的两侧。
步骤S105，在第一介质和第二介质上远离半导体层的一侧形成场板。
具体地，如图1所示，场板8形成在第一介质6和第二介质7上，其中，场板8靠近漏极3的一端位于第二介质7上。
可选地，在另一个实施例中，也可以先形成第二介质7再形成第一介质6，具体步骤如下：
在半导体层和栅极上淀积一层第二介质；
对第二介质进行刻蚀，使该第二介质位于栅极与漏极之间；
在半导体层及第二介质上淀积第一介质；以及
对第一介质进行抛光使第一介质的表面与第二介质的表面平齐，其中，场板靠近漏极的一端位于第二介质上。
当半导体器件100的制造方法应用于制造包括三种介质的半导体器件100时，该方法还包括：在半导体层的一侧形成位于第二介质与漏极之间的第三介质。
本发明提供的半导体器件，采用具有不同介电系数的至少两种介质，使得当加载偏置电压时，半导体器件内形成等效阶梯场板或等效斜场板，并在拉低栅极近漏端的电场尖峰的同时，平抑场板终端的电场尖峰，从而使整个电场分布更加均匀，不再产生明显的高尖峰电场，以及易击穿区域被消除，因此，提高了半导体器件的整体耐压性。并且，靠近栅极的介质的介电系数大于远离栅极的介质的介电系数，使得寄生电容效应逐渐减弱，因此，改善了场板对半导体器件高频特性的影响。因而，本发明采用单层的平板形的场板结构就能跟采用台阶场板、多层场板或斜场板一样达到相同或更好的效果。此外，本发明实施例采用单层的平 板的场板结构，具有制造简单、易于制造且制造成本低等优点。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“设置”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接。可以是机械连接，也可以是电性连接。可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
在本发明的描述中，还需要说明的是，术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
工业实用性
本发明的半导体器件及其制造方法，通过具有不同介电系数的至少两种介质，使得当偏置电压加载到半导体器件的漏极上时，形成等效阶梯场板或等效斜场板，并在拉低栅极近漏端的电场尖峰的同时，平抑场板终端的电场尖峰，从而使整个电场分布更加均匀，不再产生明显的高尖峰电场，以及易击穿区域被消除，因此，提高了半导体器件的整体耐压性。

Claims (19)

  1. 一种半导体器件，其特征在于，包括：
    半导体层；
    位于所述半导体层一侧的源极和漏极以及位于所述源极与所述漏极之间的栅极；
    位于所述栅极与所述漏极之间的至少两种介质，所述至少两种介质具有不同的介电系数；以及
    位于所述至少两种介质上远离所述半导体层一侧的场板。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述场板靠近所述漏极的一端位于相邻漏极的介质上方。
  3. 根据权利要求1所述的半导体器件，其特征在于，所述至少两种介质中，靠近所述栅极的介质的介电系数大于远离所述栅极的介质的介电系数。
  4. 根据权利要求3所述的半导体器件，其特征在于，所述至少两种介质的介电系数在从栅极到所述漏极的方向上依次减小。
  5. 根据权利要求4所述的半导体器件，其特征在于，所述场板在所述栅极与所述漏极之间的一端位于介电系数小的介质上方。
  6. 根据权利要求5所述的半导体器件，其特征在于，所述至少两种介质包括第一介质和第二介质，所述第一介质靠近所述栅极，所述第二介质位于所述第一介质与所述漏极之间，所述场板靠近所述漏极的一端位于所述第二介质上，所述第一介质与所述第二介质相连，所述第一介质的介电系数大于所述第二介质的介电系数。
  7. 根据权利要求6所述的半导体器件，其特征在于，所述第一介质和所述第二介质的连接处为一平面，所述平面与所述半导体层的表面之间的夹角大于0°且小于180°。
  8. 根据权利要求6所述的半导体器件，其特征在于，所述第一介质和所述第二介质的连接处为曲面。
  9. 根据权利要求6所述的半导体器件，其特征在于，所述第一介质在和所述第二介质的连接处具有第一阶梯部，所述第二介质在和第一介质的连接处具有与所述第一阶梯部匹配的第二阶梯部。
  10. 根据权利要求5所述的半导体器件，其特征在于，所述至少两种介质包括第一介质、第二介质和第三介质，所述第一介质靠近所述栅极，所述第三介质靠近所述漏极，所述第二介质连接于所述第一介质与第三介质之间，所述第一介质的介电系数大于所述第二介质，所述第二介质的介电系数大于所述第三介质。
  11. 根据权利要求6至10中任一项所述的半导体器件，其特征在于，所述场板与所述源极连接并经过所述栅极上方向所述漏极的方向延伸，且至少延伸至所述第二介质上方。
  12. 根据权利要求6至10中任一项所述的半导体器件，其特征在于，所述场板与所述栅极连接并从所述栅极向所述漏极的方向延伸，且至少延伸至所述第二介质上方。
  13. 根据权利要求1至10中任一项所述的半导体器件，其特征在于，所述半导体层包括半导体衬底及在所述半导体衬底上生长的外延层。
  14. 根据权利要求1至10中任一项所述的半导体器件，其特征在于，所述半导体层包括：衬底、位于所述衬底一侧的缓冲层、位于所述缓冲层上远离所述衬底一侧的沟道层、位于所述沟道层上远离所述缓冲层一侧的势垒层。
  15. 一种半导体器件的制造方法，其特征在于，所述方法包括：
    提供一半导体层；
    在所述半导体层上形成栅极；
    在所述半导体层上分别形成位于所述栅极两侧的源极和漏极；
    在所述半导体层上形成位于所述栅极与所述漏极之间的至少两种介质，所述至少两种介质具有不同的介电系数；以及
    在所述至少两种介质上远离所述半导体层的一侧形成场板。
  16. 根据权利要求15所述的半导体器件的制造方法，其特征在于，所述至少两种介质中，靠近所述栅极的介质的介电系数大于远离所述栅极的介质的介电系 数。
  17. 根据权利要求16所述的半导体器件的制造方法，其特征在于，在所述半导体层上形成位于所述栅极与所述漏极之间的至少两种介质的步骤包括：
    在所述半导体层和所述栅极上淀积第一介质；
    对所述第一介质进行刻蚀，保留靠近所述栅极一侧的第一介质；
    在所述半导体层和所述第一介质上淀积介电系数小于所述第一介质的第二介质；以及
    对所述第二介质进行抛光使所述第二介质的表面与所述第一介质的表面平齐，
    其中，所述场板靠近所述漏极的一端位于所述第二介质上。
  18. 根据权利要求16所述的半导体器件的制造方法，其特征在于，所述至少两种介质包括第一介质和第二介质，所述第二介质的介电系数小于所述第一介质的介电系数，
    其中，在所述半导体层上形成位于所述栅极与所述漏极之间的至少两种介质的步骤包括：
    在所述半导体层和所述栅极上淀积所述第二介质；
    对所述第二介质进行刻蚀，使所述第二介质位于所述栅极与所述漏极之间且靠近所述漏极一侧；
    在所述半导体层和所述第二介质上淀积所述第一介质；以及
    对所述第一介质进行抛光使所述第一介质的表面与所述第二介质的表面平齐，
    其中，所述场板靠近所述漏极的一端位于所述第二介质上。
  19. 根据权利要求17或18所述的半导体器件的制造方法，其特征在于，所述方法还包括：
    在所述半导体层的一侧形成位于所述第二介质与所述漏极之间的第三介质。
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