WO2018176568A1 - Tft基板的制作方法 - Google Patents

Tft基板的制作方法 Download PDF

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Publication number
WO2018176568A1
WO2018176568A1 PCT/CN2017/082815 CN2017082815W WO2018176568A1 WO 2018176568 A1 WO2018176568 A1 WO 2018176568A1 CN 2017082815 W CN2017082815 W CN 2017082815W WO 2018176568 A1 WO2018176568 A1 WO 2018176568A1
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Prior art keywords
layer
scan line
photoresist
forming
semiconductor layer
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PCT/CN2017/082815
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English (en)
French (fr)
Inventor
周志超
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US15/570,754 priority Critical patent/US10367016B2/en
Publication of WO2018176568A1 publication Critical patent/WO2018176568A1/zh

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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
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    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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Definitions

  • the present invention relates to the field of liquid crystal panel fabrication, and in particular to a method for fabricating a TFT substrate.
  • the arrangement of liquid crystals is controlled by a TFT substrate to realize display of different gray scale lights.
  • the TFT substrate is an important part in the liquid crystal panel, and its production is also an important process in the manufacturing process of the liquid crystal panel.
  • a TFT substrate using a ring-shaped gate structure in the related art has been attracting more and more attention because of its superior performance.
  • the process steps are complicated and cumbersome, resulting in high manufacturing cost.
  • the invention provides a method for fabricating a TFT substrate, comprising the following steps:
  • the second photoresist layer is removed to form an electrical connection portion on the first conductor layer and the second insulating layer, and a drain is formed on the second semiconductor layer, wherein the electrical connection portion passes through A conductor layer connects the first scan line to the second scan line.
  • the steps of forming a buffer layer, a data line, and a source on the substrate, and disposing a first scan line, a second scan line, and a gate on the buffer layer include:
  • the source region forms a source.
  • a first insulating layer is formed on the buffer layer and the gate, a second insulating layer is formed on the data line, and a first semiconductor layer is formed on the first scan line and the second scan line.
  • the step of forming a second semiconductor layer includes:
  • a first semiconductor layer is formed on the first scan line and the second scan line, and a second semiconductor layer is formed on the source.
  • the photoresist on the insulating material layer on the first scan line, the second scan line, and the source is fully exposed by a yellow light process to make the insulating material on the first scan line, the second scan line, and the source The layer is exposed;
  • the insulating material layer on the first scan line, the second scan line, and the source is etched by an etching process.
  • the step of forming a first semiconductor layer on the first scan line and the second scan line and forming the second semiconductor layer on the source includes:
  • a first semiconductor layer is formed on the first scan line and the second scan line by a physical vapor deposition method, and a second semiconductor layer is formed on the source.
  • the step of conducting the first semiconductor layer to form a first conductor layer and then removing the first photoresist layer comprises:
  • the photoresist is ashed to remove the first photoresist layer.
  • the step of removing the second photoresist layer after forming the second conductor layer on the substrate comprises:
  • the second photoresist layer is removed by a photoresist strip process.
  • the material of the first semiconductor layer and the second semiconductor layer is indium gallium zinc oxide.
  • the material of the second conductor layer is indium tin oxide.
  • the buffer layer is a silicon nitride layer, a silicon oxide layer, or an aluminum oxide layer.
  • the invention also provides a method for fabricating another TFT substrate, comprising the following steps:
  • the source region forms a source; wherein the data line is electrically connected to the source, the second scan line is electrically connected to the gate, and the gate is in a non-closed loop and is disposed around the source;
  • the second photoresist layer is removed to form an electrical connection portion on the first conductor layer and the second insulating layer, and a drain is formed on the second semiconductor layer, wherein the electrical connection portion passes through A conductor layer connects the first scan line to the second scan line.
  • the step of patterning the layer of insulating material comprises:
  • the photoresist on the insulating material layer on the first scan line, the second scan line, and the source is fully exposed by a yellow light process to make the insulating material on the first scan line, the second scan line, and the source The layer is exposed;
  • the insulating material layer on the first scan line, the second scan line, and the source is etched by an etching process.
  • the step of forming a first semiconductor layer on the first scan line and the second scan line and forming the second semiconductor layer on the source includes:
  • a first semiconductor layer is formed on the first scan line and the second scan line by a physical vapor deposition method, and a second semiconductor layer is formed on the source.
  • the step of conducting the first semiconductor layer to form a first conductor layer and then removing the first photoresist layer comprises:
  • the photoresist is ashed to remove the first photoresist layer.
  • the step of conducting the first semiconductor layer to form the first conductor layer comprises:
  • the first semiconductor layer is conductorized using argon, nitrogen, and ammonia to form a first conductor layer.
  • the step of removing the second photoresist layer after forming the second conductor layer on the substrate comprises:
  • the second photoresist layer is removed by a photoresist strip process.
  • the material of the first semiconductor layer and the second semiconductor layer is indium gallium zinc oxide.
  • the material of the second conductor layer is indium tin oxide.
  • the buffer layer is a silicon nitride layer, a silicon oxide layer, or an aluminum oxide layer.
  • the thickness of the second photoresist layer is greater than the thickness of the first photoresist layer.
  • FIG. 1 is a flow chart showing a method of fabricating a TFT substrate in a preferred embodiment of the present invention.
  • 2A-2E are schematic diagrams showing the structure of a first photomask process corresponding to the substrate formed in the method for fabricating the TFT substrate shown in FIG.
  • 3A-3E are schematic structural views of a second reticle process corresponding substrate in the method for fabricating the TFT substrate shown in FIG. 1.
  • 4A-4F are schematic structural views of a corresponding substrate of a third photomask process in the method for fabricating the TFT substrate shown in FIG. 1.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining “first” and “second” may include one or more of the features either explicitly or implicitly.
  • a plurality means two or more unless otherwise stated.
  • the term “comprises” and its variations are intended to cover a non-exclusive inclusion.
  • FIG. 1 is a schematic flow chart of a method for fabricating a TFT substrate according to a preferred embodiment of the present invention. As shown in FIG. 1, the manufacturing method of the TFT of the preferred embodiment includes the following steps:
  • S101 providing a substrate, forming a buffer layer, a data line, and a source on the substrate by using a first mask process, and disposing a first scan line, a second scan line, and a gate on the buffer layer;
  • the data line is electrically connected to the source
  • the second scan line is electrically connected to the gate
  • the gate is in a non-closed loop and is disposed around the source;
  • the second photoresist layer is removed to form an electrical connection portion on the first conductor layer and the second insulating layer, and a drain is formed on the second semiconductor layer, wherein the electrical connection portion
  • the first scan line is connected to the second scan line by the first conductor layer.
  • step S101 please refer to FIGS. 2A-2E.
  • 2A-2E are schematic diagrams showing the structure of a first photomask process corresponding to the substrate formed in the method for fabricating the TFT substrate shown in FIG. 2D is a plan view of the array substrate, and FIG. 2E is a cross-sectional view of the array substrate along the P1-P1 direction.
  • a substrate 11 is provided, a buffer layer 12 is formed on the substrate 11, and then a photoresist 13 is coated on the buffer layer 12.
  • the first scan region 131, the second scan region 132, the gate region 133A, the gate region 133B, and the data line are formed by a half exposure and full exposure process, an etching process, and a photoresist ashing process.
  • a metal layer 14 is formed on the substrate 11 by physical vapor deposition to cover the first scan region 131, the second scan region 132, the gate region 133A, the gate region 133B, and the data line. Region 121 and source region 122.
  • the material of the metal layer 14 may be copper/molybdenum, aluminum/molybdenum, molybdenum nitride/copper or the like.
  • the photoresist 13 and the metal layer 14 on the photoresist 13 are removed by a lift-off process to form a first scan line 101 and a second scan area 132 in the first scan area 131 to form a second.
  • the scan line 102, the gate region 133A, and the gate region 133B form the gate electrode 103
  • the data line region 134 forms the data line 104
  • the source region 122 forms the source electrode 105.
  • the data line 104 is electrically connected to the source 105
  • the second scan line 102 is electrically connected to the gate 103
  • the gate 103 is in a non-closed loop and is disposed around the source 105.
  • step S102 please refer to FIGS. 3A-3E.
  • 3A-3E are schematic diagrams showing the structure of a second photomask process corresponding to the substrate formed in the method for fabricating the TFT substrate shown in FIG.
  • an insulating material layer 15 is formed on the substrate by chemical vapor deposition.
  • the insulating material layer 15 is patterned. Referring to FIG. 3B and FIG. 3C, a photoresist 16 is coated on the substrate; and the photoresist 16 on the insulating material layer 15 on the first scan line 101, the second scan line 102, and the source 105 is passed through a yellow light process.
  • the pair is located on the first scan line 101, the second scan line 102, and the source 105 by an etching process
  • the upper insulating material layer 15 is etched to form a first insulating layer 151 on the buffer layer 12, the gate electrode 103, and a second insulating layer 152 is formed on the data line 104.
  • a layer of semiconductor material 17 is deposited over the entire surface of the substrate by physical vapor deposition to cover the first scan line 101, the second scan line 102, and the source.
  • the material of the semiconductor material layer 17 is indium gallium zinc oxide.
  • the semiconductor layer 17 on the photoresist layer 16 is removed by a lift-off process to form a first semiconductor layer 171A on the first scan line 101 and the second scan line 102, and a second semiconductor layer 172 on the source electrode 105.
  • steps S103-S105 please refer to Figures 4A-4F.
  • 4A-4F are schematic diagrams showing the structure of a substrate formed by a third mask process in the method for fabricating the TFT substrate shown in FIG. 4E is a plan view of the array substrate, and FIG. 4F is a cross-sectional view of the array substrate along the P2-P2 direction.
  • a photoresist 18 is coated on the substrate.
  • the photoresist on the first semiconductor layer 101 is fully exposed by a half exposure process to expose the first semiconductor layer 171A.
  • the photoresist on the second insulating layer 152 and the second semiconductor layer 172 is half-exposed to form a first photoresist layer 181 on the second insulating layer 152 and the second semiconductor layer 172 (ie, a half-exposed region).
  • a second photoresist layer 182 is formed on an insulating layer 151 (unexposed area). The thickness of the second photoresist layer 182 is greater than the thickness of the first photoresist layer 181.
  • the exposed first semiconductor layer 171A is subjected to a conductor treatment by using argon gas, nitrogen gas, and ammonia gas to form the first conductor layer 171B. Then, the photoresist 18 is ashed by introducing oxygen to make the photoresist 18 thin as a whole. Wherein, the photoresist of the half exposure region is all reacted to remove the first photoresist layer 181.
  • the second conductor layer 19 is deposited on the entire surface of the substrate by physical vapor deposition.
  • the material of the second conductor layer 19 is indium tin oxide.
  • the second photoresist layer 182 is removed by a photoresist stripping process to form an electrical connection portion 191 on the first conductor layer 171B and the second insulating layer 152, and a drain electrode 192 on the second semiconductor layer 172 to form a pixel electrode.
  • the electrical connection portion 191 connects the first scan line 101 and the second scan line 102 through the first conductor layer 171B.
  • a buffer layer, a data line, and a source are formed on the substrate by using a first mask process, and a first scan line is disposed on the buffer layer.
  • a second scanning line and a gate forming a first insulating layer on the buffer layer and the gate by using a second mask process, forming a second insulating layer on the data line, forming a first line on the first scan line and the second scan line a semiconductor layer, a second semiconductor layer is formed on the source; a first photoresist layer is formed on the second insulating layer and the second semiconductor layer by a third mask process, and a second photoresist is formed on the first insulating layer a layer, the first semiconductor layer is conductorized to form a first conductor layer, a second conductor layer is formed on the substrate, an electrical connection portion is formed on the first conductor layer and the second insulating layer, and a drain is formed on the second semiconductor layer .
  • the solution passes through the three mask processes to make the exposed first semiconductor conductor, the process step is simple, the production efficiency is improved, and the production cost is reduced.

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Abstract

提供一种TFT基板的制作方法，包括：利用第一道光罩工艺，在基板（11）上形成缓冲层（12）、数据线（104）、源极（105）、第一扫描线（101）、第二扫描线（102）以及栅极（103）；利用第二道光罩工艺，在基板（11）上形成第一绝缘层（151）、第二绝缘层（152）、第一半导体层（171A）以及第二半导体层（172）；利用第三道光罩工艺，在基板（11）上形成第一导体层（171B）、电连接部（191）以及漏极（192）。

Description

TFT基板的制作方法 技术领域
本发明涉及液晶面板制作领域，特别是涉及一种TFT基板的制作方法。
 背景技术
在信息社会的当代，作为可视信息传输媒介的显示器的重要性在进一步加强，为了在未来占据主导地位，显示器正朝着更轻、更薄、更低能耗、更低成本以及更好图像质量的趋势发展。
在液晶面板工业中，通过TFT基板来控制液晶的排列，从而实现不同灰度光线的显示，TFT基板为液晶面板中的重要部分，其生产也属于液晶面板制造过程中的重要工艺。
随着TFT技术的发展，制程Mask（光罩）需求从5/6 Mask降到现在主流的4Mask。每减少一道Mask，机器物料时间成本都会下降较多，大大提高产品竞争力。3Mask TFT因其节约一道Mask，较大幅度降低成本，相关技术较热门。
相关技术中采用环形栅极结构的TFT基板，因其性能优越，越来越受到人们的重视。然而，该环形栅极结构的TFT基板运用于量产时，其工艺步骤较复杂繁琐，导致制作成本较高。
因此，现有技术存在缺陷，急需改进。
 技术问题
本发明的目的在于提供一种改进的TFT基板的制作方法。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种TFT基板的制作方法，包括以下步骤：
提供一基板；
利用第一道光罩工艺，在该基板上形成缓冲层、数据线以及源极，并在该缓冲层上设置第一扫描线、第二扫描线以及栅极；其中，数据线与源极电连接，第二扫描线与栅极电连接，栅极呈非封闭环状且环绕源极设置；
利用第二道光罩工艺，在缓冲层、栅极上形成第一绝缘层，在数据线上形成第二绝缘层，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层；
在该基板上涂布光阻，利用第三道光罩工艺，对位于第一半导体层上的光阻全曝光，以使第一半导体层露出；对位于第二绝缘层以及第二半导体层上的光阻半曝光，以在第二绝缘层以及第二半导体层上形成第一光阻层，在第一绝缘层上形成第二光阻层；
对第一半导体层导体化以形成第一导体层，然后去除第一光阻层；
在基板上形成第二导体层后去除第二光阻层，以在第一导体层以及第二绝缘层上形成电连接部、在第二半导体层上形成漏极，其中，电连接部通过第一导体层使得第一扫描线与第二扫描线连接。
在一些实施例中，在该基板上形成缓冲层、数据线以及源极，并在该缓冲层上设置第一扫描线、第二扫描线以及栅极的步骤，包括：
在该基板上形成缓冲层；
在缓冲层上涂布光阻；
通过黄光工艺和蚀刻工艺，形成第一扫描区域、第二扫描区域、栅极区域、数据线区域以及源极区域；
在该基板上沉积金属层后剥离光阻，以在第一扫描区域形成第一扫描线、第二扫描区域形成第二扫描线、栅极区域形成栅极、数据线区域形成数据线，以及在源极区域形成源极。
在一些实施例中，在缓冲层、栅极上形成第一绝缘层，在数据线上形成第二绝缘层，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层的步骤，包括：
在该基板上形成绝缘材料层；
对该绝缘材料层进行图形化处理，以使第一扫描线、第二扫描线以及源极露出，在缓冲层、栅极上形成第一绝缘层，以及在数据线上形成第二绝缘层；
在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层。
在一些实施例中，对该绝缘材料层进行图形化处理的步骤，包括：
在该基板上涂布光阻；
通过黄光工艺，对位于第一扫描线、第二扫描线以及源极上的绝缘材料层上的光阻全曝光，以使位于第一扫描线、第二扫描线以及源极上的绝缘材料层露出；
通过刻蚀工艺，对位于第一扫描线、第二扫描线以及源极上的绝缘材料层进行刻蚀。
在一些实施例中，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层的步骤，包括：
通过物理气相沉法，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层。
在一些实施例中，对第一半导体层导体化以形成第一导体层，然后去除第一光阻层的步骤，包括：
对第一半导体层导体化以形成第一导体层；
对光阻进行灰化，以去除第一光阻层。
在一些实施例中，在基板上形成第二导体层后去除第二光阻层的步骤，包括：
通过物理气相沉积法，在基板上形成第二导体层；
通过光阻剥离工艺，去除第二光阻层。
在一些实施例中，第一半导体层、第二半导体层的材料为铟镓锌氧化物。
在一些实施例中，第二导体层的材料为氧化铟锡。
在一些实施例中，缓冲层为氮化硅层、氧化硅层或氧化铝层。
本发明还提供另一种TFT基板的制作方法，包括以下步骤：
提供一基板；
在该基板上形成缓冲层，并在缓冲层上涂布光阻，然后利用第一道光罩工艺，通过黄光工艺和蚀刻工艺，形成第一扫描区域、第二扫描区域、栅极区域、数据线区域以及源极区域；
在该基板上沉积金属层后剥离光阻，以在第一扫描区域形成第一扫描线、第二扫描区域形成第二扫描线、栅极区域形成栅极、数据线区域形成数据线，以及在源极区域形成源极；其中，数据线与源极电连接，第二扫描线与栅极电连接，栅极呈非封闭环状且环绕源极设置；
在该基板上形成绝缘材料层，利用第二道光罩工艺，对该绝缘材料层进行图形化处理，以使第一扫描线、第二扫描线以及源极露出，在缓冲层、栅极上形成第一绝缘层，以及在数据线上形成第二绝缘层；在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层；
在该基板上涂布光阻，利用第三道光罩工艺，对位于第一半导体层上的光阻全曝光，以使第一半导体层露出；对位于第二绝缘层以及第二半导体层上的光阻半曝光，以在第二绝缘层以及第二半导体层上形成第一光阻层，在第一绝缘层上形成第二光阻层；
对第一半导体层导体化以形成第一导体层，然后去除第一光阻层；
在基板上形成第二导体层后去除第二光阻层，以在第一导体层以及第二绝缘层上形成电连接部、在第二半导体层上形成漏极，其中，电连接部通过第一导体层使得第一扫描线与第二扫描线连接。
在一些实施例中，对该绝缘材料层进行图形化处理的步骤，包括：
在该基板上涂布光阻；
通过黄光工艺，对位于第一扫描线、第二扫描线以及源极上的绝缘材料层上的光阻全曝光，以使位于第一扫描线、第二扫描线以及源极上的绝缘材料层露出；
通过刻蚀工艺，对位于第一扫描线、第二扫描线以及源极上的绝缘材料层进行刻蚀。
在一些实施例中，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层的步骤，包括：
通过物理气相沉法，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层。
在一些实施例中，对第一半导体层导体化以形成第一导体层，然后去除第一光阻层的步骤，包括：
对第一半导体层导体化以形成第一导体层；
对光阻进行灰化，以去除第一光阻层。
在一些实施例中，对第一半导体层导体化以形成第一导体层的步骤包括：
使用氩气、氮气以及氨气对第一半导体层导体化，以形成第一导体层。
在一些实施例中，在基板上形成第二导体层后去除第二光阻层的步骤，包括：
通过物理气相沉积法，在基板上形成第二导体层；
通过光阻剥离工艺，去除第二光阻层。
在一些实施例中，第一半导体层、第二半导体层的材料为铟镓锌氧化物。
在一些实施例中，第二导体层的材料为氧化铟锡。
在一些实施例中，缓冲层为氮化硅层、氧化硅层或氧化铝层。
在一些实施例中，第二光阻层的厚度大于第一光阻层的厚度。
 有益效果
相较于现有的TFT基板的制作方法，本发明利用第一道光罩工艺，在该基板上形成缓冲层、数据线以及源极，并在该缓冲层上设置第一扫描线、第二扫描线以及栅极；其中，数据线与源极电连接，第二扫描线与栅极电连接，栅极呈非封闭环状且环绕源极设置；
利用第二道光罩工艺，在缓冲层、栅极上形成第一绝缘层，在数据线上形成第二绝缘层，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层；在该基板上涂布光阻，利用第三道光罩工艺，对位于第一半导体层上的光阻全曝光，以使第一半导体层露出；对位于第二绝缘层以及第二半导体层上的光阻半曝光，以在第二绝缘层以及第二半导体层上形成第一光阻层，在第一绝缘层上形成第二光阻层；对第一半导体层导体化以形成第一导体层，然后去除第一光阻层；在基板上形成第二导体层后去除第二光阻层，以在第一导体层以及第二绝缘层上形成电连接部、在第二半导体层上形成漏极，其中，电连接部通过第一导体层使得第一扫描线与第二扫描线连接。该方案通过三道光罩工艺，使露出的第一半导体导体化，工艺步骤较简单，提高了生产效率，同时降低了生产成本。
 附图说明
图1为本发明优选实施例中TFT基板的制作方法的流程示意图。
图2A-2E为图1所示TFT基板的制作方法中第一道光罩工艺对应形成基板的结构示意图。
图3A-3E为图1所示TFT基板的制作方法中第二道光罩工艺对应基板的结构示意图。
图4A-4F为图1所示TFT基板的制作方法中第三道光罩工艺对应基板的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的模块是以相同标号表示。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
参阅图1，图1为本发明优选实施例提供的TFT基板的制作方法的流程示意图。如图1所示，本优选实施例的TFT的制作方法，包括以下步骤：
S101、提供一基板，利用第一道光罩工艺，在该基板上形成缓冲层、数据线以及源极，并在该缓冲层上设置第一扫描线、第二扫描线以及栅极；其中，数据线与源极电连接，第二扫描线与栅极电连接，栅极呈非封闭环状且环绕源极设置；
S102、利用第二道光罩工艺，在缓冲层、栅极上形成第一绝缘层，在数据线上形成第二绝缘层，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层；
S103、在该基板上涂布光阻，利用第三道光罩工艺，对位于第一半导体层上的光阻全曝光，以使第一半导体层露出；对位于第二绝缘层以及第二半导体层上的光阻半曝光，以在第二绝缘层以及第二半导体层上形成第一光阻层，在第一绝缘层上形成第二光阻层；
S104、对第一半导体层导体化以形成第一导体层，然后去除第一光阻层；
S105、在基板上形成第二导体层后去除第二光阻层，以在第一导体层以及第二绝缘层上形成电连接部、在第二半导体层上形成漏极，其中，电连接部通过第一导体层使得第一扫描线与第二扫描线连接。
在一些实施方式中，步骤S101，请参考图2A-2E。图2A-2E为图1所示TFT基板的制作方法中第一道光罩工艺对应形成基板的结构示意图。其中，图2D为阵列基板的俯视图，图2E为阵列基板沿P1-P1方向的剖面图。
如图2A所示，提供一基板11，在该基板11上形成缓冲层12，然后，在缓冲层12上涂布光阻13。
随后，如图2B所示，通过半曝光和全曝光工艺、蚀刻工艺以及光阻灰化处理，形成第一扫描区域131、第二扫描区域132、栅极区域133A、栅极区域133B、数据线区域121以及源极区域122。
接着，如图2C所示，通过物理气相沉积发，在该基板11上形成金属层14，以覆盖第一扫描区域131、第二扫描区域132、栅极区域133A、栅极区域133B、数据线区域121以及源极区域122。其中，该金属层14的材料可以为铜/钼，铝/钼，钛化钼/铜等。
最后，参考图2D、图2E，通过剥离工艺，去除光阻13以及位于光阻13上的金属层14，以在第一扫描区域131形成第一扫描线101、第二扫描区域132形成第二扫描线102、栅极区域133A和栅极区域133B形成栅极103、数据线区域134形成数据线104，以及在源极区域122形成源极105。其中，数据线104与源极105电连接，第二扫描线102与栅极103电连接，栅极103呈非封闭环状且环绕源极105设置。
在一些实施方式中，步骤S102，请参考图3A-3E。图3A-3E为图1所示TFT基板的制作方法中第二道光罩工艺对应形成基板的结构示意图。
如图3A所示，通过化学气相沉积法，在该基板上形成绝缘材料层15。
随后，对该绝缘材料层15进行图形化处理。参考图3B和图3C，在该基板上涂布光阻16；通过黄光工艺，对位于第一扫描线101、第二扫描线102以及源极105上的绝缘材料层15上的光阻16全曝光，以使第一扫描线101、第二扫描线102以及源极105上的绝缘材料层15露出；通过刻蚀工艺，对位于第一扫描线101、第二扫描线102以及源极105上的绝缘材料层15进行刻蚀，以在缓冲层12、栅极103上形成第一绝缘层151，以及在数据线104上形成第二绝缘层152。
接着，参考图3D。通过物理气相沉法，在基板上整面沉积半导体材料层17，以覆盖第一扫描线101、第二扫描线102以及源极。其中，半导体材料层17的材料为铟镓锌氧化物。
最后，参考图3E。通过剥离工艺，去除光阻层16上的半导体层17，以在第一扫描线101、第二扫描线102上形成第一半导体层171A，在源极105上形成第二半导体层172。
在一些实施方式中，步骤S103-S105，请参考图4A-4F。图4A-4F为图1所示TFT基板的制作方法中第三道光罩工艺对应形成基板的结构示意图。其中，图4E为阵列基板的俯视图，图4F为阵列基板沿P2-P2方向的剖面图。
如图4A所示，在该基板上涂布光阻18。
随后，参考图4B。通过半曝光工艺，对位于第一半导体层101上的光阻全曝光，以使第一半导体层171A露出。对位于第二绝缘层152以及第二半导体层172上的光阻半曝光，以在第二绝缘层152以及第二半导体层172上（即半曝光区域）形成第一光阻层181，在第一绝缘层151上（未曝光区域）形成第二光阻层182。其中，第二光阻层182的厚度大于第一光阻层181的厚度。
接着，参考图4C。通过使用氩气、氮气以及氨气对露出的第一半导体层171A导体化处理，以形成第一导体层171B。然后，，通入氧气对对光阻18进行灰化处理，使光阻18整体减薄。其中，半曝光区域的光阻全部反应掉，以去除第一光阻层181。
然后，参考图4D。通过物理气相沉积法，在基板上整面沉积第二导体层19。其中，第二导体层19的材料为氧化铟锡。
最后，参考图4E和4F。通过光阻剥离工艺，去除第二光阻层182，以在第一导体层171B以及第二绝缘层152上形成电连接部191、在第二半导体层172上形成漏极192，同时形成像素电极Q。其中，电连接部191通过第一导体层171B使得第一扫描线101与第二扫描线102连接。
由上可知，本发明实施例提供的TFT基板的制作方法，利用第一道光罩工艺，在基板上形成缓冲层、数据线以及源极，并在该缓冲层上设置第一扫描线、第二扫描线以及栅极；利用第二道光罩工艺，在缓冲层、栅极上形成第一绝缘层，在数据线上形成第二绝缘层，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层；利用第三道光罩工艺，在第二绝缘层以及第二半导体层上形成第一光阻层，在第一绝缘层上形成第二光阻层，对第一半导体层导体化以形成第一导体层，在基板上形成第二导体层，在第一导体层以及第二绝缘层上形成电连接部、在第二半导体层上形成漏极。该方案通过三道光罩工艺，使露出的第一半导体导体化，工艺步骤较简单，提高了生产效率，同时降低了生产成本。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种TFT基板的制作方法，其中，包括以下步骤：
    提供一基板；
    利用第一道光罩工艺，在该基板上形成缓冲层、数据线以及源极，并在该缓冲层上设置第一扫描线、第二扫描线以及栅极；其中，数据线与源极电连接，第二扫描线与栅极电连接，栅极呈非封闭环状且环绕源极设置；
    利用第二道光罩工艺，在缓冲层、栅极上形成第一绝缘层，在数据线上形成第二绝缘层，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层；
    在该基板上涂布光阻，利用第三道光罩工艺，对位于第一半导体层上的光阻全曝光，以使第一半导体层露出；对位于第二绝缘层以及第二半导体层上的光阻半曝光，以在第二绝缘层以及第二半导体层上形成第一光阻层，在第一绝缘层上形成第二光阻层；
    对第一半导体层导体化以形成第一导体层，然后去除第一光阻层；
    在基板上形成第二导体层后去除第二光阻层，以在第一导体层以及第二绝缘层上形成电连接部、在第二半导体层上形成漏极，其中，电连接部通过第一导体层使得第一扫描线与第二扫描线连接。
  2. 如权利要求1所述的TFT基板的制作方法，其中，在该基板上形成缓冲层、数据线以及源极，并在该缓冲层上设置第一扫描线、第二扫描线以及栅极的步骤，包括：
    在该基板上形成缓冲层；
    在缓冲层上涂布光阻；
    通过黄光工艺和蚀刻工艺，形成第一扫描区域、第二扫描区域、栅极区域、数据线区域以及源极区域；
    在该基板上沉积金属层后剥离光阻，以在第一扫描区域形成第一扫描线、第二扫描区域形成第二扫描线、栅极区域形成栅极、数据线区域形成数据线，以及在源极区域形成源极。
  3. 如权利要求1所述的TFT基板的制作方法，其中，在缓冲层、栅极上形成第一绝缘层，在数据线上形成第二绝缘层，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层的步骤，包括：
    在该基板上形成绝缘材料层；
    对该绝缘材料层进行图形化处理，以使第一扫描线、第二扫描线以及源极露出，在缓冲层、栅极上形成第一绝缘层，以及在数据线上形成第二绝缘层；
    在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层。
  4. 如权利要求3所述的TFT基板的制作方法，其中， 对该绝缘材料层进行图形化处理的步骤，包括：
    在该基板上涂布光阻；
    通过黄光工艺，对位于第一扫描线、第二扫描线以及源极上的绝缘材料层上的光阻全曝光，以使位于第一扫描线、第二扫描线以及源极上的绝缘材料层露出；
    通过刻蚀工艺，对位于第一扫描线、第二扫描线以及源极上的绝缘材料层进行刻蚀。
  5. 如权利要求4所述的TFT基板的制作方法，其中，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层的步骤，包括：
    通过物理气相沉法，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层。
  6. 如权利要求1所述的TFT基板的制作方法，其中，对第一半导体层导体化以形成第一导体层，然后去除第一光阻层的步骤，包括：
    对第一半导体层导体化以形成第一导体层；
    对光阻进行灰化，以去除第一光阻层。
  7. 如权利要求1所述的TFT基板的制作方法，其中，在基板上形成第二导体层后去除第二光阻层的步骤，包括：
    通过物理气相沉积法，在基板上形成第二导体层；
    通过光阻剥离工艺，去除第二光阻层。
  8. 如权利要求1所述的TFT基板的制作方法，其中，第一半导体层、第二半导体层的材料为铟镓锌氧化物。
  9. 如权利要求1所述的TFT基板的制作方法，其中， 第二导体层的材料为氧化铟锡。
  10. 如权利要求1所述的TFT基板的制作方法，其中，缓冲层为氮化硅层、氧化硅层或氧化铝层。
  11. 一种TFT基板的制作方法，其中，包括以下步骤：
    提供一基板；
    在该基板上形成缓冲层，并在缓冲层上涂布光阻，然后利用第一道光罩工艺，通过黄光工艺和蚀刻工艺，形成第一扫描区域、第二扫描区域、栅极区域、数据线区域以及源极区域；
    在该基板上沉积金属层后剥离光阻，以在第一扫描区域形成第一扫描线、第二扫描区域形成第二扫描线、栅极区域形成栅极、数据线区域形成数据线，以及在源极区域形成源极；其中，数据线与源极电连接，第二扫描线与栅极电连接，栅极呈非封闭环状且环绕源极设置；
    在该基板上形成绝缘材料层，利用第二道光罩工艺，对该绝缘材料层进行图形化处理，以使第一扫描线、第二扫描线以及源极露出，在缓冲层、栅极上形成第一绝缘层，以及在数据线上形成第二绝缘层；在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层；
    在该基板上涂布光阻，利用第三道光罩工艺，对位于第一半导体层上的光阻全曝光，以使第一半导体层露出；对位于第二绝缘层以及第二半导体层上的光阻半曝光，以在第二绝缘层以及第二半导体层上形成第一光阻层，在第一绝缘层上形成第二光阻层；
    对第一半导体层导体化以形成第一导体层，然后去除第一光阻层；
    在基板上形成第二导体层后去除第二光阻层，以在第一导体层以及第二绝缘层上形成电连接部、在第二半导体层上形成漏极，其中，电连接部通过第一导体层使得第一扫描线与第二扫描线连接。
  12. 如权利要求11所述的TFT基板的制作方法，其中，对该绝缘材料层进行图形化处理的步骤，包括：
    在该基板上涂布光阻；
    通过黄光工艺，对位于第一扫描线、第二扫描线以及源极上的绝缘材料层上的光阻全曝光，以使位于第一扫描线、第二扫描线以及源极上的绝缘材料层露出；
    通过刻蚀工艺，对位于第一扫描线、第二扫描线以及源极上的绝缘材料层进行刻蚀。
  13. 如权利要求12所述的TFT基板的制作方法，其中，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层的步骤，包括：
    通过物理气相沉法，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层。
  14. 如权利要求11所述的TFT基板的制作方法，其中，对第一半导体层导体化以形成第一导体层，然后去除第一光阻层的步骤，包括：
    对第一半导体层导体化以形成第一导体层；
    对光阻进行灰化，以去除第一光阻层。
  15. 如权利要求14所述的TFT基板的制作方法，其中，对第一半导体层导体化以形成第一导体层的步骤包括：
    使用氩气、氮气以及氨气对第一半导体层导体化，以形成第一导体层。
  16. 如权利要求11所述的TFT基板的制作方法，其中，在基板上形成第二导体层后去除第二光阻层的步骤，包括：
    通过物理气相沉积法，在基板上形成第二导体层；
    通过光阻剥离工艺，去除第二光阻层。
  17. 如权利要求11所述的TFT基板的制作方法，其中，第一半导体层、第二半导体层的材料为铟镓锌氧化物。
  18. 如权利要求11所述的TFT基板的制作方法，其中，第二导体层的材料为氧化铟锡。
  19. 如权利要求11所述的TFT基板的制作方法，其中，缓冲层为氮化硅层、氧化硅层或氧化铝层。
  20. 如权利要求11所述的TFT基板的制作方法，其中，第二光阻层的厚度大于第一光阻层的厚度。
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