CN106981456A - Tft基板的制作方法 - Google Patents

Tft基板的制作方法 Download PDF

Info

Publication number
CN106981456A
CN106981456A CN201710212917.1A CN201710212917A CN106981456A CN 106981456 A CN106981456 A CN 106981456A CN 201710212917 A CN201710212917 A CN 201710212917A CN 106981456 A CN106981456 A CN 106981456A
Authority
CN
China
Prior art keywords
layer
scan line
semiconductor layer
substrate
source electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710212917.1A
Other languages
English (en)
Other versions
CN106981456B (zh
Inventor
周志超
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to CN201710212917.1A priority Critical patent/CN106981456B/zh
Priority to US15/570,754 priority patent/US10367016B2/en
Priority to PCT/CN2017/082815 priority patent/WO2018176568A1/zh
Publication of CN106981456A publication Critical patent/CN106981456A/zh
Application granted granted Critical
Publication of CN106981456B publication Critical patent/CN106981456B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H01L21/441—Deposition of conductive or insulating materials for electrodes
    • H01L21/443—Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/4757—After-treatment
    • H01L21/47573—Etching the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

本发明提供了一种TFT基板的制作方法。该制作方法包括以下步骤：利用第一道光罩工艺，在基板上形成缓冲层、数据线以及源极，并在该缓冲层上设置第一扫描线、第二扫描线以及栅极；利用第二道光罩工艺，在缓冲层、栅极上形成第一绝缘层，在数据线上形成第二绝缘层，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层；利用第三道光罩工艺，在第二绝缘层以及第二半导体层上形成第一光阻层，在第一绝缘层上形成第二光阻层，对第一半导体层导体化以形成第一导体层，在基板上形成第二导体层，在第一导体层以及第二绝缘层上形成电连接部、在第二半导体层上形成漏极。该方案工艺步骤简单，可提高生产效率，降低生产成本。

Description

TFT基板的制作方法
技术领域
本发明涉及液晶面板制作领域，特别是涉及一种TFT基板的制作方法。
背景技术
在信息社会的当代，作为可视信息传输媒介的显示器的重要性在进一步加强，为了在未来占据主导地位，显示器正朝着更轻、更薄、更低能耗、更低成本以及更好图像质量的趋势发展。
在液晶面板工业中，通过TFT基板来控制液晶的排列，从而实现不同灰度光线的显示，TFT基板为液晶面板中的重要部分，其生产也属于液晶面板制造过程中的重要工艺。
随着TFT技术的发展，制程Mask(光罩)需求从5/6Mask降到现在主流的4Mask。每减少一道Mask，机器物料时间成本都会下降较多，大大提高产品竞争力。3Mask TFT因其节约一道Mask，较大幅度降低成本，相关技术较热门。
相关技术中采用环形栅极结构的TFT基板，因其性能优越，越来越受到人们的重视。然而，该环形栅极结构的TFT基板运用于量产时，其工艺步骤较复杂繁琐，导致制作成本较高。
因此，现有技术存在缺陷，急需改进。
发明内容
本发明的目的在于提供一种改进的TFT基板的制作方法。
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种TFT基板的的制作方法，包括以下步骤：
提供一基板；
利用第一道光罩工艺，在该基板上形成缓冲层、数据线以及源极，并在该缓冲层上设置第一扫描线、第二扫描线以及栅极；其中，数据线与源极电连接，第二扫描线与栅极电连接，栅极呈玦状且环绕源极设置；
利用第二道光罩工艺，在缓冲层、栅极上形成第一绝缘层，在数据线上形成第二绝缘层，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层；
在该基板上涂布光阻，利用第三道光罩工艺，对位于第一半导体层上的光阻全曝光，以使第一半导体层露出；对位于第二绝缘层以及第二半导体层上的光阻半曝光，以在第二绝缘层以及第二半导体层上形成第一光阻层，在第一绝缘层上形成第二光阻层；
对第一半导体层导体化以形成第一导体层，然后去除第一光阻层；
在基板上形成第二导体层后去除第二光阻层，以在第一导体层以及第二绝缘层上形成电连接部、在第二半导体层上形成漏极，其中，电连接部通过第一导体层使得第一扫描线与第二扫描线连接。
在一些实施例中，在该基板上形成缓冲层、数据线以及源极，并在该缓冲层上设置第一扫描线、第二扫描线以及栅极的步骤，包括：
在该基板上形成缓冲层；
在缓冲层上涂布光阻；
通过黄光工艺和蚀刻工艺，形成第一扫描区域、第二扫描区域、栅极区域、数据线区域以及源极区域；
在该基板上沉积金属层后剥离光阻，以在第一扫描区域形成第一扫描线、第二扫描区域形成第二扫描线、栅极区域形成栅极、数据线区域形成数据线，以及在源极区域形成源极。
在一些实施例中，在缓冲层、栅极上形成第一绝缘层，在数据线上形成第二绝缘层，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层的步骤，包括：
在该基板上形成绝缘材料层；
对该绝缘材料层进行图形化处理，以使第一扫描线、第二扫描线以及源极露出，在缓冲层、栅极上形成第一绝缘层，以及在数据线上形成第二绝缘层；
在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层。
在一些实施例中，对该绝缘材料层进行图形化的步骤，包括：
在该基板上涂布光阻；
通过黄光工艺，对位于第一扫描线、第二扫描线以及源极上的绝缘材料层上的光阻全曝光，以使位于第一扫描线、第二扫描线以及源极上的绝缘材料层露出；
通过刻蚀工艺，对位于第一扫描线、第二扫描线以及源极上的绝缘材料层进行刻蚀。
在一些实施例中，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层的步骤，包括：
通过物理气相沉法，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层。
在一些实施例中，对第一半导体层导体化以形成第一导体层，然后去除第一光阻层的步骤，包括：
对第一半导体层导体化以形成第一导体层；
对光阻进行灰化，以去除第一光阻层。
在一些实施例中，在基板上形成第二导体层后去除第二光阻层的步骤，包括：
通过物理气相沉积法，在基板上形成第二导体层；
通过光阻剥离工艺，去除第二光阻层。
在一些实施例中，第一半导体层、第二半导体层的材料为铟镓锌氧化物。
在一些实施例中，第二导体层的材料为氧化铟锡。
在一些实施例中，缓冲层为氮化硅层、氧化硅层或氧化铝层。
相较于现有的TFT基板的制作方法，本发明利用第一道光罩工艺，在该基板上形成缓冲层、数据线以及源极，并在该缓冲层上设置第一扫描线、第二扫描线以及栅极；其中，数据线与源极电连接，第二扫描线与栅极电连接，栅极呈玦状且环绕源极设置；利用第二道光罩工艺，在缓冲层、栅极上形成第一绝缘层，在数据线上形成第二绝缘层，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层；在该基板上涂布光阻，利用第三道光罩工艺，对位于第一半导体层上的光阻全曝光，以使第一半导体层露出；对位于第二绝缘层以及第二半导体层上的光阻半曝光，以在第二绝缘层以及第二半导体层上形成第一光阻层，在第一绝缘层上形成第二光阻层；对第一半导体层导体化以形成第一导体层，然后去除第一光阻层；在基板上形成第二导体层后去除第二光阻层，以在第一导体层以及第二绝缘层上形成电连接部、在第二半导体层上形成漏极，其中，电连接部通过第一导体层使得第一扫描线与第二扫描线连接。该方案通过三道光罩工艺，使露出的第一半导体导体化，工艺步骤较简单，提高了生产效率，同时降低了生产成本。
附图说明
图1为本发明优选实施例中TFT基板的制作方法的流程示意图。
图2A-2E为图1所示TFT基板的制作方法中第一道光罩工艺对应形成基板的结构示意图。
图3A-3E为图1所示TFT基板的制作方法中第二道光罩工艺对应基板的结构示意图。
图4A-4F为图1所示TFT基板的制作方法中第三道光罩工艺对应基板的结构示意图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的模块是以相同标号表示。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
参阅图1，图1为本发明优选实施例提供的TFT基板的制作方法的流程示意图。如图1所示，本优选实施例的TFT的制作方法，包括以下步骤：
S101、提供一基板，利用第一道光罩工艺，在该基板上形成缓冲层、数据线以及源极，并在该缓冲层上设置第一扫描线、第二扫描线以及栅极；其中，数据线与源极电连接，第二扫描线与栅极电连接，栅极呈玦状且环绕源极设置；
S102、利用第二道光罩工艺，在缓冲层、栅极上形成第一绝缘层，在数据线上形成第二绝缘层，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层；
S103、在该基板上涂布光阻，利用第三道光罩工艺，对位于第一半导体层上的光阻全曝光，以使第一半导体层露出；对位于第二绝缘层以及第二半导体层上的光阻半曝光，以在第二绝缘层以及第二半导体层上形成第一光阻层，在第一绝缘层上形成第二光阻层；
S104、对第一半导体层导体化以形成第一导体层，然后去除第一光阻层；
S105、在基板上形成第二导体层后去除第二光阻层，以在第一导体层以及第二绝缘层上形成电连接部、在第二半导体层上形成漏极，其中，电连接部通过第一导体层使得第一扫描线与第二扫描线连接。
在一些实施方式中，步骤S101，请参考图2A-2E。图2A-2E为图1所示TFT基板的制作方法中第一道光罩工艺对应形成基板的结构示意图。其中，图2D为阵列基板的俯视图，图2E为阵列基板沿P1-P1方向的剖面图。
如图2A所示，提供一基板11，在该基板11上形成缓冲层12，然后，在缓冲层12上涂布光阻13。
随后，如图2B所示，通过半曝光和全曝光工艺、蚀刻工艺以及光阻灰化处理，形成第一扫描区域131、第二扫描区域132、栅极区域133A、栅极区域133B、数据线区域121以及源极区域122。
接着，如图2C所示，通过物理气相沉积发，在该基板11上形成金属层14，以覆盖第一扫描区域131、第二扫描区域132、栅极区域133A、栅极区域133B、数据线区域121以及源极区域122。其中，该金属层14的材料可以为铜/钼，铝/钼，钛化钼/铜等。
最后，参考图2D、图2E，通过剥离工艺，去除光阻13以及位于光阻13上的金属层14，以在第一扫描区域131形成第一扫描线101、第二扫描区域132形成第二扫描线102、栅极区域133A和栅极区域133B形成栅极103、数据线区域134形成数据线104，以及在源极区域122形成源极105。其中，数据线104与源极105电连接，第二扫描线102与栅极103电连接，栅极103呈玦状且环绕源极105设置。
在一些实施方式中，步骤S102，请参考图3A-3E。图3A-3E为图1所示TFT基板的制作方法中第二道光罩工艺对应形成基板的结构示意图。
如图3A所示，通过化学气相沉积法，在该基板上形成绝缘材料层15。
随后，对该绝缘材料层15进行图形化处理。参考图3B和图3C，在该基板上涂布光阻16；通过黄光工艺，对位于第一扫描线101、第二扫描线102以及源极105上的绝缘材料层15上的光阻16全曝光，以使第一扫描线101、第二扫描线102以及源极105上的绝缘材料层15露出；通过刻蚀工艺，对位于第一扫描线101、第二扫描线102以及源极105上的绝缘材料层15进行刻蚀，以在缓冲层12、栅极103上形成第一绝缘层151，以及在数据线104上形成第二绝缘层152。
接着，参考图3D。通过物理气相沉法，在基板上整面沉积半导体材料层17，以覆盖第一扫描线101、第二扫描线102以及源极。其中，半导体材料层17的材料为铟镓锌氧化物。
最后，参考图3E。通过剥离工艺，去除光阻层16上的半导体层17，以在第一扫描线101、第二扫描线102上形成第一半导体层171A，在源极105上形成第二半导体层172。
在一些实施方式中，步骤S103-S105，请参考图4A-4F。图4A-4F为图1所示TFT基板的制作方法中第三道光罩工艺对应形成基板的结构示意图。其中，图4E为阵列基板的俯视图，图4F为阵列基板沿P2-P2方向的剖面图。
如图4A所示，在该基板上涂布光阻18。
随后，参考图4B。通过半曝光工艺，对位于第一半导体层101上的光阻全曝光，以使第一半导体层171A露出。对位于第二绝缘层152以及第二半导体层172上的光阻半曝光，以在第二绝缘层152以及第二半导体层172上(即半曝光区域)形成第一光阻层181，在第一绝缘层151上(未曝光区域)形成第二光阻层182。其中，第二光阻层182的厚度大于第一光阻层181的厚度。
接着，参考图4C。通过使用氩气、氮气以及氨气对露出的第一半导体层171A导体化处理，以形成第一导体层171B。然后，，通入氧气对对光阻18进行灰化处理，使光阻18整体减薄。其中，半曝光区域的光阻全部反应掉，以去除第一光阻层181。
然后，参考图4D。通过物理气相沉积法，在基板上整面沉积第二导体层19。其中，第二导体层19的材料为氧化铟锡。
最后，参考图4E和4F。通过光阻剥离工艺，去除第二光阻层182，以在第一导体层171B以及第二绝缘层152上形成电连接部191、在第二半导体层172上形成漏极192，同时形成像素电极Q。其中，电连接部191通过第一导体层171B使得第一扫描线101与第二扫描线102连接。
由上可知，本发明实施例提供的TFT基板的制作方法，利用第一道光罩工艺，在基板上形成缓冲层、数据线以及源极，并在该缓冲层上设置第一扫描线、第二扫描线以及栅极；利用第二道光罩工艺，在缓冲层、栅极上形成第一绝缘层，在数据线上形成第二绝缘层，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层；利用第三道光罩工艺，在第二绝缘层以及第二半导体层上形成第一光阻层，在第一绝缘层上形成第二光阻层，对第一半导体层导体化以形成第一导体层，在基板上形成第二导体层，在第一导体层以及第二绝缘层上形成电连接部、在第二半导体层上形成漏极。该方案通过三道光罩工艺，使露出的第一半导体导体化，工艺步骤较简单，提高了生产效率，同时降低了生产成本。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (10)

1.一种TFT基板的的制作方法，其特征在于，包括以下步骤：
提供一基板；
利用第一道光罩工艺，在该基板上形成缓冲层、数据线以及源极，并在该缓冲层上设置第一扫描线、第二扫描线以及栅极；其中，数据线与源极电连接，第二扫描线与栅极电连接，栅极呈玦状且环绕源极设置；
利用第二道光罩工艺，在缓冲层、栅极上形成第一绝缘层，在数据线上形成第二绝缘层，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层；
在该基板上涂布光阻，利用第三道光罩工艺，对位于第一半导体层上的光阻全曝光，以使第一半导体层露出；对位于第二绝缘层以及第二半导体层上的光阻半曝光，以在第二绝缘层以及第二半导体层上形成第一光阻层，在第一绝缘层上形成第二光阻层；
对第一半导体层导体化以形成第一导体层，然后去除第一光阻层；
在基板上形成第二导体层后去除第二光阻层，以在第一导体层以及第二绝缘层上形成电连接部、在第二半导体层上形成漏极，其中，电连接部通过第一导体层使得第一扫描线与第二扫描线连接。
2.如权利要求1所述的TFT基板的的制作方法，其特征在于，在该基板上形成缓冲层、数据线以及源极，并在该缓冲层上设置第一扫描线、第二扫描线以及栅极的步骤，包括：
在该基板上形成缓冲层；
在缓冲层上涂布光阻；
通过黄光工艺和蚀刻工艺，形成第一扫描区域、第二扫描区域、栅极区域、数据线区域以及源极区域；
在该基板上沉积金属层后剥离光阻，以在第一扫描区域形成第一扫描线、第二扫描区域形成第二扫描线、栅极区域形成栅极、数据线区域形成数据线，以及在源极区域形成源极。
3.如权利要求1所述的TFT基板的的制作方法，其特征在于，在缓冲层、栅极上形成第一绝缘层，在数据线上形成第二绝缘层，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层的步骤，包括：
在该基板上形成绝缘材料层；
对该绝缘材料层进行图形化处理，以使第一扫描线、第二扫描线以及源极露出，在缓冲层、栅极上形成第一绝缘层，以及在数据线上形成第二绝缘层；
在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层。
4.如权利要求3所述的TFT基板的的制作方法，其特征在于，对该绝缘材料层进行图形化的步骤，包括：
在该基板上涂布光阻；
通过黄光工艺，对位于第一扫描线、第二扫描线以及源极上的绝缘材料层上的光阻全曝光，以使位于第一扫描线、第二扫描线以及源极上的绝缘材料层露出；
通过刻蚀工艺，对位于第一扫描线、第二扫描线以及源极上的绝缘材料层进行刻蚀。
5.如权利要求4所述的TFT基板的的制作方法，其特征在于，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层的步骤，包括：
通过物理气相沉法，在第一扫描线、第二扫描线上形成第一半导体层，在源极上形成第二半导体层。
6.如权利要求1所述的TFT基板的的制作方法，其特征在于，对第一半导体层导体化以形成第一导体层，然后去除第一光阻层的步骤，包括：
对第一半导体层导体化以形成第一导体层；
对光阻进行灰化，以去除第一光阻层。
7.如权利要求1所述的TFT基板的的制作方法，其特征在于，在基板上形成第二导体层后去除第二光阻层的步骤，包括：
通过物理气相沉积法，在基板上形成第二导体层；
通过光阻剥离工艺，去除第二光阻层。
8.如权利要求1所述的TFT基板的制作方法，其特征在于，第一半导体层、第二半导体层的材料为铟镓锌氧化物。
9.如权利要求1所述的TFT基板的的制作方法，其特征在于，第二导体层的材料为氧化铟锡。
10.如权利要求1所述的TFT基板的制作方法，其特征在于，缓冲层为氮化硅层、氧化硅层或氧化铝层。
CN201710212917.1A 2017-04-01 2017-04-01 Tft基板的制作方法 Active CN106981456B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201710212917.1A CN106981456B (zh) 2017-04-01 2017-04-01 Tft基板的制作方法
US15/570,754 US10367016B2 (en) 2017-04-01 2017-05-03 Method for manufacturing TFT substrate
PCT/CN2017/082815 WO2018176568A1 (zh) 2017-04-01 2017-05-03 Tft基板的制作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710212917.1A CN106981456B (zh) 2017-04-01 2017-04-01 Tft基板的制作方法

Publications (2)

Publication Number Publication Date
CN106981456A true CN106981456A (zh) 2017-07-25
CN106981456B CN106981456B (zh) 2019-08-13

Family

ID=59343808

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710212917.1A Active CN106981456B (zh) 2017-04-01 2017-04-01 Tft基板的制作方法

Country Status (3)

Country Link
US (1) US10367016B2 (zh)
CN (1) CN106981456B (zh)
WO (1) WO2018176568A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020228121A1 (zh) * 2019-05-13 2020-11-19 深圳市华星光电半导体显示技术有限公司 薄膜晶体管的制备方法及薄膜晶体管

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515375A (zh) * 2012-06-18 2014-01-15 京东方科技集团股份有限公司 阵列基板及其制造方法、以及显示装置
CN105977206A (zh) * 2016-06-27 2016-09-28 深圳市华星光电技术有限公司 一种阵列基板的制造方法及阵列基板

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106571398B (zh) * 2016-10-17 2019-12-31 深圳市华星光电技术有限公司 一种薄膜晶体管及其制造方法、液晶面板
CN106783885A (zh) * 2017-01-03 2017-05-31 深圳市华星光电技术有限公司 Tft基板的制作方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515375A (zh) * 2012-06-18 2014-01-15 京东方科技集团股份有限公司 阵列基板及其制造方法、以及显示装置
CN105977206A (zh) * 2016-06-27 2016-09-28 深圳市华星光电技术有限公司 一种阵列基板的制造方法及阵列基板

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020228121A1 (zh) * 2019-05-13 2020-11-19 深圳市华星光电半导体显示技术有限公司 薄膜晶体管的制备方法及薄膜晶体管

Also Published As

Publication number Publication date
WO2018176568A1 (zh) 2018-10-04
US20180366497A1 (en) 2018-12-20
CN106981456B (zh) 2019-08-13
US10367016B2 (en) 2019-07-30

Similar Documents

Publication Publication Date Title
CN103489877B (zh) 阵列基板及其制造方法和显示装置
CN103489876B (zh) 一种阵列基板及其制备方法、显示装置
CN102629664B (zh) 一种阵列基板及其制作方法和显示装置
CN104793416B (zh) 一种阵列基板及其制作方法和显示面板
TWI298545B (en) Method for fabricating a thin film transistor
CN104681627A (zh) 阵列基板、薄膜晶体管及制作方法、显示装置
CN103354218A (zh) 阵列基板及其制作方法和显示装置
CN105957867B (zh) 阵列基板母板及其制作方法、显示装置
CN103227148B (zh) 一种阵列基板制备方法及阵列基板和显示装置
CN101170086A (zh) 制备薄膜晶体管基底的方法
CN105655359A (zh) Tft基板的制作方法
CN115995470A (zh) 显示基板及其制造方法、显示装置
CN106019751A (zh) 阵列基板及其制造方法、显示装置
CN107871753A (zh) 阵列基板及其制备方法
CN104241296B (zh) 一种阵列基板及其制作方法和显示装置
CN102842587A (zh) 阵列基板及其制作方法、显示装置
CN110148601A (zh) 一种阵列基板、其制作方法及显示装置
CN105870169A (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
CN101021658B (zh) 液晶显示面板的半导体结构及其制作方法
CN103474439B (zh) 一种显示装置、阵列基板及其制作方法
CN104538413B (zh) 阵列基板及其制作方法、显示装置
CN104299942A (zh) 过孔制作方法、阵列基板制作方法及阵列基板、显示装置
CN106340457A (zh) 薄膜晶体管及制作方法、显示面板
CN109979882A (zh) 一种内嵌式触控面板阵列基板及其制造方法
CN106981456A (zh) Tft基板的制作方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20171030

Address after: 518132 No. 9-2 Ming Avenue, Gongming street, Guangming District, Guangdong, Shenzhen

Applicant after: Shenzhen Huaxing photoelectric semiconductor display technology Co., Ltd.

Address before: 518132 9-2, Guangming Road, Guangming New District, Guangdong, Shenzhen

Applicant before: Shenzhen Huaxing Optoelectronic Technology Co., Ltd.

GR01 Patent grant
GR01 Patent grant