WO2018120298A1 - 画素结构及工作方法、阵列基板 - Google Patents
画素结构及工作方法、阵列基板 Download PDFInfo
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- WO2018120298A1 WO2018120298A1 PCT/CN2017/071005 CN2017071005W WO2018120298A1 WO 2018120298 A1 WO2018120298 A1 WO 2018120298A1 CN 2017071005 W CN2017071005 W CN 2017071005W WO 2018120298 A1 WO2018120298 A1 WO 2018120298A1
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- common electrode
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 title claims abstract description 7
- 239000003990 capacitor Substances 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims description 6
- 238000011017 operating method Methods 0.000 claims 1
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 6
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 150000001343 alkyl silanes Chemical class 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
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Definitions
- the present invention relates to the field of TFT display devices, and in particular to a pixel structure and a working method for improving the common electrode voltage stability of a liquid crystal panel, and an array substrate.
- Crosstalk is a common phenomenon in TFT-LCD display failure, which means that the image of one area affects the picture of other areas.
- the TFT-LCD can be classified into vertical crosstalk and horizontal crosstalk depending on the position of the crosstalk. Taking the VA display mode as an example, the crosstalk picture is judged, and if there is a bad phenomenon, the horizontal direction is horizontal crosstalk.
- the causes of different types of crosstalk are different.
- the driving voltage of one data line is always 128 gray level potential, and the driving voltage of the other one is 2/3 time is 128 gray level potential, 1
- the time of /3 is 255 gray level potential, and the potentials of the two data lines are periodically reversed, resulting in a corresponding change in the potential of the common electrode line.
- the result of the change of the common electrode line potential is that the overall picture is dark, and 255 gray
- the lateral region of the step potential will appear darker horizontal blocks due to the larger variation of the common electrode line potential.
- the horizontal crosstalk solution uses a column inversion or a dot inversion (Dot Inversion) driver, but this solution is susceptible to process changes, making the left and right data lines The capacitive coupling effect on the common electrode lines is different, so that horizontal crosstalk cannot be completely eliminated.
- Dot Inversion dot Inversion
- the capacitance C DC structure between the data line and the common electrode line has a first metal layer (Metal1), an N+ layer, an AS layer (alkyl silane film), a SiNx layer (insulating layer), and a second metal.
- Layer (Metal2) the existence of the AS layer and the N+ layer between Metal1 and Metal2, resulting in a difference in the size of the C DC driven by the positive frame and the negative frame, respectively represented as C DC + and C DC -, such a change
- C DC + and C DC - such a change
- the technical problem to be solved by the present invention is the technical problem that the common electrode line ACOM driving capability is insufficient in the prior art, and the present invention provides a method of short-circuiting the common electrode line ACOM and the gate signal line in a certain manner to improve the public.
- the present invention provides a pixel structure, the pixel structure including a data line, a gate, a pixel electrode, and a common electrode line that drives the gate; a capacitance between the common electrode line and the pixel electrode is a storage capacitor; The common electrode line is electrically connected to the gate.
- the common electrode line is disposed and connected to the gate in the same layer.
- the common electrode line is shorted to the gate by the lap metal line.
- the common electrode line potential is equal to the gate potential;
- the present invention also provides an array substrate comprising the pixel structure, the common electrode line in each of the pixel structures being electrically connected to a corresponding one of the gate lines.
- the common electrode line in each of the pixel structures is electrically connected to a corresponding one of the gate lines.
- the present invention also provides a method for operating a pixel structure, the pixel structure comprising a data line, a gate, a pixel electrode, and a common electrode line driving the gate; a capacitance between the common electrode line and the pixel electrode is a storage capacitor; the common electrode line is electrically connected to the gate; the method includes:
- the potential of the n+2th gate line signal is turned on, it is a high potential, and the n+2th storage capacitor is The pixel electrode is normally charged, and the potential of the common electrode line of the n+2th storage capacitor is maintained at a low potential;
- the potential of the common electrode line of the nth stage storage capacitor is low.
- the common electrode line ACOM and the scan driving gate (Gate line) are short-circuited together in a certain manner to improve the driving capability of the common electrode line ACOM, and before each scanning driving gate Gate is opened, the public The electrode line ACOM) can maintain a stable potential Vlow.
- the advantage of using the scan driving gate Gate line to drive the common electrode line ACOM is that the potential of the scan driving gate Gate line is independently controlled by the IC, the driving capability thereof is stronger than the general design, and the control of the common electrode line can be reduced.
- the WOA trace non-COM signal wire on array (WOA)) provides a wider space for other design structures of the liquid crystal panel.
- the first effect is to improve the driving ability of the common electrode line
- Figure 1 is a schematic view of the structure of the present invention
- FIG. 2 is an equivalent circuit diagram of the present invention
- FIG. 3 is a schematic diagram of waveforms of a common electrode line ACOM and an nth gate line signal according to the present invention
- Figure 4 is a flow chart of the working method of the present invention.
- the present invention provides a pixel structure for improving the common electrode voltage regulation of a liquid crystal panel, including a data line 3 (DATA), a gate 1 (Gate), a pixel electrode 4 (Pixel), and a driving station.
- a common electrode line 2 (ACOM) of the gate a capacitance between the common electrode line 2 (ACOM) and the pixel electrode 4 (Pixel) is a storage capacitor Cst; the common electrode line 2 (ACOM) and the gate 1 Shorted, the common electrode line 2 and the lower gate 1 are disconnected.
- the potential of the gate 1 is independently controlled by the IC integrated circuit.
- the common electrode line 2 (ACOM) and the gate 1 have the same potential.
- the pixel structure for improving the common electrode voltage stabilizing of a liquid crystal panel is used for a TFT-LCD display device, wherein the array substrate includes the pixel structure, the common electrode line 2 in each of the pixel structures, and A corresponding one of the gates 1 is electrically connected.
- the embodiment further provides a working method for improving the pixel structure of the common electrode of the liquid crystal panel. As shown in FIG. 4, the method includes:
- the potential of the common electrode line (ACOM) of the nth stage storage capacitor Cstn is a low potential Vlow.
- the gate signal potential Gate n+1 of the n+1th stage is turned on.
- the common electrode line can also overlap the metal of other layers.
- the line connects the gate lines with vias.
- a conductive layer is disposed in the insulating layer to connect the common electrode line to the gate.
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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- Liquid Crystal Display Device Control (AREA)
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Abstract
Description
Claims (9)
- 一种画素结构,其中:所述画素结构包括数据线、栅极、像素电极以及驱动所述栅极的公共电极线;所述公共电极线与像素电极之间的电容为存储电容;所述公共电极线与栅极电性连接。
- 根据权利要求1所述的画素结构,其中:所述公共电极线与所述栅极同层设置且连接。
- 根据权利要求1所述的画素结构,其中:公共电极线通过搭接金属线与栅极短接。
- 根据权利要求1所述的画素结构,其中:所述公共电极线电位与栅极电位相等;所述栅极中第n级栅极信号与所述第n+1级存储电容的公共电极线电位相等;其中,n=1,2,3,…。
- 一种阵列基板,其中:包括画素结构,所述画素结构包括数据线、栅极、像素电极以及驱动所述栅极的公共电极线;所述公共电极线与像素电极之间的电容为存储电容;所述公共电极线与栅极电性连接;每一所述画素结构内的所述公共电极线和与其对应的一条栅极电性连接。
- 根据权利要求5所述的阵列基板,其中:每一所述画素结构内的所述公共电极线和与其对应的一条栅极电性连接。
- 一种画素结构的工作方法,其中,所述画素结构包括数据线、栅极、像素电极以及驱动所述栅极的公共电极线;所述公共电极线与像素电极之间的电容为存储电容;所述公共电极线与栅极电性连接;所述方法包括:(1)第n级栅极信号电位关闭后,保持在低电位,此时第n+1级存储电容的公共电极线的电位为低电位;(2)第n+1级栅极信号电位开启后,为高电位,第n+1级存储电容的像素电极正常充电,第n+1级存储电容的公共电极线的电位维持为低电位,第n+2级存储电容的公共电极线的电位为高电位;(3)第n+1级栅极信号电位关闭后,为低电位,第n+2级存储电容的公共电极线的电位为低电位;(4)第n+2级栅极线信号电位开启后,为高电位,第n+2级存储电容的像素电极正常充电,第n+2级存储电容的公共电极线的电位维持为低电位;(5)重复步骤(1)~(4)。
- 根据权利要求7所述的画素结构的工作方法,其中:所述工作方法中,第n级栅极信号电位开启之前,所述第n级存储电容的公共电极线的电位为低电位。
- 根据权利要求7所述的画素结构的工作方法,其中:所述第n级栅极信号电位关闭后经过时间t后开启,第n+1级栅极信号电位开启。
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