WO2020062371A1 - 一种显示面板的驱动电路和驱动方法 - Google Patents

一种显示面板的驱动电路和驱动方法 Download PDF

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Publication number
WO2020062371A1
WO2020062371A1 PCT/CN2018/111348 CN2018111348W WO2020062371A1 WO 2020062371 A1 WO2020062371 A1 WO 2020062371A1 CN 2018111348 W CN2018111348 W CN 2018111348W WO 2020062371 A1 WO2020062371 A1 WO 2020062371A1
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Prior art keywords
line
control line
data
display panel
alignment control
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PCT/CN2018/111348
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English (en)
French (fr)
Inventor
胡云钦
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US16/339,000 priority Critical patent/US20210358439A1/en
Publication of WO2020062371A1 publication Critical patent/WO2020062371A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • the present application relates to the field of display technology, and in particular, to a driving circuit and a driving method for a display panel.
  • PSVA Polymer-stabilized vertical alignment
  • TFT thin film transistor
  • the PSVA alignment circuit is to add a shorting bar circuit to the periphery of the bonding area of the chip. After the alignment is completed, the terminal area of the shorting bar is laser cut.
  • Array substrate gate drive (Gate On Array, GOA) technology uses the same process as the TFT to produce a line scan drive circuit to achieve progressive scan drive. It can save the cost of the gate circuit (Gate IC), can also reduce the width of the panel frame, is conducive to narrow frame design, is an important technology for panel design, and has been widely used in liquid crystal panels.
  • the GOA architecture panel uses the GOA circuit for liquid crystal alignment. Due to the heavy resistance-capacitance (RC) load of the circuit during liquid crystal alignment, it is easy to cause damage to the GOA circuit components and alignment failure.
  • RC resistance-capacitance
  • What the present application is to solve is to provide a driving circuit and a driving method of a display panel that reduce the load of a gate driving circuit of an array substrate during alignment.
  • the present application provides a driving circuit for a display panel.
  • the display panel includes a display area, a non-display area, and a driving circuit.
  • the non-display area is arranged around the display area.
  • the non-display area includes: a gate.
  • An electrode driving chip connected to the scanning line; the driving circuit includes: an alignment control line arranged to cross the scanning line; an active switch, a gate and a source of the active switch are connected to the alignment control line, and a drain Connect with the scan line.
  • the alignment control line includes a first alignment control line and a second alignment control line;
  • the active switch includes a first active switch and a second active switch;
  • the scan line includes a first scan line and a first Two scanning lines
  • the first active switch is connected to the first alignment control line and the first scan line, respectively;
  • the second active switch is connected to the second alignment control line and the second scan line, respectively.
  • the first scanning line and the second scanning line are arranged at a crossing interval.
  • the driving circuit further includes:
  • a gate control line configured as the gate driving chip, including a high-level signal line, a low-level signal line, a first clock signal and a second clock signal;
  • the gate driving chip includes a first gate driving chip and a second gate driving chip, and the first gate driving chip is respectively connected to a first scanning line, a high-level signal line, a low-level signal line, and a first A clock signal; the second gate driving chip is respectively connected to a second scan line, a high-level signal line, a low-level signal line, and a second clock signal.
  • the non-display area further includes: a data control line; the data control line includes a first data control line and a second data control line; the data line includes a first data line and a second data line The first data line is connected to the first data control line, and the second data line is connected to the second data control line; the first data line and the second data line are arranged at a cross interval.
  • the first scan lines are arranged adjacent to each other, and the second scan lines are arranged adjacent to each other.
  • all the active switches are connected to the same alignment control line.
  • the present application also discloses a driving circuit for a display panel.
  • the display panel includes a display area and a non-display area, and the non-display area is arranged around the display area.
  • the display area includes a plurality of scanning lines and a plurality of data lines. And are arranged to cross the scanning lines;
  • the non-display area includes: a gate driving chip connected to the scanning lines; a data control line connected to the data lines;
  • the driving circuit includes: an alignment control line that is arranged to cross the scanning line; an active switch, a gate and a source of the active switch are connected to the alignment control line, and a drain is connected to the scanning line;
  • the alignment control line includes a first alignment control line and a second alignment control line;
  • the active switch includes a first active switch and a second active switch;
  • the scan line includes a first scan line and a second scan line;
  • the first active switch is respectively connected to the first alignment control line and the first scan line; the second active switch is respectively connected to the second alignment control line and the second scan line; the first scan line
  • the driving circuit further includes a gate control line for the gate driving chip, including a high-level signal line, a low-level signal line, a first clock signal, and a second Clock signal;
  • the gate driving chip includes a first gate driving chip and a second gate driving chip, and the first gate driving chip is respectively connected to a first scanning line, a high-level signal line, and a low-level signal line And a first clock signal;
  • the second gate driving chip is respectively connected to a second scan line, a high-level signal line, a low-level signal line, and a second clock signal;
  • the data control line includes a first data control line And a second data control line;
  • the data line includes a first data line and a second data line;
  • the first data line is connected to the first data control line, and the second data line is connected to the
  • the first data line and the second data line are arranged at a crossing interval.
  • This application also discloses any one of the foregoing driving methods, and the driving method further includes:
  • the gate driving chip When it is detected that the potentials of all the scanning lines are at a high level, the gate driving chip is turned off.
  • the scanning line is turned on line by line during the normal display of the display panel, so at the same time, the gate drive chip only needs to drive one scanning line, and the current required is very small.
  • all active switches are required to be turned on, so that a complete electric field is formed in the entire display area of the display panel. Therefore, if a gate driver chip is used to drive all the scan lines at the same time, the load is heavy. It is easy to cause damage to the gate driver chip and alignment failure. Because the application uses an alignment control line, the gate driving chip is not used in the alignment, and the scanning line is directly powered by the alignment control line, thereby solving the heavy load of using the gate driving chip. In addition, the gate and source of the active switch are connected to the alignment control line.
  • the active switch When the alignment control line is at a high level, the active switch is automatically turned on to transfer the voltage to the scanning line. When the alignment control line is at a low level, The active switch is automatically closed, cutting off the path of the scanning line and the alignment control line, without affecting the function of the scanning line during normal display. Because the gate of the active switch has no additional control lines, the wiring in the display panel is reduced, the circuit structure and operating principle are simpler, the implementation difficulty is reduced, the wiring space is saved, and it is beneficial to achieve a narrow frame.
  • FIG. 1 is a schematic diagram of a driving circuit structure of a display panel according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of a driving circuit structure of a display panel according to an embodiment of the present application
  • FIG. 3 is a driving circuit diagram of a display panel according to an embodiment of the present application.
  • FIG. 4 is another driving circuit diagram of a display panel according to an embodiment of the present application.
  • FIG. 5 is another driving circuit diagram of a display panel according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a driving method of a driving circuit of a display panel according to an embodiment of the present application.
  • connection should be understood in a broad sense, unless explicitly stated and limited otherwise.
  • they can be fixed connections or removable.
  • Connection, or integral connection it can be mechanical or electrical connection; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements.
  • connection or integral connection; it can be mechanical or electrical connection; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements.
  • an embodiment of the present application discloses a driving circuit 200 for a display panel.
  • the display panel includes: a display area 100 and a non-display area 300, and the non-display area is arranged around the display area;
  • the display area 100 includes: a plurality of scanning lines 110 and a plurality of data lines 120 intersecting the scanning lines 110;
  • the non-display area 300 includes a gate driving chip 310 connected to the scanning lines 110;
  • the driving circuit 200 includes an alignment control line 210 intersecting with the scanning line 110, and an active switch 220; a gate and a source of the active switch 220 are connected to the alignment control line 210, and a drain is connected to the scanning line 110.
  • the scanning lines 110 are turned on line by line during normal display of the display panel, so at the same time, the gate driving chip only needs to drive one scanning line 110, and the current required is very small.
  • all the active switches 220 are required to be turned on, so that the entire display area 100 of the display panel forms a complete electric field. Therefore, if the gate driving chip 310 is used to drive all the scanning lines at the same time, the load is heavy. . It is easy to cause damage to the gate driver chip and alignment failure. Since the application uses an alignment control line 210, the gate driving chip is not used for alignment, and the scanning line is directly powered by the alignment control line, thereby solving the problem of heavy load using the gate driving chip.
  • the gate and source of the active switch 220 are connected to the alignment control line 210.
  • the alignment control line 210 When the alignment control line 210 is at a high level, the active switch is automatically turned on to transmit the voltage to the scan line 110; and the alignment control line 210 When it is at a low level, the active switch 220 is automatically turned off to cut off the path between the scanning line 110 and the alignment control 210 line, without affecting the function of the scanning line 110 during normal display. Because the gate of the active switch 220 has no additional control lines, the wiring in the display panel is reduced, the circuit structure and operating principle are simpler, the implementation difficulty is reduced, the wiring space is saved, and it is beneficial to achieve a narrow frame.
  • the alignment control line 210 includes a first alignment control line 121 and a second alignment control line 122;
  • the active switch 220 includes a first active switch 221 and a second active switch 222;
  • the scan line 110 includes a first scan line 111 and a second scan line 112;
  • the first active switch 221 is connected to the first alignment control line 121 and the first scan line 111
  • the second active switch 222 is connected to the second alignment control line 122 and the second scan line 112, respectively.
  • the line width of the alignment control line 210 needs to be increased.
  • the parasitic capacitance generated by the circuit increases accordingly, which affects the display quality.
  • the two alignment control lines can share current with each other, and the line width of a single alignment control line can be appropriately narrowed, which can effectively reduce parasitic capacitance.
  • the first scanning line 111 and the second scanning line 112 are arranged at a crossing interval.
  • the driving circuit 200 further includes:
  • a gate control line 230 for controlling the gate driving chip 310 includes a high-level signal line 231, a low-level signal line 232, a first clock signal 233, and a second clock signal 234;
  • the gate driving chip 310 includes a first gate driving chip 311 and a second gate driving chip 322.
  • the first gate driving chip 311 is connected to a first scanning line 111, a high-level signal line 231, and a low power, respectively.
  • the flat signal line 232 and the first clock signal 233; the second gate driving chip 312 is connected to the second scan line 112, the high-level signal line 231, the low-level signal line 232, and the second clock signal 234, respectively.
  • the size of the display panel is generally large, and the size of the integrated chip is generally small. If a single chip is used to drive the scan line, the fan-out area of the wire will be very dense, which is not conducive to wiring, and the fan-out area is long enough to Ensure that the pins of the gate driver chip can be connected to each scan line, which undoubtedly increases the thickness of the frame. Therefore, the use of two gate driver chips to drive two sets of scanning lines is conducive to reducing the length of the fan-out area, achieving a narrow frame, and reducing the difficulty of wiring. In addition, the two gate driver chips share the high-level signal line and the low-level signal line in the gate control line, which reduces the number of gate control lines and also reduces the width of the frame.
  • the non-display area 300 further includes:
  • the data control line 320 includes a first data control line 321 and a second data control line 322.
  • the data line 120 includes a first data line 121 and a second data line 122;
  • the first data line 121 is connected to a first data control line 321, and the second data line 122 is connected to a second data control line 322;
  • the first data line 121 and the second data line 122 are arranged at a cross interval.
  • the line width of the data control line 320 becomes larger, but as the line width becomes larger, the surface area of the data control line increases, and it will generate with the surrounding circuits. The parasitic capacitance will increase, which will affect the display quality.
  • the two data control lines 320 can share current with each other, and the line width of a single alignment control line can be appropriately narrowed, which can effectively reduce parasitic capacitance.
  • the first scanning lines 111 are arranged adjacently, and the second scanning lines 122 are arranged adjacently.
  • the scan lines 110 connected to the same alignment control line 210 are grouped together and have good consistency. That is, the same alignment control line is connected between two adjacent first scanning lines 111 or second scanning lines 112, and the voltage and current are consistent when power is applied, which can effectively avoid common mode interference.
  • all the active switches 220 are connected to the same alignment control line 210.
  • the space occupied by the alignment line is small, which is conducive to reducing the border of the display panel, which is in line with the development trend of narrow borders.
  • FIGS. 1 to 5 a driving circuit for a display panel is disclosed.
  • the display area 100 includes:
  • a plurality of data lines 120 are arranged to cross the scanning lines 110;
  • the non-display area 300 includes:
  • the gate driving chip 310 is connected to the scanning line 110;
  • the driving circuit includes:
  • the alignment control line 210 is arranged to cross the scanning line 110;
  • the active switch 220 has a gate and a source connected to the alignment control line 210 and a drain connected to the scan line 110.
  • the alignment control line 210 includes a first alignment control line 211 and a second alignment control line 212.
  • the active switch 220 includes a first active switch 221 and a second active switch 222.
  • the scan line 110 includes a first scan. Line 111 and second scan line 112;
  • the first active switch 221 is connected to the first alignment control line 121 and the first scan line 111
  • the second active switch 222 is connected to the second alignment control line 122 and the second scan line 112, respectively.
  • the first scanning lines 111 and the second scanning lines 112 are arranged at intervals.
  • the driving circuit 200 further includes:
  • a gate control line 230 for controlling the gate driving chip 310 includes a high-level signal line 231, a low-level signal line 232, a first clock signal 233, and a second clock signal 234;
  • the gate driving chip 310 includes a first gate driving chip 311 and a second gate driving chip 322.
  • the first gate driving chip 311 is connected to a first scanning line 111, a high-level signal line 231, and a low power, respectively.
  • the flat signal line 232 and the first clock signal 233; the second gate driving chip 312 is connected to the second scan line 112, the high-level signal line 231, the low-level signal line 232, and the second clock signal 234, respectively.
  • the non-display area 300 further includes:
  • the data control line 320 includes a first data control line 321 and a second data control line 322;
  • the data line 120 includes a first data line 121 and a second data line 122;
  • the first data line 121 is connected to a first data control line 321, and the second data line 122 is connected to a second data control line 322;
  • the first data line 121 and the second data line 122 are arranged at a cross interval.
  • the gate driving chip when the potentials of all the scanning lines are detected to be high, the gate driving chip is turned off.
  • TFT-LCD Transistor-Liquid Crystal Display
  • OLED Organic Light-Emitting Diode

Abstract

一种显示面板的驱动电路（200）和驱动方法。显示面板包括显示区（100）、非显示区（300）和驱动电路（200），显示区（100）包括扫描线（110）和数据线（120）；非显示区（300）包括门极驱动芯片（310）；驱动电路（200）包括配向控制线（210）和主动开关（220）。

Description

一种显示面板的驱动电路和驱动方法
本申请要求于2018年9月30日提交中国专利局、申请号为CN 201811160497.8、发明名称为“一种显示面板的驱动电路和驱动方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板的驱动电路和驱动方法。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
聚合物稳定垂直配向(Polyer-stabilized vertical Alignment，PSVA)技术主要是由带缝隙的超薄膜晶体管(Thin Film Transistor，TFT)电极控制液晶倾倒，并于液晶材料中添加感光性高分子，面板组成后，施加电场，使液晶倾倒，再利用紫外光使液晶内感光性单体反应，使液晶随着电场驱动方向产生预倾角，达到多畴的特性。PSVA配向电路是在芯片绑定(Bonding)区的外围增加短路棒(Shortting Bar)电路，在配向完成后，再将短路棒(Shorting Bar)的端子区进行镭射切割。
阵列基板栅极驱动(Gate On Array，GOA)技术采用与TFT同样制程的工艺制作出行扫描驱动电路，实现逐行扫描驱动功能。它可以节省栅极电路(Gate IC)的成本，也能够缩减面板边框的宽度，利于窄边框设计，是面板设计的一个重要技术，现在已经在液晶面板中被广泛采用。GOA架构面板是借助GOA电路进行液晶配向，由于液晶配向时电路的阻容(RC)负载较重，易导致GOA电路元件损伤及配向失败。
技术解决方案
本申请所要解决的是提供一种在配向时减少阵列基板栅极驱动电路负载的显示面板的驱动电路和驱动方法。
为实现上述目的，本申请提供了一种显示面板的驱动电路，所述显示面板包括显示区、非显示区和驱动电路，所述非显示区环绕显示区设置；所述非显示区包括：门极驱动芯片，与所述扫描线连接；所述驱动电路包括：配向控制线，与扫描线交叉设置；主动开关，所述主动开关的门极和源极与所述配向控制线连接，漏极跟所述扫描线连接。
可选的，所述配向控制线包括一条第一配向控制线和一条第二配向控制线；所述主动开关包括第一主动开关和第二主动开关；所述扫描线包括第一扫描线和第二扫描线；
所述第一主动开关分别与所述第一配向控制线和第一扫描线连接；所述第二主动开关分别与所述第二配向控制线和所述第二扫描线连接。
可选的，所述第一扫描线和所述第二扫描线交叉间隔设置。
可选的，所述驱动电路还包括：
门极控制线，设置为所述门极驱动芯片，包括高电平信号线、低电平信号线、第一时钟信号和第二时钟信号；
所述门极驱动芯片包括第一门极驱动芯片和第二门极驱动芯片，所述第一门极驱动芯片分别连接第一扫描线、高电平信号线、低电平信号线和第一时钟信号；所述第二门极驱动芯片分别连接第二扫描线、高电平信号线、低电平信号线和第二时钟信号。
可选的，所述非显示区还包括：数据控制线；所述数据控制线包括一条第一数 据控制线和一条第二数据控制线；所述数据线包括第一数据线和第二数据线；所述第一数据线连接第一数据控制线，所述第二数据线连接第二数据控制线；所述第一数据线和第二数据线交叉间隔设置。
可选的，所述第一扫描线之间相邻排列，所述第二扫描线之间相邻排列。
可选的，所有所述主动开关连接到同一根所述配向控制线。
本申请还公开一种显示面板的驱动电路，所述显示面板包括：显示区和非显示区，所述非显示区环绕显示区设置；所述显示区包括：多条扫描线，多条数据线，与扫描线交叉设置；所述非显示区包括：门极驱动芯片，与所述扫描线连接；数据控制线，与数据线连接；
所述驱动电路包括：配向控制线，与扫描线交叉设置；主动开关，所述主动开关的门极和源极与所述配向控制线连接，漏极跟扫描线连接；
所述配向控制线包括一条第一配向控制线和一条第二配向控制线；所述主动开关包括第一主动开关和第二主动开关；所述扫描线包括第一扫描线和第二扫描线；
所述第一主动开关分别与所述第一配向控制线和第一扫描线连接；所述第二主动开关分别与所述第二配向控制线和第二扫描线连；所述第一扫描线和第二扫描线交叉间隔设置；所述驱动电路还包括：门极控制线，用于所述门极驱动芯片，包括高电平信号线、低电平信号线、第一时钟信号和第二时钟信号；所述门极驱动芯片包括第一门极驱动芯片和第二门极驱动芯片，所述第一门极驱动芯片分别连接第一扫描线、高电平信号线、低电平信号线和第一时钟信号；所述第二门极驱动芯片分别连接第二扫描线、高电平信号线、低电平信号线和第二时钟信号；所述数据控制线包括一条第一数据控制线和一条第二数据控制线；所述数据线包括第一数据线和 第二数据线；所述第一数据线连接第一数据控制线，所述第二数据线连接第二数据控制线；
所述第一数据线和第二数据线交叉间隔设置。
本申请还公开了一种任意一项上述的驱动方法，所述驱动方法还包括：
当检测到所有扫描线的电位为高电平时，关闭所述门极驱动芯片。
扫描线在显示面板正常显示时是逐行导通的，因此在同一时间点，门极驱动芯片只要驱动一根扫描线，所需的电流很小。在液晶配向时，要求所有的主动开关全部打开，使得显示面板的整个显示区形成一个完整的电场，因此，如果用门极驱动芯片来做，同时驱动所有的扫描线，负载较重。易导致门极驱动芯片损伤及配向失败。本申请由于采用了配向控制线，在配向时不使用门极驱动芯片，直接由配向控制线给扫描线供电，从而解决了利用门极驱动芯片负载较重。另外，主动开关的门极和源极与所述配向控制线连接，当配向控制线处于高电平时，主动开关会自动打开，将电压传递到扫描线中；而配向控制线处于低电平时，主动开关自动关闭，切断扫描线和配向控制线的通路，不影响正常显示时扫描线的功能。由于主动开关的门极没有额外的控制线路，减少了显示面板中的布线，电路结构和运行原理更简单，降低实施难度，节省布线空间，有利于实现窄边框。
附图说明
所包括的附图用来提供对本申请实施例的理解，其构成了说明书的一部分，是本申请的实施方式的示例，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请实施例一种显示面板的驱动电路结构的示意图；
图2是本申请实施例一种显示面板的驱动电路结构的示意图；
图3是本申请实施例一种显示面板的驱动电路图；
图4是本申请实施例另一种显示面板驱动电路图；
图5是本申请实施例另一种显示面板驱动电路图；
图6是本申请实施例一种显示面板的驱动电路的驱动方法示意图。
本发明的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，应理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅是描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，应说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接， 或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和较佳的实施例对本申请进行说明。
如图1至图5所示，本申请实施例公布了一种显示面板的驱动电路200，所述显示面板包括：显示区100和非显示区300，所述非显示区环绕显示区设置；所述显示区100包括：多条扫描线110、多条与扫描线110交叉设置的数据线120；所述非显示区300包括与所述扫描线110连接的门极驱动芯片310；所述驱动电路200包括与扫描线110交叉设置的配向控制线210，以及主动开关220；所述主动开关220的门极和源极与所述配向控制线210连接，漏极跟扫描线110连接。
所述扫描线110在显示面板正常显示时是逐行导通的，因此在同一时间点，门极驱动芯片只要驱动一根扫描线110，所需的电流很小。在液晶配向是，要求所有的主动开关220全部打开，使得显示面板的整个显示区100形成一个完整的电场，因此，如果用门极驱动芯片310来做，同时驱动所有的扫描线，负载较重。易导致门极驱动芯片损伤及配向失败。本申请由于采用了配向控制线210，在配向时不使用门极驱动芯片，直接由配向控制线给扫描线供电，从而解决了利用门极驱动芯片 负载较重的问题。另外，主动开关220的门极和源极与所述配向控制线210连接，当配向控制线210处于高电平时，主动开关会自动打开，将电压传递到扫描线110中；而配向控制线210处于低电平时，主动开关220自动关闭，切断扫描线110和配向控制210线的通路，不影响正常显示时扫描线110的功能。由于主动开关220的门极没有额外的控制线路，减少了显示面板中的布线，电路结构和运行原理更简单，降低实施难度，节省布线空间，有利于实现窄边框。
本实施例可选的，所述配向控制线210包括一条第一配向控制线121和一条第二配向控制线122；所述主动开关220包括第一主动开关221和第二主动开关222；所述扫描线110包括第一扫描线111和第二扫描线112；
所述第一主动开关221分别与所述第一配向控制线121和第一扫描线111连接；所述第二主动开关222分别与所述第二配向控制线122和第二扫描线连接112。
在配向阶段，所有扫描线110同时通电，驱动电流较大，相应的，配向控制线210的线宽就需要做大，但线宽做大，配向控制线的表面积就增大，会跟周围的电路产生的寄生电容随之增大，影响显示品质。通过两条配向控制线，能够互相分担电流，单根配向控制线的线宽可以适当做窄，能有效降低寄生电容。
本实施例可选的，所述第一扫描线111和第二扫描线112交叉间隔设置。
第一配向控制线211和第二配向控制线212产生的电压和电路之间会产生一定的差异，这种差异会传导到第一扫描线111和第二扫描线112，第一扫描线111和第二扫112描线交叉间隔设置，导电过程中产生的电场干扰会相互抵消，减少线路的阻容效应。
本实施例可选的，所述驱动电路200还包括：
门极控制线230，控制所述门极驱动芯片310，包括高电平信号线231、低电平信号线232，第一时钟信号233和第二时钟信号234；
所述门极驱动芯片310包括第一门极驱动芯片311和第二门极驱动芯片322，所述第一门极驱动芯片311分别连接第一扫描线111、高电平信号线231、低电平信号线232和第一时钟信号233；所述第二门极驱动芯片312分别连接第二扫描线112、高电平信号线231、低电平信号线232和第二时钟信号234。
显示面板的尺寸一般较大，而一般集成芯片的尺寸又比较小，如果用单颗芯片来驱动扫描线，其导线的扇出区会非常密集，不利于布线，而且扇出区足够长，才能保证门极驱动芯片的引脚能连接到每根扫描线，无疑增加边框的厚度。因此，采用两颗门极驱动芯片，分别带动两组扫描线，有利于缩减扇出区的长度，实现窄边框，同时降低布线的难度。另外，两颗门极驱动芯片共用门极控制线中的高电平信号线、低电平信号线，缩减了门极控制线的数量，同样有利于缩减边框的宽度。
本实施例可选的，所述非显示区300还包括：
数据控制线320；
所述数据控制线320包括一条第一数据控制线321和一条第二数据控制线322；
所述数据线120包括第一数据线121和第二数据线122；
所述第一数据线121连接第一数据控制线321，所述第二数据线122连接第二数据控制线322；
所述第一数据线121和第二数据线122交叉间隔设置。
在配向阶段，所有数据线同时通电，驱动电流较大，相应的，数据控制线320的线宽就做大，但线宽做大，数据控制线的表面积就增大，会跟周围的电路产生的 寄生电容随之增大，影响显示品质。通过两条数据控制线320，能够互相分担电流，单根配向控制线的线宽可以适当做窄，能有效降低寄生电容。
本实施例可选的，所述第一扫描线111之间相邻排列，所述第二扫描线122之间相邻排列。
连接同一配向控制线210的扫描线110归整在一起，一致性好。即相邻的两根第一扫描线111或第二扫描线112之间连接同一根配向控制线，通电时电压电流完成一致，可以有效避免共模干扰。
本实施例可选的，所有所述主动开关220连接到同一根所述配向控制线210。
利用单根配向控制线，配向线占用的空间较小，有利于缩减显示面板的边框，符合窄边框的发展趋势。
作为本申请的另一实施例，参考图1至图5所示，公开了一种显示面板的驱动电路，
所述显示区100包括：
多条扫描线110，
多条数据线120，与扫描线110交叉设置；
所述非显示区300包括：
门极驱动芯片310，与所述扫描线110连接；
所述驱动电路包括：
配向控制线210，与扫描线110交叉设置；
主动开关220，所述主动开关220的门极和源极与所述配向控制线210连接，漏极跟扫描线110连接。
所述配向控制线210包括一条第一配向控制线211和一条第二配向控制线212；所述主动开关220包括第一主动开关221和第二主动开关222；所述扫描线110包括第一扫描线111和第二扫描线112；
所述第一主动开关221分别与所述第一配向控制线121和第一扫描线111连接；所述第二主动开关222分别与所述第二配向控制线122和第二扫描线连接112。
所述第一扫描线111和第二扫描线112交叉间隔设置。
所述驱动电路200还包括：
门极控制线230，控制所述门极驱动芯片310，包括高电平信号线231、低电平信号线232，第一时钟信号233和第二时钟信号234；
所述门极驱动芯片310包括第一门极驱动芯片311和第二门极驱动芯片322，所述第一门极驱动芯片311分别连接第一扫描线111、高电平信号线231、低电平信号线232和第一时钟信号233；所述第二门极驱动芯片312分别连接第二扫描线112、高电平信号线231、低电平信号线232和第二时钟信号234。
所述非显示区300还包括：
数据控制线320；
所述数据控制线320包括一条第一数据控制线321和一条第二数据控制线322；
所述数据线120包括第一数据线121和第二数据线122；
所述第一数据线121连接第一数据控制线321，所述第二数据线122连接第二数据控制线322；
所述第一数据线121和第二数据线122交叉间隔设置。
作为本申请的另一实施例，参考图6所示，公开了一种任意一项上述实施例中 的显示面板的驱动电路的驱动方法，包括步骤：
S61、控制所述配向控制线输出高电平信号；
S62、通过主动开关将高电平信号传输到所述扫描线。
本实施例可选的，当检测到所有扫描线的电位为高电平时，关闭所述门极驱动芯片。
本申请的技术方案可以广泛应用在薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)显示器等平板显示器。
以上内容是结合具体实施方式对本申请所作详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (17)

  1. 一种显示面板的驱动电路，所述显示面板包括显示区、非显示区和驱动电路，所述非显示区环绕所述显示区设置；
    所述显示区包括：
    多条扫描线；
    多条数据线，与所述扫描线交叉设置；
    所述非显示区包括：
    门极驱动芯片，与所述扫描线连接；
    所述驱动电路包括：
    配向控制线，与所述扫描线交叉设置；
    主动开关，所述主动开关的门极和源极与所述配向控制线连接，漏极跟扫描线连接。
  2. 如权利要求1所述的一种显示面板的驱动电路，其中，所述配向控制线包括一条第一配向控制线和一条第二配向控制线；所述主动开关包括第一主动开关和第二主动开关；所述扫描线包括第一扫描线和第二扫描线；
    所述第一主动开关分别与所述第一配向控制线和所述第一扫描线连接；所述第二主动开关分别与所述第二配向控制线和所述第二扫描线连接。
  3. 如权利要求2所述的一种显示面板的驱动电路，其中，所述第一扫描线和所述第二扫描线交叉间隔设置。
  4. 如权利要求2所述的一种显示面板的驱动电路，其中，所述驱动电路还包括：
    门极控制线，控制所述门极驱动芯片，包括高电平信号线、低电平信号线、第一时钟信号和第二时钟信号；
    所述门极驱动芯片包括第一门极驱动芯片和第二门极驱动芯片，所述第一门极驱动芯片分别连接所述第一扫描线、高电平信号线、低电平信号线和第一时钟信号；所述第二门极驱动芯片分别连接所述第二扫描线、高电平信号线、低电平信号线和第二时钟信号。
  5. 如权利要求2所述的一种显示面板的驱动电路，其中，所述非显示区还包括：
    数据控制线；
    所述数据控制线包括一条第一数据控制线和一条第二数据控制线；
    所述数据线包括第一数据线和第二数据线；
    所述第一数据线连接所述第一数据控制线，所述第二数据线连接所述第二数据控制线；
    所述第一数据线和所述第二数据线交叉间隔设置。
  6. 如权利要求2所述的一种显示面板的驱动电路，其中，所述第一扫描线之间相邻排列，所述第二扫描线之间相邻排列。
  7. 如权利要求1所述的一种显示面板的驱动电路，其中，所有所述主动开关连接到同一根所述配向控制线。
  8. 一种显示面板的驱动电路，所述显示面板包括显示区、非显示区和驱动电路，所述非显示区环绕所述显示区设置；
    所述显示区包括：
    多条扫描线，
    多条数据线，与所述扫描线交叉设置；
    所述非显示区包括：
    门极驱动芯片，与所述扫描线连接；
    数据控制线，与所述数据线连接；
    所述驱动电路包括：
    配向控制线，与所述扫描线交叉设置；
    主动开关，所述主动开关的门极和源极与所述配向控制线连接，漏极跟所述扫描线连接；
    所述配向控制线包括一条第一配向控制线和一条第二配向控制线；所述主动开关包括第一主动开关和第二主动开关；所述扫描线包括第一扫描线和第二扫描线；
    所述第一主动开关分别与所述第一配向控制线和所述第一扫描线连接；所述第二主动开关分别与所述第二配向控制线和所述第二扫描线连接；
    所述第一扫描线和第二扫描线交叉间隔设置；
    所述驱动电路还包括：
    门极控制线，控制所述门极驱动芯片，包括高电平信号线、低电平信号线、第一时钟信号和第二时钟信号；
    所述门极驱动芯片包括第一门极驱动芯片和第二门极驱动芯片，所述第一门极驱动芯片分别连接第一扫描线、高电平信号线、低电平信号线和第一时钟信号；所述第二门极驱动芯片分别连接所述第二扫描线、高电平信号线、低电平信号线和第二时钟信号；
    所述数据控制线包括一条第一数据控制线和一条第二数据控制线；
    所述数据线包括第一数据线和第二数据线；
    所述第一数据线连接所述第一数据控制线，所述第二数据线连接所述第二数据控制线；
    所述第一数据线和所述第二数据线交叉间隔设置。
  9. 一种显示面板的驱动电路的驱动方法，所述显示面板包括显示区、非显示区和驱动电路，所述非显示区环绕显示区设置；
    所述显示区包括：
    多条扫描线，
    多条数据线，与所述扫描线交叉设置；
    所述非显示区包括：
    门极驱动芯片，与所述扫描线连接；
    所述驱动电路包括：
    配向控制线，与所述扫描线交叉设置；
    主动开关，所述主动开关的门极和源极与所述配向控制线连接，漏极跟扫描线连接；
    所述驱动方法包括：
    控制配向控制线输出高电平信号；
    以及通过主动开关将高电平信号传输到所述扫描线。
  10. 如权利要求9所述的一种显示面板的驱动电路的驱动方法，其中，所述驱动方法还包括：
    当检测到所有扫描线的电位为高电平时，关闭所述门极驱动芯片。
  11. 如权利要求9所述的一种显示面板的驱动电路的驱动方法，其中，所述配向控制线包括一条第一配向控制线和一条第二配向控制线；所述主动开关包括第一主动开关和第二主动开关；所述扫描线包括第一扫描线和第二扫描线；
    所述第一主动开关分别与所述第一配向控制线和所述第一扫描线连接；所述第二主 动开关分别与所述第二配向控制线和所述第二扫描线连接。
  12. 如权利要求10所述的一种显示面板的驱动电路的驱动方法，其中，所述第一扫描线和所述第二扫描线交叉间隔设置。
  13. 如权利要求10所述的一种显示面板的驱动电路的驱动方法，其中，所述驱动电路还包括：
    门极控制线，控制所述门极驱动芯片，包括高电平信号线、低电平信号线，第一时钟信号和第二时钟信号；
    所述门极驱动芯片包括第一门极驱动芯片和第二门极驱动芯片，所述第一门极驱动芯片分别连接所述第一扫描线、高电平信号线、低电平信号线和第一时钟信号；所述第二门极驱动芯片分别连接所述第二扫描线、高电平信号线、低电平信号线和第二时钟信号。
  14. 如权利要求10所述的一种显示面板的驱动电路的驱动方法，其中，所述非显示区还包括：
    数据控制线；
    所述数据控制线包括一条第一数据控制线和一条第二数据控制线；
    所述数据线包括第一数据线和第二数据线；
    所述第一数据线连接所述第一数据控制线，所述第二数据线连接所述第二数据控制线；
    所述第一数据线和所述第二数据线交叉间隔设置。
  15. 如权利要求10所述的一种显示面板的驱动电路的驱动方法，其中，所述第一扫描线之间相邻排列，所述第二扫描线之间相邻排列。
  16. 如权利要求9所述的一种显示面板的驱动电路的驱动方法，其中，所有所述主动开关连接到同一根所述配向控制线。
  17. 如权利要求9所述的一种显示面板的驱动电路的驱动方法，其中，所有所述主动开关包括薄膜晶体管。
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