TW200912877A - Display apparatus, driving method for display apparatus and electronic apparatus - Google Patents

Abstract

Disclosed herein is a display apparatus, including, a pixel section, a plurality of scanning lines, a plurality of signal lines, and a driving circuit.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device in which a body of a _ switching device is formed on a transparent insulating substrate for display: a driving method of the device And electronic devices. CROSS REFERENCE TO RELATED APPLICATIONS This application contains the Japanese patent application filed with the Japanese Patent Application No. JP-A No. JP-A No. The Jp 2〇〇7_173459 and the jp Cong _ Π 3 ids are related to the subject matter, and all the contents of the request are incorporated herein. [Prior Art] A display device (for example, a liquid crystal cell in which a liquid crystal cell is used as a display element or an electro-optical device) is arranged such that such pixels are arranged in a matrix and displayed through a liquid crystal display surface. An image display device that outputs images. The liquid crystal display panel is characterized by its slimness and its low power consumption. Utilizing most of these features, the liquid crystal display device is suitable for use in a variety of electronic devices such as personal digital assistants (PDAs), portable telephones, digital cameras, video cameras, and personal computers. ^ Figures 1 to 1C show an example of a conventional liquid crystal display device and a gate pulse waveform of the liquid crystal display device. The liquid crystal display device 1 first shown with reference to Fig. 1A' includes an effective pixel section 2, a vertical drive circuit (VDRV) 3, and a horizontal drive circuit 128894.doc 200912877 (HDRV) 4. The effective pixel section 2 has a plurality of pixel circuits 21 arranged in a matrix. Each of the circuits of the pixel circuits 21 includes a thin film transistor TFT 22, a liquid crystal cell 23, and a holding capacitor 24, which are used as all 35 devices. The liquid crystal 7C 23 is connected to the drain electrode or the source electrode of the TFT 22 at its pixel electrode. The holding transistor 24 is connected to the TFT at one of its electrodes. The electrodeless electrode. The pixel circuits 21 are connected to the gate lines 5-1 to 5-m wired in the direction of the pixel array for the individual columns and the signal lines 6-1 to 6 wired in the direction of the other pixel array for the individual rows. -n. The gate electrodes of the pixel circuits 212TFT 22 are individually connected to the same gate lines of the gate lines 5-1 to 5-m in a row. The source or drain electrodes of the pixel circuits 21 are individually connected to the same signal lines of the signal lines 6-1 to 6-n in a single unit. Further, in each of the pixel circuits 2, the liquid crystal cell 23 is connected to the pixel electrode of the TFT 22 and to the common electrode 7 at its opposite electrode. The holding capacitor 24 is connected between the electrode of the TFT 22 and the common line 7. The common line 7 is connected to receive a predetermined AC voltage from a VC〇M circuit (not shown) as a common voltage Vc〇m, and the vc〇M circuit is formed integrally with a driving circuit and the like. On the glass substrate. The gate lines 5-1 to 5-m are individually driven by the vertical driving circuit 3, and the signal lines 6-1 to 6-n are individually driven by the horizontal 128894.doc 200912877 Road 4 is driven. The vertical driving circuit 3 receives a vertical start signal VST', a vertical clock vclk and an enable signal ENAB, and scans each field period in a vertical direction (i.e., in a column-direction) to _ column _ The unit continuously selects the pixel circuits 21 connected to the gate lines 5_丨 to 5_m.

Specifically, when a scan pulse GP1 is applied from the vertical drive circuit 3 to the scan line, pixels in the respective rows in the first column are selected, and then another scan pulse is applied to the scan line 5-2. Gp2 , select the pixel in the row in the second column. Then, gate pulses Gp3, ..., Gpm are successively applied to the material close-up = line or scan line 5-3, ..., 5-m, respectively, in a similar manner. A gate buffer 丨 to a claw is supplied to the gate lines 5-1 to 5-m, respectively, at a gate pulse Gp to an output stage of the vertical drive circuit 3. Figure 1B shows an example of a waveform at the output stage of the gate buffer 8-m to the gate line 5_„1 after the closed-pole buffer of the gate pulse G pm. Figure 1 C shows the gate The pulse Gpm is an example of a waveform at one of the wire terminal portions of the gate line 5_m.

The horizontal drive circuit 4 receives a horizontal start pulse clock Hst which is generated from a clock generator (not shown) and indicates the start of the horizontal scan and the horizontal clock Hclk whose phases are opposite to each other (which is used as a horizontal scan) reference). The horizontal driving circuit 4 generates a sampling pulse D. The horizontal driving circuit 4 successively responds to the sampling pulses thus generated, and the image data R (red), G (green) and B (blue) are continuously input thereto. The sampled image data is supplied to the signal lines 6-1 to 6-n as data signals to be written to the pixel circuits 2''. 128894.doc 200912877 The horizontal drive circuit 4 divides the equal signal lines 6-1 to ό-η into a plurality of groups, 'and includes the signal drivers 41 to 44 corresponding to the individual groups.

ί Although the liquid crystal display device 1 shown in FIG. 1 has a basic configuration, the gate line driving using the vertical driving circuit 3 as described above and the signal using the horizontal driving circuit 4 as described above have been constructed. Many technologies related to line drives. Japanese Patent No. 3,276,996 (hereinafter referred to as Patent Document 1), Japanese Patent Laid-Open Publication No. 7_5237. No. (hereinafter referred to as Patent Document 2), Japanese Patent No. 3, 27, 485 (hereinafter referred to as Patent Document 3), and Japanese Patent Special Publication No. 2 _785G5 (hereinafter referred to as Patent Document) 4), such a technique is disclosed in Japanese Patent Laid-Open Publication No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. And one pulse GP output from the vertical drive circuit 3 in the liquid crystal display device 1 shown in FIG. 1 is one of the inner sides of the panel

The resistance of the 3-pole wiring and the capacitance parasitic in the gate wiring, that is, a TFT: a dummy capacitor and a valley between the -pixel electrode and the -VCOM wiring to generate an impedance. Since the μ gate wiring at the end of each closed-circuit wiring of the vertical flip-flop circuit 3 is output from the vertical driving circuit 3 pole, the waveform indicates the impedance of the gate-causing phase (4) i due to the generated resistance. The resulting time constant is derived from the distortion of the waveform of the output at the output stage of the vertical drive circuit 3, as indicated by a dashed line in FIG. The distortion of the waveform of the closed-pole pulse results in a certain difference between the positions on the (four)-pole line that are different from the distance of the vertical drive of the vertical drive 128894.doc 200912877. Therefore, the TFTs 22 which are in different positions on the gate line of the pixel transistor are turned on by the timing of the relative displacement of each other by a pole signal, and the image quality deteriorates the image quality on the liquid crystal display device. In particular, the difference in brightness between black and gray appears in this horizontal direction. In addition, for example, under the condition of the number of pixels of 4〇Κ SUperHighVisi〇n (4,096xRGBx 1, 〇80), 'the horizontal period 更 is shorter than the number of pixels of the ^^^^^^ Like quality deterioration is more serious. In addition, a frame rate of 240 Hz (normal frame rate of 6 Hz) further reduces the out cycle to a quarter" so that an image cannot be displayed. Here, the high frame rate will be described. For example, a liquid crystal display device uses a frame number and a frame frequency for displaying a -second period to be four times larger than that commonly used for display to improve moving image characteristics - since the liquid crystal display device generally combines 60 Hz The operation 'therefore, the high frame rate is 24 〇. The technique disclosed in the patent documents 1 to 6 has the following method of deliberately making one gate pulse longer to suppress an undesired pixel electrode. One of the delay profiles of the polar line is disclosed in Patent Document 1 in that the falling edge has a potential greater than the rising edge of the gate pulse when the transistor is turned off. However, the technique does not constitute an elimination of the edge. - Closed countermeasures. Therefore, the technique does not apply to a liquid crystal display device that includes a large number of blocks that cause the resistance of the interpolar line 128894.doc •10·200912877 to reduce the shadow of the left and right sides of the screen or use a high frame rate to display one of the liquid crystal display devices . The technique disclosed in Patent Document 2 includes a data transmission performed for each pixel in the ϋ # upward, a transfer wheel that horizontally scans the signal in the vertical direction along the control clock wiring (placed for individual pixels), and The output of one of the gate pulse signals for each pixel. According to the technology, a power supply vD〇 and vss, a clock signal for an offset register, and a temporary storage m-person signal disk-output signal line for the offset are required and surround the aperture of the liquid crystal. Used in the space of these lines. This constitution causes a decrease in the aperture ratio of the liquid crystal. This results in a decrease in the transmission factor and an increase in the backlight supply power. Further, since a control clock line and a signal line are adjacent to each other, the potential intrusion is required because of the occurrence of an I-capacitance between the signal line and the control clock line. Therefore, a malfunction may occur. In addition, since the clock itself has a certain delay due to the distortion caused by the capacitance, the effect of suppressing the gate delay is not generated. , the technique disclosed in Document 3 uses a pWM (pulse waveform modulation method, which uses digital data as the signal data for display without using analog data) and receives the pixel-gate pulse The output of a CMOS circuit is used as one of the pixel potentials. 2 Yes, the technique basically does not provide a delay for the 1-pole wiring. Because of A, this technique is not suitable for including a large number of gates. The impedance is such that the pixels with reduced shadows on the left and right sides of the camp or the same frame rate are used to display one of the liquid crystal display devices. I28894.doc 200912877 In the display method disclosed in Patent Document 4, the use of a film is carried out in the following manner. A writing method of one of a transistor (TFT). In the writing method, a method of making a frame rewriting in 1/24 second (Fig. 21 of Patent Document 4) is taken from a message The left side of the frame image is continuously written by the frame image at a time of continuous displacement at 1/24 sec. or written at 1/60 sec.

However, Patent Document 4 does not describe the input timing (input method) of the image signal data in a data line driving circuit, and does not disclose a specific writing system for writing at a frame frequency of 240 Hz. . In the techniques disclosed in Patent Documents 5 and 6, a memory is constructed in one pixel to reduce power consumption.

'And construct a CMOS-SRAM (statiC static random access memory) structure one electric but 疋 'The 4 technology is about using your main & 2, from a t, wish a pixel potential and - signal line One of the circuits on the end, 彳曰 掘 仁 仁 不 不 不 不 不用 不用 不用 不用 不用 不用 不用 不用 不用 不用

Therefore, due to the certain delay along the gate line of the display, the circuit cannot be disposed of - including large &gt; display devices. Pixel or text- and speed-driven, therefore, it is necessary to provide a delay that can be used for singapore, κ-one, σ-scanning lines, and which can drive a large number of pixels at the same speed. A device, a driving method for the display device, and an electronic device. The specific sinus sinus according to one of the present invention includes: Embodiment 'Providing a display device, 128894.doc • 12- 200912877 (4) = &amp; 'It includes a plurality of pixel circuits, and the pixel data is written into a 7G 仵 ^ ^ ^ ^ ^ ±, per unit circuit by a switching element, and the pixel circuits are arranged to form a matrix including a plurality of rows; : complex = scan line 'which is arranged corresponding to the rows of the pixel circuits and is used to control the conduction of the switching elements; a plurality of signal lines, 1 non-eight', and the sub-pixel circuits Arranged and arranged to allow the pixel data to be transmitted therethrough; and like the Quarrey, output &quot;&quot; scan pulses to cause the switching elements of the circuits to become conductive to the scan lines, One wave formation The circuit is arranged in one of the wires of each scan line = configured to implement the wave formation of the (four) scan pulse in the money scan line: according to another embodiment of the present invention, a drive for a display is provided The display device includes: a pixel segment directly including a plurality of pixel circuits, the pixel data is written to each pixel circuit through a switching element, and the pixel circuits are arranged to form a plurality of rows including a plurality of rows; a plurality of sweeping lines 'corresponding to rows of the pixel circuits: configured to control conduction of the switching elements; a plurality of signal lines 'corresponding to rows of the pixel circuits And configured to allow the pixel data to be propagated therethrough; and a driver circuit configured to output a scan pulse to cause the switching elements of the pixel circuits to be electrically coupled to the scan lines, The driving method comprises the steps of: shaping a waveform of a scan pulse of the scan line between each scan line of the scan lines. Broadcasting J28894.doc • 3 - 200912877 According to another embodiment of the present invention For example, a driving method for a display device is provided. The display device includes: a pixel segment including a plurality of pixel circuits, and the pixel data system is transmitted through each pixel circuit: ^ π pieces of m pixel units The #pixel circuit is arranged to form a plurality of rows of matrixes; a plurality of scan lines arranged corresponding to the rows of the pixel circuits and configured to control the conduction of the switching elements such as (4), a plurality of a signal line disposed corresponding to the rows of the pixel circuits and configured to allow propagation of the pixel data therethrough; and a drive circuit configured to output a scan m rush to cause the pixels The switching elements of the circuit become conductive to the scan lines, the driving method comprising: stepping through a wire parallel to the signal lines - enabling the signal in response to the 4 enabling 仏 & The beginning of the operation; and the waveform of the scan pulse propagating in the scan line in the middle of each scan line of the scan line such as ^hai. According to another embodiment of the present invention, an electronic device is provided, the bean comprising: a octagonal display device, comprising: a pixel segment comprising a plurality of pixel circuits, and the pixel data is transmissive = the switching component is written to Each pixel circuit is arranged to form a matrix comprising a plurality of rows; a plurality of scan lines arranged corresponding to rows of the pixel circuits and configured to control the switching elements Conductive; a plurality of signal lines arranged corresponding to the rows of the pixel circuits 128894.doc -14-200912877 and configured to allow propagation of the pixel data therethrough; a driver circuit configured to A scan pulse is rotated to cause the switching elements of the pixel circuits to conduct to the scan lines; and a waveform shaping circuit is disposed on each of the scan lines - the scan line - and configured The waveform of the scan pulse propagating in the sweep is shaped. The driving device, the driving method for the display device, and the electronic device are advantageous because they can suppress the delay in the scanning lines and can perform display of a larger number of pixels driven by a higher speed. [Embodiment] Hereinafter, the present invention will be described in detail with reference to preferred embodiments of the invention shown in the accompanying drawings. &lt;First Embodiment&gt; Figs. 2A to 2C are diagrams showing an example of a configuration, an example, and a gate pulse waveform of a liquid crystal display device according to a first embodiment of the present invention. Referring first to FIG. 2A, the liquid crystal display device 1A includes an effective pixel section no, a vertical drive circuit (VDRV) 12A, and a horizontal drive circuit (HDRV) 130 〇 gate buffers 140-1 to 14 〇 _ The m-series are arranged in an output stage of the vertical drive circuit to the gate lines 115-1 to 115, which are called scan lines of a gate pulse Gp. In the active matrix type liquid crystal device of the present invention, waveform shaping is performed for outputting a gate pulse from the vertical driving circuit 丨2〇, and a waveform shaping circuit of voltage change is performed. Up to 15〇_lm and 丨5〇_21 to 150-2m are centrally arranged on the gate lines 115_1 to 115_ melon. Each gate line passing through the gate lines 150-1 to i5〇-m will output a gate pulse from the vertical driving circuit 120 or a gate electrode to which the waveform shaping has been applied and the voltage change has been applied thereto. The pulse is supplied to a pixel switching transistor formed by a thin film transistor. The configuration, position, and the like of the waveform shaping circuits will be described in detail below. The effective pixel section 110 has a plurality of pixel circuits 111 arranged in a matrix. Each of the circuits of the pixel circuits 111 includes a thin film transistor (TFT) 112, a liquid crystal cell 113, and a holding region or storage capacitor 114 serving as a switching element. The liquid crystal cell 113 is connected to a drain electrode or a source electrode of the TFT electrode 12 of the pixel electrode. 14 is connected to one of its electrodes and connected to the electrodeless electrode of the TFT 112. For the pixel circuits 111, the gate lines 丨丨5_丨 to 丨丨5_out extend along a direction of one of the pixel arrays of the individual columns, and the signal lines are &^丨 to &quot; The rows of individual rows are routed in the direction of the pixel array. The TFTs 112 of the pixel circuits Hi are connected in one column to their idle electrodes to the same gate lines 115_1 to 115_〇1. Further, the TFT U2 of the pixel circuits 1U is connected to the same signal line 116_丨 to 丨丨6_n in a - behavior-unit in which the source electrode or the drain electrode is connected. In addition, the liquid crystal cell 113 is connected to a drain electrode of the FT FT 2 and a counter electrode thereof to a common line 17 . The hold 128894.doc -16- 200912877 capacitor 114 is connected between the drain electrode of the add 112 and the common line .... A predetermined AC voltage is applied from the VCOM circuit (not shown) to the common line 117 as a common voltage VC〇m, which is formed integrally with a driving circuit and the like on a glass substrate. . The gate lines 11 5-1 to i i 5_m are driven by the vertical drive circuit m, and the material signal line U6_H16_n is driven by the horizontal drive circuit 130. The «Hui TFT 112 is used to select a pixel for display and supply a display signal to one of the pixel regions of the selected pixel. The TFT 112 has, for example, a bottom gate structure such as that shown in Fig. 3 or a top gate structure such as shown in Fig. 4. Referring to Fig. 3, in the TFT U2A of the bottom gate structure shown, a gate electrode 203 covered with a gate insulating film 202 is formed on, for example, a transparent insulating substrate 2'1 formed of a glass substrate. The gate electrode 203 is connected to one of the gate lines 作为5 as a scanning line, and a gate pulse as a scanning number is input from the gate line 117 to the gate electrode 203. The TFT } 12A is turned on or off in response to the scan signal. The gate electrode 203 is formed of a film such as one of molybdenum (M〇) or tantalum (Ta) metal or an alloy by a method such as sputtering. The TFT 11 2 A includes a semiconductor film 204 formed on the gate insulating film 2〇2 and configured to function as a channel forming region. The TFT 112A further includes a pair of n+ type diffusion layers 2?5 and 206 formed across the semiconductor film 204. An interlayer insulating film 2〇7 is formed on the semiconductor film 2〇4, and an interlayer insulating film 208 is formed to cover the transparent insulating substrate 2 (H, gate insulating layer 202, n+ type). The diffusion layers 205 and 206 and the interlayer insulating film 2〇7. The source electrode 210 is connected to the n+ type diffusion layer 2〇5 through a contact hole 209a formed in the interlayer insulating film 2〇8. The drain electrode 211 is connected to the other n+ type diffusion layer 2〇6 through one of the contact holes 209b formed in the interlayer insulating film 208. For example, the source electrode 2 1 is formed by patterning aluminum (A1). And the drain electrode 211. A signal line 116 is connected to the source electrode 21A, and the electrodeless electrode 211 is connected to a pixel area or a pixel electrode through a connection electrode not shown. Referring now to FIG. The TFT 11 2B of the top gate structure is shown. The TFT 112B includes a semiconductor film 222 formed on a transparent insulating substrate 221. The transparent insulating substrate 221 is formed, for example, from a glass substrate and configured for use. A channel formation region. The TFT 11 2B further includes a horizontal A pair of n+ type diffusion layers 223 and 224 are formed across the semiconductor film 222. A gate insulating film 225 is formed by covering the semiconductor film 222 and the n+ type diffusion layers 223 and 224, and a gate is formed. The electrode 226 is formed on the gate insulating film 225 opposite to the semiconductor film 222. Further, the interlayer insulating film 227 is formed by covering the transparent insulating substrate 221, the gate insulating film 225, and the gate electrode 226. A source electrode 229 is connected to the n + -type diffusion layer 223 through a contact hole 228a formed in the interlayer insulating film 227 and the gate insulating film 225. A drain electrode 230 is formed through the interlayer insulating film. 227 and the other contact hole 228a of the gate insulating film 225 are connected to another n + type diffusion layer 224. 128894.doc • 18- 200912877 Referring back to FIG. 2A, in the above liquid crystal display device 1, each pixel circuit The TFT 112 of 111 is formed by an amorphous crystal (a_si) or a transistor of one of the semiconductor films of polysilicon. The vertical driving circuit 12 receives a vertical start signal vST, a vertical clock VCK and an enable signal ENB, and In a vertical direction (i.e., in one of the columns) scanning each field period to successively select pixel circuits lu connected to the gate lines 115-1 to 115_m in units of one column. In particular, when from the vertical driving circuit 12 A scan pulse Gpl is supplied to the gate line 115_1, and pixels in the respective rows in the first column are selected, but when another scan pulse Gp2 is supplied to the gate line 115-2, the second column is selected. The pixels in each row. Then, gate pulses Gp3, Gpm are successively supplied to the interrogation lines 115-3, ..., 115-m, respectively. Fig. 2B illustrates an example of a waveform of the gate pulse Gpm at the output stage of the gate line 丨丨5_m at the gate buffer 140-m after the gate of the gate pulse Gpm is buffered. Fig. 2C illustrates an example of one of the waveforms of the open-pole pulse Gpm at the gate line (1)--the line terminal portion. The horizontal drive circuit 130 receives a horizontal start clock Hst which is generated from a clock generator (not shown) and indicates the start of the horizontal scan and the horizontal clock HCK whose phases are opposite to each other (which constitutes a reference for horizontal scanning) And generating a sampling pulse "&quot; The horizontal driving circuit 13 连续 continuously samples the image breeding R (red), G (green), and 3 (blue) input thereto in response to the sampling pulse thus generated. And sampling the image data as a signal to be written to the pixel circuits 21, 128894.doc -19-200912877, to the signal lines 1丨6_i to 丨丨6_n. The horizontal drive circuit 130 divides the signal lines 116-1 to 116-n into a plurality of groups and includes signal drivers 13 1 to 13 4 corresponding to the individual groups. Here, the waveform shaping circuits will be described. In this embodiment, the waveform shaping circuits 150-11 to 15〇-1111 and 150_21 to 15〇 of the waveform shaping and voltage change of the gate pulses from the gate buffers 14〇_丨 to 140-m are implemented. The _2111 system is centrally disposed on the gate lines 115-1 to 115-m as described above. Therefore, it can be seen from the waveform shown by a solid line in FIG. 2C that the output levels of the gate lines 115-1 to 115-m are away from the gate buffers 14〇_ι to i4〇-m. The waveform of the gate pulse at or at the distal end portion is improved relative to its distortion. It should be noted that one of the waveforms shown by a broken line in Fig. 2C exhibits distortion of the waveform of the gate pulse at the distal end portion or the terminal portion of the waveform forming circuit. Therefore, the display device facilitates display using a large number of pixels and a high frame frequency. The waveform shaping circuits 150-1 1 to 150_lm and 15 〇 21 to 15 〇 2111 are respectively disposed centrally on the wires of the gate lines 115_1 to 115_111 to form a waveform. In addition, the waveform shaping circuits 15 (Μ1 to 150_lm and 150_21 to 1 50 2m are commonly connected to one supply line 160 for one power supply voltage VDD2 (which is a high potential) and for another power supply voltage vss2 One of the supply lines 1 61 (which is a low potential). The waveform forming circuit 15 (MliLl5〇_ln^15mi5〇_2m are all 128894.doc -20. 200912877 is connected, for example, by a connection by a cascade connection One of the two CM 〇s buffer circuits is formed (as shown in Figures 5A to 5C). In the first embodiment, the waveform shaping circuits UOq 丨 to 1 50 1 m and 1 50-21 to 1 50-2m is arranged in the same coordinate in the vertical direction (i.e., in the direction in which a signal line extends) in the coordinate configuration of the matrix of the pixel circuits in, and more specifically, the waveform forming circuits MO -U to l5〇_lm are respectively arranged at the intersection of the signal line 丨16_6 and the gate lines _15_〗 to 丨15_ claws, and the waveform forming circuit 1 50-21 to 1 50-2m respectively It is disposed at the intersection of the signal lines 116_1〇 and §Hay and other gate lines 115-1 to n5-m. It should be noted that in FIG. 2A, The supply line 160 of the high-potential power supply voltage VDD2 and the supply line 161 for the low-level power supply voltage vss2 are respectively shown as a dashed line and an alternate long and short dashed line to facilitate and The gate lines and the signal lines are distinguished and understood. Figures 5A through 10 illustrate an example in which a waveform forming circuit in accordance with this embodiment is formed by a CMOS buffer. In particular, Figure 5 shows an Figure 5B shows a particular circuit, and Figure 5C illustrates the capacitance on the output side of the buffer. As shown in Figure 5B, each of the waveform shaping circuits 15 includes a CMOS buffer or counter The phase BF1 is connected to another CMOS buffer or inverter BF2 connected in a first-order connection. The CMOS buffer BF1 includes a p-type channel M〇s (pM〇s) transistor PT1 and an n-channel MOS ( NMOS) transistor NT1. 128894.doc • 21 - 200912877 The PMOS transistor PT1 is connected to the supply line 1 60 whose source is connected to the power supply voltage VDD2 for the high potential, and is connected to the NMOS at its drain The drain of the transistor NT1. By the PMOS transistor PT1 and A connection point of one of the drains of the NMOS transistor NT1 forms a node ND1. The NMOS transistor NT1 is connected to a supply line 161 whose source is connected to the power supply voltage VSS2 for the low potential. The PMOS transistor PT1 and the The gates of the NMOS transistor NT1 are connected to each other, and the input node ND1 is formed at one of the connection points of the gates. The input node ND1 is coupled to a corresponding gate line of the gate lines 115 (115-1 to 115-m). The CMOS buffer BF2 includes a PMOS transistor PT2 and an NMOS transistor NT2. The PMOS transistor PT2 is connected to the supply line 160 whose source is connected to the supply voltage VDD2 for the high potential, and its drain is connected to the drain of the NMOS transistor NT2. A node ND2 is formed by a connection point of the PMOS transistor PT2 and one of the drains of the NMOS transistor NT2. The NMOS transistor NT2 is connected to a supply line 1 61 whose source is connected to the power supply voltage VSS2 for the low potential. The PMOS transistor PT2 and the gate of the NMOS transistor NT2 are connected to each other, and one of the gate connection points is connected to the node ND1 of the CMOS buffer BF1. The node ND2 is connected as an output node to one of the gate lines 115 (115-1 to 115-m) corresponding to the gate line. A waveform shaping circuit 150 having a configuration such as one of the above outputs a gate pulse GP1 to GPM that is positively logically from the configuration side of the vertical drive circuit 128894.doc -22-200912877 path 120 (ie, Propagating along a corresponding gate line 115 (115-1 to l15_m) from the output side on the left side of Fig. 2, and further waveform shaping is also performed. The outputs of the CMOS buffers BF1 and BF2 for waveform shaping represent the capacitance Cgate of the gate line, and further indicate that the pixel electrode or the TFT (pixel transistor) is in an open state The capacitance of the liquid crystal Clcd and the storage capacitor cs of the pixels. In addition, since one of the CMOS buffers presents a negative logic output relative to one of its inputs to allow the waveform shaping circuit 15 to output a positive logic output, the waveform shaping circuit 150 is comprised of the CM 〇 s buffers. A circuit in which one of BF1 and BF2 is connected in series is formed. Since the waveform shaping circuit 150 requires an output power supply, the power supply voltage VDD2 for supplying the higher side and the power supply voltage VSS 2 of the lower side are arranged to turn on and off the supply line 16 of the pixel gate. 161 ° The wiring for the supply lines 160 and 16 is arranged parallel to the pixel signal lines. The reason is that, for example, if the supply lines 16〇 and 16丨 are wired in parallel with each other in the vicinity of the signal line 11 6 (11 6-1 to 11 6-n), the hole-to-drain ratio of the liquid crystal can be minimized. Chemical. In addition, in the case where a bus bar line exhibiting a lower impedance to the supply lines 160 and 161 for the voltages VDD2 and VSS2 is connected to the effective pixel region section 110, the power supply in the horizontal direction can be made. The voltage drop across the line is minimized. Therefore, 'the voltage corresponding to one of the high level (high voltage) and the other voltage (low voltage) corresponding to the low level can also be minimized, and the voltage is 128894.doc • 23· 200912877 at the effective pixel level The direction is output from the waveform shaping circuit 丨5〇. In addition, in the first embodiment, the supply lines 160 and 161 for the voltage and να supplied to the waveform shaping circuit 150 and the waveform shaping circuit 15A are preferably arranged at the level. The same coordinates in the direction. The reason is that since the coordinates of the waveform shaping circuit 15 该 in the horizontal direction are fixed, the gate pulse waveform is not affected by the delay. ~ As described above, according to the first embodiment, a waveform shaping circuit 丨5 for performing waveform shaping and voltage change on the wires of the gate lines for outputting one gate pulse from the vertical driving circuit 120 is arranged. 〇_ 11 to 150-lm and 150-21 to 150-2m. Therefore, with the specific embodiment of the present invention, the following effects can be achieved. In a display device including a large 1 pixel of 4K2K and using a high frame frequency of 240 Hz, the shadow in the left and right directions or the left or right direction due to the delay of one gate line is eliminated. A good difference in chroma quality results in good image quality. In addition, the output delay and distortion of the waveform of the gate pulse GP from the vertical driving circuit 12A can be suppressed, and the vertical driving on the left or right side of the image frame of one of the active matrix display devices can be reduced. The occupied area of the circuit and the buffer circuit. Thus, the image frame of the display device can be formed to have a reduced width on its left and right side portions. Further, the supply lines 160 and 161 for the voltages VDD2 and VSS2 to be supplied to the waveform shaping circuits 150 and the waveform shaping circuits 150 are placed in the same horizontal direction as 128894.doc -24-200912877 At the coordinates, the delay of the closed-pole pulse waveform can be suppressed. &lt;Second Embodiment&gt; One of the Second Embodiments and a Pole Pulse Wave Figure 6A, 6B, and 6C respectively show an example of a configuration of one of the liquid crystal display devices according to the present invention. Referring first to FIG. 6A, the configuration of the liquid crystal display device 100A according to this second embodiment is similar to that of the liquid crystal device according to the first embodiment described above, but differs in the arrangement position of the waveform shaping circuits 150. . In the liquid crystal device (8) of the first embodiment, the supply lines 16 and 161 for the voltages VDD2 and VSS2 to be supplied to the waveform forming circuit 150 and the waveform forming circuit 15A are provided. The system is arranged at the same coordinates in the horizontal direction. In contrast, in the liquid crystal display device 1A of the second embodiment, the supply lines 160 and 161 for the voltages VDD2 and VSS2 to be supplied to the waveform shaping circuit 50 and the waveform shaping circuits 15A. They are not disposed at the same coordinates in the horizontal direction and are arranged to be displaced relative to one another in a one-way relationship with the wires of the gate lines and the signal lines. In the example shown in Fig. 6A, the waveform shaping circuit 150-11 is disposed adjacent to a position where the one of the gate line 116-3 and the gate line 115-1 overlap. The waveform liters &gt; circuit 1 50-1 2 is arranged near the intersection of the signal line 11 6-4 and the gate line 11 5-2. The waveform shaping circuit 丨5 〇 _ _ 3 is arranged near the intersection of the signal line 116-5 and the gate line 11 5-3. The wave formation 128894.doc -25- 200912877 shaped circuit 150-14(m) is disposed adjacent to the intersection of the signal line 116-6 and the gate line ii5-m. At the same time, the waveform shaping circuit 150-21 is disposed near the intersection of the signal line 116_7 and the gate line 115-1. The waveform shaping circuit 15 〇 22 is disposed near the intersection of the signal line 116-8 and the gate line 11 5-2. The waveform shaping circuit 150-23 is disposed near the intersection of the signal line 116-9 and the gate line 11 5-3. The waveform shaping circuit 1 5〇_24(m) is disposed at a position (near) of the 彳s saying line 116-10 and one of the gate lines. In this example, a waveform such as in the horizontal direction When the coordinates of the shaping circuit 150 are not fixed, the partial one-sidedness is eliminated from the supply lines 160 and 161 for the power supply voltage VDD2 and the reference voltage VSS2. Therefore, the supply for the voltages VDD2 and VSS2 is ensured. The uniformity of the transmission factor of the pixels under the influence of the wiring layout of lines 160 and 161. In this example, the brightness distribution of the display device is fixed. (The configuration of another part of this second embodiment is similar to the first This configuration of a specific embodiment can also achieve effects similar to those achieved by the first embodiment described above. <Third embodiment> Figs. 7A, 7B and 7C respectively show according to the present invention. An example of one of the configurations of one of the liquid crystal display devices and an example of a dummy pulse waveform is shown in the third embodiment. Referring first to FIG. 7A, according to the third embodiment, the liquid crystal display of the example will be different. Device 100 The state is similar to the liquid 128894.doc • 26 · 200912877 crystal display devices 100 and 100A according to the above-described first embodiment, but differs in the arrangement position of the waveform forming circuits 150. In particular, In the liquid crystal display devices 100 and 100A according to the first and second embodiments, the supply lines 16 for the voltages VDD2 and VSS2 to be supplied to the waveform shaping circuits 15 and the waveform shaping circuits 150 are provided. 0 and 1 are arranged in the same coordinate in the horizontal direction. Alternatively, the supply lines 16 and 161 for the voltages VDD2 and VSS2 to be applied to the waveform forming circuit 15 and the waveform forming circuit 150 are not In the liquid crystal display device 丨〇〇b according to the third embodiment, the waveform forming circuits 150-11 to 150_nm are disposed on the gate lines and the signal lines. Almost all of the gate lines near the intersection and, or in other words 4, at the input portion of the pixel circuit (1) for the gate pulse.

If the waveform shaping circuit 15G is disposed on the wire of the (qua) line for each pixel circuit (1) in this manner, a plurality of pixel circuits 111 may be allowed to exist between different waveform shaping circuits so as not to be in them. Any dispersion of the waveform delay of the gate pulse occurs. In other words, in the case where a plurality of pixel circuits exist between the waveform forming circuit and the waveform forming circuit, the unevenness of the parasitic capacitance is eliminated: 'and the load of the pixel gates of the waveform forming circuits is ensured. capacitance. Therefore, the delay under the gate electrode condition no longer occurs. The configuration of another part of the first embodiment is similar to the configuration of the first and the second embodiment, and can also be implemented with the second specific by the first and 128894.doc •27·200912877 The effects achieved by the embodiments are similar. &lt;Fourth embodiment&gt;. . Fig. 8 shows an example of one configuration of a liquid crystal display device according to a fourth embodiment of the present invention. Referring to Fig. 8, the configuration of the liquid crystal display device 100C according to this fourth embodiment is similar to that of the liquid crystal device 100' according to the above-described first embodiment, but differs in that it uses image data therein.

One-time configuration is also effective in the time-sharing method of writing the person-to-panel system. In particular, in the case where the time-sharing switch is used as shown in FIG. 8 to reduce the image frame of the panel, if the number of time-sharing switches is not sufficiently satisfied within a horizontal selection period One electrical feature and one image feature require the application of the present invention. From this line, signals SV1 to SV4, which are nicknamed 131 to 134, are transmitted to the signals 116 (116-1 to 116-12) through a selector SEL having a plurality of transmission gates TMG. The fine control gate 81 and its -inverted signal XS1, another select signal S2 and an inverted signal XS2 thereof, another selection signal, and an inverted XS3.. Analog Switch) Conductive Status of TMG These signals are supplied externally and have complementary levels to each other. In the case of the configuration described above, the high-resolution (brain (4) and two-speed frame rate type-active matrix display device can use a selector to drive the car _ .. 叮巧勒糸The system reduces the connection terminal and improves the mechanical reliability of the connection. The configuration of the other part of the fourth embodiment is similar to the configuration of the embodiment of 128894.doc -28-200912877, and The effect of the effect achieved by the first embodiment described above is similar to that of the first embodiment described above. <Fifth Embodiment> FIG. 9 shows a liquid crystal display device according to a first embodiment of the present invention. An example of the structure. Referring to FIG. 9, the configuration of the liquid crystal display device 100D according to this fifth embodiment is similar to the liquid crystal device 100A' according to the second embodiment described above, but differs in that it is employed in The image data is also validly configured in one-panel system. It is specifically described as 'and, as shown in Figure 9, the time-sharing switch is used to fluff the image frame of the panel. Next, if The present invention may be applied to the number of time divisions of the time-sharing switch that does not adequately satisfy one of the electrical characteristics and an image feature in a horizontal selection period. Referring to Figure 9, one of the selectors SEL having a plurality of transmission gates TMG will come from The signals svi to states of the signal drivers 131 to 134 are transmitted to the signal lines 116 (116-1 to 116-12) by a selection signal 81 and an inverted signal XS1 'the other selection signal S2 and its opposite The phase signal, in turn 32, another selection signal "and its inverted signal XS3..." controls the conduction state of the transmission gate (analog switch) TMG, which are supplied externally and have mutually complementary levels. In the case of the configuration described above, the active matrix display device of one of the high resolution (UXGA) and high speed frame rate types can adopt a selection g time division driving system, which reduces the number of connection terminals and The mechanical reliability of the connection is provided. 128894.doc -29·200912877 The configuration of another part of the fifth embodiment is similar to the configuration of the second embodiment, and can also be implemented by the first And second The effect achieved by the embodiment is similar. <Sixth embodiment> An example of one configuration of a liquid crystal display device according to a sixth embodiment of the present invention is shown. Referring to FIG. 10, The configuration of the liquid crystal display device 100E according to this sixth embodiment is similar to that of the liquid crystal device 100B according to the third embodiment described above, but is different from that in which the image data is written in a time sharing manner thereto. One panel of the system is also effective in one configuration. In addition, in the case of using a minute switch as shown in Figure 以便0 to reduce the image frame of the panel, if the time-sharing switch The number of time divisions does not sufficiently satisfy one of the electrical characteristics and an image feature in a horizontal selection period, and the present invention needs to be applied. Referring to FIG. 10, signals SV1 to SV4 from the signal drivers 131 to 134 are transmitted to the signal lines 116 (116-1 to 116-12) through a selector SEL having a plurality of transmission gates 3. The selection signal 81 and its inverted signal XS1, the selection signal s2 and its inverted signal XS2, the selection signal S3 and its inverted signal XS3... are used to control the conduction state of the transmission gates (analog switches) TMG, such signals Is supplied externally and has complementary levels. In the case of the configuration described above, one of the high resolution (UXGA) and the same speed frame rate type active matrix display devices can employ a selector Time-division drive system, which reduces the number of connection terminals 128894.doc -30. 200912877 and improves the mechanical reliability of the connection. The configuration of the other part of this sixth embodiment is similar to that of the third embodiment. The configuration can also achieve effects similar to those achieved by the first to third embodiments described above. <Seventh embodiment> FIG. 11 shows a seventh embodiment according to the present invention. Liquid crystal display An example of one of the configurations is shown. Referring to Fig. 11, the configuration of the liquid crystal display device 100F according to the seventh embodiment is similar to the liquid crystal display device 100B' according to the third embodiment described above, but with the following differences. Specifically, in the liquid crystal display device 10017, the supply line (10) for the power supply voltage VDD 2 and the supply line 161 for the power supply voltage vss 2 are also routed to all of the signal lines (16 (1) ... 丨 to 116 and between all of the gate lines 115 (115_1 to 115_111).

If you use the above configuration, you can prevent the undesired voltage from invading the adjacent pixel circuit! 1丨' This system occurs between the gate line and the signal line. Therefore, good image quality can be obtained. The other part of the configuration of the seventh embodiment (4) the configuration of the third embodiment is also exemplified, and the first to third embodiments are The effect achieved is similar to the effect. It should be noted that although FIG. 11 is not in the wiring of one of the voltage supply lines in the seventh embodiment, the configuration of the seventh embodiment may be applied. Other first, second and fourth to sixth specific embodiments. Moreover, in this example, an undesired voltage can be prevented from intruding into an adjacent image 111, and an effect of obtaining good image quality can be achieved. &lt;Eighth Embodiment&gt; Figs. 12A, 12B and 12C respectively show an example of a configuration of a liquid crystal display device and an example of a gate pulse waveform according to an eighth embodiment of the present invention. Referring first to FIG. 12A', the configuration of the liquid crystal display device 100G according to the eighth embodiment is similar to the liquid crystal device 100' according to the first embodiment described above, but differs in that the waveform shaping circuit is not simple. The CMOS buffers connected by a cascade connection are configured with a certain time CMOS circuit. Here, a waveform shaping circuit 151 will be described. Further, in the eighth embodiment, the waveform shaping circuits 151-11 to 151-lm and 151- of the waveform shaping and voltage change of the gate pulses from the gate buffers 140-1 to 140-m are implemented. The 21 to 151-2m are centrally disposed on the gate lines 11 5-1 to 115-m as described above. Therefore, it can be seen from the waveform shown by a solid line in FIG. 12C that the gate lines 115-1 to 115-m are away from the gate buffers 14〇_ι to the output of the -利-瓜The waveform of the gate pulse at the terminal portion or the terminal portion of the stage is improved with respect to its distortion. It should be noted that a waveform shown by a broken line in Fig. 2C exhibits distortion of the waveform of the gate pulse at the distal end portion or the terminal portion of the waveform forming circuit. Therefore, the display device facilitates display using a large number of pixels and a high frame frequency. The waveform shaping circuits 151-11 to 151_11!1 and 151-21 to 151-2m are 128894.doc -32- 200912877 and are disposed centrally on the wires of the gate lines 11 5-1 to 11 5-m To form a waveform. In addition, the waveform shaping circuits 151-11 to 151-lm and 151-21 to 151-2111 are commonly connected to one supply line 160 for a power supply voltage 〇02 (which is a high potential) and used for Another power supply voltage vsS2 (which is a low potential) is supplied to line 161. The waveform shaping circuits 151-11 to 151-lm and 151-21 to 1512-2m are formed, for example, by a circuit including a timing CMOS and a CMOS buffer connected by a cascading connection (as shown in the figure). 13A to 13C). In this eighth embodiment, the waveform shaping circuits 丨5丨_丨丨 to 151-lm and 151-21 to 15 l-2m are arranged at the same coordinates in the vertical direction. More specifically, the waveform shaping circuits 151-11 to 151-lm are respectively disposed at intersections of the signal lines 116-6 and the gate lines 115-1 to 11 5-m. The waveform shaping circuits 15 1 - 2 1 to 1 5 1 - 2m are respectively disposed at the intersection of the signal line 116-10 and the gate lines 115-1 to 115-m. 13A to 13C illustrate an example in which the waveform shaping circuit is formed by a certain time CMOS circuit as this eighth embodiment. Specifically, Fig. 13A shows an equivalent circuit, and Fig. 13B shows a specific circuit, and Fig. 13C illustrates the capacitance on the output side of the buffer. As can be seen from FIG. 13B, each waveform shaping circuit 151 includes: a certain time CMOS buffer or inverter BF3, which replaces the configuration of the CMOS buffer BF1 shown in FIG. 5; and another CMOS buffer or counter Phaser BF2, which is connected to timing CMOS buffer BF3, is connected in a cascade. 128894.doc -33- 200912877 In addition to the configuration of the CMOS buffer BF1 shown in FIG. 5, the timing CMOS buffer BF3 further includes a PMOS transistor PT3 and an NMOS transistor NT3. The PMOS transistor PT3 is connected to the supply line 160 whose source is connected to the power supply voltage VDD2 for the high potential, and whose drain is connected to the drain of the NMOS transistor PT1. At the same time, the NMOS transistor NT3 is connected to the supply line 161 whose source is connected to the power supply voltage VSS2 for the low potential, and its drain is connected to the source of the NMOS transistor NT1. A clock CK is supplied to the gate of the NMOS transistor NT3, and an inverted or complementary signal XCK of the clock CK is supplied to the gate of the PMOS transistor PT3. When the clock CK assumes the high level, the PMOS transistor PT3 and the NMOS transistor NT3 are placed in an on state to make the timing CMOS circuit operational. The clocks CK and XCK have a function as an enable signal that controls the start of the operation of the waveform shaping circuit 151. The configuration of the other portion of the waveform shaping circuit 151 is similar to the configuration of the circuit shown in Figs. 5A to 5C, and therefore, overlapping descriptions thereof are omitted here to avoid redundancy. The waveform shaping circuit 151 having the configuration as described above outputs the gate pulses GP1 to Gpm emitted from the arrangement side of the vertical drive circuit 120 (i.e., the output side or the left side shown in Fig. 13A). The waveform is output as a positive logic and waveform shaping is further performed. 128894.doc • 34- 200912877 The timing CMOS buffer bF3 for waveform shaping and the output of the cM〇s buffer BF 1 represent the capacitance Cgate of the gate line, and are also indicated at the pixel electrode or the TFT ( The pixel transistor is in a state in which the liquid crystal capacitor Clcd is in a state of being in an open state and the capacitance of the storage capacitor Cs of the pixel. In addition, since the sigma timing CMOS buffer BF3 indicates an inverted logic output with respect to one of its inputs, the waveform shaping circuit 丨5 is connected to the timing CM 〇s buffer by the CMOS buffer BF2. BF3 is formed in order to obtain a positive logic output circuit. Since the waveform shaping circuit 151 is required for one of its output power supplies 'is therefore placed to supply the higher side power supply voltage VDD2 and the lower side power supply voltage VSS 2 to turn the supply of the pixel gate on and off. Wires of lines 160 and 161. The wires are placed parallel to the pixel signal wires. The reason is that, for example, in the case where it is parallel to the signal lines 116 (116_1 to 116_11) and placed in the vicinity of the signal lines, the decrease in the aperture ratio of the liquid crystal can be minimized. In addition, in the case where the bus lines for lowering the supply lines 16A and 1 61 for the voltages VDD2 and VSS2 are connected to the effective pixel region section 110, 'in the horizontal direction can be made The voltage drop of the power supply line is minimized. Therefore, variations in the high voltage and low voltage to be output from the wave forming circuit 153 in the horizontal direction of the effective pixels can also be minimized. When the clock (enable signal) CK or XCK (as a control signal) enters the 128894.doc -35-200912877 CMOS buffer (which forms the waveform shaping circuit 151), the timing CMOS buffer BF3 is One of the rising edges or a falling edge of the clock begins its operation. If the supply lines 1 62 for the clocks CK and XCK are wired in the vertical direction of the display device and become operative, a certain delay or in the vertical direction of the clocks CK and XCK occurs. The waveform distortion on the 'but in the horizontal direction, the clocks CK and XCK have the same history of the same parasitic capacitance. Therefore, the delay becomes fixed. Therefore, one of the signal signals transmitted along one of the gate lines arranged in the horizontal direction is subjected to one of the clock control delay waveforms. This produces a selection signal without the need for a gate selection waveform that is scanned vertically at a high speed to focus on the horizontal direction. Further, in the eighth embodiment, the supply lines 160 and 161 for the voltages VDD2 and VSS2 to be supplied to the waveform shaping circuits 151 and the waveform shaping circuits 丨5 较佳 are preferably preferred. The same coordinates are arranged in the horizontal direction, which is similar to that in the first embodiment. The reason is that since the coordinates of the waveform shaping circuit 151 in the horizontal direction are fixed, the gate pulse waveform is not affected by the delay. The configuration of another part of the eighth embodiment is similar to the configuration of the first embodiment, and effects similar to those achieved by the above-described first embodiment can be achieved. In addition, the delay can be kept fixed with high accuracy. &lt;Ninth Embodiment&gt; 128894.doc • 36 - 200912877 Figs. 14A, MB and 14C respectively show examples of waveforms configured by one of the liquid crystal display devices according to a ninth embodiment of the present invention. Example and a gate pulse Referring to FIG. 14A, the configuration of the liquid crystal display device 100H according to the ninth embodiment is similar to the liquid crystal device 100G according to the first specific embodiment, but different embodiments. In the liquid crystal device i 〇〇 g of the eighth embodiment, in the liquid crystal device i 〇〇 g of the eighth embodiment described above, the configuration bits for the waveform forming rake q ^ / 冤 1 1 特定 特定 特定 特定 特定 特定 特定 特定 特定 特定The supply lines 160 and 161 of the voltage vDD2 &amp; VSS2 supplied by 150, the supply line 162 for the clocks CK and xcK, and the waveform shaping circuits 150 are arranged at the same coordinates in the horizontal direction. In contrast, in the liquid crystal display device 1 〇〇G of the eighth embodiment, the supply lines 160 and 161 for the voltages VDD2 and VSS 2 to be supplied to the waveform shaping circuits 150 are used for the clocks CK. And the XCK supply line 162 and the waveform shaping circuits 150 are not disposed at the same coordinates in the horizontal direction and are arranged to be displaced relative to one another in a row relationship with the gate lines and the signal lines The wires are in a corresponding relationship. In the example shown in Fig. 14A, the waveform shaping circuit 1 5-11 is disposed near the position where the signal line Π 6-3 and the gate line 115-1 overlap. The wave forming circuit 150-12 is disposed adjacent to an intersection of the signal line 116-4 and the gate line 115-2. The waveform shaping circuit 1 50-13 is disposed adjacent to an intersection of the signal line 1 6-5 and the gate line 115-3. The waveform shaping circuit 150-14(m) is 128894.doc -37- 200912877 arranged in the vicinity of the signal line 11 6-6 and the gate line 11 5-m. At the same time, the waveform shaping circuit 150-21 is disposed near the intersection of the signal line 116_7 and the gate line 115-1. The waveform shaping circuit 15〇_22 is disposed adjacent to the signal line 116-8 and the gate line π5-2. The wave forming on circuit 1 50-23 is arranged near the intersection of the signal line 丨丨6_9 and one of the gate lines 115-3. The waveform shaping circuit 15A_24(m) is disposed near the intersection of the signal line 11 6-1 〇 and the gate line 丨丨5_m. In this example, the partial flakes are eliminated from the supply lines 16 and 161 for the power supply voltage VDD2 and the reference voltage VSS2, for example, in the case where the coordinates of the waveform shaping circuit 15A in the horizontal direction are not fixed. Therefore, the uniformity of the transmission factor of the pixel under the influence of the wiring layout for the supply lines 1 60 and 1 61 of the voltages £2 and VSS2 is ensured. In this example, the brightness distribution of the display device is fixed.

The configuration of another portion of the ninth embodiment is similar to the configuration of the eighth embodiment, and effects similar to those achieved by the above-described third and eighth embodiments can be achieved. &lt;Tenth embodiment&gt; Tenth concrete one gate pulse Figs. 15A, 15B and 15C respectively show an example of a configuration of a liquid crystal display device and an example of a waveform according to an embodiment of the present invention. The liquid crystal display of the ten embodiment is shown in Figs. 16A to 16J in accordance with the operation of the first display device. 128894.doc -38- 200912877 Specifically, FIG. 16A illustrates a clock VCK for one vertical drive circuit; FIG. 16B illustrates one of the waveform shaping circuits for a clock pattern 16C illustrating one of the clocks CK, XCK; 16D illustrates a vertical start signal VST (Vst). 1E illustrates a gate pulse GP1 which is immediately output as one of the first columns of the vertical drive circuit 120; FIG. 16F illustrates a gate pulse GP2' as the first for the vertical drive circuit 丨2〇 One of the two columns is output immediately; and FIG. 16G illustrates a gate pulse GP3 which is immediately output as one of the third columns for the vertical drive circuit 120. 16H illustrates a gate pulse GP1 at a distal end portion of the first column of the vertical drive circuit 12A; FIG. 161 illustrates a gate pulse Gp2 at a distal end portion of the second column of the vertical drive circuit 12A. FIG. 16J illustrates a gate pulse GP3 at a distal end portion of the third column of the vertical drive circuit 120. In addition, the time diagram of FIG. 16E indicates that one of the first columns outputs the pulse immediately; the time chart of FIG. 16F, Vgate_2_L, illustrates the second column, which immediately outputs the pulse; and the time chart of FIG. 16G, Vgate_3_L, illustrates one of the third columns. The pulse is output immediately. In addition, the time diagram Vgate_丨-r of FIG. 16H illustrates the first column—the far-end pulse; the time chart of FIG. 161, Vgate_2_Rw, says the second column—the far-end pulse; and the time chart of FIG. 16J, the vgate_3—the ruler The third column - the far end pulse. Referring to FIG. 15 A', the configuration of the liquid crystal display device 1001 according to the tenth embodiment is similar to the liquids 128894.doc • 39· 200912877 devices 100G and 100H according to the eighth and ninth embodiments described above, but The difference lies in the arrangement position of the waveform shaping circuits ι51. Specifically, in the liquid crystal display devices 100G and 100A according to the eighth and ninth embodiments, the supply of voltages VDD2 and VSS2 to be supplied to the waveform shaping circuits ι51 and the waveform shaping circuits 151 is used. Lines 1 60 and 1 61 are arranged at the same coordinates in the horizontal direction. Alternatively, the supply lines 160 and 161 for the voltages VDD2 and VSS2 to be applied to the waveform shaping circuits 15 and the waveform shaping circuits 151 are not arranged at the same coordinates. In contrast, in the liquid crystal display device 1 according to the tenth embodiment, the waveform forming circuits 1 5 1 -11 to 1 5 1 -nm are disposed on the gate lines and the signal lines. Almost all of the intersections are located on the gate line near the location, or in other words, at the input portion of the pixel circuit 1 for a gate pulse. For this tenth embodiment, a gate pulse is shaped as a good #waveform&apos; as can be seen from Figures 16A through 16J. In addition, although the waveform of the gate pulse is distorted by the parasitic capacitance of the supply line 162 for the clocks CK and XCK, etc., it is used for the clocks CK and XCK in the horizontal direction. All supply lines 62 have an equal parasitic capacitance value, so the distortion of the waveforms of the clocks CK and XCK are the same. Therefore, since the gate pulse emitted in the horizontal direction passes through the equal wave forming circuit 151, its waveform is not affected by the distortion and delay in the horizontal direction. 128894.doc -40· 200912877 In this way, since the waveform shaping circuit 151 is disposed on the wires of the gate lines for each pixel circuit 111 in this manner, a plurality of pixel circuits (1) can be allowed to exist. Any dispersion between the waveform shaping circuits so that the waveform delay of the gate pulse does not occur therein. In other words, in a plurality of pixel circuits exist between a waveform shaping circuit and another waveform shaping circuit, the parasitic capacitance of the parasitic capacitance is eliminated, and the pixel gates of the waveform shaping circuits are uniform. Load capacitance. Therefore, the delay under the gate electrode condition no longer occurs. The configuration of another part of the tenth embodiment is similar to the configuration of the eighth and ninth embodiments, and can also be implemented similarly to the effects achieved by the eighth and ninth embodiments above. The effect. &lt;Eleventh Detailed Embodiment&gt; Fig. 17 shows an example of one configuration of a liquid crystal display device according to an eleventh embodiment of the present invention. Referring to FIG. 17, the configuration of the liquid crystal display device 100J according to the eleventh embodiment is similar to the liquid crystal display device 100G according to the eighth embodiment described above, but differs in that the image data is used therein. One of the valid configurations of the knives when writing to a panel is also effective. 4 Temple set + 夕 ° 'And 'in the case of using a minute switch as shown in Figure 18 to reduce the image frame of the ^ panel, if the number of time-sharing switches is not filled with a knife One of the electrical characteristics and an image feature in the horizontal selection period requires the application of the present invention. In Fig. 17, 'the signals SV1 to SV4 from the signal drivers 131 to 134 are transmitted to the signal lines 116 (116-1 to 116) through the selector SEL having a plurality of transmission gates TMG. -12). Controlling the conduction states of the transmission gates (analog switches) by the selection signal S1 and its inverted signal XS1, the selection signal S2 and its inverted signal XS2, the selection signal S3, and the inverted signal XS3.. These signals are supplied externally and have complementary levels to each other.

In the case of adopting such a configuration as described above, one of the high-resolution (UXGA) and high-speed frame rate type active matrix display devices can use a selector time-division driving system, which reduces connection terminals. The number and the mechanical reliability of the connection. The configuration of another portion of the eleventh embodiment is similar to the configuration of the eighth embodiment, and effects similar to those achieved by the eighth embodiment described above can be achieved. &lt;Twelfth Embodiment&gt; Fig. 18 shows an example of one configuration of a liquid crystal display device according to a twelfth embodiment of the present invention. The configuration of the liquid crystal display device 1 according to the twelfth embodiment is similar to the liquid crystal display device according to the ninth embodiment described above, but differs in that it is employed in The image data is also available in a time-sharing manner in the system of the person-panel. Specifically, and in the case where a time-division switch is used as shown in FIG. 18 to reduce the image frame of the panel, the number of time division switches is one of the electrical periods in a horizontal selection period. The present invention is applied to features and image features. 128894.doc -42- 200912877 Referring to FIG. 1, signals SV1 to SV4 from the signal drivers U1 to 134 are transmitted to the signal lines 116 (116-1 to 116-) through a selector SEL having a plurality of transmission gates tmg. 12). Controlling the conduction state of the transmission gates (analog switches) TMG by the selection signal S1 and its inverted signal XS1, the selection signal S2 and its inverted signal XS2, the selection signal S3 and its inverted signal XS3 ·.. These signals are supplied externally and have complementary levels to each other. In the case of adopting such a configuration as described above, the active matrix display device of one of the high resolution (UXGA) and the frame rate type can employ a selector time-division driving system, which reduces the number of connection terminals And improve the mechanical reliability of the connection. The configuration of another portion of the twelfth embodiment is similar to the configuration of the ninth embodiment, and effects similar to those achieved by the eighth and ninth embodiments described above can be achieved. &lt;Thirteenth embodiment&gt;. Fig. 19 is a view showing an example of a configuration of a liquid crystal display device according to a thirteenth embodiment of the present invention. Referring to FIG. 19, the configuration of the liquid crystal display device according to the thirteenth embodiment is similar to that of the liquid crystal display device 10GI according to the tenth embodiment described above, but differs in that it is used in the image data of the towel. The system that writes the person-to-panel in the ^ hour mode is also effective - configuration &quot; specific D and, in the case of using a minute switch as shown in Fig. 19 in order to reduce the image sfl of the board If the number of time divisions of the time-sharing switch is not filled to satisfy one of the electrical characteristics in a horizontal selection period and an image is 128894.doc-43-200912877, the invention needs to be applied. Referring to FIG. 19, the signals $v1 to $V4 from the 4th 驱动§ drive 丨3丨 to 丨34 are transmitted to the shai 4 线 line 11 6 through the selector L having the plurality of transmission gates TMG. (丨丨6_丨至丨丨6_ ι2). Controlling the conduction state of the transmission gates (analog switches) TMG by the selection signal 81 and its inverted signal xsi, the selection signal Μ and its inverted L-number XS2, the selection signal S3, and its inverted signal XS3... These signals are supplied externally and have complementary levels to each other. In the case of the configuration as described above, the active matrix display device of the high resolution (UXGA) and high speed frame rate type can employ a -selector time division driving system, which reduces the number of connection terminals And improve the mechanical reliability of the connection. The configuration of another portion of the thirteenth embodiment is similar to the configuration of the tenth embodiment, and effects similar to those achieved by the eighth to tenth embodiments described above can be achieved. It should be noted that, although not specifically shown, the wiring scheme of the voltage supply lines in the seventh embodiment can be applied to the eighth to thirteenth embodiments. Moreover, in this example, it is possible to prevent an undesired voltage from intruding into an adjacent pixel circuit. Therefore, an effect of obtaining good image quality can be achieved. &lt;Fourteenth Embodiment&gt; Figs. 20A, 20B and 20C respectively show an example of a configuration of a liquid crystal display device according to a fourteenth embodiment of the present invention and a gate pulse 128894.doc - 44 - 200912877 Example of a waveform. Referring first to Fig. 20A, the configuration of the liquid crystal display device 100M according to this fourteenth embodiment is similar to the liquid crystal display device 1 〇〇 ' according to the above-described first embodiment but having the following difference. In the liquid crystal display device 100 according to the fourteenth embodiment, the waveform shaping circuits are not made of a CMOS buffer formed by simply adopting a cascade connection to utilize a certain time CMOS. The circuit is configured. Here, a waveform shaping circuit 152 will be described. Further, in the fourteenth embodiment, the waveform shaping circuits 152-11 to 152-lm and 152 for waveform shaping and voltage change of the gate pulses from the gate buffers 140-1 to 140-m are implemented. The -21 to 152-2m are centrally disposed on the wires of the gate lines 11 5-1 to 11 5-m as described above. Therefore, as can be seen from one of the waveforms shown by a solid line in FIG. 20C, the gate lines 115-1 to 115-m are away from the gate buffers 1404 to the distal end portion of the output stage of the papaya. The waveform of the gate pulse at the terminal or terminal portion is improved with respect to its distortion. It should be noted that one of the waveforms shown by a broken line in Fig. 2C appears in the distal portion or the terminal portion where no waveform shaping circuit is inserted. Distortion of the waveform of the pole pulse between the electrodes. Therefore, the display device facilitates display using a large number of pixels and a high frame frequency. The waveform shaping circuits 152-11 to 152-1 m and 152-21 to 152-2m respectively The system is arranged centrally on the gate lines u 5_丨 to 丨丨5_mi to form a waveform. 128894.doc •45- 200912877 In addition, the waveform shaping circuits 152_ι 1 to 152_21 to 152-2m are commonly connected to each other. A supply line 1 60 for a power supply voltage ν 〇〇 2 (which is a high potential) and a supply line 1 6 1 for a power supply voltage vsS2 (which is a low potential). 5 Hai special wave formation liters &gt; Circuit 152- 11 to 152-lm and 152-21 to 152-2m are, for example, connected by a level A NAND gate configured to connect one of the CM〇s is formed with one of the CMOS oscillators (as shown in Figures 21A through 21). In the fourteenth embodiment, the waveform shaping circuit 152 _丨丨 to 1 52-1 m and 152-21 to 152-2m are arranged at the same coordinates in the vertical direction. More specifically, the waveform shaping circuits 152_u to 152_lm are respectively arranged on the signal line 116-6 intersects with the gate lines 丨丨^丨 to 丨丨Hong claws. The waveform shaping circuits 152-21 to 152-2m are respectively disposed on the signal lines 11 6-1 0 and the gates The intersection of the pole lines 11 5-1 to 11 5-m. Figures 21A to 21C illustrate an example in which a CM〇s circuit is formed by a CMOS configuration, and an example of a waveform shaping circuit according to the fourteenth embodiment is formed. In particular, Figure 21A shows an equivalent circuit, while Figure 21B shows a special circuit, and Figure 21C illustrates the capacitance on the output side of the buffer. As shown in Figure 21B, each waveform shaping circuit 152 includes a CMOS circuit 11 configured by CM〇s and connected to a CMOS buffer of the nand circuit 1 1 or a cascade connection Phase BF11. A CMOS group of NAND circuits π includes a pair of PM〇s transistors pT11 128894.doc -46- 200912877 and PT12 and a pair of NMOS transistors NT11 and NT12. The PMOS transistors PT11 and PT12 are connected to Its source is connected to one of the supply lines 160 for the high potential power supply voltage VDD2. The PMOS transistors PT11 and PT12 are connected to their drains connected to the drain of the NMOS transistor NT 11, and a node ND11 is formed by one of the connection points of the drains. The NMOS transistor NT11 is connected to a drain whose source is connected to the NMOS transistor NT12, and the NMOS transistor NT12 is connected to a source thereof to a supply line 161 for a reference voltage VSS2 for the low potential. (The PMOS transistor PT12 and the NMOS transistor NT12 are connected to each other at their gates, and a node ND1 is formed by one of the gate connection points and is connected to the gate lines 115 (115-1 to 15) One of the -m) corresponds to the gate line. In addition, the PMOS transistor PT12 and the NMOS transistor NT1 2 are connected at their gates to a supply line for the enable signal ENB. The CMOS buffer BF11 includes a PMOS transistor PT13 and an NMOS transistor NT13. The PMOS transistor PT13 is connected at its source to the supply line 1 60 for the high potential (power supply voltage VDD2, and its drain is connected to the NMOS A drain of the transistor NT13. A node ND12 is formed by one of the connection points of the drains. The NMOS transistor NT13 is connected to a supply line 161 whose source is connected to the power supply voltage VSS2 for the low potential. The PMOS transistor PT13 and the NMOS transistor NT13 are connected to each other at their gates, and one of the gates is connected to a node ND11 of a CMOS-configured NAND circuit 11. The node ND12 serves as an output 128894. .doc -47· 200912877 The node is connected to the gate line 115(1)5_uU5_m) - Corresponding to the polarity line. The waveform shaping circuit 152 having the configuration as described above outputs a gate emitted from the arrangement side of the vertical drive circuit m (i.e., 'the wheel side or the left side shown in FIG. 2Aa). Pulse (}1&gt;1 to (}1&gt; „1 waveform as a positive logic output' and further implementation of waveform shaping. A CMOS circuit configuration for waveform shaping ii circuit iia the cm〇s buffer thief BF 11 The output indicates the capacitance of the gate line, and further includes a capacitance of the liquid crystal capacitor cled in the state in which the pixel electrode or the TFT (pixel transistor) is in an on state and the storage capacitor Cs of the pixel In addition, since a CMOS-configured NAND circuit 丨丨 indicates an inverted logic output with respect to one of the inputs, the waveform shaping circuit M2 is connected to the NAND circuit by connecting the CMOS buffer BF11 in series. 11. In order to obtain a positive logic output circuit formation, since the waveform shaping circuit 152 is required for one of its output power supplies, it is placed to supply the higher side power supply voltage vDd2 and the lower side power supply voltage vs. s 2 is used to turn on and off the wires of the supply lines 160 and 161 of the pixel gate. The wires are placed parallel to the pixel signal wires because 'for example' is parallel to the signal lines 161 ( In the case where 116-1 to 116-n) are placed in the vicinity of the signal lines, the decrease in the aperture ratio of the liquid crystal can be minimized. In addition, in the case where the bus lines for the supply voltages 160 and 128894.doc -48-200912877 16 for the voltages VDD2 and VSS2 present a lower impedance are connected to the effective pixel region section 110, The voltage drop of the power supply line in the horizontal direction is minimized. Therefore, variations in the voltages to be applied and the low voltages to be output from the wave forming circuit 15 2 in the horizontal direction of the effective pixels can also be minimized. When the enable signal ENB is input to a NAND circuit 11 configured by the CM〇s, which forms the waveform shaping circuit 152, a CM〇S configuration circuit 11 rises to the edge of the enable signal or the clock ENB or A falling edge begins its operation. If a supply line for the enable signal ENB is wired in the vertical direction of the display device and becomes operative, a certain delay or waveform distortion of the enable signal ENB occurs in the vertical direction. , but the enable signal ENB has the same history of the same parasitic capacitance. Therefore, the delay becomes fixed. Therefore, one of the signals transmitted along one of the gate lines arranged in the horizontal direction exhibits a delay waveform of one of the clocks of X s. This produces a selection apostrophe without the need for a gate select waveform that is scanned vertically at a high speed without focusing on the horizontal direction. Further, similarly, in the fourteenth embodiment, it is used for the waveform shaping circuit 152 and the waveform shaping circuits! The supply voltages 160 and 161 of the voltages VDD2 and VSS2 supplied by 52 are preferably arranged in the same coordinates in the horizontal direction, which is similar to that in the first and eighth embodiments. The reason is that since the coordinates of the waveform shaping circuit 152 in the horizontal direction 128894.doc -49 - 200912877 are fixed, the gate pulse waveform is not affected by the delay. The configuration of another portion of the fourteenth embodiment is similar to the configuration of the first specific embodiment, and effects similar to those achieved by the first embodiment described above can be achieved. In addition, the delay can be kept fixed with a high degree of accuracy. &lt;Fifteenth Embodiment&gt; Figs. 22A, 22B, and 22C respectively show an example of one configuration of a liquid crystal display device and a gate pulse waveform according to a fifteenth embodiment of the present invention. example. Referring to FIG. 22A, the liquid crystal display device 100N according to the fifteenth embodiment is similar to the liquid crystal device 100M' according to the fourteenth embodiment described above, but differs in the arrangement position of the waveform shaping circuits 152. . Specifically, in the liquid crystal device 1 〇〇M of the above-described tenth embodiment, the supply lines 160 and 161 for the voltages VDD2 and VSS2 to be supplied to the waveform shaping circuits 152 are used for the enable signal enb. The supply line 163 and the waveform shaping circuits 152 are arranged at the same coordinates in the horizontal direction. In contrast, in the liquid crystal display device i 〇〇 N of the fifteenth embodiment, the supply lines 160 and 161 for the voltages VDD2 and VSS2 to be supplied to the waveform shaping circuits 152 are used for the enable signal ENB. The supply line 163 and the waveform shaping circuits 152 are not disposed at the same coordinates in the horizontal direction, but are arranged to be displaced relative to one another in a row relationship with 128894.doc • 50- 200912877 and the gate lines and The wires of the equal signal lines are in a corresponding relationship β. In the example shown in FIG. 22A, the waveform shaping circuit is disposed near the position where the signal line 116-3 intersects with the gate line u 5_丨. The wave forming circuit 152-12 is disposed near the intersection of the signal line ι16_4 and the gate line 115-2. The waveform shaping circuit 152_13 is disposed near the intersection of the signal line 116-5 and one of the gate lines u5_3. The waveform shaping circuit 152-14(m) is disposed near the intersection of the signal line 116_6 and one of the gate lines 11 5-m. At the same time, the waveform shaping circuit 152-21 is disposed near the intersection of the signal line 116-7 and the gate line 115-1. The waveform shaping circuit 152_22 is disposed adjacent to a position of the signal line 116-8 and the gate line 115-2. The wave opening &gt; forming circuit 1 52-23 is disposed near the intersection of the signal line 116-9 and one of the gate lines 115-3. The waveform shaping circuit 152_24(m) is disposed near the intersection of the 彳§ line 11 6-1 〇 and the gate line 11 5_4m. In this example, the local one-sidedness is eliminated from the wires of the supply lines 160 and 161 for the power supply voltage VDD2 and the reference voltage VSS2, such as in the case where the coordinates of the waveform shaping circuit 1 52 in the horizontal direction are not fixed. . Therefore, the uniformity of the transmission factor of the pixels under the influence of the wiring layout of the supply lines 160 and 161 for the voltages VDD2 and VSS2 is ensured. In this example, the brightness distribution of the display device is fixed. The configuration of another part of the fifteenth embodiment is similar to the configuration of the fourteenth embodiment, and can also be implemented with the above first and tenth 128894.doc • 51 · 200912877 The effect achieved by the example is similar. &lt;Sixteenth embodiment&gt; According to one of the sixteenth embodiment of the present invention and one of the gate patterns 23A, 23B and 23C, respectively, the waveform of the liquid crystal display device according to the embodiment is shown example. Meanwhile, Figs. 24A to 24J illustrate the operation of the liquid crystal display device of the specific embodiment in accordance with the present invention. Specifically, @24A commentary - vertical start signal or start pulse vst (Vst); Figure 24B illustrates a vertical clock VCK for a vertical drive circuit; and Figure 24 (: explanation for - waveform shaping circuit - enabled Signal ENB. Figure 24D illustrates a gate pulse Gpi that is immediately output as one of the first columns of the vertical drive circuit 120; Figure 24E illustrates a gate pulse GP2 as a target for the vertical drive circuit 12 One of the second columns is output immediately; and Fig. 24F illustrates a gate pulse Gp3 which is immediately output as one of the third columns for the vertical drive circuit 120. Figure 24G illustrates the first of the vertical drive circuits 丨2〇 The gate pulse GP1 of one of the distal portions of the column; FIG. 24H illustrates a gate pulse GP2 at a distal end portion of the second column of the vertical drive circuit 12A; and FIG. 241 illustrates the vertical drive circuit 12 A gate pulse GP3 of the remote portion of the third column. In addition, the time diagram Vgatej+L of Fig. 24D illustrates that one of the first columns immediately outputs a pulse; the time chart of Fig. 24E Vgate_2_L illustrates one of the second columns immediately Output pulse; and Figure 24F The time diagram Vgate_3_L illustrates the third column of 128894.doc •52- 200912877 an immediate output pulse. The other 24G time illustrates one of the first column of the far-end pulse; the detailed time chart, dR explain the second column A far-end pulse; and the time diagram of Figure 241, Vgate, turns to one of the third column of the far-end pulse. Figure 25 illustrates the vertical start signal or the start pulse, and Figure 25B illustrates a vertical drive. The vertical clock vck of the circuit. Figure 25C illustrates the enable L25D representation for a waveform shaping circuit in the first stage as the gate pulse GP1 for the immediate output of the first column of the vertical drive circuit 12A; The interrogation pulse Gp at the distal end portion of the first column of the vertical drive circuit 120 is illustrated. Fig. 25F illustrates the activation apostrophe ENB at the intermediate stage for the waveform shaping circuit, and FIG. 25G is illustrated as a One of the vertical driving circuits 12 is immediately outputting one of the gate pulses GpM; and FIG. 25H illustrates the gate pulse GPM at the distal end of the vertical driving circuit 12 in the middle column. At the most The level of the enable signal ENB for a waveform shaping circuit, FIG. 25J illustrates a gate pulse GPF that is immediately output as one of the last columns of the vertical drive circuit ;2〇; and FIG. 25K illustrates the vertical in the last column. The gate pulse GPF at the distal end portion of one of the driving circuits 120. In addition, the time chart Vgatej-L of Fig. 25D states that one of the first columns immediately outputs a pulse, and the time chart vgate_i_r of Fig. 25E illustrates the first column. One of the far-end pulses. 128894.doc -53- 200912877 The time diagram of Figure 25G, Vgate_M_L, illustrates that one of the middle columns immediately outputs a pulse ' while the time chart vgate_M_R of Figure 25H illustrates one of the far-end pulses of the middle column. The time diagram Vgate_F_L of Fig. 25J illustrates that one of the last columns immediately outputs a pulse&apos; and the time chart Vgate_F_R of Fig. 25K illustrates one of the far-end pulses of the last column. f

Referring to FIG. 23A, the configuration of the liquid crystal display device 1000 according to the sixteenth embodiment is similar to the liquid crystal display devices 100M and 100N according to the fourteenth and fifteenth embodiments described above, but differs in that The position of the waveform shaping circuit 1 52 is arranged. Specifically, in the liquid crystal display devices 100M and 100N according to the fourteenth and fifteenth embodiments, the voltages VDD2 to be supplied to the waveform shaping circuits 152 and the waveform shaping circuits 152 and The supply lines 1 60 and 1 61 of VSS 2 are arranged at the same coordinates in the horizontal direction. Alternatively, the supply lines 16A and i6i for the voltages VDD2 and VSS2 to be applied to the waveform shaping circuit 152 and the waveform shaping circuit 52 are not arranged at the same coordinates. In contrast, in the liquid crystal display device according to the sixteenth embodiment, the waveform forming circuits 152 from the seventh to the 152 sides are arranged on the (four) gate lines and almost all of the signal lines. The closed-pole line near the position, or in other words t, is at the input portion of the pixel circuit lu for the gate pulse. For the sixteenth embodiment, the waveform of the gate pulse is formed as - as can be seen from Figs. 24A to 24J. Further, 128894.doc 200912877 In addition, although the waveform of the enable signal ENB is distorted by the parasitic capacitance or the like of the supply lines 163, since all the supply lines 163 with the (four) enable signal ENB in the horizontal direction have an equal The parasitic capacitance value, so the waveform distortion of the enable signal ENB is the same. Therefore, since the gate pulse emitted in the horizontal direction passes through the equal wave forming circuit 152, its waveform is not affected by the distortion and delay in the horizontal direction. In this way, since the waveform shaping circuit 152 is arranged in this way for each pixel circuit on the wires of the gate lines, it is possible to allow a plurality of pixel circuits (1) to exist in different waveforms. Any dispersion between the shaping circuits such that the waveform delay of a gate pulse does not occur therein. In other words, in the case where a plurality of material circuits exist between a waveform shaping circuit and another waveform shaping circuit, the unevenness of the parasitic capacitance is eliminated: 'and the uniform load of the pixel gates of the waveform shaping circuits is ensured. In the case of Taniguchi, there is no longer a delay in the condition of the gate electrode. The configuration of the other part of the tenth embodiment is similar to the configuration of the fourteenth and fifteenth embodiments, and can also be implemented by the above fourteenth and fifteenth embodiments. The effect achieved by the example is similar. &lt;Seventeenth Embodiment&gt; Fig. 26 shows a liquid example of a seventeenth embodiment of one of the configurations of the apparatus according to the present invention.

- Figure 26, according to this seventeenth embodiment, '-the acupoints are 不 文 文 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 类似于 类似于 类似于200912877 100M, but the difference is that it is also effective in one of the systems in which the image data is written to a panel. In addition, in the case where a time-division switch is used as shown in FIG. 26 to reduce the image frame of the panel, if the number of time-sharing switches is not sufficiently satisfied, the horizontal selection period is not satisfied. The inner &lt;one electrical feature and one image feature need to apply the invention. In Fig. 26, signals SV1 to SV4 from the ## drivers #131 to 134 are transmitted to the signal lines 1 16 (116-1 to 116-12) through a selector having a plurality of transmission gates TMQ. Controlling the conduction state of the transmission idle (analog switch) TMG by the selection signal 81 and its inverted signal XS1, the selection signal and its inverted signal XS2, the selection signal 83 and its inverted signal XS3... The signals are supplied externally and have complementary levels to each other. In the case of private use of the above-mentioned configuration, the active matrix display device of the high resolution (UXGA) and the return velocity frame rate type can adopt the -selector time-division driving system, and (4) reduce the connection terminal. The number and the mechanical reliability of the connection. The configuration of another portion of the fourteenth embodiment is similar to the configuration of the fifteenth embodiment, and effects similar to those achieved by the fourteenth embodiment described above can be achieved. &lt;Eighteenth Embodiment&gt; Fig. 27 shows an example of a configuration of a liquid crystal display device according to an eighteenth embodiment of the present invention. Referring to FIG. 27, the liquid crystal display device 128894.doc* 56 - 200912877 according to the eighteenth embodiment is configured similarly to the liquid device (10) N according to the above fifteenth embodiment, but is different therefrom. The reason is that it is also effective in the system that writes the person-to-panel in the time-sharing manner, and 'uses the time-sharing switch as shown in Figure 27 to: reduce the panel In the case of an image frame, the number of time divisions of the time-sharing switch does not sufficiently satisfy one of the electrical characteristics and an image sign in a horizontal selection period. ,

Referring to Figure 27, signals SVi through SV4 from the signal drivers 131 through 134 are passed through the selectors SEL having the plurality of transmission gates tmg to the signal lines 116 (116-1 through 116-12). Controlling the conduction state of the transmission gates (analog switches) TMG by the selection signal 81 and its inverted signal XS1, the selection signal s2 and its inverted signal XS2, the selection signal S3 and its inverted signal XS3... These signals are supplied externally and have complementary levels to each other. In the case of adopting such a configuration as described above, one of the high-resolution (UXGA) and south speed frame rate types of active matrix display devices can use a selector time-division driving system, which reduces connection terminals. The number and the mechanical reliability of the connection. The configuration of another part of the eighteenth embodiment is similar to the configuration of the fifteenth embodiment, and can also be implemented by the fourteenth and fifteenth embodiments. The effect is similar. &lt;Nineteenth Detailed Embodiment&gt; Fig. 28 shows an example of a configuration of a liquid crystal display device according to a nineteenth embodiment of the present invention. 128894.doc • 57- 200912877 Referring to FIG. 2, the configuration of the liquid crystal display device i〇〇R according to the nineteenth embodiment is similar to the liquid crystal display device 1000 according to the sixteenth embodiment described above, but different therefrom The point is that it is also effectively configured in a system in which image data is written to a panel in a time sharing manner. Specifically, in addition, when the time-sharing switch is used as shown in FIG. 28 to reduce the image frame of the panel, if the number of time-sharing switches is not sufficiently satisfied within a horizontal selection period An electrical feature and an image feature require the application of the present invention. Referring to Fig. 28, signals svi to sv4 from the far-end signal drivers 131 to 134 are transmitted to the chirp signal lines 116 (116-1 to 116-12) through the selector SEL having the plurality of transmission gates TMG. The transmission gates (analog switches) TMG are controlled by the selection signal s 1 and its inverted signal xs 丨, the selection signal S2 and its inverted k-number XS2, the selection signal S3 and its inverted signal XS3 ... In the conductive state, the signals are supplied from the outside and have mutually complementary levels. In the case of adopting such a configuration as described above, one of the high-resolution (UXGA) and high-speed frame rate type active matrix display devices can employ a selector time-division driving system, which reduces the number of connection terminals And improve the mechanical reliability of the connection. The configuration of another part of the nineteenth embodiment is similar to the configuration of the sixteenth embodiment, and can also be implemented similarly to the effects achieved by the fourteenth to sixteenth embodiments described above. The effect. &lt;Twenth Detailed Embodiment&gt; Figs. 29A, 29B and 29C respectively show an example of a configuration of a liquid crystal display device according to an embodiment of the twentieth specific 128894.doc-58-200912877 of the present invention. An example of a pulse waveform. Referring first to Fig. 29A, the configuration of the liquid crystal display device 100S according to the twentieth embodiment is similar to the liquid crystal device 1 according to the sixteenth embodiment described above, but with the following differences. Specifically, in the liquid crystal display device 100S according to the twentieth embodiment, the supply line 丨6〇 for the power supply voltage 〇〇2 and the supply line 161 for ρ the power supply voltage VSS2 are also The wiring is routed between all of the signal 'slots 丨 16016·1 to 116_m) and all of the gate lines 115 (115-1 to 115_m). ^ With the above configuration, the Bayer T prevents an undesired voltage from intruding into the adjacent #素电路1 1 1 '. This occurs between the interrogating line and the signal line. Therefore, good image quality can be obtained. The configuration of another part of the twentieth embodiment is similar to the configuration of the tenth embodiment, and can also be implemented similarly to the effects achieved by the fourteenth and tenth embodiments. The effect. It should be noted that although one of the wiring schemes of the voltage supply line in the twentieth embodiment is not shown in FIG. 29A, the group sorrow of the twentieth embodiment may also be applied to other fourteenth and tenth Five and seventeenth to nineteenth embodiments. Moreover, in this example, it is possible to prevent an undesired voltage from intruding into an adjacent pixel circuit 111, and an effect of obtaining a good image quality can be achieved. The configuration of one of the waveform shaping circuits 15A, i5i, and 152 on an equivalent circuit in the first to the twentieth embodiments of the present invention, 128894.doc • 59·200912877, a configuration, a power supply Supply line plan. The following describes the arrangement positions of one of the waveform shaping circuits 15G, 151 and 152 on the device. In this embodiment, in the transmissive liquid crystal display device, the waveform forming circuits 15A, 151, and 152 are substantially arranged to be slightly lower than a black color filter mask. Meanwhile, in the reflective type or the transmissive and reflective type liquid crystal display device, the waveform forming circuits 150, 151 and 152 are arranged in a reflective region. 30A and 30B show the transmission type one liquid crystal display device. Referring to Figures 30A and 30B, the transmissive liquid crystal display device 3 shown includes a bottom gate type TFT such as described above with reference to Figure 3, and is configured such that a liquid crystal layer 330 is sandwiched between a TFT substrate 3 10 Between an opposing substrate 32〇. As shown in FIG. 30A, the TFT substrate 310 includes a glass substrate 311, a planarization film 312 formed on the glass substrate 311, a transparent electrode 313 formed on the planarization film 312, and a transparent electrode 313 formed thereon. One of the upper alignment films 314. The opposite substrate 320 includes a glass substrate 31, a light blocking region 322 formed on the glass substrate 321, and an alignment film 323 formed on the light blocking region 322. It should be noted that in Fig. 30B, the same elements as those shown in Fig. 3 are denoted by the same reference numerals. In addition, since the structure of the TFT itself is explained above, the overlapping description thereof is omitted here to avoid redundancy. 128894.doc -60- 200912877 Fig. 31 shows a first example of one of the pixel circuits of the transmissive liquid crystal display device in which the wave forming circuit described above with reference to Figs. 5A to 5C is employed. As shown in Fig. 31, the components ρτι, pT2, NT 1 and ΝΤ2 of the waveform shaping circuit 150 and the wiring system are arranged slightly lower than the light blocking region 322 formed by a black color filter mask. In this $IL example, a gate pulse GP, which is input with a positive logic, is positively applied to the gate of the TFT 112 of the pixel circuit 1 i i after it has passed through the buffers BF 1 and BF2. Since the waveform shaping circuit 150 is formed of a polycrystalline germanium TFT (thin film transistor), light from the backlight is blocked by the waveform shaping circuit 15 and this constitutes one of the reasons for the decrease in the transmission factor of the pixel. Therefore, a certain luminance dispersion may occur in the case of a specific pixel including a waveform shaping circuit 150 formed of a TFT (Thin Film Transistor) and a power supply for the voltage of the waveform shaping circuit 15A and VSS2. Lines 160 and 1 61. a light blocking region 322 formed by a black color patch mask (which is used to reduce the dispersion of luminance between the pixels) is placed on the circuit to thereby fix the brightness by fixing the transmission factor dispersion. Fig. 32 shows a second example of one of the pixel circuits of the transmissive liquid crystal display device in which the wave forming 幵y circuit explained above with reference to Figs. 5A to 5C is employed. The second example is similar to the first example shown in FIG. 31, but differs in that it is used by the buffer BF1 to input a threshold pulse of one of the gate pulses 128894.doc -61 - 200912877 GP. In turn, the gate pulse 〇15 is applied to the gate of the TFT 112 of the pixel circuit 111 in a positive logic. Then, the gate pulse GP is outputted in negative logic through the buffer bf2. Therefore, the pixel circuit 111 is positioned between the output of the buffer BF1 and the input of the buffer BF2. Figure 33 shows a third example 0 in which the pixel circuit of one of the transmissive liquid crystal display devices of the waveform shaping circuit described above is employed (the third example is similar to the first one shown in Fig. 31) An example, but differs in that it is configured to prevent an undesirable voltage from intruding from the signal line 116 and a gate line 115. In particular, in this third example, the signal line 丨丨6 And the gate line 115 is sandwiched between the supply line 16A for the power supply voltage VDD2 and the supply line 161 for the reference voltage VSS2 to prevent an undesired voltage from the signal line 116 and the gate The epipolar line 115 intrudes. Fig. 34 shows a fourth example of one of the pixel circuits of the transmissive liquid crystal display device in which the waveform shaping circuit described above with reference to Figs. 5A to 5C is employed. This fourth example is similar to that shown in Fig. 32. The second example, but differs in that it is configured to prevent an undesirable voltage from intruding from a signal line 116 and a gate line H5. In particular, in this third example, the signal line 116 And the gate line 11 5 Between the supply line 160 for the power supply voltage VDD2 and the supply line 161 for the reference voltage VSS2, in order to prevent a voltage of 128894.doc-62-200912877 from being undesired from the signal line 116 and the gate Line 115 intrudes. A,, ', and the different types of transmissive and reflective liquid crystal display devices - pixels: open and ΓΒ display using the above referenced figure from 5 to: (the transmission and reflection type liquid crystal of the waveform forming circuit described) A first example of a pixel of a display device. First, the transmissive and reflective liquid crystal display device 4 shown in FIG. 35A includes a transparent insulating substrate 40 and a thin film transistor (tft) 4 〇 2 : pixel a region 403 or the like (which is formed on the transparent insulating substrate 4?). The transmissive and reflective liquid crystal display device 4 further includes a relative relationship with the transparent insulating substrate 40, the TFT 402, and the pixel region 4? The transparent and reflective liquid crystal display device 400 further includes a protective layer 4〇5, a color filter 4〇5&, an opposite electrode 406 and a liquid crystal layer 407 (which Formed on the transparent insulating insulating substrate 404. The liquid crystal layer 407 is sandwiched between the pixel region 4〇3 and the opposite electrode 406. Such pixel regions 403 are arranged in a matrix for use in a gate line 11 5 for supplying a gate pulse GP and a signal line 116 for supplying a display signal to the TFTs 4 〇 2 are provided in a perpendicular relationship with each other to be provided around the individual pixel regions 403, thereby The pixel segment is formed. Further, a holding capacitor wiring (hereinafter referred to as a CS line) formed of a metal wire is provided on the transparent insulating substrate 401 and the TFT 402 side so as to be parallel to the gate lines 11 5 and extended. The CS lines are matched to the pixel electrodes to form a holding capacitor CS and are connected to the opposite electrodes 128894.doc -63 - 200912877 406 °. In addition, one of the reflective displays is intended for use in a reflective area. A transmission area of one of the displays is provided in each of the pixel areas 4〇3. The transparent insulating substrate 401 is formed of a transparent material (e.g., glass). The TFT 402, a diffusion layer 408, and a planarization layer 4 are formed on the transparent insulating substrate 401. Specifically, the diffusion layer 4 is formed on the TFT 402 with an insulating film interposed therebetween, and the planarization layer 409 is formed on the diffusion layer 408. Further, a transparent electrode 41 and a reflective electrode 411 are formed on the planarization layer 4〇9. The reflective electrode 411 forms a pixel region 403 having the above-described reflective region A and transmissive region b. Referring now to Fig. 35B, the components ρτι, PT2, NT 1 and NT2 of the waveform shaping circuit 15 are arranged in the reflection area a with the wiring system. Since the waveform shaping circuit 150 is formed of a polysilicon TFT (thin film transistor) as described above, light from the backlight is blocked by the waveform shaping circuit 15 and this constitutes a cause of a decrease in the transmission factor of the pixel. . In this regard, a method may be used in which there is an object that does not pass light of the backlight from the reflective liquid crystal, the waveform shaping circuit 150 is advantageously arranged to be slightly lower than the reflection of the reflective liquid crystal. region. With the configuration of the waveform shaping circuit 150, the degree of freedom in forming the TFT layout of the CMOS for the wave forming circuit 150 is significantly increased as compared with the degree of freedom of the transmission type. Therefore, since the width of the power supply line (for example, the power supply lines for the power supply voltage VDD2 and the reference voltage VSS2) can be increased, the delay of one of the CMOS outputs due to the power supply line resistance becomes less May occur. 128894.doc • 64 - 200912877 FIG. 3A shows a pixel circuit of a reflective liquid crystal display device and FIG. 35B shows a pixel circuit of a reflective liquid crystal display device in which the waveform forming circuit described above with reference to FIGS. 5 to 8 is used. In a first example, the device structure of the pixel circuit of the reflective liquid crystal display device is similar to that of the transmissive and reflective liquid crystal display device, except that it does not have the transmissive region B. Therefore, overlapping descriptions of the device structure are omitted here to avoid redundancy. Moreover, in this example, the components PT1, PT2, NT1, and NT2 of the waveform shaping circuit 1S are arranged in the reflection area a as shown in Fig. 36B. Figure 37 shows a second example in which one of the pixel circuits of one of the transmissive and reflective liquid crystal display devices of the waveform shaping circuit described above is employed with reference to Figures 5 to 5 (this illustrated example is similar to Figures 35A and 35B). The first example is shown, but differs in that it is configured to prevent an undesirable voltage from intruding from the signal line 116 and the gate line 115. In particular, in this example, the signal line 116 And the gate line 115 is sandwiched between the supply line 160 for the power supply voltage VDD2 and the supply line 161 for the reference voltage VSS2 to prevent an undesired voltage from the signal line 11 and the gate Figure 38 shows a pixel circuit in which one of the reflective liquid crystal display devices of the waveform shaping circuit described above is used as the second example 0. The second example is similar to the figure. The first example shown at 36, but different therefrom, 128894.doc-65-200912877 is configured to prevent an undesirable voltage from intruding from a signal line 116 and a gate line 11 5 . 'In this second fan In the example, the signal line 161 and the gate line 115 are sandwiched between the supply line 160 for the power supply voltage VDD2 and the supply line 161 for the reference voltage VSS2 to prevent an undesired voltage. Invading from the signal line 116 and the gate line 115. Fig. 39 shows a first example of one of the pixel circuits of the transmissive liquid crystal display device in which the waveform shaping circuit described above with reference to Figs. πA to 13C is employed. It is shown that the components ρτΐ, PT2, PT3, NT1, NT2 and NT3 of the waveform shaping circuit 151 and the wiring system are arranged slightly lower than the light blocking region 322 formed by a black color filter mask. In this example, One of the positive logic inputs, the gate pulse Gp, is positively applied to the gate of the TFT 112 of the pixel circuit 111 after it passes through the buffers BF 3 and BF 2. Since the waveform shaping circuit 1 5 1 is composed of one A polycrystalline germanium TFT (thin film transistor) is formed so that light from the backlight is blocked by the waveform shaping circuit, and this constitutes a decrease in the transmission factor of the pixel. Therefore, 'may occur in the case of a specific pixel. One brightness Dispersing, the characteristic pixel includes a waveform shaping circuit 151 formed of a TFT (Thin Film Transistor) and power supply lines 160 and 160 for voltages vdD2 and VSS2 of the waveform shaping circuit 151. Therefore, a black color filter is used. A light blocking region 322 formed by the mask (which is used to reduce the redundancy dispersion between the pixels) is placed on the circuit to fix the brightness dispersion by fixing the transmission factor by 128894.doc -66-200912877 Fig. 40 shows a second example of one of the pixel circuits in which the transmissive liquid crystal display of the waveform shaping circuit described above with reference to the drawings is illustrated. This second example is similar to the first (four) shown in FIG. 39, but differs in that it is inverted by the buffer BF3 with the level of one of the gate pulses GP of the negative logic input. The gate pulse is applied to the idle electrode of the TFT 112 of the pixel circuit (1). Then, through the buffer leg (the gate pulse GP is outputted with a negative logic. Therefore, the pixel circuit 111 is positioned between the output of the buffer BF3 and the input of the buffer BF11. Figure 41 shows the above A third example of one of the pixel circuits of the transmissive liquid crystal display device of the waveform shaping circuit illustrated in FIGS. 13A to 13C. This third example is similar to the first example shown in FIG. 39, but differs in that it is The configuration is configured to prevent an undesired voltage from intruding from a signal line 116 and a gate line 115. In particular, in the third example, the signal line 116 and the inter-pole line 115 are clipped for use in the A supply line ι60 of the power supply voltage VDD2 is interposed between the supply line 161 for the reference voltage VSS2 to prevent an undesired voltage from intruding from the signal line 116 and the gate line 115. Fig. 42 shows the above reference drawing A fourth example of one of the pixel circuits of the transmissive liquid crystal display device of the waveform shaping circuit illustrated in 13A to 13C. 128894.doc -67- 200912877 This fourth example is similar to the second example shown in FIG. The difference is that it is configured to prevent an undesirable voltage from intruding from a signal line 116 and a gate line 115. In particular, in this fourth example, the signal line 116 and the gate line 115 is sandwiched between the supply line 160 for the power supply voltage VDD2 and the supply line 161 for the reference voltage VSS2 to prevent an undesired voltage from intruding from the signal line 11 6 and the gate line 11 5 Figure 43 shows a first example of one of the pixel circuits of the transmissive and reflective liquid crystal display device in which the waveform shaping circuit described above with reference to Figures 13A to 13C is employed. Referring now to Figure 43, the component PT1 of the waveform shaping circuit 151 , PT2, PT3, NT1, NT2, and NT3 are arranged in the reflective region a. Since the waveform shaping circuit 115 is formed of a polysilicon TFT (thin film transistor) as described above, light from the backlight is affected by The waveform shaping circuit 151 resists, and this constitutes one of the reasons for the decrease in the transmission factor of the pixel. In this respect, a method can be used in which there is a light that is not like the reflective liquid crystal. In the object passing therethrough, the waveform shaping circuit 115 is advantageously arranged to be slightly lower than the reflective area of the reflective liquid crystal. The configuration of the waveform shaping circuit 115 is used to form the waveform shaping circuit. The degree of freedom of the CMOS TFT layout of 151 is significantly increased as compared with the degree of freedom of the transmissive type. Therefore, 'the power supply line can be increased (for example, the power supply for the power supply voltage VDD2 and the reference voltage VSS2) The width of the line), therefore due to the power supply line resistance - the delay of the CM 〇 S output becomes less likely to occur. 128894.doc -68- 200912877 Fig. 44 shows a first example of one of the pixel circuits of the reflective liquid crystal display device in which the waveform shaping circuit described above with reference to Figs. 13a to 13C is employed. Referring to Fig. 44', also in the illustrated configuration, the components PT1, PT2, PT3, NT1 'NT2 and NT3 of the waveform shaping circuit 1 and the wiring system are arranged in the reflection area A. Fig. 45 shows a second example of a pixel circuit of a transmissive and reflective liquid crystal display device in which the waveform shaping circuit described above with reference to Figs. 13A to 13C is employed. This second example is similar to the first example shown in Figure 43, but differs in that it is configured to prevent an undesirable voltage from intruding from the signal line 116 and the gate line 115. Specifically, in this example, the signal line 116 and the gate line 115 are sandwiched between the supply line 160 for the power supply voltage VDD2 and the supply line 161 for the reference voltage VSS2 to prevent one. Unwanted voltages intrude from the signal line 116 and the gate line 1 i 5 . Fig. 46 shows a second example of one of the pixel circuits of the reflective liquid crystal display device in which the waveform forming circuit explained above with reference to Figs. 13a to nc is employed. This second example is similar to the first example shown in Figure 44, but differs in that it is configured to prevent an undesirable voltage from intruding from a signal line 116 and a gate line 115. In particular, in this example: the signal line 丨16 and the idle line Π5 are cool in the supply line 16 for the power supply voltage 乂〇〇2 and are used for 128894.doc • 69 - 200912877 The reference voltage VSS2 is between supply lines 161 to prevent an undesirable voltage from intruding from the signal line 116 and the gate line 115. Fig. 47 shows a first example of one of the pixel circuits of the transmissive liquid crystal display device in which the waveform shaping circuit explained above with reference to Figs. 21A to 21C is employed. As shown in Fig. 47, the components PT1, PT2, PT3, NT1, NT2, and NT3 of the waveform shaping circuit 152 and the wiring system are arranged to be slightly lower than the light blocking region 322 formed by a black enamel mask. In this example, a gate pulse Gp, which is input with a positive logic, is positively applied to the gate of the TFT 112 of the pixel circuit m after it has passed through the dedicated buffer states BF1 and BF2. Since the waveform shaping circuit 1 52 is formed of a polycrystalline TFT (thin film transistor), light from the backlight is blocked by the waveform shaping circuit 1 52, and this causes one of the decrease in the transmission factor of the pixel. Therefore, a luminance dispersion may occur in the case of a specific pixel, and the specific pixel includes a waveform shaping circuit 152 formed of a TFT (Thin Film Transistor) and a power supply of voltages ν 2 and VSS 2 for the waveform shaping circuit 152. Lines 160 and 160. Therefore, a light blocking region 322 formed by a black color filter mask (which is used to reduce luminance dispersion between the pixels) is placed on the circuit to thereby fix the transmission factor to suppress the luminance dispersion. . Fig. 48 shows a second example of one of the pixel circuits of the transmissive liquid crystal display device in which the waveform forming circuit explained above with reference to Figs. 21a to 21c is employed. 128894.doc •70·200912877 The second example is similar to the first example shown in Figure 47, but is different from that by the NAND circuit 11 to input a gate pulse GP with a negative logic. The quasi-inversion causes the gate pulse gP to be applied to the gate of the TFT 112 of the pixel circuit 111 in positive logic. Then, the gate pulse gp is outputted in negative logic through the buffer BF11. Therefore, the pixel circuit 111 is positioned between the output of the NAND circuit 11 and the input of the buffer BF11. Fig. 49 shows a third example of one of the pixel circuits of the transmissive liquid crystal display device in which the waveform forming circuit explained above with reference to Figs. 2 to 2 1C is employed. This second example is similar to the first example shown in Figure 47, but differs in that it is configured to prevent an undesirable voltage from intruding from a signal line 116 and a gate line 1丨5. Specifically, in this third example, the signal line 丨丨6 and the gate line Π5 are sandwiched between the supply line 160 for the power supply voltage VDD2 and the supply line 161 for the reference voltage VSS2. In order to prevent an undesired voltage from intruding from the signal line 116 and the gate line π 5 . Fig. 50 shows a fourth example of one of the pixel circuits of the transmissive liquid crystal display device in which the waveform is turned on and the circuit described above with reference to Figs. 21a to 21C. This fourth example is similar to the second example shown in Figure 48, but differs in that it is configured to prevent undesired voltages from invading from a signal line 116 and a gate line 115. Specifically, in this fourth example, the signal line 116 and the gate line 128894.doc • 71 · 200912877 115 are clamped to the supply line 16〇 for the power supply voltage ¥〇1) 2 and used for The reference voltage VSS2 is between the supply lines 161 to prevent an undesired voltage from intruding from the signal line 116 and the gate line 丨丨5. Fig. 51 shows a first example of a pixel circuit of a transmissive and reflective liquid crystal display device in which the waveform shaping circuit explained above with reference to Figs. 21A to 21C is employed. Referring now to Fig. 51, the components pTu, ΡΤ12, ΡΤ13, ΝΤΙ1, ΝΤ12, and ΝΤ13 of the waveform shaping circuit 152 and the wiring system are disposed in the reflection (region Α. Since the waveform shaping circuit 152 is composed of a polysilicon TFT (thin film) The crystal is formed so that the light from the backlight is blocked by the waveform shaping circuit 152, and this constitutes one of the reasons for the decrease in the transmission factor of the pixel. In this respect, a method can be used, in which a liquid crystal is not reflected. The object forming the light from which the backlight passes, the waveform shaping circuit 152 being advantageously arranged slightly below the reflective area of the reflective liquid crystal. The configuration of the waveform shaping circuit 152 is used to form The waves

The degree of freedom of the TFT layout of the CMOS forming circuit 152 is significantly increased as compared with the degree of freedom of the transmission type. Therefore, since the width of the power supply line (for example, the power supply lines for the power supply voltage and the reference voltage VSS2) can be increased, the delay of one of the CMOS outputs due to the power supply line resistance becomes less likely occur. Fig. 52 shows a first example of one of the pixel circuits of the reflective liquid crystal display device in which the waveform forming circuit explained above with reference to Figs. 21A to 21C is employed. 128894.d〇c - 72- 200912877 Referring to FIG. 52, also in the illustrated configuration, the components PT11, PT12, PT13, NT11, NT12, and NT13 of the waveform shaping circuit 152 and the wiring system are disposed in the reflective area A. Fig. 53 shows a second example of a pixel circuit of a transmissive and reflective liquid crystal display device in which the waveform shaping circuit explained above with reference to Figs. 21A to 21C is employed. This first example is similar to the first example shown in Figure 51 but differs in that it is configured to prevent an undesirable voltage from intruding from the signal line 116 and the gate line 115. Specifically, in this example, the signal line 11 6 and the gate line 丨丨 5 are sandwiched between the supply line 160 for the power supply voltage VDD2 and the supply line 161 for the reference voltage VSS2. In order to prevent an undesired voltage from intruding from the signal line 161 and the gate line 115. Fig. 54 shows a second example of one of the pixel circuits of the transmissive liquid crystal display device in which the waveform shaping circuit explained above with reference to Figs. 21a to 21C is employed. This second example is similar to the first example shown in Figure 52, but differs in that it is configured to prevent an undesirable voltage from intruding from a signal line 116 and a gate line 115. Specifically, in this second example, the signal line 丨丨6 and the gate line 115 are sandwiched between the supply line 160 for the power supply voltage vdD2 and the supply line 161 for the reference voltage VSS2. In order to prevent - an undesired voltage from entering from the signal line 11 6 and the gate line n 5 . The active matrix display device of 128894.doc • 73- 200912877 is used as an OA (Office ^, office automation) device (for example, personal computer and word processing for television reception) according to the active matrix liquid crystal display device of the above specific embodiment. Display device, etc.). The display device of the present invention can act on one of the display segments of any other electronic device (e.g., a portable television or PDA), and miniaturization and downsizing of devices for such electronic devices is progressing. In particular, the display device according to the present invention can be applied to such various electronic devices as shown by way of example in FIGS. A to 55 G. In particular, the display device can be applied to one of electronic devices in various fields. The display device, the Yanhai 4 electronic device will output the image signal to the Yanhai t sub-device or the image signal generated in the electronic device as ~ image, for example, a digital camera, a notebook A personal computer, a portable telephone, a video camera, etc. Next, a specific example of an electronic device to which the display device of the present invention is applied will be described. Fig. 55A shows an example of a television receiver to which the present invention is applied. Referring to Fig. 55A, The television receiver 500 includes an image display screen section 〇3 composed of a front panel 501, a glass enamel 502, etc. The display device according to the present invention can be used as the image display screen section 5〇3. Figures 55B and 55C show an example of a digital camera to which the present invention is applied. Referring to Figures 55B and 55C, the digital camera 51 includes an image pickup lens 511, a flash illumination section 512, and a display. Section 513, a control switch 514, etc. A display device in accordance with the present invention can be used as the display section 513. Figure 55D shows an example of a video camera to which the present invention is applied. Referring to Figure I28894.doc -74.200912877 55D, The video camera 520 includes: a main body section 52 ι ; a lens 522 is provided on the front side of the main body section 521 for picking up an image of an image pickup object; a start/stop switch (2) Used to start or stop image pickup; display section 524; etc. A display device according to the present invention can be used as the display section 524. Figures 55E and 55F show a portable terminal to which the present invention is applied. An example of a device. Referring to Figures 55E and 55F, the portable terminal device 53A includes an upper side housing 53 1 connecting section 533,

a lower side housing 532, a display section 534, a sub display section, an image light 536, a camera 537, and the like in the form of a hinge can be used as the display section 534 according to the present invention. Or the sub display section 53 5 . Figure 55G shows an example of Yinglin's invention of a notebook computer. Referring to Fig. 55G, the notebook type personal computer 54 includes a main body 541, a keyboard 542 for operating to input a human-character or the like, a display portion 543 for displaying an image, and the like. A display device according to the present invention can be used as the display section 543. It should be noted that in the above specific embodiments, the present invention is applied to the liquid crystal display device of the active matrix type. However, the present invention is not limited thereto, and can be equally applied to other active matrix type display devices such as an electroluminescence (EL) display device in which a device is used as an electro-optic element per pixel. μ Those skilled in the art should understand that various modifications, combinations, sub-combinations and alterations may be made in accordance with design requirements and other factors as long as they are within the scope of the patent application or its equivalent. 128894.doc -75- 200912877 [Simple diagram of the diagram] Figure ΙΑ, 1B and 1C respectively show a circuit diagram and waveform of one of the ordinary liquid crystal display devices, and an example of I*, an example and a gate pulse waveform. 2A, 2B and 2C are respectively a circuit diagram and a waveform diagram showing an example of one configuration of a liquid crystal display device and an example of a dummy pulse waveform according to a first embodiment of the present invention;

Figure 3 is a schematic cross-sectional view showing one of the bottom gate structures tft; Figure 4 is a schematic cross-sectional view showing one of the top gate structures τρτ; Figures 5A, 5B and 5C are shown in 2A is a circuit diagram of an example of a waveform shaping circuit in the liquid crystal display device shown in FIG. 2A, wherein the waveform shaping circuit is formed by a CMOS buffer; FIGS. 6A, 6B and 6 (: shows the 仂 于 于. According to a second embodiment of the present invention, one of the examples of the liquid crystal display device, the Schain-_ _ ^ configuration, and the pattern of the gate pulse waveform; FIGS. 7A, 7B, and 7C are respectively... A circuit diagram and a waveform diagram of an example of a liquid crystal display device according to a third embodiment of the present invention, which is an example of a gate pulse waveform; FIG. 8 is a diagram showing The invention is a configuration of one of the liquid crystal display devices of the fourth embodiment - a circuit diagram of the example ceremony; FIG. 9, 1 and 1 respectively, a flaw - the fifth and sixth according to the present invention And the liquid crystal display of the seventh embodiment. One of the devices is configured An exemplary circuit 128894.doc * 76 - 200912877 FIG. 12A, 12B and 12C respectively show an example of one configuration of a liquid crystal display device and a gate pulse waveform according to an eighth embodiment of the present invention. FIG. 13A, FIG. 13B and FIG. 13C are diagrams showing a waveform shaping circuit of a liquid crystal display device shown in FIG. 12A, wherein the waveform shaping circuit is formed by a CMOS circuit; FIG. And MC respectively show a circuit diagram and a waveform diagram of an example of one configuration of a liquid crystal display device and an example of a gate pulse waveform according to a ninth embodiment of the present invention; FIGS. 15A, 15B and 15C are respectively An example of a configuration of a liquid crystal display device according to a tenth embodiment of the present invention and a circuit diagram and a waveform diagram of an example of a gate pulse waveform are shown; FIG. 1 is a diagram of a 6A to 16J system diagram. A timing chart showing the operation of the liquid crystal display device; FIGS. 1, 7, and 19 are respectively showing one of the configurations of the liquid crystal display device according to the eleventh to eleventh embodiments of the present invention. 20A, 20B, and 20C are respectively an example of a configuration of a liquid crystal display device according to a fourteenth embodiment of the present invention, and a circuit diagram and a waveform diagram of an example of a idle pulse waveform. 21A, 21B and 21C are circuit diagrams showing a waveform shaping circuit of a liquid crystal display device shown in FIG. 20A, wherein the waveform shaping circuit is formed by a timing of a NAND circuit including a CMOS configuration (: 〇8 circuit formation) 22A, 22B and 22C respectively show one of the configuration of one of the liquid crystal display devices of one of the fifteenth embodiment of the invention, i. A circuit diagram and a waveform diagram of an example of a pulse waveform; FIGS. 23A, 23B and 23C respectively show a group of liquid crystal display devices according to a tenth embodiment of the present invention, which can be used as a target. A circuit diagram and a waveform diagram of an example of a gate pulse waveform; FIGS. 24A to 241 are timing diagrams illustrating the operation of the liquid crystal display device shown in FIG. 23A; FIGS. 25A to 25B are diagrams showing FIG. Timing diagrams of different operations of the liquid crystal display device; FIGS. 26, 27 and 28 are circuit diagrams showing an example of a configuration of one of the liquid crystal display devices according to the seventeenth, tenth, and nineteenth embodiments of the present invention, respectively. 29A, 29B, and 29C are respectively a circuit diagram and a waveform diagram showing an example of one configuration of a liquid crystal display device and an example of a gate pulse waveform according to a twentieth embodiment of the present invention; And a cross-sectional view of a transmissive liquid crystal display device; and FIGS. 31, 32, 33 and 34 are plan views showing first, second, third and fourth examples of a pixel type circuit of a transmissive liquid crystal display device, The waveform forming circuit shown in FIG. 5 is used; FIG. 35A and FIG. 35B are respectively a cross-sectional view of the pixel circuit of the transmissive and reflective liquid crystal display device and one of the pixel circuits of the transmissive and reflective type. A plan view of the example in which the waveform shaping circuit shown in FIG. 5A is used; FIG. 3 6A and 3 6B are respectively a reflection and reflection type liquid crystal display device 128894.doc -78- 200912877: pixel The cross-section of the road shows the reflection type - one of the pixel circuits - the plan view of the first example - which uses the waveform shaping circuit shown in FIG. 5A; FIG. 37 shows the transmission and reflection type liquid crystal display device a plan view of a first yoke of one of the pixel circuits, wherein the waveform forming circuit shown in FIG. 5 is used; FIG. 38 is a plan view showing a first example of a pixel circuit of the reflective liquid crystal display device, wherein FIG. 5 is used. Figs. 39, 40, 41 and 42 are plan views showing first, second, third and fourth examples of a pixel circuit of a transmissive liquid crystal display device, wherein the waveform shown in Fig. 13 is used. FIG. 43 is a plan view showing a first example of one of the pixel circuits of the transmissive and reflective liquid crystal display device, wherein the waveform forming circuit shown in FIG. 3 is used; FIG. 44 is a view showing the transmissive liquid crystal display device. A plan view of a first example of a pixel circuit in which the waveform shaping circuit shown in FIG. 13 is employed; FIG. 45 shows one of the transmissive and reflective liquid crystal display devices. A plan view of a second example of a prime circuit in which the waveform shaping circuit shown in FIG. 13 is employed; FIG. 46 is a plan view showing a second example of one of the pixel circuits of the reflective liquid crystal display device, wherein FIG. 13 is used. The waveform forming circuit is shown; Figures 47, 48, 49 and 50 are plan views showing the first, second, third and fourth examples of the image of a transmissive liquid crystal display device, 128894.doc • 79·200912877, wherein A waveform forming circuit shown in FIG. 21 is used; FIG. 51 is a plan view showing an example of a pixel circuit of the transmissive and reflective liquid crystal display device, wherein the waveform is used to form a circuit; FIG. A plan view showing a first example of one of the pixel circuits of a 5 Hz reflective liquid crystal display device, wherein the waveform shaping circuit shown in FIG. 21 is used;

Figure 5 is a plan view showing a second example of one of the pixel circuits of the transmissive and reflective liquid crystal display device, wherein the waveform forming circuit shown in Figure 2A is used; Figure 54 is a view showing one of the reflective liquid crystal display devices. One of the pixel circuits is a plan view of a snake case in which the waveform shaping circuit shown in Fig. 21 is employed; Figs. 55A to 55G are diagrams showing a few examples of an electronic device to which the display device according to the present invention is applied. [Main component symbol description] 1 LCD device 2 Effective pixel section 3 4 5-1 to 5-m Vertical drive circuit (VDRV) Horizontal drive circuit (HDRV) Gate line 6-1 to 6-n Signal line 7 shared Line 128894.doc -80- 200912877 8-1 to 8-m Gate Buffer 11 NAND' Electric 1 Lou 21 Pixel Circuit 22 Thin Film Transistor TFT 23 Liquid Crystal Cell 24 Holding Capacitor 41 to 44 Signal Driver 100 Liquid Crystal Display Device 100A LCD Display device 100B liquid crystal display device 100C liquid crystal display device 100D liquid crystal display device 100E liquid crystal display device 100F liquid crystal display device 100G liquid crystal display device 100H liquid crystal display device 1001 liquid crystal display device 100J liquid crystal display device 100K liquid crystal display device 100L liquid crystal display device 100M liquid crystal display device 100N liquid crystal display device 1000 liquid crystal display device 100P liquid crystal display device 128894.doc - 81 - 200912877

100Q

100R

100S 110 111 112

112A

112B 113 114 115 115 (115-1 to 115-m) 116 (116-1 to 116-n) 117 120 130 131 to 134 131 to 134 140-1 to 140-m 150 150-1 to 150-m 150- 11 to 150-lm 150-21 to 150-2m 151 (151-11 to 151-lm liquid crystal display device liquid crystal display device liquid crystal display device effective pixel segment pixel circuit thin film transistor (TFT)

TFT

TFT liquid crystal cell holding area or storage capacitor gate line gate line signal line common line vertical drive circuit (VDRV) horizontal drive circuit (HDRV) signal driver signal driver gate buffer waveform shaping circuit gate line waveform shaping circuit waveform shaping circuit Waveform shaping circuit 128894.doc -82- 200912877

And 151-21 to 151-2m) 152 Waveform forming circuit 160 Supply line 161 Supply line 162 Supply line 163 Supply line 201 Transparent insulating substrate 202 Gate insulating film 203 Gate electrode 204 Semiconductor film 205 n+ type diffusion layer 206 n+ type diffusion layer 207 interlayer insulating film 208 interlayer insulating film 209a contact hole 209b contact hole 210 source electrode 211 drain electrode 221 transparent insulating substrate 222 semiconductor film 223 and 224 n+ type diffusion layer 225 gate insulating film 226 gate electrode 227 interlayer insulating film 128894. Doc -83 - 200912877 228a contact hole 229 source electrode 230 drain electrode 300 transmissive liquid crystal display device 310 TFT substrate 311 glass substrate 312 planarization film 313 transparent electrode 314 orientation film 320 opposite substrate 321 glass substrate 322 light blocking region 323 orientation Film 400 Transmissive and Reflective Liquid Crystal Display Device 401 Transparent Insulating Substrate 402 Thin Film Transistor (TFT) 403 Pixel Area 404 Transparent Insulating Substrate 405 Protective Layer 405a Diagonal Sheet 406 Counter Electrode 407 Liquid Crystal Layer 408 Diffusion Layer 409 Planarization Layer 128894.doc -84- 200912877 410 Electrode 411 Reflective electrode 500 TV receiver 501 Front panel 502 Glass filter 503 Image display screen section 510 Digital camera 511 Image pickup lens 512 Flash illumination section 513 Display section 514 Control switch 520 Video camera 521 Body section 522 Lens 523 Start/Stop Switch 524 Display Section 530 Portable Terminal Unit 53 1 Upper Side Housing 532 Lower Side Housing 533 is connected in one of the hinges. Section 534 is displayed in section 535. Segment 536 Image Light 537 Camera 128894.doc -85- 200912877 540 Notebook PC 541 Body 542 Keyboard 543 Display Section A Reflecting Area B Transmissive Area BF1 CMOS Buffer or Inverter BF2 CMOS Buffer or Inverter BF3 Timing CMOS Buffer BF11 CMOS Buffer or Inverter ENAB Enable Signal ND1 Node ND2 Node ND11 Node ND12 Node NT1 n-Channel MOS (NMOS) Transistor NT2 NMOS Transistor NT3 NMOS Transistor NT11 and NT12 NMOS Transistor NT13 NMOS Crystal PT1 p-channel MOS (PMOS) transistor PT2 PMOS transistor PT3 PMOS transistor PT11 and PT12 PMOS transistor 128894.doc -86- 200912877 PT13 PMOS transistor SI selection signal S2 selection signal S3 selection signal SEL selector SV1 to SV4 signal TMG transmission gate VST (Vst) vertical start signal XS1 inverted signal XS2 reverse Phase signal XS3 inverted signal 128894.doc -87-

Claims (1)

200912877 X. Patent Application Range: 1. A display device comprising: a circuit, through a switching element, the pixel circuit is a pixel segment comprising a plurality of pixel devices for writing pixel data to each pixel circuit Forming a matrix comprising a plurality of rows; a plurality of scan lines arranged corresponding to the rows of the inch of the animal path and configured to control the conduction of the switching elements; a plurality of signal lines corresponding to the lines of the pixel-seeking pixel circuit and configured to allow propagation of the pixel data therethrough; and output-scanning pulses to cause the pixel circuits to The switching elements become conductive to the scan lines, wherein the waveform shaping circuit is disposed in one of the scan lines of the scan lines and configured to propagate in the trace Wait for the waveform shaping of the pulse. For example, the ',' and 'eight' lines of the sliding item 1 are such that "the same coordinate is positioned in the extending direction of the wide-number line in the coordinate configuration of the matrix of the pixel circuits. - the mode: set = the middle of the corresponding scan lines of the scan lines. 3. The display device of claim 1 wherein the waveform shaping circuits are such that they are at the coordinates of the matrix of the pixel circuits In the extending direction of the line in the configuration, it is positioned in the middle of the wires of the corresponding scan lines of the scanning lines of the type of coordinates of the coordinates of the coordinates of the coordinates of the first and second lines. The circuit is disposed in the middle of the wires of the scanning line of J2S894.doc 200912877 in the manner of /, 疋 located at the wheel level of the pixel circuits. 5. The display device of claim 1, further comprising: a substrate having a light blocking region, the waveform shaping circuit being disposed in the light blocking region. The display device of claim 1, wherein the display device is one of a reflective type or a transmissive and reflective type liquid crystal a display device, wherein the wave forming circuit is disposed in a reflective region of the CMOS liquid crystal display device. 7. The display device as claimed in claim 1, further comprising a power supply line connected to the waveform shaping circuit And extending parallel to the signal lines. 8. The display device of claim 7, the φ 兮 band, the β 纠 & amp amp amp 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该线盥兮楚的w &amp;孔深兴 The #知描线one adjacent scanning line 9·The display device of claim 1 is dry An output signal is formed by - logic. For the input signal to it - 10. For the display device of the requester, it further includes a plurality of signal drivers, which are individually corresponding to: the sum, the plurality of selector switches, the corresponding signal lines of the signal lines The threshold, the number driver and the image data are supplied. Inter-' and configured for time-sharing selection 11. The display device of claim 1 controls the waveform shaping circuit to include: a step in which the operation can be resumed, and the display device is placed in 128894 .doc 200912877 One of the supply lines of the supply line is formed for the enable signal and parallel to the signal lines, the waveform shaping circuit forming an output signal with positive logic with respect to one of the input signals. 12. The display device of claim 11, wherein the waveform shaping circuit comprises a CMOS circuit, one of the CMOS configurations, responsive to the enable signal to control the NAND circuit to begin its operation. 13. A driving method for a display device, the display device comprising: a pixel segment comprising a plurality of pixel circuits, the pixel data being written to each pixel circuit through a switching element, the pixel circuits Arranging to form a matrix comprising a plurality of rows; a plurality of scan lines arranged corresponding to the rows of the pixel circuits and configured to control conduction of the switching elements; a plurality of signal lines, Arranging corresponding to the rows of the pixel circuits and configured to allow propagation therethrough: pixel data; and a driver circuit configured to: - scan pulses to cause the pixel circuits to The switching elements are electrically conductive to the 玄4, and the driving method comprises the following steps: the waveform of the scanning pulse transmitted in the scanning line in the middle of each scanning line of 5 Hz or the like Forming. 14. A method for driving a display device, the display device package: a *pixel segment comprising a plurality of pixel circuits, wherein each of the plurality of "path-pixel circuits" is transmissive-switching components a unit, the (four) circuit is arranged to include a complex circuit matrix; a plurality of scan lines are arranged corresponding to the pixel rows and configured to control the switching elements of the I28894.doc 200912877 conductive, plural Signal lines, which are arranged corresponding to the rows of the pixel circuits, are configured to allow propagation of the pixel data therethrough; and a drive m configured to output a scan pulse to enable such The switching elements of the pixel circuit become conductive to the scan lines, the driving method comprising the steps of: supplying an enable signal through a wire parallel to one of the signal lines to control the waveform forming operation in response to the enable # number Starting the 丨 and shaping the waveform of the scan pulse propagating in the scan line between each scan line of the scan lines. 15. An electronic device, The method comprises: a display device comprising: a pixel segment comprising a plurality of pixel circuits, the pixel data being written to each pixel circuit through a switching element, the pixel circuits being arranged to form a plurality of rows a matrix; , a plurality of scan lines, (4) arranged in the rows of the pixel circuits and configured to control the conduction of the switching elements; a plurality of signal lines arranged and configured to correspond to the The rows of the pixel circuits allow the pixel data to be propagated therethrough; _ 丨 # # 评 T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T Arranged in the wires of each of the scan lines and configured to effect waveform shaping of the scan pulses in the scan lines. The electronic device of claim 5, wherein the waveform shaping circuit is controlled to start its operation in response to an enable signal, and the display device further comprises a parallel with the signal lines - One of the wires of the signal-providing supply line, the ice-shaped + signal is input as one of the positive material_transfer=transfer material μ I28894.doc