KR101532655B1 - Display apparatus, driving method for display apparatus and electronic apparatus - Google Patents

Abstract

A display device including a pixel portion, a plurality of scan lines, a plurality of signal lines, and a driver circuit is disclosed.

Switching element, waveform shaping, scan line, scan pulse

Description

TECHNICAL FIELD [0001] The present invention relates to a display device, a driving method of the display device, and an electronic apparatus.

The present invention relates to a display device in which a thin film transistor as a switching device is formed on a transparent insulating substrate, a driving method of the display device, and an electronic device.

The present invention relates to Japanese Patent Application JP 2008-119202 filed on April 30, 2008, Japanese Patent Application JP 2008-119202, both of which are filed on June 29, 2007, Japanese Patent Application JP 2007-173459 and JP 2007-173460 The subject matter of which is incorporated herein by reference in its entirety.

A display device, for example, a liquid crystal display device in which a liquid crystal cell is used as a display element or an electro-optical element is an image display device in which pixels are arranged in a matrix form and an output image is displayed through a liquid crystal display surface.

The liquid crystal display device is characterized by being ultra-thin and low in power consumption. The liquid crystal display device making full use of the characteristics is applied to a wide range of electronic devices such as a personal digital assistant (PDA), a cellular phone, a digital camera, a video camera, and a personal computer.

1A to 1C show an example of a general liquid crystal display device and a gate pulse waveform of the liquid crystal display device.

1A, the liquid crystal display 1 includes an effective pixel portion 2, a vertical driving circuit (VDRV) 3, and a horizontal driving circuit (HDRV) 4, .

The effective pixel portion 2 has a plurality of pixel circuits 21 arranged in a matrix form.

Each pixel circuit 21 includes a thin film transistor (TFT) 22 serving as a switching element, a liquid crystal cell 23, and a storage capacitor 24. The liquid crystal cell 23 has its pixel electrode connected to the drain electrode or the source electrode of the TFT 22. One electrode of the storage capacitor 24 is connected to the drain electrode of the TFT 22.

The pixel circuit 21 includes gate lines 5-1 to 5-m wired along the pixel arrangement direction for each row and signal lines 6-1 to 6-n wired along the pixel arrangement direction for each column, Respectively.

The gate electrodes of the TFT 22 of the pixel circuit 21 are connected to the same gate lines 5-1 to 5-m on the row. The source electrode or the drain electrode of the pixel circuit 21 are connected to the same signal lines 6-1 to 6-n on a column basis, respectively.

In each liquid crystal cell 23, its pixel electrode is connected to the drain electrode of the TFT 22, and its counter electrode is connected to the common line 7. The storage capacitor 24 is connected between the drain electrode of the TFT 22 and the common line 7.

The common line 7 is connected to the glass substrate so as to receive a predetermined alternating voltage as a common voltage Vcom from a VCOM circuit not shown in the figure formed integrally with a drive circuit or the like.

The gate lines 5-1 to 5-m are respectively driven by the vertical driving circuit 3 and the signal lines 6-1 to 6-n are driven by the horizontal driving circuit 4, respectively.

The vertical driving circuit 3 receives the vertical start signal VST, the vertical clock Vclk and the enable signal ENAB and is connected to the pixel circuits 21 connected to the gate lines 5-1 to 5- In the vertical direction, that is, in the row direction, for every one field period.

Particularly, when the scanning pulse Gp1 is applied from the vertical driving circuit 3 to the scanning line 5-1, the pixel of the first row is selected and the other scanning pulse Gp2 is applied to the scanning line 5-2. The pixel of the column of the second row is selected. Thereafter, gate pulses Gp3, ..., Gpm are applied to the gate lines or scan lines 5-3, ..., 5-m, respectively.

The gate buffers 8-1 to 8-m are provided in the output stage of the gate pulse Gp from the vertical driving circuit 3 to the respective gate lines 5-1 to 5-m.

Fig. 1B shows an example of waveforms in the output stage from the gate buffer 8-m to the gate line 5-m after gate buffering of the gate pulse Gpm.

1C shows an example of waveform at the wiring end of the gate line 5-m of the gate pulse Gpm.

The horizontal driving circuit 4 receives a horizontal start pulse Hst indicating the start of horizontal scanning generated from the clock generator, not shown, and mutually opposite horizontal clocks Hclk used as a reference of the horizontal scanning. Next, the horizontal drive circuit 4 generates a sampling pulse.

The horizontal drive circuit 4 successively samples the image data R (red), G (green), and B (blue) input in response to the generated sampling pulse and records the sampled image data in the pixel circuit 21 To the signal lines 6-1 to 6-n as data signals.

The horizontal driving circuit 4 divides the signal lines into a plurality of groups and includes signal drivers 41 to 44 corresponding to the divided groups.

Although the liquid crystal display device 1 shown in Fig. 1 has a basic structure, the gate line driving by the vertical driving circuit 3 and the driving of the signal line by the horizontal driving circuit 4 as described above Have been proposed. Such techniques are disclosed in, for example, Japanese Patent No. 3,276,996 (hereinafter referred to as Patent Document 1), Japanese Patent Application Laid-Open No. 2007-52370 (hereinafter referred to as Patent Document 2), Japanese Patent No. 3,270,485 (Hereinafter referred to as Patent Document 3), Japanese Patent Application Laid-Open No. 2006-78505 (hereinafter referred to as Patent Document 4), Japanese Patent Application Laid-Open No. 2005-148424 (hereinafter referred to as Patent Document 5 And Japanese Patent Application Laid-Open No. 2005-148425 (hereinafter referred to as Patent Document 6).

Incidentally, the gate pulse Gp outputted from the vertical driving circuit 3 of the liquid crystal display 1 shown in Fig. 1 is usually the resistance of the gate wiring in the panel and the capacitance parasitic to the gate wiring, that is, The gate capacitance, and the capacitance between the pixel electrode and the VCOM wiring.

As a result, the gate output waveform at the end of each gate wiring of the vertical driving circuit 3, that is, at the far end of the gate wiring from the vertical driving circuit 3 is corrected by the impedance generated as shown by the broken line in Fig. The output of the output stage immediately after the vertical driving circuit 3 is slightly distorted.

The distortion of the waveform of the gate pulse causes a slight difference in the waveform between the positions at different distances from the output stage of the vertical driving circuit 3 on the gate line.

As a result, the TFTs 22 as the pixel transistors at other positions on the gate lines are turned on by the gate signals at the timing deviated from each other, resulting in deterioration of image quality in the liquid crystal display device. Particularly, a luminance difference of black and gray in the horizontal direction appears.

Further, regarding the number of pixels of 4K2K super high vision (4,096 x RGB x 1,080), since the horizontal period (1H) is much shorter than the high vision (1,920 x RGB x 1,080) More serious.

In addition, a high frame rate of 240 Hz (typically 60 Hz) further reduces the 1H period to 1/4, rendering the picture itself impossible to display.

Here, a high frame rate is described. For example, a liquid crystal display uses a technique of improving the moving picture characteristics by displaying the frame number and the frame frequency displayed in one second to increase to four times the normal number. Since the liquid crystal display normally operates at 60 Hz, the high frame rate is 240 Hz.

On the other hand, the techniques disclosed in Patent Documents 1 to 6 have disadvantages as described below.

The technique disclosed in Patent Document 1 is directed to a method of suppressing an undesired potential in a pixel electrode when the transistor is turned off by making the falling edge of the gate pulse intentionally longer than the rising edge. However, this technique does not provide a countermeasure against eliminating the delay distribution according to the gate line.

Therefore, this technique is incompatible with liquid crystal displays that include a high number of pixels, such that the resistance of the gate line causes shading reduction on the left and right of the screen, or that use a high frame rate for display.

The technique disclosed in Patent Document 2 includes data transmission in the vertical direction performed for each pixel, transmission of the horizontal scanning signal in the vertical direction in accordance with the control clock wiring arranged for each pixel, and output of the gate pulse signal for each pixel do.

According to this technique, the power supply (VDD and VSS) for the shift register, the clock signal, and the clock signal for the shift register and the input signal line and the output signal line are required, and a space for these lines is required around the opening of the liquid crystal . This causes a decrease in the aperture ratio of the liquid crystal.

This results in a decrease in transmittance and an increase in power to the backlight.

Further, since the control clock line and the signal line are adjacent to each other, an invasion of an undesired potential by the parasitic capacitance between the signal line and the control clock line occurs. As a result, malfunctions are likely to occur. Furthermore, since the clock itself has a delay caused by the distortion caused by the capacitance, there is no effect of suppressing the gate delay.

The technique disclosed in Patent Document 3 uses a PWM (Pulse Wave Modulation) method in which not only an analog signal but also digital data is used as signal data for display, and the gate pulse of the pixel is received and the output of the CMOS circuit is the output of the pixel potential Is used.

However, this technique fundamentally does not provide delay measures for gate wiring. Therefore, this technique is incompatible with liquid crystal displays in which the resistance of the gate line includes a high number of pixels, such as causing shading on the left and right of the screen, or using a high frame rate for display.

In the display method disclosed in Patent Document 4, a recording method using a thin film transistor (TFT) is performed in the following manner.

In the above-described recording method, the pixel display is sequentially performed from the left, and recording of one frame image in 1/240 second or recording of liquid crystal in 1/60 second is performed at the timing of sequentially deviating, The rewriting is performed as shown in Fig. 21 of Patent Document 4).

However, Patent Document 4 does not describe the input timing (input method) of the image signal data in the data line driving circuit, and the concrete recording system at the image frame frequency of 240 Hz is not disclosed.

In the techniques disclosed in Patent Documents 5 and 6, a memory is embedded in a pixel for reduction of power consumption, and a circuit of a CMOS SRAM structure is constituted.

However, this technique relates only to the circuit for supplying the pixel potential and the wiring of the signal line, and does not disclose a circuit configuration for solving the gate delay.

Therefore, since a delay occurs in accordance with the gate line of the display device, the circuit can not cope with a display device including a high number of pixels or driven at a high speed.

Therefore, it is required to provide a display device, a method of driving the display device, and an electronic device capable of suppressing the delay along the scanning line and capable of driving a high number of pixels at a high speed.

According to the embodiment of the present invention, there is provided a liquid crystal display comprising: a pixel portion including a plurality of pixel circuits arranged to form a matrix of a plurality of columns and pixel data is written through switching elements; A plurality of scan lines arranged corresponding to the rows of the pixel circuits and controlling conduction of the switching elements; A plurality of signal lines arranged corresponding to columns of the pixel circuits and propagating the pixel data; And a driving circuit for outputting a scanning pulse for making the switching element of the pixel circuit conductive to the plurality of scanning circuits, wherein the waveform shaping circuit is arranged in the wiring of each scanning line, And the waveform shaping of the scan pulse is performed.

According to another embodiment of the present invention, there is provided a liquid crystal display comprising: a pixel portion including a plurality of pixel circuits arranged to form a matrix of a plurality of columns and pixel data is written through switching elements; A plurality of scan lines arranged corresponding to the rows of the pixel circuits and controlling conduction of the switching elements; A plurality of signal lines arranged corresponding to columns of the pixel circuits and propagating the pixel data; And a driving circuit for outputting a scanning pulse for causing a switching element of the pixel circuit to conduct to the plurality of scanning circuits, the driving method comprising the steps of: applying a scanning pulse to the plurality of scanning lines, There is provided a method of driving a display device, comprising the step of shaping a waveform.

According to another embodiment of the present invention, there is provided a liquid crystal display comprising: a pixel portion including a plurality of pixel circuits arranged to form a matrix of a plurality of columns and pixel data is written through switching elements; A plurality of scan lines arranged corresponding to the rows of the pixel circuits and controlling conduction of the switching elements; A plurality of signal lines arranged corresponding to columns of the pixel circuits and propagating the pixel data; And a driving circuit for outputting a scanning pulse for causing a switching element of the pixel circuit to conduct to the plurality of scanning circuits, the method comprising: supplying an enable signal through a wiring parallel to the signal line, Controlling the start of the waveform shaping operation according to the enable signal; And shaping the waveform of the scanning pulse propagated in the middle of each scanning line of the plurality of scanning lines.

According to another embodiment of the present invention, there is provided an electronic apparatus including a display device, wherein the display device includes a plurality of pixel circuits arranged to form a matrix of a plurality of columns and pixel data is recorded through a switching element A pixel portion; A plurality of scan lines arranged corresponding to the rows of the pixel circuits and controlling conduction of the switching elements; A plurality of signal lines arranged corresponding to columns of the pixel circuits and propagating the pixel data; A driving circuit for outputting a scanning pulse for making a switching element of the pixel circuit conductive to the plurality of scanning circuits; And a waveform shaping circuit arranged in the wiring of each scanning line and performing waveform shaping of the scanning pulse propagated to the scanning line.

The display device, the driving method of the display device, and the electronic device are advantageous in that they can suppress the delay in the scanning line and perform display of a high number of pixels driven at high speed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

≪ Embodiment 1 >

FIGS. 2A to 2C show a configuration example of a liquid crystal display device and a gate pulse example according to the first embodiment of the present invention.

2A, a liquid crystal display 100 includes an effective pixel region 110, a vertical driving circuit (VDRV) 120, and a horizontal driving circuit (HDRV) 130.

The gate buffers 140-1 to 140-m are arranged in the output stage from the vertical driving circuit 120 to the gate lines 115-1 to 115-m which are the scanning lines of the gate pulse Gp.

In the active matrix type liquid crystal display device of this embodiment, the waveform shaping circuits 150-11 to 150-1m and 150-21 to 151 -2m are arranged in the middle on the gate lines 115-1 to 115-m.

The gate pulse output from the vertical driving circuit 120 or the gate pulse after waveform shaping and voltage change processing is supplied is supplied to the pixel switching transistor composed of the thin film transistor through each gate line 115-1 to 115-m.

The configuration, arrangement, and the like of the waveform shaping circuit will be described in detail later.

The effective pixel area unit 110 includes a plurality of pixel circuits 111 arranged in a matrix form.

Each pixel circuit 111 includes a thin film transistor (TFT) 112 as a switching element, a liquid crystal cell 113, and a holding region or a storage capacitor 144.

The liquid crystal cell 113 has its pixel electrode connected to the drain electrode or the source electrode of the TFT 112. One electrode of the storage capacitor 114 is connected to the drain electrode of the TFT 112. [

The gate lines 115-1 to 115-m extend along the pixel arrangement direction for each row and the signal lines 116-1 to 116-n extend to the pixel arrangement Direction.

The gate electrode of the TFT 112 of the pixel circuit 111 is connected to the same gate lines 115-1 to 115-m on the respective stages. In addition, the source electrode or the drain electrode of the TFT 112 of the pixel circuit 111 is connected to the same signal line 116-1 to 116-n in each column unit.

Furthermore, the liquid crystal cell 113 has its pixel electrode connected to the drain electrode of the TFT 112, and its counter electrode connected to the common line 117. The storage capacitor 114 is connected between the drain electrode of the thin film transistor TFT and the common line 117.

In the common line 117, a predetermined ac voltage is applied as a common voltage Vcom from a VCOM circuit (not shown) formed integrally with a driver circuit or the like on the glass substrate.

The gate lines 115-1 to 115-m are driven by the vertical driving circuit 120 and the signal lines 116-1 to 116-n are driven by the horizontal driving circuit 130. [

The TFT 112 is a switching element for selecting a pixel to be displayed and supplying a display signal to the pixel region of the selected pixel.

The TFT 112 has, for example, a bottom gate structure as shown in Fig. 3, or a top gate structure as shown in Fig.

Referring to FIG. 3, in the TFT 112A of the illustrated bottom gate structure, a gate electrode 203 covered with a gate insulating film 202 is formed on a transparent insulating substrate 201 formed of, for example, a glass substrate have.

The gate electrode 203 is connected to the gate line 115 as a scanning line and a gate pulse which is a scanning signal is inputted from the gate line 115 to the gate electrode 203. The TFT 21A is turned on or off according to the scanning signal. The gate electrode 203 is formed of a metal or an alloy film of molybdenum (Mo) or tantalum (Ta) by a method such as sputtering.

The TFT 112A includes a semiconductor film 204 formed on the gate insulating film 202 and serving as a channel forming region. The TFT 112A further includes a pair of n ⁺ diffusion layers 205 and 206 formed across the semiconductor film 204. [ An interlayer insulating film 207 is formed on the semiconductor film 204 and another interlayer insulating film 208 is formed on the insulating substrate 201, the gate insulating film 202, the n ⁺ diffusion layers 205 and 206, As shown in Fig.

The source electrode 210 is connected to the n < ^{+ &} gt ^; diffusion layer 205 through the contact hole 209a formed in the interlayer insulating film 208. [ On the other hand, the drain electrode 211 is connected to the other n ⁺ diffusion layer 206 through the contact hole 209b formed in the interlayer insulating film 208. [

The source electrode 210 and the drain electrode 211 are formed by, for example, patterning aluminum (Al). The signal line 116 is connected to the source electrode 210 and the drain electrode 211 is connected to the pixel region or the pixel electrode through a connection electrode not shown.

Referring to Fig. 4, the TFT 112B of the upper gate structure is shown. The TFT 112B includes a semiconductor film 222 serving as a channel forming region on a transparent insulating substrate 221 formed of, for example, a glass substrate. The TFT 112B further includes a pair of n ⁺ diffusion layers 223 and 224 formed across the semiconductor film 222. [

The gate insulating film 225 is formed so as to cover the semiconductor film 222 and the pair of n ⁺ diffusion layers 223 and 224 and the gate electrode 226 is formed on the gate insulating film 225 facing the semiconductor film 222 . An interlayer insulating film 227 is formed so as to cover the substrate 221, the gate insulating film 225, and the gate electrode 226.

The source electrode 229 is connected to the n < ^{+ &} gt ^; diffusion layer 223 via the interlayer insulating film 227 and the contact hole 228a formed in the gate insulating film 225. [ The drain electrode 230 is connected to the other n ⁺ diffusion layer 224 via the interlayer insulating film 227 and the contact hole 228b formed in the gate insulating film 225. [

Referring again to FIG. 2A, in the above-described liquid crystal display device 1, the TFT 112 of each pixel circuit 111 is formed by a transistor of a semiconductor thin film made of amorphous silicon (a-Si) or polysilicon .

The vertical driving circuit 120 receives the vertical start signal VST, the vertical clock VCK and the enable signal ENB and controls the pixel circuits 111 connected to the gate lines 115-1 to 115- The scanning is performed in the vertical direction, that is, in the row direction, for every one field period so as to sequentially select on the row.

Particularly, when the gate pulse Gp1 is supplied from the vertical driving circuit 120 to the gate line 115-1, the pixel of the first row is selected, but the gate pulse Gp2 is supplied to the gate line 115-1 When supplied, the pixels of the column of the second row are selected. Thereafter, the gate pulses Gp3, ..., Gpm are sequentially supplied to the gate lines 115-3, ..., and 115-m, respectively.

2B shows an example of the waveform of the output stage to the gate line 115-m after gate buffering of the gate pulse Gpm in the gate buffer 140-m.

2C shows an example of the waveform at the wiring end of the gate line 115-m of the gate pulse Gpm.

The horizontal driving circuit 130 receives a horizontal start pulse Hst indicating the start of the horizontal scanning generated by a clock generator not shown and horizontal clock HCK of opposite phases which are the basis of the horizontal scanning, .

The horizontal driving circuit 130 sequentially samples the input image data R (red), G (green), and B (blue) in response to the generated sampling pulses and records the sampled image data in the pixel circuit 21 To the signal lines 116-1 to 116-n as data signals.

The horizontal driving circuit 130 divides the signal lines 116-1 to 116-n into a plurality of groups and includes signal drivers 131 to 134 corresponding to individual groups.

Here, the waveform shaping circuit is described.

In this embodiment, the waveform shaping circuits 150-11 to 150-1m and 150-21 to 150-2m for waveform shaping and voltage changing of the gate pulse from the gate buffers 140-1 to 140m are the same as those described above Are arranged in the middle of the gate lines 115-1 to 115-m.

Thus, as can be seen from the waveforms shown by the solid lines in Fig. 2C, the gate electrodes of the gate lines 115-1 to 115- The waveform of the pulse is improved from the distortion. The waveform shown by the broken line in Fig. 2 (c) shows the distortion of the waveform of the gate pulse at the far end or the far end when the waveform shaping circuit is not intervened.

Thus, the display device can easily display the image with a high number of pixels and a high frame frequency.

The waveform shaping circuits 150-11 to 150-1m, 150-21 to 150-2m are disposed in the middle of the wiring of the gate lines 115-1 to 115-m for waveform shaping.

The waveform shaping circuits 150-11 to 150-1m and 150-21 to 150-2m supply the supply voltage of the supply voltage VDD2 and the reference voltage VSS2 of low potential, Are commonly connected to the line 161.

The waveform shaping circuits 150-11 to 150-1m, 150-21 to 150-2m are respectively formed from a circuit including two CMOS buffers connected in a cascade connection as shown in, for example, Figs. 5A to 5C do.

In the first embodiment, the waveform shaping circuits 150-11 to 150-1m, 150-21 to 150-2m are arranged in the vertical direction, that is, in the extending direction of the signal line As shown in Fig.

Specifically, the waveform shaping circuits 150-11 to 150-1m are disposed at the intersections of the signal lines 116-6 and the gate lines 115-1 to 115-m, respectively. The waveform shaping circuits 150-21 to 150-2m are disposed at the intersections of the signal lines 116-10 and the gate lines 115-1 to 115-m.

2A, the supply line 160 of the high-potential power supply voltage VDD2 and the supply line 161 of the low-potential reference voltage VSS2 are configured to be easily distinguished from the gate line and the signal line, Are indicated by dashed lines and one-dot chain lines, respectively.

5A to 5C show an example in which the waveform shaping circuit according to the present embodiment is formed of a CMOS buffer. Fig. 5A shows an equivalent circuit, Fig. 5B shows a specific circuit, and Fig. 5C shows a capacity of the buffer output side.

As shown in FIG. 5B, each waveform shaping circuit 150 includes a CMOS buffer or inverter BF2 and a CMOS buffer or inverter BF2 different from the CMOS buffer or inverter BF1 connected in cascade connection.

The CMOS buffer BF1 includes a p-channel MOS (PMOS) transistor PT1 and an n-channel MOS (NMOS) transistor NT1.

The source of the PMOS transistor PT1 is connected to the supply line 160 of the high potential supply voltage VDD2, and the drain thereof is connected to the drain of the NMOS transistor NT1. The node ND1 is formed by the connection point of the PMOS transistor PT1 and the drain of the NMOS transistor NT1. The source of the NMOS transistor NT1 is connected to the supply line 161 of the reference voltage VSS2 of low potential.

The gates of the PMOS transistor PT1 and the NMOS transistor NT1 are connected to each other and the input node ND1 is formed by the junction of the gates. And its input node ND1 is connected to one of the corresponding gate lines 115-1 to 115-m.

The CMOS buffer BF2 includes a PMOS transistor PT2 and an NMOS transistor NT2.

The source of the PMOS transistor PT2 is connected to the supply line 160 of the high potential supply voltage VDD2, and the drain thereof is connected to the drain of the NMOS transistor NT2. And the node ND2 is formed by the connection point of the PMOS transistor PT2 and the drain of the NMOS transistor NT2. The source of the NMOS transistor NT2 is connected to the supply line 161 of the reference voltage VSS2 of low potential.

The gates of the PMOS transistor PT2 and the NMOS transistor NT2 are connected to each other and the gate connection point thereof is connected to the node ND1 of the CMOS buffer BF1. And the node ND2 is connected to one of the corresponding gate lines 115-1 to 115-m as an output node.

The waveform shaping circuit 150 having the above-described configuration is connected to the gate line 115-1 to 115-m propagating along the corresponding gate line 115-1 to 115-m from the arrangement side of the vertical driving circuit 120, Outputs the pulses Gp1 to Gpm as a positive logic, and performs waveform shaping.

The output of the CMOS buffers BF1 and BF2 for waveform shaping refers to the capacitance of the gate line Cgate and corresponds to the capacitance of the liquid crystal capacitor Clcd in the state in which the pixel electrode or TFT (pixel transistor) But also a capacity including the capacity Cs.

Since the first stage of the CMOS buffer represents the negative logic output with respect to the input, the waveform shaping circuit 150 outputs the positive logic output to the waveform shaping circuit 150 by the CMOS buffers BF1 and BF2, Connected to each other.

Supply lines 160 and 161 for supplying the power supply voltage VDD2 on the high potential side and the power supply voltage VSS on the low potential side for turning on and off the pixel gates in order that the waveform shaping circuit 150 requires its output power. .

The wirings of the supply lines 160 and 161 are arranged in parallel with the pixel signal lines.

This is because, for example, the lowering of the aperture ratio of the liquid crystal can be minimized when the supply lines 160 and 161 are wired in parallel near the signal lines 116 (116-1 to 116n) When the bus wiring showing a low resistance with respect to the supply lines 160 and 161 of the voltages VDD2 and VSS2 is connected on the effective pixel region 110, the voltage drop of the power supply line in the horizontal direction is minimized It can be.

As a result, the fluctuation of the voltage (high voltage) corresponding to the high level and the voltage (low voltage) corresponding to the low level outputted from the waveform shaping circuit 150 in the horizontal direction of the effective pixel can be minimized.

In the first embodiment, it is preferable that the wirings 160 and 161 of the voltages VDD2 and VSS2 supplied to the waveform shaping circuit 150 and the waveform shaping circuit 150 are arranged at the same coordinates in the horizontal direction .

The reason is that since the coordinates of the waveform shaping circuit 150 in the horizontal direction are constant, the delay of the gate pulse waveform does not suffer a delay.

As described above, according to the first embodiment, the waveform shaping circuits 150-11 to 150-1m (not shown) for waveform shaping and voltage change in the middle of the wiring of the gate line with respect to the gate pulse output from the vertical driving circuit 120 , 150-21 to 151-2m) are disposed.

Therefore, according to the first embodiment, the following effects can be obtained.

      In a display device including a high number of pixels of 4K2K and using a high frame frequency of 240Hz, the left and right shading due to the delay of the gate lines or the difference in chromaticity between left and right do not occur and good image quality can be obtained.

Further, the output delay of the gate pulse Gp from the vertical driving circuit 120 and the generation of the distortion of the waveform can be suppressed, and the vertical driving circuit and the buffer circuit occupied by the left and right sides of the frame of the active matrix display device The area can be reduced. Therefore, the left and right portions of the frame of the display device can be formed with a reduced width.

The wirings 160 and 161 of the voltages VDD2 and VSS2 supplied to the waveform shaping circuit 150 and the waveform shaping circuit 150 are arranged at the same coordinates in the horizontal direction so that the delay of the gate pulse waveform can be suppressed have.

≪ Embodiment 2 >

6A, 6B and 6C show an example of the configuration of a liquid crystal display device and an example of a gate pulse waveform according to a second embodiment of the present invention.

Referring to FIG. 6A, the liquid crystal display 100A according to the second embodiment is similar in configuration to the liquid crystal display 100 according to the first embodiment, but the arrangement position of the waveform shaping circuit 150 is different .

Particularly, in the liquid crystal display device 100 according to the first embodiment described above, the supply lines 160 and 161 of the voltages VDD2 and VSS2 supplied to the waveform shaping circuit 150 and the waveform shaping circuit 150 And are arranged at the same coordinates in the horizontal direction.

In contrast, in the liquid crystal display device 100A according to the second embodiment, the supply lines 160 and 161 of the voltages VDD2 and VSS2 supplied to the waveform shaping circuit 150 and the waveform shaping circuit 150 are horizontal But are arranged in a line-by-line relationship in relation to each other in correspondence with the wiring of the gate line and the signal line.

In the example of Fig. 6A, the waveform shaping circuit 150-11 is disposed in the vicinity of the intersection of the signal line 116-30 and the gate line 115-1. The waveform shaping circuit 150-12 is disposed in the vicinity of the intersection of the signal line 116-4 and the gate line 115-2. The waveform shaping circuit 150-13 is disposed in the vicinity of the intersection of the signal line 116-5 and the gate line 115-3. The waveform shaping circuit 150-14 (m) is disposed near the intersection of the signal line 116-5 and the gate line 115-m.

On the other hand, the waveform shaping circuit 150-21 is disposed near the intersection of the signal line 116-7 and the gate line 115-1. The waveform shaping circuit 150-22 is disposed near the intersection of the signal line 116-8 and the gate line 115-2. The waveform shaping circuit 150-23 is arranged near the intersection of the signal line 116-9 and the gate line 115-3. The waveform shaping circuit 150-24 (m) is disposed near the intersection of the signal line 116-10 and the gate line 115-m.

In this case, if the horizontal coordinate of the waveform shaping circuit 150 is not fixed, the local tilt is removed from the supply lines 160 and 161 of the power supply voltage VDD2 and the reference voltage VSS2. Therefore, the uniformity of the transmittance of the pixel is ensured under the influence of the wiring arrangement by the supply lines 160 and 161 of the voltages VDD2 and VSS2.

In this case, the luminance distribution of the display device is fixed.

Other structures in the second embodiment are similar to those in the first embodiment, and the same effects as those obtained by the first embodiment described above can be obtained.

≪ Third Embodiment >

FIGS. 7A, 7B and 7C show a configuration example of a liquid crystal display and a gate pulse example according to a third embodiment of the present invention.

7A, the liquid crystal display device 100B according to the third embodiment is similar in construction to the liquid crystal display devices 100 and 100A according to the first and second embodiments, but the arrangement of the waveform shaping circuit 150 Location is different.

Particularly, in the liquid crystal display devices 100 and 100A according to the first and second embodiments, the supply lines 160 and 161 of the voltages VDD2 and VSS2 supplied to the waveform shaping circuit 150 and the waveform shaping circuits 150 are arranged at the same coordinates in the horizontal direction.

Conversely, the supply lines 160 and 161 of the voltages VDD2 and VSS2 supplied to the waveform shaping circuit 150 and the waveform shaping circuit 150 are not arranged at the same coordinates.

In contrast, in the liquid crystal display device 100B according to the third embodiment, the gate lines in the vicinity of almost all the intersections of the gate lines and the signal lines, that is, the gate lines of the pixel circuits 111, And shaping circuits 150-11 to 150-nm are arranged.

In this manner, when the waveform shaping circuit 150 is arranged for each pixel circuit 111 on the wiring of the gate line, a plurality of pixel circuits 111 exist between the waveform shaping circuits, So that it is possible to prevent the deviation from occurring.

In other words, when there are a plurality of pixel circuits between the waveform shaping circuit and another waveform shaping circuit, the non-uniformity of the parasitic capacitance is eliminated, and the uniform load capacitance of the pixel gate of the waveform shaping circuit is ensured. Thus, the delay at the gate electrode no longer occurs.

In the third embodiment, the other structures are similar to those of the first and second embodiments, and effects similar to those obtained by the first and second embodiments described above can be obtained.

<Fourth Embodiment>

8 shows a configuration example of a liquid crystal display device according to the fourth embodiment of the present invention.

Referring to Fig. 8, the liquid crystal display device 100C according to the fourth embodiment is similar in configuration to the liquid crystal display device 100 according to the first embodiment, but is also applicable to a method in which image data is recorded in a time- Configuration.

Particularly, even when the time-divisional switch is used as shown in Fig. 8 for reducing the frame size of the panel, if the time-divisional number of the time-divisional switch does not sufficiently satisfy the electric characteristics and image characteristics during the horizontal selection period, .

Signals SV1 to SV4 from the signal drivers 131 to 134 are transmitted to the signal lines 116 (116-1 to 116-12) via a selector SEL having a plurality of transfer gates (TMG).

The conduction state of the transfer gate (analog switch) TMG is selected by the selection signal S1 and the inverted signal XS1, the selection signal S2 and the inverted signal XS2 thereof which are supplied from the outside and have mutually complementary levels, Is controlled by the signal S3 and its inverted signals XS3, ....

In the case of employing the above-described configuration, the selector time division driving method is adopted for the active matrix display device of high definition (UXGA) and high frame rate method in which the number of connection terminals is reduced and the mechanical reliability of connection is improved Lt; / RTI &gt;

In the fourth embodiment, the other structures are similar to those of the first embodiment, and the same effects as those obtained by the first embodiment described above can be obtained.

<Fifth Embodiment>

Fig. 9 shows a configuration example of a liquid crystal display device according to the fifth embodiment of the present invention.

Referring to Fig. 9, the liquid crystal display device 100D according to the fifth embodiment is similar in construction to the liquid crystal display device 100A according to the second embodiment, but is also applicable to a method in which image data is recorded in a time- Configuration.

Particularly, even in the case where the time-divisional switch is used as shown in Fig. 9 for reducing the frame size of the panel, if the time division does not sufficiently satisfy the electric characteristics and the image characteristics during the horizontal selection period, do.

9, the signals SV1 to SV4 from the signal drivers 131 to 134 are transmitted to the signal lines 116-1 to 116-12 through a selector SEL having a plurality of transmission gates TMG do.

The conduction state of the transfer gate (analog switch) TMG is controlled by the selection signal S1 having its complementary level supplied from the outside and the inverted signal XS1, the selection signal S2 and its inverted signal XS2, Is controlled by the signal S3 and its inverted signals XS3, ....

In the case of adopting such a configuration as described above, for an active matrix display device of a high definition (UXGA) and high-speed ripple frame rate scheme, the number of connection terminals is reduced and a selector time- Can be adopted.

In the fifth embodiment, the other structures are similar to those of the second embodiment, and the same effects as those obtained by the above-described first and second embodiments can be obtained.

<Sixth Embodiment>

10 shows a configuration example of a liquid crystal display device according to the sixth embodiment of the present invention.

Referring to Fig. 10, the liquid crystal display device 100E according to the sixth embodiment is similar in configuration to the liquid crystal display device 100B according to the third embodiment, but is also applicable to a method in which image data is recorded in a time- Configuration.

Particularly, even when the time-divisional switch is used as shown in Fig. 10 for reducing the frame size of the panel, when the time-divisional number of the time-divisional switch does not sufficiently satisfy the electric characteristics and image characteristics during the horizontal selection period, .

10, the signals SV1 to SV4 from the signal drivers 131 to 134 are transmitted to the signal lines 116-1 to 116-12 through a selector SEL having a plurality of transmission gates TMG do.

The conduction state of the transfer gate (analog switch) TMG is selected by the selection signal S1 and the inverted signal XS1, the selection signal S2 and the inverted signal XS2 thereof which are supplied from the outside and have mutually complementary levels, Is controlled by the signal S3 and its inverted signals XS3, ....

In the case of adopting such a configuration as described above, the active matrix display device of high-definition (UXGA) and high-speed full-frame rate system is provided with a selector time division driving method Can be adopted.

In the sixth embodiment, the other structures are similar to those of the third embodiment, and the same effects as those obtained by the first to third embodiments described above can be obtained.

<Seventh Embodiment>

11 shows a configuration example of a liquid crystal display device according to a seventh embodiment of the present invention.

Referring to Fig. 11, the liquid crystal display device 100F according to the seventh embodiment is similar in configuration to the liquid crystal display device 100B according to the third embodiment, but differs in the following respects.

Particularly, in the liquid crystal display device 100F, the supply line 160 for the supply voltage VDD2 and the supply line 161 for the supply voltage VSS2 are connected to all the signal lines 116 (116-1 to 116m) And also between all the gate lines 115-1 to 115-m.

When the above-described configuration is employed, intrusion of unwanted voltages in the adjacent pixel circuits 111 occurring between the gate lines and the signal lines can be prevented. As a result, a good image quality is obtained.

The other structures of the seventh embodiment are similar to those of the third embodiment, and the same effects as those obtained by the first to third embodiments described above can be obtained.

Although the wiring of the voltage supply line in the seventh embodiment is not shown in Fig. 11, the configuration of the seventh embodiment can be applied to other first, second, and fourth to sixth embodiments. Even in this case, the intrusion of unwanted voltages in the adjacent pixel circuits 111 can be prevented, and a good image quality can be obtained.

&Lt; Eighth Embodiment >

12A, 12B, and 12C each show a configuration example of a liquid crystal display device and an example of a gate pulse waveform according to an eighth embodiment of the present invention.

12A, the liquid crystal display device 100G according to the eighth embodiment is similar in construction to the liquid crystal display device 100 according to the first embodiment described above, but the waveform shaping circuit is formed of a CMOS (Complementary Metal Oxide Semiconductor) But is configured using a clocked CMOS circuit rather than a buffer.

Here, the waveform shaping circuit 151 is described.

Also in the eighth embodiment, as described above, waveform shaping and voltage change of the gate pulse by the gate buffers 140-1 to 140-m are performed in the middle of the wiring of the gate lines 115-1 to 115- The waveform shaping circuits 150-11 to 150-1m, 150-21 to 150-2m are arranged.

Thus, as shown by the solid line in Fig. 12C, the gate pulse of the gate pulse at the far end or the end portion deviating from the output stage of the gate buffers 140-1 to 140-m of the gate lines 115-1 to 115- The waveform is improved from its distortion. In addition, the waveform shown by the broken line in Fig. 12C shows the distortion of the waveform of the gate pulse at the far end or the end portion when the waveform shaping circuit is not intervened.

Thus, the display device is easy to display at a high frame rate and a high frame frequency.

   The waveform shaping circuits 151-11 to 151-1m and 151-21 to 151-2m are disposed in the middle of the wiring of the gate lines 115-1 to 115-m for waveform shaping.

The waveform shaping circuits 151-11 to 151-1m and 151-21 to 151-2m are connected to the power supply voltage VDD2 supply line 160 of high potential and the supply line 161 of the reference voltage VSS2 of low potential ). The waveform shaping circuits 151-11 to 151-1m and 151-21 to 151-2m are each formed of a circuit including a clocked CMOS buffer and a CMOS buffer connected in a cascade connection as shown in Fig.

In the eighth embodiment, the waveform shaping circuits 151-11 to 151-1m and 151-21 to 151-2m are arranged at the same coordinates in the vertical direction.

Specifically, the waveform shaping circuits 151-11 to 151-1m are disposed at the intersections of the signal lines 116-6 and the gate lines 115-1 to 115-m, respectively. The waveform shaping circuits 151-21 to 151-2m are disposed at the intersections of the signal lines 116-10 and the gate lines 115-1 to 115-m, respectively.

13A to 13C show an example in which the waveform shaping circuit is constituted by a clocked CMOS circuit as in the eighth embodiment.

In particular, FIG. 13A shows an equivalent circuit, FIG. 13B shows a specific circuit, and FIG. 13C shows a capacity on the buffer output side.

13B, each of the waveform shaping circuits 151 is connected to a clocked CMOS buffer or inverter BF3 instead of the CMOS buffer BF1 of FIG. 5 and a clocked CMOS buffer BF3 as a cascade connection And another CMOS buffer or inverter (BF2) connected to the inverter.

The clocked CMOS buffer BF3 includes the PMOS transistor PT3 and the NMOS transistor NT3 in addition to the configuration of the CMOS buffer BF1 of FIG.

The source of the PMOS transistor PT3 is connected to the supply line 160 of the high potential supply voltage VDD2, and the drain thereof is connected to the source of the PMOS transistor PT1.

On the other hand, the NMOS transistor NT3 has its source connected to the supply line 161 of the low-potential supply voltage VSS2, and its drain connected to the source of the NMOS transistor NT1.

The clock CK is supplied to the gate of the NMOS transistor NT3 and the complement of the clock CK or the complementary signal XCK is supplied to the gate of the PMOS transistor PT3.

When the clock CK is at the high level, the PMOS transistor PT3 and the NMOS transistor NT3 are placed in the ON state for operating the clocked CMOS circuit.

The clocks (CK, XCK) have a function as an enable signal that can control the start of operation of the waveform shaping circuit 151.

Other configurations of the waveform shaping circuit 151 are similar to those of Figs. 5A to 5C, and therefore the same detailed description is omitted here to avoid duplication.

The waveform shaping circuit 151 having the above configuration outputs the waveforms of the gate pulses Gp1 to Gpm transferred from the arrangement side of the vertical drive circuit 120, that is, the output side or the left side in Fig. 13A, as a positive logic output And further waveform shaping is performed.

The output of the clocked CMOS buffer BF3 and CMOS buffer BF1 for waveform shaping means the capacitance of the gate line Cgate and the liquid crystal capacitance Clcd in the state in which the pixel electrode or TFT (pixel transistor) ) And the storage capacitance Cs of the pixel.

Furthermore, since the clocked CMOS buffer BF3 indicates the inverted logic output with respect to the input, the waveform shaping circuit 151 is connected to the CMOS buffer BF3 clocked to obtain the positive logic output of the CMOS buffer BF2 Circuit.

Supply lines 160 and 161 for supplying the power supply voltage VDD2 on the high potential side and the power supply voltage VSS2 on the low potential side for turning on and off the pixel gates because the waveform shaping circuit 151 requires the output power source, Are arranged.

This wiring is arranged in parallel with the pixel signal wiring. This is because, for example, the decrease in the aperture ratio of the liquid crystal can be minimized when they are arranged in the vicinity of the signal lines 116 (116-1 to 116n).

Further, when a bus line having a low resistance to the supply lines 160 and 161 of the voltages VDD2 and VSS2 is connected to the effective pixel region 110, the voltage drop of the power line in the horizontal direction is minimized .

As a result, variations in the high and low voltages output from the waveform shaping circuit 150 in the horizontal direction of the effective pixels can be minimized.

When the clock enters the CMOS buffer forming the waveform shaping circuit 151, the clocked CMOS buffer BF3 starts to operate as a control signal at the rising edge or the falling edge of the clock (enable signal) (CK or XCK) do.

Even if delay or distortion of the clocks CK and XCK in the vertical direction occurs when the supply line 162 of the clock CK or XCK is wired in the vertical direction of the display device, CK, XCK) have the same history of the same parasitic capacity. Therefore, the delay becomes fixed.

As a result, the signal transmitted along the gate line arranged in the horizontal direction becomes a waveform of the delay controlled by the clock. This causes a selection signal to be generated in the gate selection waveform which is scanned at a high speed in a vertical direction without being conspicuous in the horizontal direction.

Also in the eighth embodiment, supply lines 160 and 161 of the voltages VDD2 and VSS2 supplied to the waveform shaping circuit 151 and the waveform shaping circuit 151 are connected in the horizontal direction It is preferable that they are arranged at the same coordinates.

This is because the horizontal coordinate of the waveform shaping circuit 151 is fixed, so that the gate pulse waveform does not suffer a delay.

Other structures in the eighth embodiment are similar to those in the first embodiment, and effects similar to those obtained by the first embodiment described above can be obtained. Of course, the delay can be kept constant with a high degree of accuracy.

&Lt; Example 9 &

Figs. 14A, 14B and 14C show an example of the configuration of a liquid crystal display device and an example of a gate pulse waveform according to a ninth embodiment of the present invention, respectively.

14A, the liquid crystal display device 100H according to the ninth embodiment is similar in configuration to the liquid crystal display device 100G according to the eighth embodiment, but the arrangement position of the waveform shaping circuit 150 is different.

Particularly, in the liquid crystal display device 100G according to the eighth embodiment, the supply lines 160 and 161 of the voltages (VDD2 and VSS2) supplied to the waveform shaping circuit 150, and the lines CK and XCK 162 and the waveform shaping circuit 150 are arranged at the same coordinates in the horizontal direction.

In contrast, in the liquid crystal display device 100H according to the ninth embodiment, the supply lines 160 and 161 and the clocks CK and XCK of the voltages VDD2 and VSS2 supplied to the waveform shaping circuit 150, The waveform shaping circuit 162 and the waveform shaping circuit 150 are not arranged at the same coordinates in the horizontal direction but arranged in a line-by-line relationship in a relationship corresponding to the wiring of the gate line and the signal line.

In the example of Fig. 14A, the waveform shaping circuit 150-11 is disposed in the vicinity of the intersection of the signal line 116-3 and the gate line 115-1. The waveform shaping circuit 150-12 is arranged near the intersection of the signal line 116-4 and the gate line 115-2.

The waveform shaping circuit 150-13 is arranged near the intersection of the signal line 116-5 and the gate line 115-3. The waveform shaping circuit 150-14 (m) is arranged near the intersection of the signal line 116-6 and the gate line 115-m.

On the other hand, the waveform shaping circuit 150-21 is disposed near the intersection of the signal line 116-7 and the gate line 115-1. The waveform shaping circuit 150-22 is arranged near the intersection of the signal line 116-8 and the gate line 115-2. The waveform shaping circuit 150-23 is arranged near the intersection of the signal line 116-9 and the gate line 115-3. The waveform shaping circuit 150-24 (m) is disposed near the intersection of the signal line 116-10 and the gate line 115-m.

In this case, when the horizontal coordinate of the waveform shaping circuit 150 is not constant, the local tilt is removed from the supply lines 160 and 161 of the power supply voltage VDD2 and the reference voltage VSS2. Therefore, the uniformity of the transmittance of the pixel in the influence of the wiring arrangement by the supply lines 160 and 161 of the voltages VDD2 and VSS2 is ensured.

In this case, the luminance distribution of the display device is fixed.

The other structures in the ninth embodiment are similar to those in the eighth embodiment, and the same effects as those obtained by the first and eighth embodiments can be obtained.

<Tenth Embodiment>

15A, 15B and 15C show an example of the configuration of the liquid crystal display device and the example of the gate pulse waveform according to the tenth embodiment of the present invention, respectively.

16A to 16J show operations of the liquid crystal display device according to the tenth embodiment.

In particular, FIG. 16A shows a vertical clock VCK for a vertical driving circuit; 16B shows a clock CK for the waveform shaping circuit; 16C shows the inverted signal XCK of the clock CK; 16D shows the vertical start signal VST (Vst).

16E shows the gate pulse Gp1 as the output immediately after the first row of the vertical driving circuit 120; 16F shows a gate pulse Gp2 as an output immediately after the second row of the vertical driving circuit 120; FIG. 16G shows the gate pulse Gp3 as an output immediately after the third row of the vertical driving circuit 120. FIG.

16H shows the gate pulse Gp1 at the farthest end of the first row of the vertical driving circuit 120; 16I shows a gate pulse Gp2 at the far end of the second row of the vertical driving circuit 120; 16J shows the gate pulse Gp3 at the farthest end of the third row of the vertical driving circuit 120. Fig.

The timing chart Vgate_1_L in Fig. 16E shows an output pulse immediately after the first row; The timing chart Vgate_2_L in Fig. 16F shows an output pulse immediately after the second row; The timing chart Vgate_3_L of Fig. 16G shows the output pulse immediately after the third row.

The timing chart Vgate_1_R in Fig. 16H indicates the far-end pulse of the first row; The timing chart Vgate_2_R in Fig. 16I shows an output pulse immediately after the second row; The timing chart Vgate_3_R in Fig. 16J shows the output pulse immediately after the third row.

15A, the liquid crystal display 100I according to the tenth embodiment is similar in construction to the liquid crystal display devices 100G, 100H according to the eighth and ninth embodiments, but the arrangement of the waveform shaping circuit 151 The location is different.

Particularly, in the liquid crystal display devices 100G and 100H according to the eighth and ninth embodiments, the wirings 160 and 161 of the voltages VDD2 and VSS2 supplied to the waveform shaping circuit 151 and the waveform shaping circuit 151 Are arranged at the same coordinates in the horizontal direction.

Conversely, in the liquid crystal display device according to the tenth embodiment, the wirings 160 and 161 of the voltages (VDD2 and VSS2) supplied to the waveform shaping circuit 151 and the waveform shaping circuit 151 are not arranged at the same coordinates Do not.

On the other hand, in the liquid crystal display device 100I according to the tenth embodiment, in the gate lines near the intersections of almost all the gate lines and the signal lines, in other words, in the input section for the gate pulse of the pixel circuit 111, Circuits 151-11 to 151-nm are arranged.

According to the tenth embodiment, as shown in Figs. 16A to 16J, the gate pulse is well waveform-shaped.

Even if the waveform of the gate pulse is distorted by the parasitic capacitance of the supply line 162 of the clocks CK and XCK, the supply line 162 of all the clocks CK and XCK in the horizontal direction becomes the same parasitic capacitance value The distortion of the waveforms of the clocks CK and XCK becomes the same.

Next, since the waveform of the gate pulse propagated in the horizontal direction passes through the waveform shaping circuit 151, distortion and delay of the waveform in the horizontal direction do not occur.

In this way, since the waveform shaping circuit 151 is arranged for each pixel circuit 111 on the wiring of the gate line, a plurality of pixel circuits 111 exist between the waveform shaping circuits, No deviation occurs.

In other words, since there are a plurality of pixel circuits between the waveform shaping circuit and the other waveform shaping circuits, the non-uniformity of the parasitic capacitance is eliminated, and the uniform load capacity of the pixel gate of the waveform shaping circuit is ensured. Thus, the delay at the gate electrode no longer occurs.

The other configurations in the tenth embodiment are similar to those in the eighth and ninth embodiments, and the same effects as those obtained by the eighth and ninth embodiments described above can be obtained.

&Lt; Eleventh Embodiment >

Fig. 17 shows a configuration example of a liquid crystal display device according to an eleventh embodiment of the present invention.

Referring to Fig. 17, the liquid crystal display 100J according to the eleventh embodiment is similar in construction to the liquid crystal display 100G according to the first embodiment, but is also applicable to a system in which image data is recorded in a time- The configuration is adopted.

Particularly, even when the time-divisional switch is used as shown in Fig. 18 for the reduction of frame size of the panel, if the time-divisional number of the time-divisional switch does not sufficiently satisfy the electric characteristic and the image characteristic during the horizontal selection period, .

17, the signals SV1 to SV4 from the signal drivers 131 to 134 are inputted to the signal lines 116 (116-1 to 116-12) via the selector SEL having a plurality of transfer gates (TMG) .

The conduction state of the transfer gate (analog switch) TMG is controlled by the selection signal S1 having its complementary level supplied from the outside and the inverted signal XS1, the selection signal S2 and its inverted signal XS2, Is controlled by the signal S3 and its inverted signals XS3, ....

In the active matrix type display device of the high definition (UXGA) and high frame rate method, when the above-described configuration is adopted, the number of connection terminals is reduced and the selectivity of the selector time division driving method Employment becomes possible.

The other structures in the eleventh embodiment are similar to those in the eighth embodiment, and the same effects as those obtained by the eighth embodiment described above can be obtained.

<Twelfth Embodiment>

18 shows a configuration example of a liquid crystal display device according to a twelfth embodiment of the present invention.

Referring to Fig. 18, the liquid crystal display device 100K according to the twelfth embodiment is similar in construction to the liquid crystal display device 100H according to the ninth embodiment, but is also applicable to a method in which image data is recorded in a time- The configuration is adopted.

Particularly, even when the time-divisional switch is used as shown in Fig. 18 for the reduction of frame size of the panel, if the time-divisional number of the time-divisional switch does not sufficiently satisfy the electric characteristic and the image characteristic during the horizontal selection period, .

18, the signals SV1 to SV4 from the signal drivers 131 to 134 are connected to the signal lines 116 (116-1 to 116-12) via a selector SEL having a plurality of transfer gates (TMG) Lt; / RTI &gt;

The conduction state of the transfer gate (analog switch) TMG is controlled by the selection signal S1 having its complementary level supplied from the outside and the inverted signal XS1, the selection signal S2 and its inverted signal XS2, Is controlled by the signal S3 and its inverted signals XS3, ....

In the case of adopting such a configuration as described above, in the active matrix type display device of high-definition (UXGA) and high-speed frame rate scheme, the number of connection terminals is reduced and the selector time- Can be adopted.

The other structures in the twelfth embodiment are similar to those in the ninth embodiment, and the same effects as those obtained by the eighth and ninth embodiments described above can be obtained.

&Lt; Thirteenth Embodiment &

Fig. 19 shows a configuration example of a liquid crystal display device according to a thirteenth embodiment of the present invention.

Referring to FIG. 19, the liquid crystal display 100L according to the thirteenth embodiment is similar in construction to the liquid crystal display 100I according to the tenth embodiment, but is also applicable to a system in which image data is recorded in a time- The configuration is adopted.

Particularly, even when the time-divisional switch is used as shown in Fig. 19 for reducing the frame size of the panel, when the time-divisional number of the time-divisional switch does not sufficiently satisfy the electric characteristic and the image characteristic during the horizontal selection period, .

19, the signals SV1 to SV4 by the signal drivers 131 to 134 are connected to the signal lines 116 (116-1 to 116-12) via a selector SEL having a plurality of transmission gates (TMG) .

The conduction state of the transfer gate (analog switch) TMG is controlled by the selection signal S1 having its complementary level supplied from the outside and the inverted signal XS1, the selection signal S2 and its inverted signal XS2, Is controlled by the signal S3 and its inverted signals XS3, ....

In the case of adopting such a configuration as described above, in the active matrix type display device of high-definition (UXGA) and high-speed frame rate scheme, the number of connection terminals is reduced and the selector time- Can be adopted.

The other structures in the thirteenth embodiment are similar to those in the tenth embodiment, and the same effects as those obtained by the eighth to tenth embodiments described above can be obtained.

Although the wiring of the voltage supply line in the seventh embodiment is not shown in the drawing here, it can be applied to the eighth to thirteenth embodiments.

Even in that case, an intrusion of an unwanted voltage into the adjacent pixel circuits 111 can be prevented. Accordingly, good image quality can be achieved.

<Fourteenth Embodiment>

20A, 20B and 20C show a configuration example of a liquid crystal display device and a gate pulse waveform according to a fourteenth embodiment of the present invention.

20A, the liquid crystal display device 100M according to the fourteenth embodiment is similar in configuration to the liquid crystal display device 100 according to the first embodiment, but differs in the following points.

In particular, in the liquid crystal display device 100M according to the fourteenth embodiment, the waveform shaping circuit is constituted by a clocked CMOS circuit instead of a circuit formed of a CMOS buffer simply connected in a cascade connection.

Here, the waveform shaping circuit 152 is described.

Also in the fourteenth embodiment, as described above, waveform shaping and voltage change of the gate pulse by the gate buffers 140-1 to 140-m are performed in the middle of the wiring of the gate lines 115-1 to 115- The waveform shaping circuits 152-11 to 152-1m and 152-21 to 152-2m are arranged.

Thus, as shown by the solid line in Fig. 20C, the gate pulse of the gate pulse at the distal end portion or the end portion deviating from the output stage of the gate buffers 140-1 to 140-m of the gate lines 115-1 to 115- The waveform is improved from distortion. In addition, the waveform shown by the broken line in Fig. 20C shows the distortion of the waveform of the gate pulse at the distal end portion or the end portion when the waveform shaping circuit is not intervened.

Thus, the display device can be easily displayed by a high number of pixels and a high frame frequency.

The waveform shaping circuits 152-11 to 152-1m and 152-21 to 152-2m are arranged in the middle of the lines of the gate lines 115-1 to 115-m for waveform shaping.

Further, the waveform shaping circuits 152-11 to 152-1m and 152-21 to 152-2m supply the supply voltage of the supply voltage VDD2 of high potential and the reference voltage VSS2 of low potential Are commonly connected to the line 161.

The waveform shaping circuits 152-11 to 152-1m and 152-21 to 152-2m may include a CMOS configuration NAND gate and a CMOS buffer connected in a cascade connection as shown in FIGS. 21A to 21C, for example. Respectively.

In the fourteenth embodiment, the waveform shaping circuits 152-11 to 152-1m, 152-21 to 152-2m are arranged at the same coordinates in the vertical direction.

More specifically, the waveform shaping circuits 152-11 to 152-1m are disposed at the intersections of the signal lines 116-6 and the gate lines 115-1 to 115-m. The waveform shaping circuits 152-21 to 152-2m are disposed at the intersections of the signal lines 116-10 and the gate lines 115-1 to 115-m.

Figs. 21A to 21C show an example in which the waveform shaping circuit according to the fourteenth embodiment is constituted by a clocked CMOS circuit of a CMOS configuration.

Particularly, Fig. 21A shows an equivalent circuit, Fig. 21B shows a concrete circuit, and Fig. 21C shows a capacity on the buffer output side.

As shown in Fig. 21B, each waveform shaping circuit 152 includes a CMOS buffer or inverter BF11 connected in cascade connection with a NAND circuit 11 and a NAND circuit 11 of CMOS configuration.

The CMOS configuration NAND circuit 11 includes a pair of PMOS transistors PT11 and PT12 and NMOS transistors NT11 and NT12.

The sources of the PMOS transistors PT11 and PT12 are connected to the supply line 160 of the high potential supply voltage VDD2. The drains of the PMOS transistors PT11 and PT12 are connected to the drain of the NMOS transistor NT11 and the node ND11 is formed by the connection point of the drains.

The source of the NMOS transistor NT11 is connected to the drain of the NMOS transistor NT12 and the source of the NMOS transistor NT12 is connected to the supply line 161 of the reference voltage VSS2 of low potential.

The gates of the PMOS transistor PT12 and the NMOS transistor NT12 are connected to each other and a node ND1 is formed by a junction point of the gate thereof to be connected to the corresponding gate line 115-1 to 115-m.

The gates of the PMOS transistor PT12 and the NMOS transistor NT12 are connected to the supply line of the enable signal ENB.

The CMOS buffer BF11 includes a PMOS transistor PT13 and an NMOS transistor NT13.

The source of the PMOS transistor PT13 is connected to the supply line 160 of the high potential supply voltage VDD2, and the drain thereof is connected to the drain of the NMOS transistor NT13. And the node ND12 is formed by the connection point of the drains.

The source of the NMOS transistor NT13 is connected to the supply line 161 of the reference voltage VSS2 of low potential.

The gates of the PMOS transistor PT13 and the NMOS transistor NT13 are connected to each other and the node is connected to the node ND11 of the NAND circuit 11 of the CMOS configuration. And the node ND12 is connected to the corresponding gate line 115-1 to 115-m as an output node.

The waveform shaping circuit 152 having such a configuration as described above outputs the waveforms of the gate pulses Gp1 to Gpm transmitted from the arrangement side of the vertical driving circuit 120, that is, the output side or the left side in Fig. And waveform shaping is performed.

The output of the NAND circuit 11 and the CMOS buffer BF11 in the CMOS configuration for waveform shaping means the capacitance Cgate of the gate line and the capacitance of the liquid crystal capacitor Cgate in the state in which the pixel electrode or TFT (pixel transistor) (Capacitance) Clcd and the pixel storage capacitance Cs.

In addition, since the NAND circuit 11 of the CMOS configuration represents an inverted logic output with respect to the input, the waveform shaping circuit 152 is connected to the NAND circuit 11 in series to the CMOS buffer BF11 in order to obtain a positive logic output Circuit.

Since the waveform shaping circuit 152 requires the output power supply, the supply lines 160 and 161 for supplying the high-side supply voltage VDD2 and the low-side reference voltage VSS for on / Wiring is disposed.

This wiring is arranged in parallel with the pixel signal wiring. This is because, for example, the decrease in the aperture ratio of the liquid crystal can be minimized when they are arranged in the vicinity of the signal lines 116 (116-1 to 116-n) in parallel.

When a bus wiring having a low resistance to the supply lines 160 and 161 of the voltages VDD2 and VSS2 is connected to the upper portion of the effective pixel region 110, the voltage drop in the horizontal power line is minimized .

As a result, variations in the high and low voltages output from the waveform shaping circuit 152 in the horizontal direction of the effective pixels can be minimized.

The NAND circuit 11 of the CMOS configuration has the enable signal ENB as the control pulse when the enable signal ENB is input to the NAND circuit 11 of the CMOS configuration forming the waveform shaping circuit 152 The operation is started at the rising edge or the falling edge.

When the supply line 163 of the enable signal ENB is wired in the vertical direction of the display device, the delay of the enable signal ENB in the vertical direction or the distortion of the waveform occurs, ENB) have a history of the same parasitic capacity. Therefore, the delay is fixed.

As a result, the signal transmitted along the gate line arranged in the horizontal direction shows a clock-controlled delay waveform. This causes the selection signal to be generated without regard to the horizontal direction in the gate selection waveform that is scanned at high speed in the vertical direction.

Also in the fourteenth embodiment, supply lines 160 and 161 of voltages VDD2 and VSS2 supplied to the waveform shaping circuit 152 and the waveform shaping circuit 152, which are the same as the first and eighth embodiments, Are preferably arranged at the same coordinates in the horizontal direction.

The reason is that since the horizontal coordinate of the waveform shaping circuit 152 is constant, the delay of the gate pulse waveform does not occur.

Other structures in the fourteenth embodiment are similar to those in the first embodiment, and the same effect obtained by the first effect described above can be obtained. Of course, the delay can be kept constant with high accuracy.

&Lt; Embodiment 15 &

22A, 22B and 22C show a configuration example of a liquid crystal display device and a gate pulse waveform according to a fifteenth embodiment of the present invention, respectively.

22A, the liquid crystal display device 100N according to the fifteenth embodiment is similar in configuration to the liquid crystal display device 100G according to the fourteenth embodiment, but the arrangement position of the waveform shaping circuit 152 is different.

Particularly, in the liquid crystal display device 100M according to the fourteenth embodiment, the supply lines 160 and 161 of the voltages VDD2 and VSS2 supplied to the waveform shaping circuit 152, the supply lines of the enable signals ENB, The waveform shaping circuit 163, and the waveform shaping circuit 152 are arranged at the same coordinates in the horizontal direction.

On the other hand, in the liquid crystal display device 100N according to the fifteenth embodiment, the liquid crystal display device 100N is not arranged at the same coordinates in the horizontal direction but arranged in a line-by-line relationship corresponding to the wiring of the gate line and the signal line.

In the example of Fig. 22A, the waveform shaping circuit 152-11 is disposed near the intersection of the signal line 116-3 and the gate line 115-1. The waveform shaping circuit 152-12 is disposed near the intersection of the signal line 116-4 and the gate line 115-2. The waveform shaping circuit 152-13 is disposed near the intersection of the signal line 116-5 and the gate line 115-3. The waveform shaping circuit 152-14 (m) is disposed near the intersection of the signal line 116-5 and the gate line 115-m.

On the other hand, the waveform shaping circuit 152-21 is disposed near the intersection of the signal line 116-7 and the gate line 115-1. The waveform shaping circuit 152-22 is arranged near the intersection of the signal line 116-8 and the gate line 115-2. The waveform shaping circuit 152-23 is arranged near the intersection of the signal line 116-9 and the gate line 115-3. The waveform shaping circuit 152-24 (m) is disposed near the intersection of the signal line 116-10 and the gate line 115-4m.

In this case, when the coordinates of the waveform shaping circuit 152 in the horizontal direction are not constant, a local gradient is removed from the wiring of the power supply voltage VDD2 and the supply lines 160 and 161 of the reference voltage VSS2 . Therefore, the uniformity of the transmittance of the pixel is ensured under the influence of the wiring arrangement of the supply lines 160 and 161 of the voltages VDD2 and VSS2.

In this case, the luminance distribution of the display device becomes constant.

The other structures in the fifteenth embodiment are similar to those in the fourteenth embodiment, and the same effects as those obtained by the first and fourteenth embodiments described above can be obtained.

<Sixteenth Embodiment>

23A, 23B and 23C show a configuration example of a liquid crystal display device and a gate pulse waveform according to a sixteenth embodiment of the present invention, respectively.

24A to 24J show operations of the liquid crystal display according to the sixteenth embodiment.

In particular, FIG. 24A shows a vertical start signal VST (Vst); 24B shows a vertical clock VCK for a vertical driving circuit; And Fig. 24C shows the waveform shaping circuit enable signal ENB.

24D shows the immediately-after gate pulse Gp1 in the first row of the vertical driving circuit 120; 24E shows the immediately-after gate pulse Gp2 in the second row of the vertical driving circuit 120; 24F shows the immediately-after gate pulse Gp3 in the third row of the vertical driving circuit 120, respectively.

24G shows a gate pulse Gp1 at the farthest end of the first row of the vertical driving circuit 120; 24H shows a gate pulse Gp2 at the far end of the second row of the vertical driving circuit 120; 24 (i) shows the gate pulse Gp3 at the far end of the third row of the vertical driving circuit 120, respectively.

The timing chart Vgate_1_L in Fig. 24D shows an output pulse immediately after the first row; The timing chart Vgate_2_L in FIG. 24E shows an output pulse immediately after the second row; Vgate_3_L in FIG. 24F shows output pulses immediately after the third row.

The timing chart Vgate_1_R in Fig. 24G shows the far-end pulse in the first row; The timing chart Vgate_2_R in Fig. 24H shows an output pulse immediately after the second row; The timing chart Vgate_3_R in FIG. 24 (i) shows output pulses immediately after the third row.

25A shows a vertical start signal or a start pulse VST (Vst); And Fig. 24B shows the vertical clock VCK for the vertical driving circuit, respectively.

Fig. 25C shows the enable signal ENB in the first stage for the waveform shaping circuit; FIG. 25D shows the immediately-after gate pulse Gp1 in the first row of the vertical driving circuit 120; 25E shows the gate pulse Gp1 at the farthest end of the first row of the vertical driving circuit 120, respectively.

Fig. 25F shows the enable signal ENB at the intermediate stage for the waveform shaping circuit; 25G shows an immediate gate pulse GpM at the intermediate stage of the vertical driving circuit 120; 25H shows the gate pulse GpM at the far end in the intermediate stage of the vertical driving circuit 120, respectively.

Fig. 25I shows the enable signal ENB at the final stage for the waveform shaping circuit; 25J shows a gate pulse GpF immediately after the last row of the vertical driving circuit 120; 25K shows the gate pulse GpF at the far end of the vertical driving circuit 120, respectively.

The timing chart Vgate_1_L in Fig. 25D shows the output pulse immediately after the first row; The timing chart Vgate_1_R in Fig. 25E shows the far-end pulse of the first row.

The timing chart Vgate_M_L in Fig. 25G shows the output pulse immediately after the intermediate stage; The timing chart Vgate_M_R in Fig. 25H shows the far-end pulse at the intermediate stage.

The timing chart Vgate_F_L in FIG. 25J shows an output pulse immediately after the last row; And the timing chart Vgate_F_R in FIG. 25K shows the far-end far-end pulse.

23A, the liquid crystal display 100O according to the sixteenth embodiment is similar in construction to the liquid crystal display devices 100M and 100N according to the fourteenth and fifteenth embodiments, but the arrangement of the waveform shaping circuit 152 The location is different.

Particularly in the liquid crystal display devices 100M and 100N according to the fourteenth and sixteenth embodiments, the supply lines 160 and 161 of the voltages VDD2 and VSS2 supplied to the waveform shaping circuit 152 and the waveform shaping circuit 152 are arranged at the same coordinates in the horizontal direction.

Conversely, the supply lines 160, 161 of the voltages VDD2, VSS2 supplied to the waveform shaping circuit 152 and the waveform shaping circuit 152 are not arranged at the same coordinates.

On the other hand, in the liquid crystal display device 100O according to the sixteenth embodiment, the gate lines near the intersections of almost all the gate lines and the signal lines, in other words, the input waveforms of the gate pulses of the pixel circuits 111, And shaping circuits 152-11 to 152-nm are arranged.

According to the sixteenth embodiment, the gate pulse is well waveform-shaped as shown in Figs. 24A to 24J.

Although the waveform of the enable signal ENB is distorted by the parasitic capacitance of the supply line 163 or the like, the supply line 163 of all the enable signals ENB in the horizontal direction has the same parasitic capacitance value The distortion of the waveform of the enable signal ENB is the same.

Next, since the gate pulse transmitted in the horizontal direction passes through the waveform shaping circuit 152, distortion and delay of the waveform in the horizontal direction do not occur.

In this way, since the waveform shaping circuit 152 is arranged for each pixel circuit 111 on the wiring of the gate line, a plurality of pixel circuits 111 exist between the waveform shaping circuits, and the delay variation of the waveform of the gate pulse does not occur .

In other words, since there are a plurality of pixel circuits between the waveform shaping circuit and other waveform shaping circuits, the non-uniformity of the parasitic capacitance is eliminated, and the uniform load capacitance of the pixel gate of the waveform shaping circuit is ensured. Therefore, no delay occurs in the gate electrode.

The other structures in the sixteenth embodiment are similar to those in the fourteenth and fifteenth embodiments, and the same effects as those obtained by the fourteenth and fifteenth embodiments described above can be obtained.

<Seventeenth Embodiment>

Fig. 26 shows a configuration example of a liquid crystal display device according to a seventeenth embodiment of the present invention.

Referring to Fig. 26, the liquid crystal display device 100P according to the seventeenth embodiment is similar in configuration to the liquid crystal display device 100M according to the fourteenth embodiment, and is also applicable to a method in which image data is recorded in a time- The configuration is adopted.

Particularly, even when the time-divisional switch is used as shown in Fig. 26 for reducing the frame size of the panel, if the time-divisional number of the time-divisional switch does not sufficiently satisfy the electric characteristic and the image characteristic during the horizontal selection period, .

26, the signals SV1 to SV4 from the signal drivers 131 to 134 are input to the signal lines 116 (116-1 to 116-12) via the selector SEL having multiple transfer gates (TMG) Lt; / RTI &gt;

The conduction state of the transfer gate (analog switch) TMG is controlled by the selection signal S1 having its complementary level supplied from the outside and the inverted signal XS1, the selection signal S2 and its inverted signal XS2, Is controlled by the signal S3 and its inverted signals XS3, ....

In the case of adopting such a configuration as described above, in the active matrix type display device of high-definition (UXGA) and high-speed frame rate scheme, the number of connection terminals is reduced and the selector time- Can be adopted.

The other structures in the seventeenth embodiment are similar to those in the fourteenth embodiment, and the same effects as those obtained by the fourteenth embodiment can be obtained.

<Eighteenth Embodiment>

Fig. 27 shows a configuration example of a liquid crystal display device according to an eighteenth embodiment of the present invention.

Referring to Fig. 27, the liquid crystal display 100Q according to the eighteenth embodiment is similar in construction to the liquid crystal display 100N according to the fifteenth embodiment, but is also applicable to a system in which image data is recorded in a time- The configuration is adopted.

Particularly, even when the time-divisional switch is used as shown in Fig. 27 for reducing the frame size of the panel, when the time-divisional number of the time-divisional switch does not sufficiently satisfy the electric characteristic and the image characteristic during the horizontal selection period, .

27, the signals SV1 to SV4 from the signal drivers 131 to 134 are input to the signal lines 116 (116-1 to 116-12) via the selector SEL having multiple transfer gates (TMG) Lt; / RTI &gt;

The conduction state of the transfer gate (analog switch) TMG is controlled by the selection signal S1 having its complementary level supplied from the outside and the inverted signal XS1, the selection signal S2 and its inverted signal XS2, Is controlled by the signal S3 and its inverted signals XS3, ....

In the case of adopting such a configuration as described above, in the active matrix type display device of high-definition (UXGA) and high-speed frame rate scheme, the number of connection terminals is reduced and the selector time- Can be adopted.

The other structures in the eighteenth embodiment are similar to those in the fifteenth embodiment, and the same effects as those obtained by the fourteenth and fifteenth embodiments described above can be obtained.

&Lt; Example 19 &

Fig. 28 shows a configuration example of a liquid crystal display device according to a nineteenth embodiment of the present invention.

Referring to Fig. 28, the liquid crystal display device 100R according to the nineteenth embodiment is similar in configuration to the liquid crystal display device 100O according to the sixteenth embodiment, and is also applicable to a method in which image data is recorded in a time- Configuration is adopted.

Particularly, in the case where the time division switch of the time division switch does not sufficiently satisfy the electric characteristics and the image characteristics during the horizontal selection period, even when the time division switch is used as shown in Fig. 28, Application is required.

28, the signals SV1 to SV4 by the signal drivers 131 to 134 are connected to the signal lines 116 (116-1 to 116-12) via the selector SEL having a plurality of transfer gates (TMG) .

The conduction state of the transfer gate (analog switch) TMG is controlled by the selection signal S1 having its complementary level supplied from the outside and the inverted signal XS1, the selection signal S2 and its inverted signal XS2, Is controlled by the signal S3 and its inverted signals XS3, ....

In the case of adopting such a configuration as described above, in the active matrix type display device of high-definition (UXGA) and high-speed frame rate scheme, the number of connection terminals is reduced and the selector time- Can be adopted.

The other structures in the nineteenth embodiment are similar to those in the sixteenth embodiment, and the same effects as those obtained by the above-described fourteenth to sixteenth embodiments can be obtained.

<Twentieth Embodiment>

29A, 29B and 29C show an example of the configuration of the liquid crystal display device and the example of the gate pulse waveform according to the 20th embodiment of the present invention.

29A, the liquid crystal display device 100S according to the twentieth embodiment is similar in configuration to the liquid crystal display device 100O according to the sixteenth embodiment, but differs in the following points.

The liquid crystal display device 100S according to the 20th embodiment is configured such that the supply line 160 of the supply voltage VDD2 and the supply line 161 of the reference voltage VSS2 are connected to all the signal lines 116-116- m and all the gate lines 115 (115-1 to 115-m).

When the configuration as described above is employed, the intrusion of an undesired voltage generated in the gate line and the signal line into the adjacent pixel circuit 111 can be prevented. Thus, a good image quality can be obtained.

The other structures in the twentieth embodiment are similar to those in the tenth embodiment, and the same effects as those obtained by the above-described fourteenth to sixteenth embodiments can be obtained.

Although the wiring of the voltage supply line in the twentieth embodiment is not shown in the drawing here, it is also applicable to the other fourteenth, fifteenth, and seventeenth to nineteenth embodiments. In this case as well, intrusion of undesired voltages into the adjacent pixel circuits 111 can be prevented, and good image quality can be obtained.

In the first to twentieth embodiments of the present invention, the arrangement positions and configurations of the waveform shaping circuits 150, 151 and 152 in the equivalent circuit, the power supply lines, and the like have been described.

Hereinafter, the arrangement positions of the waveform shaping circuits 150, 151, and 152 in the device will be described.

In the present embodiment, in the transmissive liquid crystal display device, the waveform shaping circuits 150, 151, and 152 are basically disposed directly below the black color filter mask.

On the other hand, in the reflective or transmissive liquid crystal display device, the waveform shaping circuits 150, 151, and 152 are disposed in the reflective region.

30A and 30B show a transmissive liquid crystal display device.

30A and 30B, the transmissive liquid crystal display 300 includes a lower gate type TFT as described previously with reference to FIG. 3, and a liquid crystal display 300 is provided between the TFT substrate 310 and the counter substrate 320. [ Layer 330 is inserted.

30A, the TFT substrate 310 includes a glass substrate 311, a planarization film 312 formed on the glass substrate 311, a transparent electrode 313 formed on the planarization film 312, And an alignment film 314 formed on the electrode 313.

The counter substrate 320 includes a glass substrate 321, a light blocking region 322 formed on the glass substrate 321, and an alignment film 323 formed on the light blocking region 322.

In Fig. 30B, the same constituent parts as those in Fig. 3 are denoted by the same reference numerals. Since the structure of the TFT itself has already been described, the redundant description is omitted in order to avoid verbosity.

Fig. 31 shows a first example of the pixel circuit of the transmissive liquid crystal display device when the waveform shaping circuit described above with reference to Figs. 5A to 5C is employed.

31, the constituent elements PT1, PT2, NT1 and NT2 of the waveform shaping circuit 150 and the wiring are disposed immediately below the light shielding region 322 made of the black color filter mask.

In this example, the gate pulse Gp input with the positive logic is applied to the gate of the TFT 112 of the pixel circuit 111 through the buffers BF1 and BF2 and then to the positive logic.

Since the waveform shaping circuit 150 is formed of a polysilicon TFT (thin film transistor), the light from the backlight is blocked by the waveform shaping circuit 150, which causes a decrease in the transmittance of the pixel.

Therefore, in the arbitrary pixel including the waveform shaping circuit 150 formed of a TFT (thin film transistor) and the power supply lines 160 and 161 of the voltages VDD2 and VSS2 to the waveform shaping circuit 150, So that a deviation easily occurs.

Therefore, the light shielding region 322 made of the black color filter mask for suppressing the luminance deviation between the pixels is disposed directly above the circuit, so that the transmittance is made constant and the luminance deviation is suppressed.

Fig. 32 shows a second example of the pixel circuit of the transmissive liquid crystal display device when the waveform shaping circuit described above with reference to Figs. 5A to 5C is employed.

The second example is similar to the first example of Fig. 31, but the gate pulse Gp input with the negative logic is level-inverted by the buffer BF1, and the gate of the TFT 112 of the pixel circuit 111 As shown in FIG. Next, the gate pulse Gp is outputted as a negative logic through the buffer BF2.

Therefore, the pixel circuit 111 is disposed between the output of the buffer BF1 and the input of the buffer BF2.

Fig. 33 shows a third example of the pixel circuit of the transmissive liquid crystal display device when the waveform shaping circuit described above with reference to Figs. 5A to 5C is employed.

The third example is similar to the first example of FIG. 31, but differs in that it is configured to prevent intrusion of undesired voltages from the signal line 116 and the gate line 115.

The signal line 116 and the gate line 115 are connected to the supply line 160 of the supply voltage VDD2 to prevent intrusion of undesired voltages from the signal line 116 and the gate line 115. In the third example, And the supply line 161 of the reference voltage VSS2.

Fig. 34 shows a fourth example of the pixel circuit of the transmissive liquid crystal display device when the waveform shaping circuit described above with reference to Figs. 5A to 5C is employed.

The fourth example is similar to the second example of FIG. 32, but differs in that it is configured to prevent the ingress of undesired voltages from the signal line 116 and the gate line 115.

The signal line 116 and the gate line 115 are connected to the supply line 160 of the supply voltage VDD2 to prevent intrusion of undesired voltages from the signal line 116 and the gate line 115. In the third example, And the supply line 161 of the reference voltage VSS2.

FIG. 35A shows a pixel circuit of a transmissive reflection type liquid crystal display device, and FIG. 35B shows a first example of a pixel circuit of a transmissive reflection type liquid crystal display device when the waveform shaping circuit described above with reference to FIGS. 5A to 5C is employed. Fig.

35A, a transmissive reflection type liquid crystal display device 400 includes a transparent insulating substrate 401, a thin film transistor (TFT) 402 formed on a transparent insulating substrate 401, a pixel region 403, and the like .

The transmissive reflection type liquid crystal display device 400 further includes a transparent insulating substrate 404, a TFT 402, and a pixel region 403 which are provided to face the transparent insulating substrate 401. The transmissive reflection type liquid crystal display device 400 further includes an overcoat layer 405, a color filter 405a, a counter electrode 406 and a liquid crystal layer 407 formed on the transparent insulation substrate 404. [ The liquid crystal layer 407 is inserted between the pixel region 403 and the counter electrode 406.

The pixel region 403 is arranged in a matrix and has a gate line 115 for supplying a gate pulse Gp to the TFT 402 and a signal line 116 for supplying a display signal to the TFT 402, Are provided around the individual pixel region 403 to constitute a pixel portion.

A storage capacitor wiring (hereinafter referred to as CS line) formed of a metal film extending parallel to the gate line 115 is provided on the transparent insulating substrate 401 and the TFT 402 side. The CS line forms a storage capacitor CS with the pixel electrode, and is connected to the counter electrode 406.

Further, a reflective region A for performing reflective display and a transmissive region (B) for performing transmissive display are provided in each pixel region 403.

The transparent insulating substrate 401 is formed of, for example, a transparent material such as glass. A TFT 402, a scattering layer 408, and a planarization layer 409 are formed on the transparent insulating substrate 401. Particularly, the scattering layer 408 is formed on the TFT 402 with the insulating film interposed therebetween, and the planarization layer 409 is formed on the scattering layer 408. [ Further, the transparent electrode 410 and the reflective electrode 411 are formed on the planarization layer 409. The reflective electrode 411 forms the pixel region 403 having the reflective region A and the transmissive region B described above.

35B, the constituent elements PT1, PT2, NT1 NT2 and the wiring of the waveform shaping circuit 150 are arranged in the reflective region A. [

As described above, since the waveform shaping circuit 150 is formed of a polysilicon TFT (thin film transistor), the light from the backlight is blocked by the waveform shaping circuit 150, which causes a decrease in the transmittance of the pixel .

In this regard, a method in which the waveform shaping circuit 151 is positively disposed directly below the reflection area of the reflection liquid crystal is useful when there is one that does not pass the light of the backlight like the reflection liquid crystal.

By the arrangement of the waveform shaping circuit 150, the degree of freedom of the TFT arrangement for forming the CMOS used in the waveform shaping circuit 150 is significantly increased as compared with the transmissive type. Thus, since the width of the power supply line of the power supply voltage VDD2 and the reference voltage VSS2 can be increased, the delay caused by the power supply line resistance of the CMOS output becomes difficult to occur.

36A is a pixel circuit of a reflection type liquid crystal display device, and FIG. 36B shows a first example of a pixel circuit of a reflection type liquid crystal display device when the above-described waveform shaping circuit is employed with reference to FIGS. 5A to 5C .

The device structure of the pixel circuit of the reflective liquid crystal display device is similar to the transmissive reflective liquid crystal display device except that it does not have the transmissive region B. [ Therefore, a redundant description of the device structure is omitted here to avoid verbosity.

In this case also, the constituent elements PT1, PT2, NT1 and NT2 of the waveform shaping circuit 150 and the wiring are arranged in the reflection region A as shown in Fig. 36B.

Fig. 37 shows a second example of the pixel circuit of the transmissive reflection type liquid crystal display device when the above-described waveform shaping circuit is employed with reference to Figs. 5A to 5C.

The second example is similar to the first example of FIGS. 35A and 35B, but differs in that it is configured to prevent the intrusion of undesired voltages from the signal line 116 and the gate line 115.

The signal line 116 and the gate line 115 are connected to the supply line 160 of the supply voltage VDD2 so as to prevent the intrusion of undesired voltages from the signal line 116 and the gate line 115. [ And the supply line 161 of the reference voltage VSS2.

Fig. 38 shows a second example of the pixel circuit of the reflection type liquid crystal display device when the waveform shaping circuit described above is employed with reference to Figs. 5A to 5C.

The second example is similar to the first example of FIG. 36, but differs in that it is configured to prevent intrusion of undesired voltages from the signal line 116 and the gate line 115.

The signal line 116 and the gate line 115 are connected to the supply line 160 of the supply voltage VDD2 so as to prevent the intrusion of undesired voltages from the signal line 116 and the gate line 115. [ And the supply line 161 of the reference voltage VSS2.

Fig. 39 shows a first example of the pixel circuit of the transmissive liquid crystal display device when the above-described waveform shaping circuit is employed with reference to Figs. 13A to 13C.

The constituent elements PT1, PT2, NT1 and NT2 of the waveform shaping circuit 151 and the wiring are arranged immediately below the light shielding region 322 formed by the black color filter mask, as shown in Fig.

In this example, the gate pulse Gp input with the positive logic is applied to the gate of the TFT 112 of the pixel circuit 111 through the buffers BF3 and BF2 and then to the positive logic.

Since the waveform shaping circuit 151 is formed of a polysilicon TFT (thin film transistor), the light from the backlight is shielded by the waveform shaping circuit 151, which causes a decrease in the transmittance of the pixel.

Therefore, in the arbitrary pixel including the waveform shaping circuit 151 formed of a TFT (thin film transistor) and the power supply lines 160 and 161 of the voltages VDD2 and VSS2 for the waveform shaping circuit 151, So that a deviation easily occurs.

Therefore, the light shielding region 322 formed by the black color filter mask for reducing the luminance deviation between the pixels is disposed on the circuit so as to make the transmittance constant, thereby suppressing the luminance deviation.

Fig. 40 shows a second example of the pixel circuit of the transmissive liquid crystal display device when the waveform shaping circuit described above is employed with reference to Figs. 13A to 13C.

The second example is similar to the first example of Fig. 39, but the gate pulse Gp input with the negative logic is level-inverted by the buffer BF3 and is applied to the gate of the TFT 112 of the pixel circuit 111 with positive logic And is configured to be applied. Then, the gate pulse Gp is outputted as a negative logic through the buffer BF1.

Therefore, the pixel circuit 111 is disposed between the output of the buffer BF3 and the input of the buffer BF11.

Fig. 41 shows a third example of the pixel circuit of the transmissive liquid crystal display device when the above-described waveform shaping circuit is employed with reference to Figs. 13A to 13C.

The third example is similar to the first example of FIG. 39, except that it is configured to prevent the intrusion of undesired voltages from the signal line 116 and the gate line 115 is prevented.

The signal line 116 and the gate line 115 are connected to the supply line 160 of the supply voltage VDD2 so as to prevent the intrusion of undesired voltages from the signal line 116 and the gate line 115. [ And the supply line 161 of the reference voltage VSS2.

Fig. 42 shows a fourth example of the pixel circuit of the transmissive liquid crystal display device when the above-described waveform shaping circuit is employed with reference to Figs. 13A to 13C.

The fourth example is similar to the second example of Fig. 40, except that the intrusion of undesired voltages from the signal line 116 and the gate line 115 is prevented.

The signal line 116 and the gate line 115 are connected to the supply line 160 of the supply voltage VDD2 so as to prevent the intrusion of undesired voltages from the signal line 116 and the gate line 115. [ And the supply line 161 of the reference voltage VSS2.

Fig. 43 shows a first example of the pixel circuit of the transmissive reflection type liquid crystal display device when the above-described waveform shaping circuit is employed with reference to Figs. 13A to 13C.

The constituent elements PT1, PT2, NT1 and NT2 of the waveform shaping circuit 151 and the wiring are arranged in the reflection region A, as shown in Fig.

As described above, since the waveform shaping circuit 151 is formed of a polysilicon TFT (thin film transistor), the light from the backlight is shielded by the waveform shaping circuit 151, which causes a decrease in the transmittance of the pixel .

In this regard, a method in which the waveform shaping circuit 151 is positively disposed directly below the reflection area of the reflection liquid crystal is useful when there is one that does not pass the light of the backlight like the reflection liquid crystal.

By the arrangement of the waveform shaping circuit 151, the degree of freedom of the TFT arrangement for forming the CMOS used in the waveform shaping circuit 151 is significantly increased as compared with the transmissive type. Thus, since the width of the power supply line of the power supply voltage VDD2 and the reference voltage VSS2 can be increased, the delay caused by the power supply line resistance of the CMOS output becomes difficult to occur.

Fig. 44 shows a first example of the pixel circuit of the reflection type liquid crystal display device when the above-described waveform shaping circuit is employed with reference to Figs. 13A to 13C.

44, the constituent elements PT1, PT2, NT1 and NT2 of the waveform shaping circuit 151 and the wiring are arranged in the reflection region A. [

Fig. 45 shows a second example of the pixel circuit of the transmissive reflection type liquid crystal display device when the waveform shaping circuit described above is employed with reference to Figs. 13A to 13C.

The second example is similar to the first example of FIG. 43, but differs in that it is configured to prevent the intrusion of undesired voltages from the signal line 116 and the gate line 115 is prevented.

The signal line 116 and the gate line 115 are connected to the supply line 160 of the supply voltage VDD2 so as to prevent the intrusion of undesired voltages from the signal line 116 and the gate line 115. [ And the supply line 161 of the reference voltage VSS2.

Fig. 46 shows a second example of the pixel circuit of the reflection type liquid crystal display device when the waveform shaping circuit described above is employed with reference to Figs. 13A to 13C.

The second example is similar to the first example of FIG. 44, but differs in that it is configured to prevent the intrusion of undesired voltages from the signal line 116 and the gate line 115 is prevented.

The signal line 116 and the gate line 115 are connected to the supply line 160 of the supply voltage VDD2 so as to prevent the intrusion of undesired voltages from the signal line 116 and the gate line 115. [ And the supply line 161 of the reference voltage VSS2.

Fig. 47 shows a first example of the pixel circuit of the transmissive liquid crystal display device when the waveform shaping circuit of Figs. 21A to 21C is employed.

The constituent elements PT1, PT2, PT3, NT1, NT2 and NT3 of the waveform shaping circuit 152 and the wiring are arranged immediately below the light shielding region 322 formed by the black color filter mask, as shown in Fig. do.

In this example, the gate pulse Gp input with the positive logic passes through the buffers BF1 and BF2 and is then applied to the gate of the TFT 112 of the pixel circuit 111 with positive logic.

Since the waveform shaping circuit 152 is formed of a polysilicon TFT (thin film transistor), the light from the backlight is blocked by the waveform shaping circuit 152, which causes a decrease in the transmittance of the pixel.

Therefore, in any pixel including the waveform shaping circuit 152 formed of a TFT (thin film transistor) and the power supply lines 160 and 161 of the voltages VDD2 and VSS2 for the waveform shaping circuit 152, So that a deviation easily occurs.

Therefore, the light shielding region 322 made of the black color filter mask for suppressing the luminance deviation between the pixels is disposed directly above the circuit, so that the transmittance is made constant and the luminance deviation is suppressed.

Fig. 48 shows a second example of the pixel circuit of the transmissive liquid crystal display device when the waveform shaping circuit described above with reference to Figs. 21A to 21C is employed.

The second example is similar to the first example of Fig. 47, but the gate pulse Gp input with the negative logic is level inverted by the NAND circuit 11, and the gate of the TFT 112 of the pixel circuit 111 Which is different from that applied to the gate. Next, the gate pulse Gp is outputted as a negative logic through the buffer BF11.

Therefore, the pixel circuit 111 is disposed between the output of the NAND circuit 11 and the input of the buffer BF11.

Fig. 49 shows a third example of the pixel circuit of the transmissive liquid crystal display device when the waveform shaping circuit described above with reference to Figs. 21A to 21C is employed.

The third example is similar to the first example of FIG. 47, but differs in that it is configured to prevent the intrusion of undesired voltages from the signal line 116 and the gate line 115.

The signal line 116 and the gate line 115 are connected to the supply line 160 of the supply voltage VDD2 to prevent intrusion of undesired voltages from the signal line 116 and the gate line 115. In the third example, And the supply line 161 of the reference voltage VSS2.

Fig. 50 shows a fourth example of the pixel circuit of the transmissive liquid crystal display device when the waveform shaping circuit described above with reference to Figs. 21A to 21C is employed.

The fourth example is similar to the second example of FIG. 48, but differs in that it is configured to prevent the ingress of undesired voltages from the signal line 116 and the gate line 115.

The signal line 116 and the gate line 115 are connected to the supply line 160 of the supply voltage VDD2 to prevent intrusion of undesired voltages from the signal line 116 and the gate line 115. In the fourth example, And the supply line 161 of the reference voltage VSS2.

Fig. 51 shows a first example of a pixel circuit of a transmissive reflection type liquid crystal display device when the waveform shaping circuit described above with reference to Figs. 21A to 21C is employed.

51, the constituent elements PT11, PT12, PT13, NT11, NT12, and NT13 and the wiring of the waveform shaping circuit 152 are arranged in the reflection area A.

As described above, since the waveform shaping circuit 152 is formed of a polysilicon TFT (thin film transistor), the light from the backlight is blocked by the waveform shaping circuit 152, which causes a decrease in the transmittance of the pixel .

In this regard, a method in which the waveform shaping circuit 152 is positively disposed directly below the reflection area of the reflection liquid crystal is useful when there is one that does not pass the light of the backlight, such as a reflection liquid crystal.

The arrangement of the waveform shaping circuit 152 greatly increases the degree of freedom of the TFT arrangement for forming the CMOS used in the waveform shaping circuit 152 compared with the transmissive type. Thus, since the width of the power supply line of the power supply voltage VDD2 and the reference voltage VSS2 can be increased, the delay caused by the power supply line resistance of the CMOS output becomes difficult to occur.

Fig. 52 shows a first example of the pixel circuit of the reflection type liquid crystal display device when the waveform shaping circuit described above with reference to Figs. 21A to 21C is employed.

52, the constituent elements PT11, PT12, PT13, NT11, NT12, and NT13 of the waveform shaping circuit 152 and the wiring are arranged in the reflective region A in the illustrated arrangement.

Fig. 53 shows a second example of the pixel circuit of the transmissive reflection type liquid crystal display device when the waveform shaping circuit described above with reference to Figs. 21A to 21C is employed.

The second example is similar to the first example of FIG. 51, but differs in that it is configured to prevent the ingress of undesired voltages from the signal line 116 and the gate line 115.

In particular, in this example, the signal line 116 and the gate line 115 are connected to the supply line 160 of the supply voltage VDD2 to prevent the ingress of undesired voltages from the signal line 116 and the gate line 115, And the supply line 161 of the reference voltage VSS2.

Fig. 54 shows a second example of the pixel circuit of the reflection type liquid crystal display device when the waveform shaping circuit described above with reference to Figs. 21A to 21C is employed.

The second example is similar to the first example of FIG. 52, but differs in that it is configured to prevent intrusion of undesired voltages from the signal line 116 and the gate line 115.

In particular, in this example, the signal line 116 and the gate line 115 are connected to the supply line 160 of the supply voltage VDD2 to prevent the ingress of undesired voltages from the signal line 116 and the gate line 115, And the supply line 161 of the reference voltage VSS2.

The active matrix type display device typified by the active matrix type liquid crystal display device according to the embodiment described above is used as a display device such as an OA device such as a personal computer and a word processor, and a television receiver. INDUSTRIAL APPLICABILITY The display device of the present invention can be suitably applied as a display portion of an electronic device such as a cellular phone or PDA for miniaturization and compactness of the apparatus main body.

Particularly, the display apparatus according to the present invention can be applied to various electric apparatuses shown as examples of Figs. 55A to 55G.

Particularly, the display device is applicable to a display device of an electronic device in all fields displaying video signals inputted to electronic devices such as digital cameras, notebook type personal computers, mobile phones, video cameras, or the like, or video signals generated in electronic devices It is possible to apply.

Hereinafter, an example of an electronic apparatus to which the display apparatus of the present invention is applied will be described.

55A shows an example of a television to which the present invention is applied. 55A, the television 500 includes an image display screen section 303 including a front panel 501, a glass filter 502, and the like. The display apparatus according to the present invention can be used as the image display screen unit 503. [

55B and 55C show an example of a digital camera to which the present invention is applied. 55B and 55C, the digital camera 510 includes a photographing lens 511, a flash light emitting portion 512, a display portion 513, a control switch 514, and the like. The display device according to the present invention can be used in the display portion 513.

55D shows an example of a video camera to which the present invention is applied. 55D, the video camera 520 includes a main body portion 521, a subject photographing lens 522, a start / stop switch 523 operated at the time of photographing, a display portion 524, and the like. The display device according to the present invention can be used in the display portion 524.

55E and 55F show a portable terminal apparatus to which the present invention is applied. 55E and 55F, the portable terminal device 530 includes an upper housing 531, a lower housing 532, a hinge-shaped connecting portion 533, a display portion 534, a sub-display portion 535, 536, a camera 537, and the like. The display device according to the present invention can be used for the display portion 534 or the sub-display portion 535. [

55G shows a notebook type personal computer to which the present invention is applied. 55G, the notebook-type personal computer 540 includes a main body 541, a keyboard 542 operated to input characters and the like, a display portion 543 for displaying an image, and the like. The display device according to the present invention can be used in the display portion 543. [

Further, in the above embodiment, the present invention is applied to an active matrix liquid crystal display device. However, the present invention is not limited thereto, and can be similarly applied to other active matrix type display devices such as an EL display device in which an electroluminescence (EL) device is used as an electro-optical element of each pixel.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims and their equivalents, .

1A, 1B, and 1C are circuit diagrams and waveform diagrams each showing an exemplary configuration example of a general liquid crystal display device and an example of a gate pulse waveform,

2A, 2B and 2C are circuit diagrams and waveform diagrams showing a configuration example of a liquid crystal display device and a gate pulse waveform according to the first embodiment of the present invention, respectively,

3 is a schematic view showing a TFT of a bottom gate structure,

4 is a schematic view showing a TFT of a top gate structure,

5A, 5B and 5C are circuit diagrams showing an example of a waveform shaping circuit in the liquid crystal display of FIG. 2A formed of a CMOS buffer,

6A, 6B and 6C are diagrams showing a configuration example of a liquid crystal display device and a gate pulse waveform according to a second embodiment of the present invention,

7A, 7B and 7C are circuit diagrams showing a configuration example of the liquid crystal display device according to the third embodiment of the present invention,

8 is a circuit diagram showing a configuration example of a liquid crystal display device according to a fourth embodiment of the present invention,

Figs. 9, 10 and 11 are circuit diagrams showing a configuration example of the liquid crystal display device according to the fifth, sixth, and seventh embodiments of the present invention, respectively,

12A, 12B and 12C are a circuit diagram and a waveform diagram showing an example of the configuration of a liquid crystal display device and an example of a gate pulse waveform according to an eighth embodiment of the present invention,

13A, 13B and 13C are diagrams showing the waveform shaping circuit of the liquid crystal display device of Fig. 12A formed by the clocked COMS circuit,

14A, 14B and 14C are circuit diagrams and waveform diagrams each showing a configuration example of a liquid crystal display device and an example of a gate pulse waveform according to a ninth embodiment of the present invention,

15A, 15B and 15C are a circuit diagram and a waveform diagram showing an example of the configuration of a liquid crystal display device and an example of a gate pulse waveform according to a tenth embodiment of the present invention,

16A to 16J are timing charts of the liquid crystal display device shown in Fig. 15A,

17, 18, and 19 are circuit diagrams showing a configuration example of the liquid crystal display device according to the eleventh to thirteenth embodiments of the present invention,

20A, 20B and 20C are a circuit diagram and a waveform diagram showing an example of the configuration of a liquid crystal display device and an example of a gate pulse waveform according to a fourteenth embodiment of the present invention,

21A, 21B and 21C are circuit diagrams showing the waveform shaping circuit of the liquid crystal display of Fig. 20A, which is constituted by a clocked CMOS circuit including a NAND of a CMOS configuration,

22A, 22B and 22C are circuit diagrams and waveform diagrams each showing a configuration example of a liquid crystal display device and an example of a gate pulse waveform according to a fifteenth embodiment of the present invention,

23A, 23B and 23C are circuit diagrams and waveform diagrams, respectively, of a configuration example of a liquid crystal display device and an example of a gate pulse waveform according to a sixteenth embodiment of the present invention,

24A to 24I are timing charts of the liquid crystal display device shown in Fig. 23A,

25A to 25K are timing charts for explaining another operation of the liquid crystal display device shown in Fig. 23A,

Figs. 26, 27, and 28 are circuit diagrams and waveform diagrams each showing a configuration example of a liquid crystal display device and an example of a gate pulse waveform according to the seventeenth, eighteenth, and nineteenth embodiments of the present invention,

29A, 29B and 29C are a circuit diagram and a waveform diagram showing an example of a configuration example of a liquid crystal display device and an example of a gate pulse waveform according to a twentieth embodiment,

30A and 30B are cross-sectional views of a transmissive liquid crystal display device,

Figs. 31, 32, 33, and 34 are plan views showing first, second, third, and fourth examples of the pixel circuit of the transmissive liquid crystal display device when the waveform shaping circuit of Fig.

Figs. 35A and 35B are a cross-sectional view of a pixel circuit of a transmission reflection type liquid crystal display device and a plan view showing a first example of a pixel circuit of a transmission reflection type liquid crystal display device when the waveform shaping circuit of Fig. 5A is employed,

Figs. 36A and 36B are a cross-sectional view of a pixel circuit of a reflection type liquid crystal display device and a plan view showing a first example of a pixel circuit of a reflection type liquid crystal display device when the waveform shaping circuit of Fig. 5A is employed,

Fig. 37 is a plan view showing a second example of the pixel circuit of the transmissive reflection type liquid crystal display device when the waveform shaping circuit of Fig. 5 is employed,

Fig. 38 is a plan view showing a second example of the pixel circuit of the reflection type liquid crystal display device when the waveform shaping circuit of Fig. 5 is employed,

Figs. 39, 40, 41, and 42 are plan views showing first, second, third, and fourth examples of the pixel circuit of the transmissive liquid crystal display device when the waveform shaping circuit of Fig. 13 is employed ,

Fig. 43 is a plan view showing a first example of the pixel circuit of the transmissive reflection type liquid crystal display device when the waveform shaping circuit of Fig. 13 is employed,

Fig. 44 is a plan view showing a first example of the pixel circuit of the reflection type liquid crystal display device when the waveform shaping circuit of Fig. 13 is employed,

45 is a plan view showing a second example of the pixel circuit of the transmissive reflection type liquid crystal display device when the waveform shaping circuit of Fig. 13 is employed,

Fig. 46 is a plan view showing a second example of the pixel circuit of the reflection type liquid crystal display device when the waveform shaping circuit of Fig. 13 is employed,

Figs. 47, 48, 49, and 50 are plan views showing first, second, third, and fourth examples of the pixel circuit of the transmissive liquid crystal display device when the waveform shaping circuit of Fig. 21 is employed ,

Fig. 51 is a plan view showing a second example of the pixel circuit of the transmissive reflection type liquid crystal display device when the waveform shaping circuit of Fig. 21 is employed,

Fig. 52 is a plan view showing a first example of the pixel circuit of the reflection type liquid crystal display device when the waveform shaping circuit of Fig. 21 is employed,

Fig. 53 is a plan view showing a second example of the pixel circuit of the transmissive reflection type liquid crystal display device when the waveform shaping circuit of Fig. 21 is employed,

Fig. 54 is a plan view showing a second example of the pixel circuit of the reflection type liquid crystal display device when the waveform shaping circuit of Fig. 21 is employed,

55A to 55G are schematic diagrams showing several examples of electronic devices to which the display device according to the present invention is applied.

[Description of Reference Numerals]

100, 100A to 100M: liquid crystal display device 110: effective pixel portion

115-1 to 115-m: scan lines 116-1 to 116-n: signal lines

120: vertical driving circuit (VDRV) 130: horizontal driving circuit (HDRV)

131 to 134: Signal driver 150, 151, 152: Waveform shaping circuit

160: supply line of the power source voltage VDD2 161: supply line of the reference voltage VSS2

162: clock supply line 163: enable signal supply line

Claims (16)

A substrate having a light shielding region; A pixel portion including a plurality of pixel circuits in which pixel data is written through a switching element and arranged in a matrix; A plurality of scan lines arranged along a row of the pixel circuits and controlling conduction of the switching elements; A plurality of signal lines arranged along the columns of the pixel circuits for propagating the pixel data; A driving circuit configured to output a scanning pulse for turning on a switching element of each of the pixel circuits to each of the scanning lines; A waveform shaping circuit arranged in the shielding region and configured to perform waveform shaping of a scan pulse propagated through the scan line; A first supply line for supplying a first voltage to the waveform shaping circuit; And And a second supply line for supplying a second voltage having a level lower than the level of the first voltage to the waveform shaping circuit, Wherein the waveform shaping circuit is disposed at an intersection of the signal line and the scanning line, Wherein the first supply line and the second supply line are disposed in parallel with each of the signal lines, Wherein the first supply line, the second supply line, and the waveform shaping circuit are disposed at the same coordinates in the horizontal direction. The method according to claim 1, Wherein the waveform shaping circuit is arranged in the middle of the wiring of the corresponding scanning line so that the waveform shaping circuit is located on the same coordinate in the extending direction of the signal line in the coordinate arrangement of the matrix of the pixel circuit. The method according to claim 1, Wherein the waveform shaping circuit is disposed in the middle of the wiring of the corresponding scanning line so that the waveform shaping circuit is located on another coordinate in a direction in which the signal line extends in the coordinate arrangement of the matrix of the pixel circuit. The method according to claim 1, Wherein the waveform shaping circuit is disposed in the middle of the wiring of the scanning line so as to be located in the input stage of the pixel circuit. delete The method according to claim 1, Wherein the display device is a reflection type or transmission reflection type liquid crystal display device and the waveform shaping circuit is arranged in a reflection region of the liquid crystal display device. The method according to claim 1, And a power supply line connected to the waveform shaping circuit and extending in parallel with the signal line. 8. The method of claim 7, Wherein the power supply line is disposed between each of the signal lines and one of the adjacent scan lines. The method according to claim 1, Wherein the waveform shaping circuit is formed of a CMOS circuit and forms an output signal of a positive logic with respect to the input signal. The method according to claim 1, A plurality of signal drivers respectively corresponding to the signal lines, and Further comprising a plurality of selector switches disposed between the signal driver and one of the corresponding signal lines, for selecting and supplying image data in a time-sharing manner. The method according to claim 1, Wherein the waveform shaping circuit is capable of controlling the start of operation according to an enable signal, Wherein the waveform shaping circuit forms an output signal of a positive logic with respect to the input signal. The display apparatus of claim 1, wherein the waveform shaping circuit forms an output signal of positive logic with respect to the input signal. 12. The method of claim 11, Wherein the waveform shaping circuit includes a NAND circuit of a CMOS configuration capable of controlling the start of operation in accordance with the enable signal. A substrate having a light shielding region; A pixel portion including a plurality of pixel circuits in which pixel data is written through a switching element and arranged in a matrix; A plurality of scan lines arranged along a row of the pixel circuits and controlling conduction of the switching elements; A plurality of signal lines arranged along the columns of the pixel circuits for propagating the pixel data; A driving circuit configured to output a scanning pulse for turning on a switching element of each of the pixel circuits to each of the scanning lines; A waveform shaping circuit arranged in the shielding region and configured to perform waveform shaping of a scan pulse propagated through the scan line; A first supply line for supplying a first voltage to the waveform shaping circuit; And a second supply line for supplying a second voltage having a level lower than the level of the first voltage to the waveform shaping circuit, wherein the waveform shaping circuit is disposed at an intersection of the signal line and the scan line, 1 supply line and a second supply line are arranged in parallel with each of the signal lines, and the first supply line, the second supply line and the waveform shaping circuit are arranged at the same coordinates in the horizontal direction, And shaping the waveform of the scanning pulse propagated in the middle of each scanning line of the plurality of scanning lines in the shielding area. A substrate having a light shielding region; A pixel portion including a plurality of pixel circuits in which pixel data is written through a switching element and arranged in a matrix; A plurality of scan lines arranged along a row of the pixel circuits and controlling conduction of the switching elements; A plurality of signal lines arranged along the columns of the pixel circuits for propagating the pixel data; A driving circuit configured to output a scanning pulse for turning on a switching element of each of the pixel circuits to each of the scanning lines; A waveform shaping circuit arranged in the shielding region and configured to perform waveform shaping of a scan pulse propagated through the scan line; A first supply line for supplying a first voltage to the waveform shaping circuit; And a second supply line for supplying a second voltage having a level lower than the level of the first voltage to the waveform shaping circuit, wherein the waveform shaping circuit is disposed at an intersection of the signal line and the scan line, 1 supply line and a second supply line are arranged in parallel with each of the signal lines, and the first supply line, the second supply line and the waveform shaping circuit are arranged at the same coordinates in the horizontal direction, Supplying an enable signal through a wiring parallel to the signal line to control the start of the waveform shaping operation according to the enable signal; And And shaping the waveform of the scanning pulse propagated in the middle of each scanning line of the plurality of scanning lines in the shielding area. 1. An electronic device including a display device, The display device includes: A substrate having a light shielding region; A pixel portion including a plurality of pixel circuits in which pixel data is written through a switching element and arranged in a matrix; A plurality of scan lines arranged along a row of the pixel circuits and controlling conduction of the switching elements; A plurality of signal lines arranged along the columns of the pixel circuits for propagating the pixel data; A driving circuit configured to output a scanning pulse for turning on a switching element of each of the pixel circuits to each of the scanning lines; A waveform shaping circuit arranged in the shielding region and configured to perform waveform shaping of a scan pulse propagated through the scan line; A first supply line for supplying a first voltage to the waveform shaping circuit; And And a second supply line for supplying a second voltage having a level lower than the level of the first voltage to the waveform shaping circuit, Wherein the waveform shaping circuit is disposed at an intersection of the signal line and the scanning line, Wherein the first supply line and the second supply line are disposed in parallel with each of the signal lines, Wherein the first supply line, the second supply line, and the waveform shaping circuit are arranged at the same coordinates in the horizontal direction. 16. The method of claim 15, Wherein the waveform shaping circuit is capable of controlling the start of operation in accordance with an enable signal and the display device further comprises a wiring of the supply line for the enable signal formed in parallel with the signal line, Thereby forming an output signal having a positive logic.

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