WO2019169809A1 - 显示面板及其降低电容负载的方法 - Google Patents

显示面板及其降低电容负载的方法 Download PDF

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Publication number
WO2019169809A1
WO2019169809A1 PCT/CN2018/093366 CN2018093366W WO2019169809A1 WO 2019169809 A1 WO2019169809 A1 WO 2019169809A1 CN 2018093366 W CN2018093366 W CN 2018093366W WO 2019169809 A1 WO2019169809 A1 WO 2019169809A1
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layer
substrate
conductive
trace
electrode layer
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PCT/CN2018/093366
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English (en)
French (fr)
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单剑锋
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惠科股份有限公司
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Priority to US16/329,179 priority Critical patent/US10782577B2/en
Publication of WO2019169809A1 publication Critical patent/WO2019169809A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/137—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present application relates to the field of circuit load design, and in particular to a display panel and a method for reducing the capacitive load thereof.
  • each pixel includes a Thin-Film Transistor (TFT) whose gate is connected to a horizontal scanning line and the source is connected to a vertical direction.
  • the data line is connected to the pixel electrode. If a certain positive scanning voltage is provided in a horizontal scanning line, all the transistors on the scanning line are turned on, and the pixel electrodes of the scanning line are connected with the vertical data lines, and the signal of the data line is connected.
  • the voltage is written in each pixel capacitance of the scanning line to control the transmittance of the liquid crystal of different pixels to achieve the effect of controlling the color.
  • the gate drive circuit for driving the gate of each pixel transistor uses a shift register circuit (Shift Register) to generate a continuous drive signal to the scan line to control the turn-on and turn-off of each pixel transistor in the display.
  • the shift register circuit is directly fabricated on an Array substrate instead of a driver chip made of an external silicon chip.
  • Such a technique is also called a Gate Driver on Array (GOA).
  • GOA Gate Driver on Array
  • the shift register circuit is directly formed on the border of the display panel, which can reduce the production process and reduce the product cost, thereby improving the high integration of the active matrix panel and making the panel thinner.
  • the process architecture of the display panel is divided into two types: SOC (System on chip) and GOA (Gate driver on array).
  • SOC System on chip
  • GOA Gate driver on array
  • the smaller the frame the more desired. Therefore, compared to the SOC version design, the GOA has a smaller border.
  • GOA is an important technology in panel design. The main advantage is that it can eliminate the gate drive integrated circuit and reduce the product cost. Therefore, GOA products are bound to be the mainstream trend in the future, so how to solve the problem of excessive circuit load is currently on the market. A major challenge for GOA products.
  • an object of the present invention is to provide a display panel including: a first substrate; a first conductive layer formed on the first substrate; a first passivation layer formed on the first a conductive layer covering the first substrate; a second passivation layer formed on the first passivation layer; and a first electrode layer formed on the second passivation layer and covering a portion The first conductive layer and the first passivation layer; a second substrate disposed opposite the first substrate; a liquid crystal layer between the first substrate and the second substrate; and a first a second electrode layer is formed on the second substrate; wherein a conductive bridge hole is formed on the first conductive layer, and the first electrode layer is simultaneously covered on the first conductive layer; The conductive bridge hole transmits a voltage signal to the first electrode layer and the second electrode layer.
  • Another object of the present application is to provide another display panel, including: a first substrate; a first conductive layer formed on the first substrate; a first passivation layer formed on the first conductive layer And covering the first substrate; a second passivation layer is formed on the first passivation layer; and a first electrode layer is formed on the second passivation layer and covering a portion of the first a conductive layer and a first passivation layer; a second substrate disposed opposite the first substrate; a liquid crystal layer between the first substrate and the second substrate, formed on the first electrode And covering the second passivation layer; and a second electrode layer is formed on the second substrate; wherein a conductive bridge hole is formed in the first conductive layer trace, and at the same time a first electrode layer overlying the first conductive layer; transmitting a voltage signal to the first electrode layer and the second electrode layer through the conductive bridge hole; at the first conductive layer and the first A capacitor is formed between the two electrode layers.
  • a further object of the present application is to provide a method for reducing a capacitive load, comprising: providing a first substrate; forming a first metal layer on the first substrate; forming a first passivation layer through And forming, on the first conductive layer, the first substrate; forming a second passivation layer on the first passivation layer; and forming a second blunt layer by using a first electrode layer And covering a portion of the first conductive layer and the first passivation layer; providing a second substrate opposite to the first substrate; transmitting a liquid crystal layer on the first substrate and the Forming a second substrate between the first electrode layer and covering the second passivation layer; and forming a second electrode layer on the second substrate; wherein, in the a conductive layer trace forms a conductive bridge hole, and simultaneously covers the first electrode layer on the first conductive layer; transmits a voltage signal to the first electrode layer and through the conductive bridge hole a second electrode layer, such that the dielectric coefficient of the liquid crystal layer approaches a parallel vector Power factor.
  • the first conductive layer further includes a first trace, a second trace, and a third trace.
  • the first trace forms at least one conductive bridge hole.
  • the second trace forms at least one conductive bridge hole.
  • the third trace forms at least one conductive bridge hole.
  • the liquid crystal layer has a dielectric coefficient including a dielectric constant of a parallel vector and a dielectric constant of a vertical vector.
  • the method for reducing a capacitive load further includes a first trace, a second trace, and a third trace, respectively formed on the trace At least one conductive bridge hole.
  • the method for reducing a capacitive load the liquid crystal layer has a dielectric coefficient, and the dielectric coefficient includes a dielectric constant of a parallel vector and a dielectric constant of a vertical vector.
  • the application can reduce the load of the gate drive circuit and reduce the power of the panel.
  • FIG. 1 is a schematic diagram of an exemplary display panel.
  • FIG. 2 is a schematic diagram of a display panel according to an embodiment of the present application.
  • Figure 3a is a schematic diagram of an exemplary capacitive load circuit.
  • FIG. 3b is a schematic diagram of a capacitive load circuit according to an embodiment of the present application.
  • Figure 4a is a schematic diagram of an exemplary metal trace.
  • FIG. 4b is a schematic diagram of a metal trace according to an embodiment of the present application.
  • Figure 5a is a schematic diagram of an exemplary capacitive load device.
  • FIG. 5b is a schematic diagram of a device for a capacitive load according to an embodiment of the present application.
  • the word “comprising” is to be understood to include the component, but does not exclude any other component.
  • “on” means located above or below the target component, and does not mean that it must be on the top based on the direction of gravity.
  • FIG. 1 is a schematic diagram of an exemplary display panel.
  • an exemplary display panel 10 includes a color filter substrate 100 , an array substrate 110 , and a driving chip 105 for driving the circuit.
  • FIG. 2 is a schematic diagram of a display panel according to an embodiment of the present application.
  • a display panel 11 having a gate array driving includes a color filter substrate 100, an array substrate 110, a driving chip 105, and a gate array driving.
  • the circuit 103 is configured to form the gate driving circuit 103 on the array substrate 110.
  • the so-called GOA is to arrange the gate driving circuit on the array substrate to replace the driving chip fabricated by the external silicon chip. Since the GOA technology can be directly disposed around the panel, the production process is simplified, the integration of the display panel is improved, and the panel is made thinner. With the advancement of technology, the display panel industry has developed a dual-drive GOA circuit, which is to arrange two sets of GOA circuits on both sides of the panel.
  • FIG. 3a is a schematic diagram of an exemplary capacitive load circuit.
  • a capacitive load circuit 300 includes a clock voltage signal 310, a signal resistor 320, a signal capacitor 330, a shunt capacitor 340, and an active switch T10.
  • FIG. 3b is a schematic diagram of a capacitive load circuit according to an embodiment of the present application.
  • a capacitive load circuit 301 includes a clock voltage signal 310, a signal resistor 320, a signal capacitor 330, and an active switch T10.
  • the control terminal 101a of the active switch T10 is electrically coupled to the control terminal 101a.
  • the first end 101b of the active switch T10 is electrically coupled to the signal capacitor 330, and a second end 101c of the active switch T10 is electrically coupled to a gate line.
  • a metal layer trace region 400 includes a first trace 410, a second trace 420, and a third trace 430.
  • the conductive trace 425 is formed on the second trace 420.
  • a conductive bridge hole 435 is formed on the third trace 430.
  • a display panel 500 includes: a first substrate 510; a first metal layer 520 is formed on the first substrate 510; and a first passivation layer 530 is formed on the first substrate a conductive layer 520 covering the first substrate 510; a second metal layer 540 formed on the first passivation layer 530; a second passivation layer 550 formed on the first passivation layer 530 And a first electrode layer 560 is formed on the second passivation layer 550 and covers a portion of the first conductive layer 520, the second metal layer 540, and the first passivation layer 530; a second substrate 590 disposed opposite the first substrate 510; a liquid crystal layer 570 between the first substrate 510 and the second substrate 590; and a second electrode layer 580 formed on the first substrate a second substrate 590; wherein, the first conductive layer 520 is traced to form a conductive bridge hole 425; the second metal layer 540 is traced to form a conductive bridge
  • At least one conductive bridge hole 425 is formed on the second trace 420.
  • At least one conductive bridge hole 435 is formed on the third trace 430.
  • a metal trace area 401 includes a first trace 410, a second trace 420, and a third trace 430.
  • the conductive trace 415 is formed on the first trace 410.
  • a conductive bridge hole 425 is formed on the second trace 420, and a conductive bridge hole 435 is formed on the third trace 430.
  • a display panel 501 includes: a first substrate 510; a first metal layer 520 is formed on the first substrate 510; a first passivation layer 530 is formed on the first substrate a conductive layer 520 covering the first substrate 510; a second passivation layer 550 formed on the first passivation layer 530; and a first electrode layer 560 formed on the second passivation layer 550, and covering a portion of the first conductive layer 520 and the first passivation layer 530; a second substrate 590 disposed opposite the first substrate 510; a liquid crystal layer 570 located on the first substrate 510 And a second electrode layer 580 is formed on the second substrate 590; wherein the first conductive layer 520 is traced to form a conductive bridge hole 415, and at the same time The first electrode layer 560 covers the first conductive layer 520; a voltage signal is transmitted through the conductive bridge hole 415 to the first electrode layer 560 and the second electrode layer 580.
  • the first conductive layer 520 further includes a first trace 410, a second trace 420, and a third trace 430.
  • At least one conductive bridge hole 415 is formed on the first trace 410.
  • At least one conductive bridge hole 425 is formed on the second trace 420.
  • At least one conductive bridge hole 435 is formed on the third trace 430.
  • the liquid crystal layer 570 has a dielectric coefficient including a dielectric constant of a parallel vector and a dielectric constant of a vertical vector.
  • a display panel 501 includes: a first substrate 510; a first conductive layer 520 is formed on the first substrate 510; a first passivation layer 530 is formed on the first substrate a conductive layer 520 covering the first substrate 510; a second passivation layer 550 formed on the first passivation layer 530; and a first electrode layer 560 formed on the second passivation layer 550, and covering a portion of the first conductive layer 520 and the first passivation layer 530; a second substrate 590 disposed opposite the first substrate 510; a liquid crystal layer 570 located on the first substrate 510 And the second substrate 590 is formed on the first electrode layer 560 and covers the second passivation layer 550; and a second electrode layer 580 is formed on the second substrate 590; Between the first conductive layer 520, a conductive bridge hole 415 is formed, and the first electrode layer 560 is simultaneously covered on the first conductive layer 520; a voltage signal is transmitted through the first conductive layer 520;
  • the first conductive layer 520 further includes a first trace 410, a second trace 420, and a third trace 430.
  • At least one conductive bridge hole 415 is formed on the first trace 410.
  • At least one conductive bridge hole 425 is formed on the second trace 420.
  • At least one conductive bridge hole 435 is formed on the third trace 430.
  • the liquid crystal layer 570 has a dielectric coefficient including a dielectric constant of a parallel vector and a dielectric constant of a vertical vector.
  • a method for reducing a capacitive load includes: providing a first substrate 510; forming a first conductive layer 520 on the first substrate 510; and transmitting a first passivation a layer 530 is formed on the first conductive layer 520 and covers the first substrate 510; formed on the first passivation layer 530 through a second passivation layer 550; and by a first electrode
  • the layer 560 is formed on the second passivation layer 550 and covers a portion of the first conductive layer 520 and the first passivation layer 550; and a second substrate 590 is disposed opposite to the first substrate 510;
  • the first liquid crystal layer 570 is disposed between the first substrate 510 and the second substrate 590, formed on the first electrode layer 560, and covers the second passivation layer 550;
  • the second electrode layer 580 is formed on the second substrate 590; wherein the first conductive layer 520 is traced to form a conductive bridge hole 415, and the first electrode layer 560
  • the first conductive layer 520 further includes a first trace 410, a second trace 420, and a third trace 430, respectively.
  • the wires form at least one electrically conductive bridging hole 415, 425, 435.
  • the liquid crystal layer 570 has a dielectric coefficient including a dielectric constant of a parallel vector and a dielectric constant of a vertical vector.
  • the display panel may include an LCD (Liquid Crystal Display) panel, wherein the LCD (Liquid Crystal Display) panel includes: a thin film transistor (TFT) substrate, a color filter layer (color filter)
  • TFT thin film transistor
  • color filter color filter
  • the CF substrate is a liquid crystal layer formed between the two substrates, and the display panel is also an OLED (Organic Light-Emitting Diode) panel or a QLED (Quantum Dots Light-Emitting Diode) panel.
  • the application can reduce the load of the gate drive circuit and reduce the power of the panel.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Optics & Photonics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Power Engineering (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请提供一种显示面板及其降低电容负载的方法，显示面板，包括：一第一基板；一第一导电层形成于第一基板上；一第一钝化层形成于第一导电层上，并覆盖第一基板；一第二钝化层形成于第一钝化层上；以及一第一电极层形成于第二钝化层上，并覆盖部分第一导电层及第一钝化层；一第二基板，与第一基板对向设置；一液晶层，位于第一基板以及第二基板之间；以及一第二电极层形成于第二基板上；其中，在第一导电层走线形成一导电桥接洞，并同时将第一电极层覆盖于第一导电层上；通过导电桥接洞传送一电压讯号于第一电极层及第二电极层。

Description

显示面板及其降低电容负载的方法 技术领域
本申请涉及一种电路负载设计领域，特别是涉及一种显示面板及其降低电容负载的方法。
背景技术
在主动式矩阵液晶显示器(Active Matrix Liquid Crystal Display)中，每个像素包含一个薄膜晶体管(Thin-Film Transistor,TFT)，其晶体管的闸极连接至水平方向扫描线，源极连接至垂直方向的数据线，而漏极则连接至像素电极。若在水平方向的某一条扫描线提供足够的正电压，会使得在该条扫描线所有的晶体管打开，而在该条扫描线的像素电极会与垂直方向的数据线连接，将数据线的讯号电压写入在该条扫描线的每一个像素电容中，控制不同像素液晶的透光度进而达到控制色彩的效果。
传统用以驱动每个像素晶体管闸极的闸极驱动电路是使用移位寄存器电路(Shift Register)来产生连续的驱动讯号到扫描线，以控制显示器中每个像素晶体管的开启和关闭。范例性的是将移位寄存器电路直接制作在阵列(Array)基板上，来代替由外接硅芯片制作的驱动芯片，这样的技术又称作闸极驱动电路基板技术(Gate Driver on Array,GOA)。进一步来说，将移位寄存器电路直接制作在显示面板的边框(Border)上，可减少制作程序，并且降低产品成本，进而提高主动式矩阵面板的高集成度，使面板能更薄型化。
显示面板的工艺架构，以闸极驱动设计来分，可以分为SOC(System on chip)和GOA(Gate driver on array)两种，就产品需求的角度来看，边框越小，也是大家所期望的，所以相较SOC版设计，GOA有较小的边框(Border)。GOA在面板设计上是一项重要技术，主要优点是可以免去闸极驱动集成电路，降低产品成本，所以GOA产品势必是未来的主流趋势，所以如何解决电路负载过大问题，是目前市场上GOA产品面临的一个重大挑战。
发明内容
为了解决上述技术问题，本申请的目的在于，提供一种显示面板，包括：一第一基板；一第一导电层形成于所述第一基板上；一第一钝化层形成于所述第一导电层上，并覆盖所述第一基板；一第二钝化层形成于所述第一钝化层上；以及一第一电极层形成于所述第二钝化层上，并覆盖部分所述第一导电层及第一钝化层；一第二基板，与所述第一基板对向设置；一液晶层，位于所述第一基板以及所述第二基板之间；以及一第二电极层形成于所述第二基板上；其中，在所述第一导电层走线形成一导电桥接洞，并同时将所述第一电极层覆盖于所述第一导电层上；通过所述导电桥接洞 传送一电压讯号于所述第一电极层及所述第二电极层。
本申请的另一目的为提供另一种显示面板，包括：一第一基板；一第一导电层形成于所述第一基板上；一第一钝化层形成于所述第一导电层上，并覆盖所述第一基板；一第二钝化层形成于所述第一钝化层上；以及一第一电极层形成于所述第二钝化层上，并覆盖部分所述第一导电层及第一钝化层；一第二基板，与所述第一基板对向设置；一液晶层，位于所述第一基板以及所述第二基板之间，形成于所述第一电极层上，并覆盖所述第二钝化层；以及一第二电极层形成于所述第二基板上；其中，在所述第一导电层走线形成一导电桥接洞，并同时将所述第一电极层覆盖于所述第一导电层上；通过所述导电桥接洞传送一电压讯号于所述第一电极层及所述第二电极层；在所述第一导电层与所述第二电极层之间形成一电容。
本申请的又一目的为提供一种降低电容负载的方法，包括：提供一第一基板；透过一第一金属层形成于所述第一基板上；透过一第一钝化层形成于所述第一导电层上，并覆盖所述第一基板；透过一第二钝化层形成于所述第一钝化层上；以及藉由一第一电极层形成于所述第二钝化层上，并覆盖部分所述第一导电层及第一钝化层；提供一第二基板，与所述第一基板对向设置；透过一液晶层，位于所述第一基板以及所述第二基板之间，形成于所述第一电极层上，并覆盖所述第二钝化层；以及透过一第二电极层形成于所述第二基板上；其中，在所述第一导电层走线形成一导电桥接洞，并同时将所述第一电极层覆盖于所述第一导电层上；透过所述导电桥接洞传送一电压讯号于所述第一电极层及所述第二电极层，使所述液晶层的所述介质系数趋近为平行向量的介电系数。
本申请的目的及解决其技术问题是采用以下技术方案来实现的。
在本申请的一实施例中，所述第一导电层更包括一第一走线、一第二走线及一第三走线。
在本申请的一实施例中，所述第一走线形成至少一导电桥接洞。
在本申请的一实施例中，所述第二走线形成至少一导电桥接洞。
在本申请的一实施例中，所述第三走线形成至少一导电桥接洞。
在本申请的一实施例中，所述液晶层具有一介质系数，所述介质系数包括平行向量的介电系数与垂直向量的介电系数。
在本申请的一实施例中，所述降低电容负载的方法，所述第一导电层更包括一第一走线、一第二走线及一第三走线，分别在所述走线形成至少一导电桥接洞。
在本申请的一实施例中，所述降低电容负载的方法，所述液晶层具有一介质系数，所述介电系数包括平行向量的介电系数与垂直向量的介电系数。
本申请可以降低闸极驱动电路走线负载及降低平板功率。
附图说明
图1为范例性的显示面板示意图。
图2为本申请一实施例的显示面板示意图。
图3a为范例性的电容负载电路示意图。
图3b为本申请一实施例的电容负载电路示意图。
图4a为范例性的金属走线示意图。
图4b为本申请一实施例的金属走线示意图。
图5a为范例性的电容负载的装置示意图。
图5b为本申请一实施例的电容负载的装置示意图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度。在附图中，为了理解和便于描述，夸大了一些层和区域的厚度。将理解的是，当例如层、膜、区域或基底的组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本申请为达成预定发明目的所采取的技术手段及功效，以下结合附图及具体的实施例，对依据本申请提出的一种显示面板及其降低电容负载的方法，其具体实施方式、结构、特征及其功效，详细说明如后。
图1为范例性的显示面板示意图。请参考图1，一种范例性显示面板10，包括一彩色滤光片基板100、一阵列基板110及一驱动芯片105，用以驱动电路。
图2为本申请一实施例的显示面板示意图。请参考图2，在本申请的一实施例中，一种具有闸极阵列驱动的显示面板11，包括一彩色滤光片基板100、一阵列基板110、一驱动芯片105及一闸极阵列驱动电路103，用以将所述闸极驱动电路103制作在阵列基板110上。而所谓GOA是 将闸极驱动电路配置于阵列基板上，以取替由外接硅芯片制作之驱动芯片。由于GOA技术可直接配置在面板周围，因而简化制作程序，提高显示面板的整合度，使得面板更加薄型化。而随着科技的进展，显示面板产业更研发出双驱GOA电路，此技术是将两组GOA电路分别配置于面板之两侧。
图3a为范例性的电容负载电路示意图。请参考图3a，一种电容负载电路300包括：一时钟电压讯号310、一讯号电阻320、一讯号电容330、一并联电容340以及一主动开关T10；其中所述主动开关T10的一控制端101a电性耦接所述并联电容340，所述主动开关T10的一第一端101b电性耦接所述并联电容340，所述主动开关T10的一第二端101c电性耦接一闸极线。
图3b为本申请一实施例的电容负载电路示意图。请参考图3b，一种电容负载电路301包括：一时钟电压讯号310、一讯号电阻320、一讯号电容330以及一主动开关T10；其中所述主动开关T10的一控制端101a电性耦接所述讯号电容330，所述主动开关T10的一第一端101b电性耦接所述讯号电容330，所述主动开关T10的一第二端101c电性耦接一闸极线。
图4a为范例性的金属走线示意图、图4b为本申请一实施例的金属走线示意图、图5a为范例性的电容负载的装置示意图及图5b为本申请一实施例的电容负载的装置示意图。请参考图4a，一种金属层走线区400，包括第一走线410、第二走线420及第三走线430；其中所述第二走线420上形成一导电桥接洞425，所述第三走线430上形成一导电桥接洞435。
请参考图4a及图5a，一种显示面板500，包括：一第一基板510；一第一金属层520形成于所述第一基板510上；一第一钝化层530形成于所述第一导电层520上，并覆盖所述第一基板510；一第二金属层540形成于所述第一钝化层530上；一第二钝化层550形成于所述第一钝化层530上；以及一第一电极层560形成于所述第二钝化层550上，并覆盖部分所述第一导电层520、所述第二金属层540及所述第一钝化层530；一第二基板590，与所述第一基板510对向设置；一液晶层570，位于所述第一基板510以及所述第二基板590之间；以及一第二电极层580形成于所述第二基板590上；其中，在所述第一导电层520走线形成一导电桥接洞425；在所述第二金属层540走线形成一导电桥接洞435；在所述第一导电层520与所述第二电极层580之间形成一电容595。
在本申请的一实施例中，所述第二走线420上形成至少一导电桥接洞425。
在本申请的一实施例中，所述第三走线430上形成至少一导电桥接洞435。
请参考图4b，一种金属层走线区401，包括第一走线410、第二走线420及第三走线430；其中所述第一走线410上形成一导电桥接洞415，所述第二走线420上形成一导电桥接洞425，所述第三走线430上形成一导电桥接洞435。
请参考图4b及图5b，一种显示面板501，包括：一第一基板510；一第一金属层520形成 于所述第一基板510上；一第一钝化层530形成于所述第一导电层520上，并覆盖所述第一基板510；一第二钝化层550形成于所述第一钝化层530上；以及一第一电极层560形成于所述第二钝化层550上，并覆盖部分所述第一导电层520及第一钝化层530；一第二基板590，与所述第一基板510对向设置；一液晶层570，位于所述第一基板510以及所述第二基板590之间；以及一第二电极层580形成于所述第二基板590上；其中，在所述第一导电层520走线形成一导电桥接洞415，并同时将所述第一电极层560覆盖于所述第一导电层520上；通过所述导电桥接洞415传送一电压讯号于所述第一电极层560及所述第二电极层580。
在本申请的一实施例中，所述第一导电层520更包括一第一走线410、一第二走线420及一第三走线430。
在本申请的一实施例中，所述第一走线410上形成至少一导电桥接洞415。
在本申请的一实施例中，所述第二走线420上形成至少一导电桥接洞425。
在本申请的一实施例中，所述第三走线430上形成至少一导电桥接洞435。
在本申请的一实施例中，所述液晶层570具有一介质系数，所述介质系数包括平行向量的介电系数与垂直向量的介电系数。
请参考图4b及图5b，一种显示面板501，包括：一第一基板510；一第一导电层520形成于所述第一基板510上；一第一钝化层530形成于所述第一导电层520上，并覆盖所述第一基板510；一第二钝化层550形成于所述第一钝化层530上；以及一第一电极层560形成于所述第二钝化层550上，并覆盖部分所述第一导电层520及第一钝化层530；一第二基板590，与所述第一基板510对向设置；一液晶层570，位于所述第一基板510以及所述第二基板590之间，形成于所述第一电极层560上，并覆盖所述第二钝化层550；以及一第二电极层580形成于所述第二基板590上；其中，在所述第一导电层520走线形成一导电桥接洞415，并同时将所述第一电极层560覆盖于所述第一导电层520上；通过所述导电桥接洞415传送一电压讯号于所述第一电极层560及所述第二电极层580；在所述第一导电层520与所述第二电极层580之间形成一电容595。
在本申请的一实施例中，所述第一导电层520更包括一第一走线410、一第二走线420及一第三走线430。
在本申请的一实施例中，所述第一走线410上形成至少一导电桥接洞415。
在本申请的一实施例中，所述第二走线420上形成至少一导电桥接洞425。
在本申请的一实施例中，所述第三走线430上形成至少一导电桥接洞435。
在本申请的一实施例中，所述液晶层570具有一介质系数，所述介质系数包括平行向量的介电系数与垂直向量的介电系数。
请参考图4b及图5b，一种降低电容负载的方法，包括：提供一第一基板510；透过一第一导电层520形成于所述第一基板510上；透过一第一钝化层530形成于所述第一导电层520上，并覆盖所述第一基板510；透过一第二钝化层550形成于所述第一钝化层530上；以及藉由一第一电极层560形成于所述第二钝化层550上，并覆盖部分所述第一导电层520及第一钝化层550；提供一第二基板590，与所述第一基板510对向设置；透过一液晶层570，位于所述第一基板510以及所述第二基板590之间，形成于所述第一电极层560上，并覆盖所述第二钝化层550；以及透过一第二电极层580形成于所述第二基板590上；其中，在所述第一导电层520走线形成一导电桥接洞415，并同时将所述第一电极层560覆盖于所述第一导电层520上；透过所述导电桥接洞415传送一电压讯号于所述第一电极层560及所述第二电极层580，因而使所述液晶层570的所述介质系数趋近为平行向量的介电系数(举例:由电压信号大小控制介电系数方向的倾斜度)，而有效降低电路走线的电容值。
请参考图4b及图5b，在本申请的一实施例中，第一导电层520更包括一第一走线410、一第二走线420及一第三走线430，分别在所述走线形成至少一导电桥接洞415、425、435。
请参考图5b，在本申请的一实施例中，所述液晶层570具有一介质系数，所述介质系数包括平行向量的介电系数与垂直向量的介电系数。
在本申请的某些实施例中，显示面板可包括LCD(Liquid Crystal Display)面板，其中LCD(Liquid Crystal Display)面板包括：开关阵列(thin film transistor，TFT)基板、彩色滤光层(color filter，CF)基板与形成于两基板之间的液晶层，显示面板亦或为OLED(Organic Light-Emitting Diode)面板，或QLED(Quantum Dots Light-Emitting Diode)面板。
本申请可以降低闸极驱动电路走线负载及降低平板功率。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。所述用语通常不是指相同的实施例；但它也可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的实施例，并非对本申请作任何形式上的限制，虽然本申请已以具体的实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (18)

  1. 一种显示面板，包括：
    一第一基板；
    一第一导电层形成于所述第一基板上；
    一第一钝化层形成于所述第一导电层上，并覆盖所述第一基板；
    一第二钝化层形成于所述第一钝化层上；以及
    一第一电极层形成于所述第二钝化层上，并覆盖部分所述第一导电层及第一钝化层；
    一第二基板，与所述第一基板对向设置；
    一液晶层，位于所述第一基板以及所述第二基板之间；以及
    一第二电极层形成于所述第二基板上；
    其中，在所述第一导电层走线形成一导电桥接洞，并同时将所述第一电极层覆盖于所述第一导电层上；通过所述导电桥接洞传送一电压讯号于所述第一电极层及所述第二电极层。
  2. 如权利要求1所述的显示面板，其中，所述第一导电层更包括一第一走线。
  3. 如权利要求2所述的显示面板，其中，所述第一走线形成至少一导电桥接洞。
  4. 如权利要求1所述的显示面板，其中，所述第一导电层更包括一第二走线。
  5. 如权利要求4所述的显示面板，其中，所述第二走线形成至少一导电桥接洞。
  6. 如权利要求1所述的显示面板，其中，所述第一导电层更包括一第三走线。
  7. 如权利要求6所述的显示面板，其中，所述第三走线形成至少一导电桥接洞。
  8. 如权利要求1所述的显示面板，其中，所述液晶层具有一介质系数，所述介质系数包括平行向量的介电系数与垂直向量的介电系数。
  9. 一种显示面板，包括：
    一第一基板；
    一第一导电层形成于所述第一基板上；
    一第一钝化层形成于所述第一导电层上，并覆盖所述第一基板；
    一第二钝化层形成于所述第一钝化层上；以及
    一第一电极层形成于所述第二钝化层上，并覆盖部分所述第一导电层及第一钝化层；
    一第二基板，与所述第一基板对向设置；
    一液晶层，位于所述第一基板以及所述第二基板之间，形成于所述第一电极层上，并覆盖所述第二钝化层；以及
    一第二电极层形成于所述第二基板上；
    其中，在所述第一导电层走线形成一导电桥接洞，并同时将所述第一电极层覆盖于所述第一导电层上；通过所述导电桥接洞传送一电压讯号于所述第一电极层及所述第二电极层；在所述第一导电层与所述第二电极层之间形成一电容。
  10. 一种降低电容负载的方法，包括：
    提供一第一基板；
    透过一第一导电层形成于所述第一基板上；
    透过一第一钝化层形成于所述第一导电层上，并覆盖所述第一基板；
    透过一第二钝化层形成于所述第一钝化层上；以及
    藉由一第一电极层形成于所述第二钝化层上，并覆盖部分所述第一导电层及第一钝化层；
    提供一第二基板，与所述第一基板对向设置；
    透过一液晶层，位于所述第一基板以及所述第二基板之间，形成于所述第一电极层上，并覆盖所述第二钝化层；以及
    透过一第二电极层形成于所述第二基板上；
    其中，在所述第一导电层走线形成一导电桥接洞，并同时将所述第一电极层覆盖于所述第一导电层上；透过所述导电桥接洞传送一电压讯号于所述第一电极层及所述第二电极层，使所述液晶层的所述介质系数趋近为平行向量的介电系数。
  11. 如权利要求10所述的降低电容负载的方法，其中，所述第一导电层更包括一第一走线。
  12. 如权利要求11所述的降低电容负载的方法，其中，所述第一走线形成至少一导电桥接洞。
  13. 如权利要求10所述的降低电容负载的方法，其中，所述第一导电层更包括一第二走线。
  14. 如权利要求13所述的降低电容负载的方法，其中，所述第二走线形成至少一导电桥接洞。
  15. 如权利要求10所述的降低电容负载的方法，其中，所述第一导电层更包括一第三走线。
  16. 如权利要求15所述的降低电容负载的方法，其中，所述第三走线形成至少一导电桥接洞。
  17. 如权利要求10所述的降低电容负载的方法，其中，所述液晶层具有一介质系数，所述介质系数包括平行向量的介电系数。
  18. 如权利要求10所述的降低电容负载的方法，其中，所述液晶层具有一介质系数，所述介质系数包括垂直向量的介电系数。
PCT/CN2018/093366 2018-03-08 2018-06-28 显示面板及其降低电容负载的方法 WO2019169809A1 (zh)

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